./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.12.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 63182f13 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/bin/uautomizer-YU5uOKAj3y/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/bin/uautomizer-YU5uOKAj3y/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/bin/uautomizer-YU5uOKAj3y/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/bin/uautomizer-YU5uOKAj3y/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.12.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/bin/uautomizer-YU5uOKAj3y/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/bin/uautomizer-YU5uOKAj3y --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 962623ba1d780e7ad35b9b6d7f5839750bc2f361556d46080824a3701cf71595 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-63182f1 [2021-11-13 18:09:32,119 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-13 18:09:32,122 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-13 18:09:32,165 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-13 18:09:32,166 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-13 18:09:32,171 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-13 18:09:32,175 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-13 18:09:32,180 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-13 18:09:32,183 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-13 18:09:32,191 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-13 18:09:32,192 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-13 18:09:32,195 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-13 18:09:32,195 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-13 18:09:32,201 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-13 18:09:32,205 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-13 18:09:32,213 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-13 18:09:32,215 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-13 18:09:32,217 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-13 18:09:32,224 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-13 18:09:32,232 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-13 18:09:32,236 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-13 18:09:32,241 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-13 18:09:32,246 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-13 18:09:32,247 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-13 18:09:32,260 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-13 18:09:32,261 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-13 18:09:32,262 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-13 18:09:32,263 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-13 18:09:32,265 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-13 18:09:32,267 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-13 18:09:32,268 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-13 18:09:32,269 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-13 18:09:32,271 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-13 18:09:32,273 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-13 18:09:32,275 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-13 18:09:32,275 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-13 18:09:32,276 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-13 18:09:32,276 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-13 18:09:32,277 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-13 18:09:32,278 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-13 18:09:32,278 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-13 18:09:32,279 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/bin/uautomizer-YU5uOKAj3y/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-13 18:09:32,324 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-13 18:09:32,324 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-13 18:09:32,324 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-13 18:09:32,325 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-13 18:09:32,326 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-13 18:09:32,326 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-13 18:09:32,327 INFO L138 SettingsManager]: * Use SBE=true [2021-11-13 18:09:32,327 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-13 18:09:32,327 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-13 18:09:32,328 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-13 18:09:32,328 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-13 18:09:32,328 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-13 18:09:32,328 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-13 18:09:32,329 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-13 18:09:32,329 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-13 18:09:32,329 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-13 18:09:32,329 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-13 18:09:32,330 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-13 18:09:32,330 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-13 18:09:32,330 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-13 18:09:32,330 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-13 18:09:32,331 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-13 18:09:32,331 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-13 18:09:32,331 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-13 18:09:32,332 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-13 18:09:32,332 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-13 18:09:32,332 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-13 18:09:32,332 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-13 18:09:32,333 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-13 18:09:32,333 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-13 18:09:32,333 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-13 18:09:32,333 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-13 18:09:32,335 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-13 18:09:32,335 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/bin/uautomizer-YU5uOKAj3y/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/bin/uautomizer-YU5uOKAj3y Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 962623ba1d780e7ad35b9b6d7f5839750bc2f361556d46080824a3701cf71595 [2021-11-13 18:09:32,672 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-13 18:09:32,697 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-13 18:09:32,701 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-13 18:09:32,702 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-13 18:09:32,709 INFO L275 PluginConnector]: CDTParser initialized [2021-11-13 18:09:32,710 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/bin/uautomizer-YU5uOKAj3y/../../sv-benchmarks/c/systemc/token_ring.12.cil-1.c [2021-11-13 18:09:32,793 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/bin/uautomizer-YU5uOKAj3y/data/627f3bf23/e3a3ea7d58eb41ada3c38033e9763165/FLAG011a5269c [2021-11-13 18:09:33,439 INFO L306 CDTParser]: Found 1 translation units. [2021-11-13 18:09:33,440 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/sv-benchmarks/c/systemc/token_ring.12.cil-1.c [2021-11-13 18:09:33,456 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/bin/uautomizer-YU5uOKAj3y/data/627f3bf23/e3a3ea7d58eb41ada3c38033e9763165/FLAG011a5269c [2021-11-13 18:09:33,705 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/bin/uautomizer-YU5uOKAj3y/data/627f3bf23/e3a3ea7d58eb41ada3c38033e9763165 [2021-11-13 18:09:33,708 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-13 18:09:33,713 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-13 18:09:33,719 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-13 18:09:33,719 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-13 18:09:33,724 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-13 18:09:33,725 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 06:09:33" (1/1) ... [2021-11-13 18:09:33,729 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5f992995 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:09:33, skipping insertion in model container [2021-11-13 18:09:33,730 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 06:09:33" (1/1) ... [2021-11-13 18:09:33,739 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-13 18:09:33,830 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-13 18:09:34,009 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/sv-benchmarks/c/systemc/token_ring.12.cil-1.c[671,684] [2021-11-13 18:09:34,189 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-13 18:09:34,206 INFO L203 MainTranslator]: Completed pre-run [2021-11-13 18:09:34,245 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/sv-benchmarks/c/systemc/token_ring.12.cil-1.c[671,684] [2021-11-13 18:09:34,385 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-13 18:09:34,424 INFO L208 MainTranslator]: Completed translation [2021-11-13 18:09:34,425 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:09:34 WrapperNode [2021-11-13 18:09:34,426 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-13 18:09:34,427 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-13 18:09:34,427 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-13 18:09:34,427 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-13 18:09:34,437 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:09:34" (1/1) ... [2021-11-13 18:09:34,473 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:09:34" (1/1) ... [2021-11-13 18:09:34,640 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-13 18:09:34,641 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-13 18:09:34,642 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-13 18:09:34,642 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-13 18:09:34,653 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:09:34" (1/1) ... [2021-11-13 18:09:34,667 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:09:34" (1/1) ... [2021-11-13 18:09:34,682 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:09:34" (1/1) ... [2021-11-13 18:09:34,683 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:09:34" (1/1) ... [2021-11-13 18:09:34,750 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:09:34" (1/1) ... [2021-11-13 18:09:34,788 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:09:34" (1/1) ... [2021-11-13 18:09:34,795 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:09:34" (1/1) ... [2021-11-13 18:09:34,809 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-13 18:09:34,810 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-13 18:09:34,811 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-13 18:09:34,811 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-13 18:09:34,812 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:09:34" (1/1) ... [2021-11-13 18:09:34,821 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-13 18:09:34,834 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/bin/uautomizer-YU5uOKAj3y/z3 [2021-11-13 18:09:34,853 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/bin/uautomizer-YU5uOKAj3y/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-13 18:09:34,923 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4991e521-ae20-4d71-b980-6bcb0da1aea4/bin/uautomizer-YU5uOKAj3y/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-13 18:09:34,960 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-13 18:09:34,964 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-13 18:09:34,965 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-13 18:09:34,965 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-13 18:09:37,919 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-13 18:09:37,920 INFO L299 CfgBuilder]: Removed 15 assume(true) statements. [2021-11-13 18:09:37,925 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 06:09:37 BoogieIcfgContainer [2021-11-13 18:09:37,926 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-13 18:09:37,928 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-13 18:09:37,929 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-13 18:09:37,933 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-13 18:09:37,934 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-13 18:09:37,934 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 06:09:33" (1/3) ... [2021-11-13 18:09:37,936 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@640afce0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 06:09:37, skipping insertion in model container [2021-11-13 18:09:37,936 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-13 18:09:37,936 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:09:34" (2/3) ... [2021-11-13 18:09:37,937 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@640afce0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 06:09:37, skipping insertion in model container [2021-11-13 18:09:37,937 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-13 18:09:37,938 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 06:09:37" (3/3) ... [2021-11-13 18:09:37,941 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.12.cil-1.c [2021-11-13 18:09:38,043 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-13 18:09:38,043 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-13 18:09:38,043 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-13 18:09:38,043 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-13 18:09:38,043 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-13 18:09:38,044 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-13 18:09:38,044 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-13 18:09:38,044 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-13 18:09:38,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1798 states, 1797 states have (on average 1.4997217584863662) internal successors, (2695), 1797 states have internal predecessors, (2695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:38,253 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1631 [2021-11-13 18:09:38,254 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:38,254 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:38,289 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:38,289 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:38,289 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-13 18:09:38,296 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1798 states, 1797 states have (on average 1.4997217584863662) internal successors, (2695), 1797 states have internal predecessors, (2695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:38,329 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1631 [2021-11-13 18:09:38,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:38,330 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:38,345 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:38,346 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:38,368 INFO L791 eck$LassoCheckResult]: Stem: 437#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1725#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 125#L1778true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 113#L846true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1178#L853true assume !(1 == ~m_i~0);~m_st~0 := 2; 979#L853-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 271#L858-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3#L863-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 758#L868-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 885#L873-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1654#L878-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1613#L883-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1685#L888-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 384#L893-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 786#L898-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1787#L903-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 715#L908-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1404#L913-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 846#L1206true assume !(0 == ~M_E~0); 373#L1206-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1172#L1211-1true assume !(0 == ~T2_E~0); 1334#L1216-1true assume !(0 == ~T3_E~0); 261#L1221-1true assume !(0 == ~T4_E~0); 1255#L1226-1true assume !(0 == ~T5_E~0); 92#L1231-1true assume !(0 == ~T6_E~0); 1409#L1236-1true assume !(0 == ~T7_E~0); 1238#L1241-1true assume !(0 == ~T8_E~0); 296#L1246-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 417#L1251-1true assume !(0 == ~T10_E~0); 930#L1256-1true assume !(0 == ~T11_E~0); 8#L1261-1true assume !(0 == ~T12_E~0); 1624#L1266-1true assume !(0 == ~E_M~0); 1566#L1271-1true assume !(0 == ~E_1~0); 874#L1276-1true assume !(0 == ~E_2~0); 1556#L1281-1true assume !(0 == ~E_3~0); 807#L1286-1true assume 0 == ~E_4~0;~E_4~0 := 1; 212#L1291-1true assume !(0 == ~E_5~0); 1651#L1296-1true assume !(0 == ~E_6~0); 650#L1301-1true assume !(0 == ~E_7~0); 1116#L1306-1true assume !(0 == ~E_8~0); 1075#L1311-1true assume !(0 == ~E_9~0); 195#L1316-1true assume !(0 == ~E_10~0); 1490#L1321-1true assume !(0 == ~E_11~0); 662#L1326-1true assume 0 == ~E_12~0;~E_12~0 := 1; 121#L1331-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1782#L598true assume 1 == ~m_pc~0; 151#L599true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1207#L609true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1741#L610true activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1432#L1497true assume !(0 != activate_threads_~tmp~1#1); 1686#L1497-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1295#L617true assume !(1 == ~t1_pc~0); 307#L617-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1731#L628true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 234#L629true activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1479#L1505true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 726#L1505-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1325#L636true assume 1 == ~t2_pc~0; 292#L637true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 560#L647true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 204#L648true activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1469#L1513true assume !(0 != activate_threads_~tmp___1~0#1); 757#L1513-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 492#L655true assume !(1 == ~t3_pc~0); 1439#L655-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1705#L666true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 136#L667true activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1789#L1521true assume !(0 != activate_threads_~tmp___2~0#1); 1568#L1521-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1594#L674true assume 1 == ~t4_pc~0; 51#L675true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1663#L685true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 878#L686true activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 205#L1529true assume !(0 != activate_threads_~tmp___3~0#1); 490#L1529-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1346#L693true assume !(1 == ~t5_pc~0); 616#L693-2true is_transmit5_triggered_~__retres1~5#1 := 0; 374#L704true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1115#L705true activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1080#L1537true assume !(0 != activate_threads_~tmp___4~0#1); 425#L1537-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 387#L712true assume 1 == ~t6_pc~0; 907#L713true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 685#L723true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 952#L724true activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1673#L1545true assume !(0 != activate_threads_~tmp___5~0#1); 774#L1545-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 769#L731true assume 1 == ~t7_pc~0; 123#L732true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 226#L742true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 868#L743true activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1089#L1553true assume !(0 != activate_threads_~tmp___6~0#1); 995#L1553-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 182#L750true assume !(1 == ~t8_pc~0); 860#L750-2true is_transmit8_triggered_~__retres1~8#1 := 0; 277#L761true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1763#L762true activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1102#L1561true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 348#L1561-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 724#L769true assume 1 == ~t9_pc~0; 1732#L770true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 103#L780true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 539#L781true activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 926#L1569true assume !(0 != activate_threads_~tmp___8~0#1); 1365#L1569-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1019#L788true assume !(1 == ~t10_pc~0); 626#L788-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1241#L799true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 822#L800true activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1141#L1577true assume !(0 != activate_threads_~tmp___9~0#1); 180#L1577-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1026#L807true assume 1 == ~t11_pc~0; 1218#L808true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 759#L818true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1278#L819true activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1799#L1585true assume !(0 != activate_threads_~tmp___10~0#1); 1783#L1585-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1182#L826true assume !(1 == ~t12_pc~0); 388#L826-2true is_transmit12_triggered_~__retres1~12#1 := 0; 782#L837true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1610#L838true activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 1369#L1593true assume !(0 != activate_threads_~tmp___11~0#1); 486#L1593-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 430#L1344true assume !(1 == ~M_E~0); 521#L1344-2true assume !(1 == ~T1_E~0); 1747#L1349-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 655#L1354-1true assume !(1 == ~T3_E~0); 1007#L1359-1true assume !(1 == ~T4_E~0); 1587#L1364-1true assume !(1 == ~T5_E~0); 235#L1369-1true assume !(1 == ~T6_E~0); 983#L1374-1true assume !(1 == ~T7_E~0); 660#L1379-1true assume !(1 == ~T8_E~0); 713#L1384-1true assume !(1 == ~T9_E~0); 1769#L1389-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1246#L1394-1true assume !(1 == ~T11_E~0); 1674#L1399-1true assume !(1 == ~T12_E~0); 1470#L1404-1true assume !(1 == ~E_M~0); 298#L1409-1true assume !(1 == ~E_1~0); 1428#L1414-1true assume !(1 == ~E_2~0); 908#L1419-1true assume !(1 == ~E_3~0); 109#L1424-1true assume !(1 == ~E_4~0); 666#L1429-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1273#L1434-1true assume !(1 == ~E_6~0); 1658#L1439-1true assume !(1 == ~E_7~0); 134#L1444-1true assume !(1 == ~E_8~0); 854#L1449-1true assume !(1 == ~E_9~0); 351#L1454-1true assume !(1 == ~E_10~0); 1327#L1459-1true assume !(1 == ~E_11~0); 740#L1464-1true assume !(1 == ~E_12~0); 787#L1469-1true assume { :end_inline_reset_delta_events } true; 1521#L1815-2true [2021-11-13 18:09:38,375 INFO L793 eck$LassoCheckResult]: Loop: 1521#L1815-2true assume !false; 928#L1816true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 689#L1181true assume false; 1759#L1196true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 106#L846-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1653#L1206-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1670#L1206-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 739#L1211-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 173#L1216-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 500#L1221-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1032#L1226-3true assume !(0 == ~T5_E~0); 207#L1231-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 371#L1236-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1784#L1241-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1362#L1246-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1156#L1251-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 835#L1256-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 185#L1261-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 545#L1266-3true assume !(0 == ~E_M~0); 206#L1271-3true assume 0 == ~E_1~0;~E_1~0 := 1; 520#L1276-3true assume 0 == ~E_2~0;~E_2~0 := 1; 467#L1281-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1216#L1286-3true assume 0 == ~E_4~0;~E_4~0 := 1; 902#L1291-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1666#L1296-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1584#L1301-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1448#L1306-3true assume !(0 == ~E_8~0); 555#L1311-3true assume 0 == ~E_9~0;~E_9~0 := 1; 143#L1316-3true assume 0 == ~E_10~0;~E_10~0 := 1; 186#L1321-3true assume 0 == ~E_11~0;~E_11~0 := 1; 632#L1326-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1418#L1331-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 914#L598-42true assume !(1 == ~m_pc~0); 1054#L598-44true is_master_triggered_~__retres1~0#1 := 0; 1191#L609-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 227#L610-14true activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1449#L1497-42true assume !(0 != activate_threads_~tmp~1#1); 1704#L1497-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 672#L617-42true assume 1 == ~t1_pc~0; 497#L618-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 415#L628-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 718#L629-14true activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1440#L1505-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 258#L1505-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1424#L636-42true assume !(1 == ~t2_pc~0); 529#L636-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1745#L647-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 820#L648-14true activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1101#L1513-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1003#L1513-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 856#L655-42true assume 1 == ~t3_pc~0; 1603#L656-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1064#L666-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 297#L667-14true activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1758#L1521-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1214#L1521-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1112#L674-42true assume !(1 == ~t4_pc~0); 841#L674-44true is_transmit4_triggered_~__retres1~4#1 := 0; 775#L685-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84#L686-14true activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 970#L1529-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 615#L1529-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1197#L693-42true assume !(1 == ~t5_pc~0); 1514#L693-44true is_transmit5_triggered_~__retres1~5#1 := 0; 881#L704-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1466#L705-14true activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 877#L1537-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1159#L1537-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 355#L712-42true assume !(1 == ~t6_pc~0); 1591#L712-44true is_transmit6_triggered_~__retres1~6#1 := 0; 997#L723-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 735#L724-14true activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1788#L1545-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 420#L1545-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1379#L731-42true assume !(1 == ~t7_pc~0); 255#L731-44true is_transmit7_triggered_~__retres1~7#1 := 0; 1383#L742-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1095#L743-14true activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 366#L1553-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1061#L1553-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 210#L750-42true assume 1 == ~t8_pc~0; 542#L751-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1562#L761-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 896#L762-14true activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 152#L1561-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1696#L1561-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 614#L769-42true assume 1 == ~t9_pc~0; 480#L770-14true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1119#L780-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1239#L781-14true activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1596#L1569-42true assume !(0 != activate_threads_~tmp___8~0#1); 259#L1569-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 620#L788-42true assume !(1 == ~t10_pc~0); 906#L788-44true is_transmit10_triggered_~__retres1~10#1 := 0; 1699#L799-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 578#L800-14true activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1677#L1577-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1626#L1577-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1542#L807-42true assume !(1 == ~t11_pc~0); 60#L807-44true is_transmit11_triggered_~__retres1~11#1 := 0; 544#L818-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 126#L819-14true activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 127#L1585-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1155#L1585-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 257#L826-42true assume 1 == ~t12_pc~0; 1743#L827-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 986#L837-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1340#L838-14true activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 253#L1593-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1487#L1593-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 838#L1344-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1225#L1344-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 776#L1349-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 334#L1354-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 790#L1359-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1662#L1364-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1553#L1369-3true assume !(1 == ~T6_E~0); 1272#L1374-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 213#L1379-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1162#L1384-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 333#L1389-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 514#L1394-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1727#L1399-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1293#L1404-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1232#L1409-3true assume !(1 == ~E_1~0); 1361#L1414-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1386#L1419-3true assume 1 == ~E_3~0;~E_3~0 := 2; 976#L1424-3true assume 1 == ~E_4~0;~E_4~0 := 2; 161#L1429-3true assume 1 == ~E_5~0;~E_5~0 := 2; 789#L1434-3true assume 1 == ~E_6~0;~E_6~0 := 2; 962#L1439-3true assume 1 == ~E_7~0;~E_7~0 := 2; 130#L1444-3true assume 1 == ~E_8~0;~E_8~0 := 2; 191#L1449-3true assume !(1 == ~E_9~0); 1447#L1454-3true assume 1 == ~E_10~0;~E_10~0 := 2; 785#L1459-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1775#L1464-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1268#L1469-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 676#L926-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 83#L993-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 403#L994-1true start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1592#L1834true assume !(0 == start_simulation_~tmp~3#1); 1108#L1834-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 910#L926-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 584#L993-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 745#L994-2true stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 1252#L1789true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1597#L1796true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 76#L1797true start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 977#L1847true assume !(0 != start_simulation_~tmp___0~1#1); 1521#L1815-2true [2021-11-13 18:09:38,383 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:38,383 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2021-11-13 18:09:38,395 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:38,396 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [355406077] [2021-11-13 18:09:38,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:38,398 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:38,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:38,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:38,711 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:38,711 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [355406077] [2021-11-13 18:09:38,712 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [355406077] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:38,713 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:38,713 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:38,715 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2044560740] [2021-11-13 18:09:38,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:38,722 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:38,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:38,724 INFO L85 PathProgramCache]: Analyzing trace with hash 1437628410, now seen corresponding path program 1 times [2021-11-13 18:09:38,724 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:38,725 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706101546] [2021-11-13 18:09:38,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:38,726 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:38,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:38,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:38,861 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:38,861 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1706101546] [2021-11-13 18:09:38,862 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1706101546] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:38,862 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:38,862 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:09:38,862 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1622531877] [2021-11-13 18:09:38,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:38,865 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:38,866 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:38,921 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-11-13 18:09:38,922 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-11-13 18:09:38,930 INFO L87 Difference]: Start difference. First operand has 1798 states, 1797 states have (on average 1.4997217584863662) internal successors, (2695), 1797 states have internal predecessors, (2695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:39,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:39,041 INFO L93 Difference]: Finished difference Result 1796 states and 2661 transitions. [2021-11-13 18:09:39,042 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-11-13 18:09:39,049 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1796 states and 2661 transitions. [2021-11-13 18:09:39,073 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:39,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1796 states to 1790 states and 2655 transitions. [2021-11-13 18:09:39,101 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-13 18:09:39,105 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-13 18:09:39,105 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2655 transitions. [2021-11-13 18:09:39,116 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:39,116 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2655 transitions. [2021-11-13 18:09:39,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2655 transitions. [2021-11-13 18:09:39,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-13 18:09:39,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4832402234636872) internal successors, (2655), 1789 states have internal predecessors, (2655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:39,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2655 transitions. [2021-11-13 18:09:39,246 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2655 transitions. [2021-11-13 18:09:39,247 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2655 transitions. [2021-11-13 18:09:39,247 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-13 18:09:39,247 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2655 transitions. [2021-11-13 18:09:39,262 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:39,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:39,263 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:39,267 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:39,267 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:39,268 INFO L791 eck$LassoCheckResult]: Stem: 4447#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 4448#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 3871#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3841#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3842#L853 assume !(1 == ~m_i~0);~m_st~0 := 2; 5103#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4150#L858-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3603#L863-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3604#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4875#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5014#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5380#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5381#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4360#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4361#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4901#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4821#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4822#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4974#L1206 assume !(0 == ~M_E~0); 4339#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4340#L1211-1 assume !(0 == ~T2_E~0); 5233#L1216-1 assume !(0 == ~T3_E~0); 4132#L1221-1 assume !(0 == ~T4_E~0); 4133#L1226-1 assume !(0 == ~T5_E~0); 3795#L1231-1 assume !(0 == ~T6_E~0); 3796#L1236-1 assume !(0 == ~T7_E~0); 5264#L1241-1 assume !(0 == ~T8_E~0); 4194#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4195#L1251-1 assume !(0 == ~T10_E~0); 4415#L1256-1 assume !(0 == ~T11_E~0); 3615#L1261-1 assume !(0 == ~T12_E~0); 3616#L1266-1 assume !(0 == ~E_M~0); 5367#L1271-1 assume !(0 == ~E_1~0); 5002#L1276-1 assume !(0 == ~E_2~0); 5003#L1281-1 assume !(0 == ~E_3~0); 4928#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4036#L1291-1 assume !(0 == ~E_5~0); 4037#L1296-1 assume !(0 == ~E_6~0); 4743#L1301-1 assume !(0 == ~E_7~0); 4744#L1306-1 assume !(0 == ~E_8~0); 5176#L1311-1 assume !(0 == ~E_9~0); 3997#L1316-1 assume !(0 == ~E_10~0); 3998#L1321-1 assume !(0 == ~E_11~0); 4760#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 3861#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3862#L598 assume 1 == ~m_pc~0; 3921#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3922#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5246#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5338#L1497 assume !(0 != activate_threads_~tmp~1#1); 5339#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5295#L617 assume !(1 == ~t1_pc~0); 4217#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4218#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4077#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4078#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4838#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4839#L636 assume 1 == ~t2_pc~0; 4186#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4187#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4017#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4018#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 4874#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4537#L655 assume !(1 == ~t3_pc~0); 4538#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5251#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3891#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3892#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 5368#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5369#L674 assume 1 == ~t4_pc~0; 3711#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3712#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5009#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4019#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 4020#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4534#L693 assume !(1 == ~t5_pc~0); 4697#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4341#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4342#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5178#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 4427#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4364#L712 assume 1 == ~t6_pc~0; 4365#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4792#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4793#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5079#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 4890#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4888#L731 assume 1 == ~t7_pc~0; 3865#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3866#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4060#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4997#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 5116#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3975#L750 assume !(1 == ~t8_pc~0); 3646#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3645#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4161#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5191#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4298#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4299#L769 assume 1 == ~t9_pc~0; 4834#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3819#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3820#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4603#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 5055#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5136#L788 assume !(1 == ~t10_pc~0); 4711#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4712#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4943#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4944#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 3971#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3972#L807 assume 1 == ~t11_pc~0; 5145#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4723#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4876#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5287#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 5392#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5235#L826 assume !(1 == ~t12_pc~0); 4367#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4368#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4896#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 5327#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 4527#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4436#L1344 assume !(1 == ~M_E~0); 4437#L1344-2 assume !(1 == ~T1_E~0); 4578#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4750#L1354-1 assume !(1 == ~T3_E~0); 4751#L1359-1 assume !(1 == ~T4_E~0); 5125#L1364-1 assume !(1 == ~T5_E~0); 4079#L1369-1 assume !(1 == ~T6_E~0); 4080#L1374-1 assume !(1 == ~T7_E~0); 4756#L1379-1 assume !(1 == ~T8_E~0); 4757#L1384-1 assume !(1 == ~T9_E~0); 4820#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5266#L1394-1 assume !(1 == ~T11_E~0); 5267#L1399-1 assume !(1 == ~T12_E~0); 5346#L1404-1 assume !(1 == ~E_M~0); 4198#L1409-1 assume !(1 == ~E_1~0); 4199#L1414-1 assume !(1 == ~E_2~0); 5036#L1419-1 assume !(1 == ~E_3~0); 3832#L1424-1 assume !(1 == ~E_4~0); 3833#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 4767#L1434-1 assume !(1 == ~E_6~0); 5285#L1439-1 assume !(1 == ~E_7~0); 3887#L1444-1 assume !(1 == ~E_8~0); 3888#L1449-1 assume !(1 == ~E_9~0); 4303#L1454-1 assume !(1 == ~E_10~0); 4304#L1459-1 assume !(1 == ~E_11~0); 4854#L1464-1 assume !(1 == ~E_12~0); 4855#L1469-1 assume { :end_inline_reset_delta_events } true; 4902#L1815-2 [2021-11-13 18:09:39,269 INFO L793 eck$LassoCheckResult]: Loop: 4902#L1815-2 assume !false; 5056#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4725#L1181 assume !false; 4796#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4748#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3606#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4335#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 4886#L1008 assume !(0 != eval_~tmp~0#1); 4887#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3825#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3826#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5386#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4853#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3959#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3960#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4550#L1226-3 assume !(0 == ~T5_E~0); 4023#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4024#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4336#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5323#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5226#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4962#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3981#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 3982#L1266-3 assume !(0 == ~E_M~0); 4021#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4022#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4494#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4495#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5032#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5033#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5375#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5343#L1306-3 assume !(0 == ~E_8~0); 4619#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3905#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3906#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3983#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4718#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5043#L598-42 assume !(1 == ~m_pc~0); 5044#L598-44 is_master_triggered_~__retres1~0#1 := 0; 5158#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4061#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4062#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 5344#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4774#L617-42 assume 1 == ~t1_pc~0; 4546#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4411#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4412#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4826#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4126#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4127#L636-42 assume 1 == ~t2_pc~0; 5328#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4591#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4941#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4942#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5121#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4983#L655-42 assume !(1 == ~t3_pc~0); 4563#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4564#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4196#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4197#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5250#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5195#L674-42 assume !(1 == ~t4_pc~0); 4969#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 4891#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3780#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3781#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4695#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4696#L693-42 assume 1 == ~t5_pc~0; 4951#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4952#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5012#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5007#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5008#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4310#L712-42 assume !(1 == ~t6_pc~0); 4311#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 4637#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4845#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4846#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4419#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4420#L731-42 assume !(1 == ~t7_pc~0); 4118#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4119#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5186#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4327#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4328#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4031#L750-42 assume 1 == ~t8_pc~0; 4032#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4606#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5029#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3924#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3925#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4694#L769-42 assume 1 == ~t9_pc~0; 4516#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4517#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5200#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5265#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 4128#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4129#L788-42 assume 1 == ~t10_pc~0; 4702#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4916#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4646#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4647#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5384#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5362#L807-42 assume !(1 == ~t11_pc~0); 3732#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 3733#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3872#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 3873#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3874#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4123#L826-42 assume 1 == ~t12_pc~0; 4124#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4316#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5108#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 4113#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4114#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4965#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4966#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4892#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4273#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4274#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4906#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5364#L1369-3 assume !(1 == ~T6_E~0); 5284#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4038#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4039#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4271#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4272#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4570#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5293#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5256#L1409-3 assume !(1 == ~E_1~0); 5257#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5322#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5102#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3939#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3940#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4905#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3879#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3880#L1449-3 assume !(1 == ~E_9~0); 3989#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4899#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4900#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5281#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4779#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3778#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3779#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 4395#L1834 assume !(0 == start_simulation_~tmp~3#1); 5015#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 5038#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4472#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4651#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 4863#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5271#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3764#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 3765#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 4902#L1815-2 [2021-11-13 18:09:39,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:39,271 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2021-11-13 18:09:39,272 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:39,272 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1586029532] [2021-11-13 18:09:39,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:39,273 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:39,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:39,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:39,395 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:39,396 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1586029532] [2021-11-13 18:09:39,396 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1586029532] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:39,396 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:39,396 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:39,397 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [828639263] [2021-11-13 18:09:39,397 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:39,398 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:39,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:39,399 INFO L85 PathProgramCache]: Analyzing trace with hash 1784148501, now seen corresponding path program 1 times [2021-11-13 18:09:39,399 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:39,399 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409956802] [2021-11-13 18:09:39,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:39,400 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:39,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:39,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:39,596 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:39,596 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [409956802] [2021-11-13 18:09:39,596 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [409956802] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:39,597 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:39,597 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:39,597 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1810360857] [2021-11-13 18:09:39,598 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:39,598 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:39,599 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:39,600 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:09:39,600 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:09:39,600 INFO L87 Difference]: Start difference. First operand 1790 states and 2655 transitions. cyclomatic complexity: 866 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:39,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:39,705 INFO L93 Difference]: Finished difference Result 1790 states and 2654 transitions. [2021-11-13 18:09:39,706 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:09:39,707 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2654 transitions. [2021-11-13 18:09:39,727 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:39,745 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2654 transitions. [2021-11-13 18:09:39,746 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-13 18:09:39,748 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-13 18:09:39,749 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2654 transitions. [2021-11-13 18:09:39,753 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:39,753 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2654 transitions. [2021-11-13 18:09:39,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2654 transitions. [2021-11-13 18:09:39,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-13 18:09:39,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.48268156424581) internal successors, (2654), 1789 states have internal predecessors, (2654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:39,804 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2654 transitions. [2021-11-13 18:09:39,804 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2654 transitions. [2021-11-13 18:09:39,804 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2654 transitions. [2021-11-13 18:09:39,805 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-13 18:09:39,805 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2654 transitions. [2021-11-13 18:09:39,819 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:39,819 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:39,819 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:39,828 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:39,828 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:39,831 INFO L791 eck$LassoCheckResult]: Stem: 8034#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 8035#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 7458#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7428#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7429#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 8690#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7737#L858-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7190#L863-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7191#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8462#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8601#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8967#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8968#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7947#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7948#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8488#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8408#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8409#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8561#L1206 assume !(0 == ~M_E~0); 7926#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7927#L1211-1 assume !(0 == ~T2_E~0); 8820#L1216-1 assume !(0 == ~T3_E~0); 7719#L1221-1 assume !(0 == ~T4_E~0); 7720#L1226-1 assume !(0 == ~T5_E~0); 7382#L1231-1 assume !(0 == ~T6_E~0); 7383#L1236-1 assume !(0 == ~T7_E~0); 8851#L1241-1 assume !(0 == ~T8_E~0); 7781#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7782#L1251-1 assume !(0 == ~T10_E~0); 8002#L1256-1 assume !(0 == ~T11_E~0); 7202#L1261-1 assume !(0 == ~T12_E~0); 7203#L1266-1 assume !(0 == ~E_M~0); 8954#L1271-1 assume !(0 == ~E_1~0); 8589#L1276-1 assume !(0 == ~E_2~0); 8590#L1281-1 assume !(0 == ~E_3~0); 8515#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 7623#L1291-1 assume !(0 == ~E_5~0); 7624#L1296-1 assume !(0 == ~E_6~0); 8330#L1301-1 assume !(0 == ~E_7~0); 8331#L1306-1 assume !(0 == ~E_8~0); 8763#L1311-1 assume !(0 == ~E_9~0); 7584#L1316-1 assume !(0 == ~E_10~0); 7585#L1321-1 assume !(0 == ~E_11~0); 8347#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 7448#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7449#L598 assume 1 == ~m_pc~0; 7508#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7509#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8833#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8925#L1497 assume !(0 != activate_threads_~tmp~1#1); 8926#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8882#L617 assume !(1 == ~t1_pc~0); 7804#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7805#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7664#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7665#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8425#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8426#L636 assume 1 == ~t2_pc~0; 7773#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7774#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7604#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7605#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 8461#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8124#L655 assume !(1 == ~t3_pc~0); 8125#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8838#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7478#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7479#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 8955#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8956#L674 assume 1 == ~t4_pc~0; 7298#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7299#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8596#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7606#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 7607#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8121#L693 assume !(1 == ~t5_pc~0); 8284#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7928#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7929#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8765#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 8014#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7951#L712 assume 1 == ~t6_pc~0; 7952#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8379#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8380#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8666#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 8477#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8475#L731 assume 1 == ~t7_pc~0; 7452#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7453#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7647#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8584#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 8703#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7562#L750 assume !(1 == ~t8_pc~0); 7233#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7232#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7748#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8778#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7885#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7886#L769 assume 1 == ~t9_pc~0; 8421#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7406#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7407#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8190#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 8642#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8723#L788 assume !(1 == ~t10_pc~0); 8298#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8299#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8530#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8531#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 7558#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7559#L807 assume 1 == ~t11_pc~0; 8732#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8310#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8463#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 8874#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 8979#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8822#L826 assume !(1 == ~t12_pc~0); 7954#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 7955#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8483#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 8914#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 8114#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8023#L1344 assume !(1 == ~M_E~0); 8024#L1344-2 assume !(1 == ~T1_E~0); 8165#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8337#L1354-1 assume !(1 == ~T3_E~0); 8338#L1359-1 assume !(1 == ~T4_E~0); 8712#L1364-1 assume !(1 == ~T5_E~0); 7666#L1369-1 assume !(1 == ~T6_E~0); 7667#L1374-1 assume !(1 == ~T7_E~0); 8343#L1379-1 assume !(1 == ~T8_E~0); 8344#L1384-1 assume !(1 == ~T9_E~0); 8407#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8853#L1394-1 assume !(1 == ~T11_E~0); 8854#L1399-1 assume !(1 == ~T12_E~0); 8933#L1404-1 assume !(1 == ~E_M~0); 7785#L1409-1 assume !(1 == ~E_1~0); 7786#L1414-1 assume !(1 == ~E_2~0); 8623#L1419-1 assume !(1 == ~E_3~0); 7419#L1424-1 assume !(1 == ~E_4~0); 7420#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 8354#L1434-1 assume !(1 == ~E_6~0); 8872#L1439-1 assume !(1 == ~E_7~0); 7474#L1444-1 assume !(1 == ~E_8~0); 7475#L1449-1 assume !(1 == ~E_9~0); 7890#L1454-1 assume !(1 == ~E_10~0); 7891#L1459-1 assume !(1 == ~E_11~0); 8441#L1464-1 assume !(1 == ~E_12~0); 8442#L1469-1 assume { :end_inline_reset_delta_events } true; 8489#L1815-2 [2021-11-13 18:09:39,832 INFO L793 eck$LassoCheckResult]: Loop: 8489#L1815-2 assume !false; 8643#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8312#L1181 assume !false; 8383#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8335#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7193#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7922#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 8473#L1008 assume !(0 != eval_~tmp~0#1); 8474#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7412#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7413#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8973#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8440#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7546#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7547#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8137#L1226-3 assume !(0 == ~T5_E~0); 7610#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7611#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7923#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8910#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8813#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8549#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7568#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 7569#L1266-3 assume !(0 == ~E_M~0); 7608#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7609#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8081#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8082#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8619#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8620#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8962#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8930#L1306-3 assume !(0 == ~E_8~0); 8206#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7492#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7493#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7570#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 8305#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8630#L598-42 assume !(1 == ~m_pc~0); 8631#L598-44 is_master_triggered_~__retres1~0#1 := 0; 8745#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7648#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7649#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 8931#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8361#L617-42 assume 1 == ~t1_pc~0; 8133#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7998#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7999#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8413#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7713#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7714#L636-42 assume !(1 == ~t2_pc~0); 8177#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 8178#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8528#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8529#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8708#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8570#L655-42 assume !(1 == ~t3_pc~0); 8150#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 8151#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7783#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7784#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8837#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8782#L674-42 assume !(1 == ~t4_pc~0); 8556#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 8478#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7367#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7368#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8282#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8283#L693-42 assume 1 == ~t5_pc~0; 8538#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8539#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8599#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8594#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8595#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7897#L712-42 assume !(1 == ~t6_pc~0); 7898#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 8224#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8432#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8433#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8006#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8007#L731-42 assume !(1 == ~t7_pc~0); 7705#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 7706#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8773#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7914#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7915#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7618#L750-42 assume 1 == ~t8_pc~0; 7619#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8193#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8616#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7511#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7512#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8281#L769-42 assume 1 == ~t9_pc~0; 8103#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8104#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8787#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8852#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 7715#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7716#L788-42 assume 1 == ~t10_pc~0; 8289#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8503#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8233#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8234#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8971#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8949#L807-42 assume !(1 == ~t11_pc~0); 7319#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 7320#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7459#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 7460#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7461#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7710#L826-42 assume !(1 == ~t12_pc~0); 7712#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 7903#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8695#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 7700#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 7701#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8552#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8553#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8479#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7860#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7861#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8493#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8951#L1369-3 assume !(1 == ~T6_E~0); 8871#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7625#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7626#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7858#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7859#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8157#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8880#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8843#L1409-3 assume !(1 == ~E_1~0); 8844#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8909#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8689#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7526#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7527#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8492#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7466#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7467#L1449-3 assume !(1 == ~E_9~0); 7576#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8486#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8487#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8868#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8366#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7365#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7366#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 7982#L1834 assume !(0 == start_simulation_~tmp~3#1); 8602#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8625#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 8059#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 8238#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 8450#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8858#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7351#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 7352#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 8489#L1815-2 [2021-11-13 18:09:39,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:39,836 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2021-11-13 18:09:39,836 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:39,836 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [813261532] [2021-11-13 18:09:39,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:39,837 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:39,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:39,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:39,948 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:39,948 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [813261532] [2021-11-13 18:09:39,949 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [813261532] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:39,949 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:39,949 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:39,949 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [429100041] [2021-11-13 18:09:39,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:39,950 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:39,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:39,951 INFO L85 PathProgramCache]: Analyzing trace with hash 1198130711, now seen corresponding path program 1 times [2021-11-13 18:09:39,951 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:39,952 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [152511785] [2021-11-13 18:09:39,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:39,952 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:39,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:40,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:40,053 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:40,054 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [152511785] [2021-11-13 18:09:40,054 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [152511785] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:40,054 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:40,055 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:40,055 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1628549743] [2021-11-13 18:09:40,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:40,056 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:40,056 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:40,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:09:40,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:09:40,057 INFO L87 Difference]: Start difference. First operand 1790 states and 2654 transitions. cyclomatic complexity: 865 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:40,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:40,112 INFO L93 Difference]: Finished difference Result 1790 states and 2653 transitions. [2021-11-13 18:09:40,112 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:09:40,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2653 transitions. [2021-11-13 18:09:40,132 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:40,150 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2653 transitions. [2021-11-13 18:09:40,150 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-13 18:09:40,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-13 18:09:40,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2653 transitions. [2021-11-13 18:09:40,157 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:40,157 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2653 transitions. [2021-11-13 18:09:40,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2653 transitions. [2021-11-13 18:09:40,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-13 18:09:40,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.482122905027933) internal successors, (2653), 1789 states have internal predecessors, (2653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:40,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2653 transitions. [2021-11-13 18:09:40,261 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2653 transitions. [2021-11-13 18:09:40,261 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2653 transitions. [2021-11-13 18:09:40,261 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-13 18:09:40,261 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2653 transitions. [2021-11-13 18:09:40,277 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:40,278 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:40,278 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:40,281 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:40,281 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:40,282 INFO L791 eck$LassoCheckResult]: Stem: 11621#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11622#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11045#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11015#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11016#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 12277#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11324#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10777#L863-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10778#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12049#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12188#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12554#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12555#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11534#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11535#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12075#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 11995#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11996#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12148#L1206 assume !(0 == ~M_E~0); 11513#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11514#L1211-1 assume !(0 == ~T2_E~0); 12407#L1216-1 assume !(0 == ~T3_E~0); 11306#L1221-1 assume !(0 == ~T4_E~0); 11307#L1226-1 assume !(0 == ~T5_E~0); 10969#L1231-1 assume !(0 == ~T6_E~0); 10970#L1236-1 assume !(0 == ~T7_E~0); 12438#L1241-1 assume !(0 == ~T8_E~0); 11368#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11369#L1251-1 assume !(0 == ~T10_E~0); 11589#L1256-1 assume !(0 == ~T11_E~0); 10789#L1261-1 assume !(0 == ~T12_E~0); 10790#L1266-1 assume !(0 == ~E_M~0); 12541#L1271-1 assume !(0 == ~E_1~0); 12176#L1276-1 assume !(0 == ~E_2~0); 12177#L1281-1 assume !(0 == ~E_3~0); 12102#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 11210#L1291-1 assume !(0 == ~E_5~0); 11211#L1296-1 assume !(0 == ~E_6~0); 11917#L1301-1 assume !(0 == ~E_7~0); 11918#L1306-1 assume !(0 == ~E_8~0); 12350#L1311-1 assume !(0 == ~E_9~0); 11171#L1316-1 assume !(0 == ~E_10~0); 11172#L1321-1 assume !(0 == ~E_11~0); 11934#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 11035#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11036#L598 assume 1 == ~m_pc~0; 11095#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11096#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12420#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12512#L1497 assume !(0 != activate_threads_~tmp~1#1); 12513#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12469#L617 assume !(1 == ~t1_pc~0); 11391#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11392#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11251#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11252#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12012#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12013#L636 assume 1 == ~t2_pc~0; 11360#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11361#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11191#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11192#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 12048#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11711#L655 assume !(1 == ~t3_pc~0); 11712#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12425#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11065#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11066#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 12542#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12543#L674 assume 1 == ~t4_pc~0; 10885#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10886#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12183#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11193#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 11194#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11708#L693 assume !(1 == ~t5_pc~0); 11871#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11515#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11516#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12352#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 11601#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11538#L712 assume 1 == ~t6_pc~0; 11539#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11966#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11967#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12253#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 12064#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12062#L731 assume 1 == ~t7_pc~0; 11039#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11040#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11234#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12171#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 12290#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11149#L750 assume !(1 == ~t8_pc~0); 10820#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10819#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11335#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12365#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11472#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11473#L769 assume 1 == ~t9_pc~0; 12008#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10993#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10994#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11777#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 12229#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12310#L788 assume !(1 == ~t10_pc~0); 11885#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11886#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12117#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12118#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 11145#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 11146#L807 assume 1 == ~t11_pc~0; 12319#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11897#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12050#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 12461#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 12566#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12409#L826 assume !(1 == ~t12_pc~0); 11541#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11542#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12070#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 12501#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 11701#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11610#L1344 assume !(1 == ~M_E~0); 11611#L1344-2 assume !(1 == ~T1_E~0); 11752#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11924#L1354-1 assume !(1 == ~T3_E~0); 11925#L1359-1 assume !(1 == ~T4_E~0); 12299#L1364-1 assume !(1 == ~T5_E~0); 11253#L1369-1 assume !(1 == ~T6_E~0); 11254#L1374-1 assume !(1 == ~T7_E~0); 11930#L1379-1 assume !(1 == ~T8_E~0); 11931#L1384-1 assume !(1 == ~T9_E~0); 11994#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12440#L1394-1 assume !(1 == ~T11_E~0); 12441#L1399-1 assume !(1 == ~T12_E~0); 12520#L1404-1 assume !(1 == ~E_M~0); 11372#L1409-1 assume !(1 == ~E_1~0); 11373#L1414-1 assume !(1 == ~E_2~0); 12210#L1419-1 assume !(1 == ~E_3~0); 11006#L1424-1 assume !(1 == ~E_4~0); 11007#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 11941#L1434-1 assume !(1 == ~E_6~0); 12459#L1439-1 assume !(1 == ~E_7~0); 11061#L1444-1 assume !(1 == ~E_8~0); 11062#L1449-1 assume !(1 == ~E_9~0); 11477#L1454-1 assume !(1 == ~E_10~0); 11478#L1459-1 assume !(1 == ~E_11~0); 12028#L1464-1 assume !(1 == ~E_12~0); 12029#L1469-1 assume { :end_inline_reset_delta_events } true; 12076#L1815-2 [2021-11-13 18:09:40,283 INFO L793 eck$LassoCheckResult]: Loop: 12076#L1815-2 assume !false; 12230#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11899#L1181 assume !false; 11970#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11922#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10780#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11509#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 12060#L1008 assume !(0 != eval_~tmp~0#1); 12061#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10999#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11000#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12560#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12027#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11133#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11134#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11724#L1226-3 assume !(0 == ~T5_E~0); 11197#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11198#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11510#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12497#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12400#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12136#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11155#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11156#L1266-3 assume !(0 == ~E_M~0); 11195#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11196#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11668#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11669#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12206#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12207#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12549#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12517#L1306-3 assume !(0 == ~E_8~0); 11793#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11079#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11080#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11157#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11892#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12217#L598-42 assume !(1 == ~m_pc~0); 12218#L598-44 is_master_triggered_~__retres1~0#1 := 0; 12332#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11235#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11236#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 12518#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11948#L617-42 assume 1 == ~t1_pc~0; 11720#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11585#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11586#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12000#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11300#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11301#L636-42 assume !(1 == ~t2_pc~0); 11764#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 11765#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12115#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12116#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12295#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12157#L655-42 assume !(1 == ~t3_pc~0); 11737#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 11738#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11370#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11371#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12424#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12369#L674-42 assume 1 == ~t4_pc~0; 12370#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12065#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10954#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10955#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11869#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11870#L693-42 assume 1 == ~t5_pc~0; 12125#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12126#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12186#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12181#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12182#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11484#L712-42 assume !(1 == ~t6_pc~0); 11485#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 11811#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12019#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12020#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11593#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11594#L731-42 assume 1 == ~t7_pc~0; 11457#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11293#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12360#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11501#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11502#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11205#L750-42 assume 1 == ~t8_pc~0; 11206#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11780#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12203#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11098#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11099#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11868#L769-42 assume 1 == ~t9_pc~0; 11690#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11691#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12374#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12439#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 11302#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11303#L788-42 assume 1 == ~t10_pc~0; 11876#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12090#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11820#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 11821#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12558#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12536#L807-42 assume 1 == ~t11_pc~0; 12225#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10907#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11046#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 11047#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11048#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11297#L826-42 assume 1 == ~t12_pc~0; 11298#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11490#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12282#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 11287#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 11288#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12139#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12140#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12066#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11447#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11448#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12080#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12538#L1369-3 assume !(1 == ~T6_E~0); 12458#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11212#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11213#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11445#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11446#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11744#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12467#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12430#L1409-3 assume !(1 == ~E_1~0); 12431#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12496#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12276#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11113#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11114#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12079#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11053#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11054#L1449-3 assume !(1 == ~E_9~0); 11163#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12073#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12074#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12455#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11953#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10952#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10953#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 11569#L1834 assume !(0 == start_simulation_~tmp~3#1); 12189#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 12212#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11646#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11825#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 12037#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12445#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10938#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 10939#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 12076#L1815-2 [2021-11-13 18:09:40,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:40,285 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2021-11-13 18:09:40,286 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:40,287 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1647735678] [2021-11-13 18:09:40,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:40,289 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:40,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:40,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:40,366 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:40,366 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1647735678] [2021-11-13 18:09:40,368 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1647735678] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:40,368 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:40,368 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:40,369 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1677911470] [2021-11-13 18:09:40,369 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:40,369 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:40,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:40,375 INFO L85 PathProgramCache]: Analyzing trace with hash -1380802157, now seen corresponding path program 1 times [2021-11-13 18:09:40,375 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:40,380 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1121703440] [2021-11-13 18:09:40,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:40,381 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:40,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:40,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:40,480 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:40,480 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1121703440] [2021-11-13 18:09:40,487 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1121703440] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:40,487 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:40,487 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:40,488 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1121409767] [2021-11-13 18:09:40,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:40,488 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:40,488 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:40,490 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:09:40,490 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:09:40,492 INFO L87 Difference]: Start difference. First operand 1790 states and 2653 transitions. cyclomatic complexity: 864 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:40,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:40,546 INFO L93 Difference]: Finished difference Result 1790 states and 2652 transitions. [2021-11-13 18:09:40,547 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:09:40,548 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2652 transitions. [2021-11-13 18:09:40,567 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:40,583 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2652 transitions. [2021-11-13 18:09:40,583 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-13 18:09:40,586 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-13 18:09:40,586 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2652 transitions. [2021-11-13 18:09:40,589 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:40,590 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2652 transitions. [2021-11-13 18:09:40,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2652 transitions. [2021-11-13 18:09:40,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-13 18:09:40,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.481564245810056) internal successors, (2652), 1789 states have internal predecessors, (2652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:40,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2652 transitions. [2021-11-13 18:09:40,643 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2652 transitions. [2021-11-13 18:09:40,644 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2652 transitions. [2021-11-13 18:09:40,644 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-13 18:09:40,644 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2652 transitions. [2021-11-13 18:09:40,660 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:40,660 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:40,660 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:40,663 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:40,664 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:40,664 INFO L791 eck$LassoCheckResult]: Stem: 15208#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 15209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 14632#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14602#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14603#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 15864#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14911#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14364#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14365#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 15636#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15775#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16141#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16142#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15121#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15122#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15662#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15582#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 15583#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15735#L1206 assume !(0 == ~M_E~0); 15100#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15101#L1211-1 assume !(0 == ~T2_E~0); 15994#L1216-1 assume !(0 == ~T3_E~0); 14893#L1221-1 assume !(0 == ~T4_E~0); 14894#L1226-1 assume !(0 == ~T5_E~0); 14556#L1231-1 assume !(0 == ~T6_E~0); 14557#L1236-1 assume !(0 == ~T7_E~0); 16025#L1241-1 assume !(0 == ~T8_E~0); 14955#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14956#L1251-1 assume !(0 == ~T10_E~0); 15176#L1256-1 assume !(0 == ~T11_E~0); 14376#L1261-1 assume !(0 == ~T12_E~0); 14377#L1266-1 assume !(0 == ~E_M~0); 16128#L1271-1 assume !(0 == ~E_1~0); 15763#L1276-1 assume !(0 == ~E_2~0); 15764#L1281-1 assume !(0 == ~E_3~0); 15689#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 14797#L1291-1 assume !(0 == ~E_5~0); 14798#L1296-1 assume !(0 == ~E_6~0); 15504#L1301-1 assume !(0 == ~E_7~0); 15505#L1306-1 assume !(0 == ~E_8~0); 15937#L1311-1 assume !(0 == ~E_9~0); 14758#L1316-1 assume !(0 == ~E_10~0); 14759#L1321-1 assume !(0 == ~E_11~0); 15521#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 14622#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14623#L598 assume 1 == ~m_pc~0; 14682#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14683#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16007#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16099#L1497 assume !(0 != activate_threads_~tmp~1#1); 16100#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16056#L617 assume !(1 == ~t1_pc~0); 14978#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14979#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14838#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14839#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15599#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15600#L636 assume 1 == ~t2_pc~0; 14947#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14948#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14778#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14779#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 15635#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15298#L655 assume !(1 == ~t3_pc~0); 15299#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16012#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14652#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14653#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 16129#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16130#L674 assume 1 == ~t4_pc~0; 14472#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14473#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15770#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14780#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 14781#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15295#L693 assume !(1 == ~t5_pc~0); 15458#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15102#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15103#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15939#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 15188#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15125#L712 assume 1 == ~t6_pc~0; 15126#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15553#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15554#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 15840#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 15651#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15649#L731 assume 1 == ~t7_pc~0; 14626#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14627#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14821#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15758#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 15877#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14736#L750 assume !(1 == ~t8_pc~0); 14407#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14406#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14922#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15952#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15059#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15060#L769 assume 1 == ~t9_pc~0; 15595#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14580#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14581#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15364#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 15816#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15897#L788 assume !(1 == ~t10_pc~0); 15472#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 15473#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15704#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 15705#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 14732#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14733#L807 assume 1 == ~t11_pc~0; 15906#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15484#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15637#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 16048#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 16153#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15996#L826 assume !(1 == ~t12_pc~0); 15128#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 15129#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15657#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 16088#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 15288#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15197#L1344 assume !(1 == ~M_E~0); 15198#L1344-2 assume !(1 == ~T1_E~0); 15339#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15511#L1354-1 assume !(1 == ~T3_E~0); 15512#L1359-1 assume !(1 == ~T4_E~0); 15886#L1364-1 assume !(1 == ~T5_E~0); 14840#L1369-1 assume !(1 == ~T6_E~0); 14841#L1374-1 assume !(1 == ~T7_E~0); 15517#L1379-1 assume !(1 == ~T8_E~0); 15518#L1384-1 assume !(1 == ~T9_E~0); 15581#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16027#L1394-1 assume !(1 == ~T11_E~0); 16028#L1399-1 assume !(1 == ~T12_E~0); 16107#L1404-1 assume !(1 == ~E_M~0); 14959#L1409-1 assume !(1 == ~E_1~0); 14960#L1414-1 assume !(1 == ~E_2~0); 15797#L1419-1 assume !(1 == ~E_3~0); 14593#L1424-1 assume !(1 == ~E_4~0); 14594#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 15528#L1434-1 assume !(1 == ~E_6~0); 16046#L1439-1 assume !(1 == ~E_7~0); 14648#L1444-1 assume !(1 == ~E_8~0); 14649#L1449-1 assume !(1 == ~E_9~0); 15064#L1454-1 assume !(1 == ~E_10~0); 15065#L1459-1 assume !(1 == ~E_11~0); 15615#L1464-1 assume !(1 == ~E_12~0); 15616#L1469-1 assume { :end_inline_reset_delta_events } true; 15663#L1815-2 [2021-11-13 18:09:40,665 INFO L793 eck$LassoCheckResult]: Loop: 15663#L1815-2 assume !false; 15817#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15486#L1181 assume !false; 15557#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15509#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14367#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15096#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 15647#L1008 assume !(0 != eval_~tmp~0#1); 15648#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14586#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14587#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16147#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15614#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14720#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14721#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15311#L1226-3 assume !(0 == ~T5_E~0); 14784#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14785#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15097#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16084#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15987#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15723#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14742#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14743#L1266-3 assume !(0 == ~E_M~0); 14782#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14783#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15255#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15256#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15793#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15794#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16136#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16104#L1306-3 assume !(0 == ~E_8~0); 15380#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14666#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14667#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14744#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 15479#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15804#L598-42 assume !(1 == ~m_pc~0); 15805#L598-44 is_master_triggered_~__retres1~0#1 := 0; 15919#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14822#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14823#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 16105#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15535#L617-42 assume 1 == ~t1_pc~0; 15307#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15172#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15173#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15587#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14887#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14888#L636-42 assume !(1 == ~t2_pc~0); 15351#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 15352#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15702#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15703#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15882#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15744#L655-42 assume 1 == ~t3_pc~0; 15745#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15325#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14957#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14958#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16011#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15956#L674-42 assume !(1 == ~t4_pc~0); 15730#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 15652#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14541#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14542#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15456#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15457#L693-42 assume 1 == ~t5_pc~0; 15712#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15713#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15773#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15768#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15769#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15071#L712-42 assume !(1 == ~t6_pc~0); 15072#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 15398#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15606#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 15607#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15180#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15181#L731-42 assume 1 == ~t7_pc~0; 15044#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14880#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15947#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15088#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15089#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14792#L750-42 assume 1 == ~t8_pc~0; 14793#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15367#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15790#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14685#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14686#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15455#L769-42 assume 1 == ~t9_pc~0; 15277#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15278#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15961#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16026#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 14889#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14890#L788-42 assume 1 == ~t10_pc~0; 15463#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15677#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15407#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 15408#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16145#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16123#L807-42 assume 1 == ~t11_pc~0; 15812#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14494#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14633#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 14634#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14635#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 14884#L826-42 assume 1 == ~t12_pc~0; 14885#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 15077#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15869#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 14874#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 14875#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15726#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15727#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15653#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15034#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15035#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15667#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16125#L1369-3 assume !(1 == ~T6_E~0); 16045#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14799#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14800#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15032#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15033#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15331#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16054#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16017#L1409-3 assume !(1 == ~E_1~0); 16018#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16083#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15863#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14700#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14701#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15666#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14640#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14641#L1449-3 assume !(1 == ~E_9~0); 14750#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15660#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 15661#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16042#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15540#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14539#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14540#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 15156#L1834 assume !(0 == start_simulation_~tmp~3#1); 15776#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15799#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 15233#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15412#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 15624#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16032#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14525#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 14526#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 15663#L1815-2 [2021-11-13 18:09:40,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:40,666 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2021-11-13 18:09:40,666 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:40,667 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889848190] [2021-11-13 18:09:40,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:40,667 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:40,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:40,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:40,732 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:40,732 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [889848190] [2021-11-13 18:09:40,732 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [889848190] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:40,733 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:40,733 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:40,733 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743920285] [2021-11-13 18:09:40,733 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:40,734 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:40,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:40,735 INFO L85 PathProgramCache]: Analyzing trace with hash 1846949459, now seen corresponding path program 1 times [2021-11-13 18:09:40,735 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:40,735 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1001096751] [2021-11-13 18:09:40,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:40,736 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:40,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:40,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:40,803 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:40,803 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1001096751] [2021-11-13 18:09:40,804 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1001096751] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:40,804 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:40,804 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:40,804 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [541083249] [2021-11-13 18:09:40,804 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:40,805 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:40,805 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:40,805 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:09:40,806 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:09:40,806 INFO L87 Difference]: Start difference. First operand 1790 states and 2652 transitions. cyclomatic complexity: 863 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:40,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:40,859 INFO L93 Difference]: Finished difference Result 1790 states and 2651 transitions. [2021-11-13 18:09:40,860 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:09:40,863 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2651 transitions. [2021-11-13 18:09:40,886 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:40,905 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2651 transitions. [2021-11-13 18:09:40,905 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-13 18:09:40,907 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-13 18:09:40,908 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2651 transitions. [2021-11-13 18:09:40,912 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:40,912 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2651 transitions. [2021-11-13 18:09:40,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2651 transitions. [2021-11-13 18:09:40,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-13 18:09:40,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4810055865921787) internal successors, (2651), 1789 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:40,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2651 transitions. [2021-11-13 18:09:40,968 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2651 transitions. [2021-11-13 18:09:40,968 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2651 transitions. [2021-11-13 18:09:40,968 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-13 18:09:40,968 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2651 transitions. [2021-11-13 18:09:40,981 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:40,981 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:40,981 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:40,985 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:40,985 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:40,986 INFO L791 eck$LassoCheckResult]: Stem: 18797#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18798#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 18221#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18194#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18195#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 19451#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18498#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17951#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17952#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19223#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 19362#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19728#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19729#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18710#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18711#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19249#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19169#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 19170#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19322#L1206 assume !(0 == ~M_E~0); 18687#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18688#L1211-1 assume !(0 == ~T2_E~0); 19581#L1216-1 assume !(0 == ~T3_E~0); 18480#L1221-1 assume !(0 == ~T4_E~0); 18481#L1226-1 assume !(0 == ~T5_E~0); 18145#L1231-1 assume !(0 == ~T6_E~0); 18146#L1236-1 assume !(0 == ~T7_E~0); 19612#L1241-1 assume !(0 == ~T8_E~0); 18542#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18543#L1251-1 assume !(0 == ~T10_E~0); 18763#L1256-1 assume !(0 == ~T11_E~0); 17963#L1261-1 assume !(0 == ~T12_E~0); 17964#L1266-1 assume !(0 == ~E_M~0); 19715#L1271-1 assume !(0 == ~E_1~0); 19350#L1276-1 assume !(0 == ~E_2~0); 19351#L1281-1 assume !(0 == ~E_3~0); 19278#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 18384#L1291-1 assume !(0 == ~E_5~0); 18385#L1296-1 assume !(0 == ~E_6~0); 19091#L1301-1 assume !(0 == ~E_7~0); 19092#L1306-1 assume !(0 == ~E_8~0); 19524#L1311-1 assume !(0 == ~E_9~0); 18345#L1316-1 assume !(0 == ~E_10~0); 18346#L1321-1 assume !(0 == ~E_11~0); 19108#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 18211#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18212#L598 assume 1 == ~m_pc~0; 18269#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18270#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19594#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19686#L1497 assume !(0 != activate_threads_~tmp~1#1); 19687#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19643#L617 assume !(1 == ~t1_pc~0); 18565#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18566#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18425#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18426#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19186#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19187#L636 assume 1 == ~t2_pc~0; 18534#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18535#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18365#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18366#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 19222#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18886#L655 assume !(1 == ~t3_pc~0); 18887#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19599#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18239#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18240#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 19716#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19717#L674 assume 1 == ~t4_pc~0; 18059#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18060#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19357#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18369#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 18370#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18882#L693 assume !(1 == ~t5_pc~0); 19045#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 18692#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18693#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19526#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 18775#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18712#L712 assume 1 == ~t6_pc~0; 18713#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19140#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19141#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19427#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 19238#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19236#L731 assume 1 == ~t7_pc~0; 18213#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18214#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18410#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19346#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 19464#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18323#L750 assume !(1 == ~t8_pc~0); 17994#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17993#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18509#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19539#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18646#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18647#L769 assume 1 == ~t9_pc~0; 19184#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18167#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18168#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18951#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 19403#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19484#L788 assume !(1 == ~t10_pc~0); 19059#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19060#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19293#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 19294#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 18321#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18322#L807 assume 1 == ~t11_pc~0; 19493#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19071#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19224#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 19635#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 19740#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19583#L826 assume !(1 == ~t12_pc~0); 18717#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 18718#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19244#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 19675#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 18875#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18784#L1344 assume !(1 == ~M_E~0); 18785#L1344-2 assume !(1 == ~T1_E~0); 18926#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19099#L1354-1 assume !(1 == ~T3_E~0); 19100#L1359-1 assume !(1 == ~T4_E~0); 19473#L1364-1 assume !(1 == ~T5_E~0); 18427#L1369-1 assume !(1 == ~T6_E~0); 18428#L1374-1 assume !(1 == ~T7_E~0); 19106#L1379-1 assume !(1 == ~T8_E~0); 19107#L1384-1 assume !(1 == ~T9_E~0); 19168#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19614#L1394-1 assume !(1 == ~T11_E~0); 19615#L1399-1 assume !(1 == ~T12_E~0); 19694#L1404-1 assume !(1 == ~E_M~0); 18546#L1409-1 assume !(1 == ~E_1~0); 18547#L1414-1 assume !(1 == ~E_2~0); 19384#L1419-1 assume !(1 == ~E_3~0); 18180#L1424-1 assume !(1 == ~E_4~0); 18181#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 19118#L1434-1 assume !(1 == ~E_6~0); 19633#L1439-1 assume !(1 == ~E_7~0); 18235#L1444-1 assume !(1 == ~E_8~0); 18236#L1449-1 assume !(1 == ~E_9~0); 18651#L1454-1 assume !(1 == ~E_10~0); 18652#L1459-1 assume !(1 == ~E_11~0); 19202#L1464-1 assume !(1 == ~E_12~0); 19203#L1469-1 assume { :end_inline_reset_delta_events } true; 19250#L1815-2 [2021-11-13 18:09:40,986 INFO L793 eck$LassoCheckResult]: Loop: 19250#L1815-2 assume !false; 19404#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19073#L1181 assume !false; 19144#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19096#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17954#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18684#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 19234#L1008 assume !(0 != eval_~tmp~0#1); 19235#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18175#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18176#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19734#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19201#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18307#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18308#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18898#L1226-3 assume !(0 == ~T5_E~0); 18371#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18372#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18683#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19671#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19574#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19310#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18329#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18330#L1266-3 assume !(0 == ~E_M~0); 18367#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18368#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18842#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18843#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19380#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19381#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19723#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19691#L1306-3 assume !(0 == ~E_8~0); 18967#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18253#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18254#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18331#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 19065#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19391#L598-42 assume !(1 == ~m_pc~0); 19392#L598-44 is_master_triggered_~__retres1~0#1 := 0; 19506#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18408#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18409#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 19692#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19122#L617-42 assume 1 == ~t1_pc~0; 18894#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18759#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18760#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19174#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18474#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18475#L636-42 assume !(1 == ~t2_pc~0); 18938#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 18939#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19289#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19290#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19469#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19331#L655-42 assume 1 == ~t3_pc~0; 19332#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18912#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18544#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18545#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19598#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19543#L674-42 assume !(1 == ~t4_pc~0); 19317#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 19239#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18128#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18129#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19043#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19044#L693-42 assume 1 == ~t5_pc~0; 19299#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19300#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19360#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19355#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19356#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18658#L712-42 assume !(1 == ~t6_pc~0); 18659#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 18985#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19193#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19194#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18767#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18768#L731-42 assume !(1 == ~t7_pc~0); 18466#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 18467#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19534#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18675#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18676#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18379#L750-42 assume 1 == ~t8_pc~0; 18380#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18954#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19377#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18272#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18273#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19042#L769-42 assume 1 == ~t9_pc~0; 18864#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18865#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19548#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19613#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 18476#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18477#L788-42 assume 1 == ~t10_pc~0; 19050#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19264#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18994#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 18995#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19732#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19710#L807-42 assume !(1 == ~t11_pc~0); 18080#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 18081#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18219#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 18220#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18222#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18471#L826-42 assume 1 == ~t12_pc~0; 18472#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 18664#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19456#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 18461#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18462#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19313#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19314#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19240#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18621#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18622#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19254#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19712#L1369-3 assume !(1 == ~T6_E~0); 19632#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18386#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18387#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18619#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18620#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18918#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19641#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19604#L1409-3 assume !(1 == ~E_1~0); 19605#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19670#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19450#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18287#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18288#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19253#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18227#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18228#L1449-3 assume !(1 == ~E_9~0); 18337#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19247#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 19248#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 19629#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19127#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18126#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18127#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 18743#L1834 assume !(0 == start_simulation_~tmp~3#1); 19363#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19386#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18820#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18999#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 19211#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19619#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18112#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 18113#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 19250#L1815-2 [2021-11-13 18:09:40,987 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:40,987 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2021-11-13 18:09:40,987 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:40,988 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [344039338] [2021-11-13 18:09:40,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:40,988 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:41,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:41,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:41,036 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:41,036 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [344039338] [2021-11-13 18:09:41,036 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [344039338] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:41,036 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:41,036 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:41,037 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1184828065] [2021-11-13 18:09:41,037 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:41,037 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:41,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:41,038 INFO L85 PathProgramCache]: Analyzing trace with hash -112792235, now seen corresponding path program 1 times [2021-11-13 18:09:41,038 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:41,047 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [659706033] [2021-11-13 18:09:41,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:41,049 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:41,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:41,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:41,107 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:41,107 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [659706033] [2021-11-13 18:09:41,107 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [659706033] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:41,107 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:41,107 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:41,109 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1034501769] [2021-11-13 18:09:41,109 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:41,110 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:41,110 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:41,111 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:09:41,112 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:09:41,112 INFO L87 Difference]: Start difference. First operand 1790 states and 2651 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:41,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:41,196 INFO L93 Difference]: Finished difference Result 1790 states and 2650 transitions. [2021-11-13 18:09:41,199 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:09:41,200 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2650 transitions. [2021-11-13 18:09:41,221 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:41,239 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2650 transitions. [2021-11-13 18:09:41,239 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-13 18:09:41,241 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-13 18:09:41,242 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2650 transitions. [2021-11-13 18:09:41,246 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:41,246 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2650 transitions. [2021-11-13 18:09:41,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2650 transitions. [2021-11-13 18:09:41,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-13 18:09:41,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4804469273743017) internal successors, (2650), 1789 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:41,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2650 transitions. [2021-11-13 18:09:41,308 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2650 transitions. [2021-11-13 18:09:41,308 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2650 transitions. [2021-11-13 18:09:41,308 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-13 18:09:41,309 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2650 transitions. [2021-11-13 18:09:41,322 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:41,322 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:41,322 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:41,326 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:41,326 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:41,327 INFO L791 eck$LassoCheckResult]: Stem: 22382#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 22383#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 21808#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21778#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21779#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 23038#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22085#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21538#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21539#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22810#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22949#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 23315#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23316#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22297#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22298#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22836#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22756#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22757#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22909#L1206 assume !(0 == ~M_E~0); 22274#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22275#L1211-1 assume !(0 == ~T2_E~0); 23168#L1216-1 assume !(0 == ~T3_E~0); 22067#L1221-1 assume !(0 == ~T4_E~0); 22068#L1226-1 assume !(0 == ~T5_E~0); 21732#L1231-1 assume !(0 == ~T6_E~0); 21733#L1236-1 assume !(0 == ~T7_E~0); 23199#L1241-1 assume !(0 == ~T8_E~0); 22129#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22130#L1251-1 assume !(0 == ~T10_E~0); 22350#L1256-1 assume !(0 == ~T11_E~0); 21550#L1261-1 assume !(0 == ~T12_E~0); 21551#L1266-1 assume !(0 == ~E_M~0); 23302#L1271-1 assume !(0 == ~E_1~0); 22937#L1276-1 assume !(0 == ~E_2~0); 22938#L1281-1 assume !(0 == ~E_3~0); 22865#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 21971#L1291-1 assume !(0 == ~E_5~0); 21972#L1296-1 assume !(0 == ~E_6~0); 22678#L1301-1 assume !(0 == ~E_7~0); 22679#L1306-1 assume !(0 == ~E_8~0); 23111#L1311-1 assume !(0 == ~E_9~0); 21932#L1316-1 assume !(0 == ~E_10~0); 21933#L1321-1 assume !(0 == ~E_11~0); 22695#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 21798#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21799#L598 assume 1 == ~m_pc~0; 21856#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21857#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23181#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23273#L1497 assume !(0 != activate_threads_~tmp~1#1); 23274#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23230#L617 assume !(1 == ~t1_pc~0); 22152#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22153#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22012#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22013#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22773#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22774#L636 assume 1 == ~t2_pc~0; 22121#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22122#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21952#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21953#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 22809#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22472#L655 assume !(1 == ~t3_pc~0); 22473#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23186#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21826#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21827#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 23303#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23304#L674 assume 1 == ~t4_pc~0; 21646#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21647#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22944#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21954#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 21955#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22469#L693 assume !(1 == ~t5_pc~0); 22632#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 22279#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22280#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23113#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 22362#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22299#L712 assume 1 == ~t6_pc~0; 22300#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22727#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22728#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23014#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 22825#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22823#L731 assume 1 == ~t7_pc~0; 21800#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21801#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21995#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22933#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 23051#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21910#L750 assume !(1 == ~t8_pc~0); 21581#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 21580#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22096#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23126#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22233#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22234#L769 assume 1 == ~t9_pc~0; 22771#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21754#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21755#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22538#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 22990#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23071#L788 assume !(1 == ~t10_pc~0); 22646#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22647#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22879#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22880#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 21906#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21907#L807 assume 1 == ~t11_pc~0; 23080#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22658#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22811#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 23222#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 23327#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 23170#L826 assume !(1 == ~t12_pc~0); 22304#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22305#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22831#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 23262#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 22462#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22371#L1344 assume !(1 == ~M_E~0); 22372#L1344-2 assume !(1 == ~T1_E~0); 22513#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22686#L1354-1 assume !(1 == ~T3_E~0); 22687#L1359-1 assume !(1 == ~T4_E~0); 23060#L1364-1 assume !(1 == ~T5_E~0); 22014#L1369-1 assume !(1 == ~T6_E~0); 22015#L1374-1 assume !(1 == ~T7_E~0); 22693#L1379-1 assume !(1 == ~T8_E~0); 22694#L1384-1 assume !(1 == ~T9_E~0); 22755#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 23201#L1394-1 assume !(1 == ~T11_E~0); 23202#L1399-1 assume !(1 == ~T12_E~0); 23281#L1404-1 assume !(1 == ~E_M~0); 22133#L1409-1 assume !(1 == ~E_1~0); 22134#L1414-1 assume !(1 == ~E_2~0); 22971#L1419-1 assume !(1 == ~E_3~0); 21767#L1424-1 assume !(1 == ~E_4~0); 21768#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22705#L1434-1 assume !(1 == ~E_6~0); 23220#L1439-1 assume !(1 == ~E_7~0); 21822#L1444-1 assume !(1 == ~E_8~0); 21823#L1449-1 assume !(1 == ~E_9~0); 22238#L1454-1 assume !(1 == ~E_10~0); 22239#L1459-1 assume !(1 == ~E_11~0); 22789#L1464-1 assume !(1 == ~E_12~0); 22790#L1469-1 assume { :end_inline_reset_delta_events } true; 22837#L1815-2 [2021-11-13 18:09:41,327 INFO L793 eck$LassoCheckResult]: Loop: 22837#L1815-2 assume !false; 22991#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22660#L1181 assume !false; 22731#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22683#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21541#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22270#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 22821#L1008 assume !(0 != eval_~tmp~0#1); 22822#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21762#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21763#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23321#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22788#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21894#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21895#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22485#L1226-3 assume !(0 == ~T5_E~0); 21958#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21959#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22271#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23259#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23161#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22897#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21918#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21919#L1266-3 assume !(0 == ~E_M~0); 21956#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21957#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22429#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22430#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22967#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22968#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23310#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23278#L1306-3 assume !(0 == ~E_8~0); 22554#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21840#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21841#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 21920#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22653#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22978#L598-42 assume !(1 == ~m_pc~0); 22979#L598-44 is_master_triggered_~__retres1~0#1 := 0; 23093#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21996#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21997#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 23279#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22709#L617-42 assume 1 == ~t1_pc~0; 22482#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22346#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22347#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22761#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22061#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22062#L636-42 assume !(1 == ~t2_pc~0); 22524#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 22525#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22875#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22876#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23056#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22915#L655-42 assume !(1 == ~t3_pc~0); 22497#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 22498#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22131#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22132#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23185#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23130#L674-42 assume !(1 == ~t4_pc~0); 22904#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 22826#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21715#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21716#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22630#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22631#L693-42 assume 1 == ~t5_pc~0; 22886#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22887#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22946#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22941#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22942#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22245#L712-42 assume !(1 == ~t6_pc~0); 22246#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 22572#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22780#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22781#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22354#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22355#L731-42 assume !(1 == ~t7_pc~0); 22053#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 22054#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23121#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22262#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22263#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21966#L750-42 assume !(1 == ~t8_pc~0); 21968#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 22541#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22964#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21859#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21860#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22629#L769-42 assume 1 == ~t9_pc~0; 22450#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22451#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23135#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23200#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 22063#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22064#L788-42 assume 1 == ~t10_pc~0; 22637#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22851#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22581#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22582#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23319#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23296#L807-42 assume !(1 == ~t11_pc~0); 21667#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 21668#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21806#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 21807#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21809#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22058#L826-42 assume 1 == ~t12_pc~0; 22059#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 22251#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23043#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 22048#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22049#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22900#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22901#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22827#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22208#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22209#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22841#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23299#L1369-3 assume !(1 == ~T6_E~0); 23219#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21973#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21974#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22206#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22207#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22505#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 23228#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23191#L1409-3 assume !(1 == ~E_1~0); 23192#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23257#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23037#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21874#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21875#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22840#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21814#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21815#L1449-3 assume !(1 == ~E_9~0); 21924#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22833#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 22834#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 23216#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22714#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21713#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21714#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22330#L1834 assume !(0 == start_simulation_~tmp~3#1); 22950#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22973#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22407#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22586#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 22798#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23206#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21699#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 21700#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 22837#L1815-2 [2021-11-13 18:09:41,328 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:41,328 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2021-11-13 18:09:41,329 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:41,329 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1024082307] [2021-11-13 18:09:41,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:41,329 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:41,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:41,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:41,374 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:41,374 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1024082307] [2021-11-13 18:09:41,375 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1024082307] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:41,375 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:41,375 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:41,375 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1335365366] [2021-11-13 18:09:41,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:41,376 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:41,376 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:41,376 INFO L85 PathProgramCache]: Analyzing trace with hash -1085730025, now seen corresponding path program 1 times [2021-11-13 18:09:41,377 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:41,377 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120343385] [2021-11-13 18:09:41,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:41,377 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:41,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:41,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:41,446 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:41,446 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1120343385] [2021-11-13 18:09:41,447 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1120343385] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:41,447 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:41,447 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:41,447 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1269058756] [2021-11-13 18:09:41,448 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:41,448 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:41,448 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:41,449 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:09:41,449 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:09:41,449 INFO L87 Difference]: Start difference. First operand 1790 states and 2650 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:41,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:41,508 INFO L93 Difference]: Finished difference Result 1790 states and 2649 transitions. [2021-11-13 18:09:41,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:09:41,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2649 transitions. [2021-11-13 18:09:41,529 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:41,548 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2649 transitions. [2021-11-13 18:09:41,548 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-13 18:09:41,551 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-13 18:09:41,551 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2649 transitions. [2021-11-13 18:09:41,555 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:41,556 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2649 transitions. [2021-11-13 18:09:41,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2649 transitions. [2021-11-13 18:09:41,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-13 18:09:41,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4798882681564245) internal successors, (2649), 1789 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:41,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2649 transitions. [2021-11-13 18:09:41,616 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2649 transitions. [2021-11-13 18:09:41,616 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2649 transitions. [2021-11-13 18:09:41,617 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-13 18:09:41,617 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2649 transitions. [2021-11-13 18:09:41,629 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:41,630 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:41,630 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:41,633 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:41,634 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:41,634 INFO L791 eck$LassoCheckResult]: Stem: 25969#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25970#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 25395#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25363#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25364#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 26625#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25672#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25125#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25126#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26397#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26536#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26902#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26903#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25884#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25885#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26423#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26343#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26344#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26496#L1206 assume !(0 == ~M_E~0); 25861#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25862#L1211-1 assume !(0 == ~T2_E~0); 26755#L1216-1 assume !(0 == ~T3_E~0); 25654#L1221-1 assume !(0 == ~T4_E~0); 25655#L1226-1 assume !(0 == ~T5_E~0); 25317#L1231-1 assume !(0 == ~T6_E~0); 25318#L1236-1 assume !(0 == ~T7_E~0); 26786#L1241-1 assume !(0 == ~T8_E~0); 25716#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25717#L1251-1 assume !(0 == ~T10_E~0); 25937#L1256-1 assume !(0 == ~T11_E~0); 25137#L1261-1 assume !(0 == ~T12_E~0); 25138#L1266-1 assume !(0 == ~E_M~0); 26889#L1271-1 assume !(0 == ~E_1~0); 26524#L1276-1 assume !(0 == ~E_2~0); 26525#L1281-1 assume !(0 == ~E_3~0); 26450#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 25558#L1291-1 assume !(0 == ~E_5~0); 25559#L1296-1 assume !(0 == ~E_6~0); 26265#L1301-1 assume !(0 == ~E_7~0); 26266#L1306-1 assume !(0 == ~E_8~0); 26698#L1311-1 assume !(0 == ~E_9~0); 25519#L1316-1 assume !(0 == ~E_10~0); 25520#L1321-1 assume !(0 == ~E_11~0); 26282#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 25383#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25384#L598 assume 1 == ~m_pc~0; 25443#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25444#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26768#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26860#L1497 assume !(0 != activate_threads_~tmp~1#1); 26861#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26817#L617 assume !(1 == ~t1_pc~0); 25739#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25740#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25599#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25600#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26360#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26361#L636 assume 1 == ~t2_pc~0; 25708#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25709#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25539#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25540#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 26396#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26059#L655 assume !(1 == ~t3_pc~0); 26060#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26773#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25413#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25414#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 26890#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26891#L674 assume 1 == ~t4_pc~0; 25233#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25234#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26531#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25541#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 25542#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26056#L693 assume !(1 == ~t5_pc~0); 26219#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25864#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25865#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26700#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 25949#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25886#L712 assume 1 == ~t6_pc~0; 25887#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26314#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26315#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26601#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 26412#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26410#L731 assume 1 == ~t7_pc~0; 25387#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25388#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25582#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26519#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 26638#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25497#L750 assume !(1 == ~t8_pc~0); 25168#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25167#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25683#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26713#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25820#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25821#L769 assume 1 == ~t9_pc~0; 26358#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25341#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25342#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26125#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 26577#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26658#L788 assume !(1 == ~t10_pc~0); 26233#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 26234#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26466#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26467#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 25493#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25494#L807 assume 1 == ~t11_pc~0; 26667#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26245#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26398#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 26809#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 26914#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26757#L826 assume !(1 == ~t12_pc~0); 25889#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 25890#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26418#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 26849#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 26049#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25958#L1344 assume !(1 == ~M_E~0); 25959#L1344-2 assume !(1 == ~T1_E~0); 26100#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26273#L1354-1 assume !(1 == ~T3_E~0); 26274#L1359-1 assume !(1 == ~T4_E~0); 26647#L1364-1 assume !(1 == ~T5_E~0); 25601#L1369-1 assume !(1 == ~T6_E~0); 25602#L1374-1 assume !(1 == ~T7_E~0); 26280#L1379-1 assume !(1 == ~T8_E~0); 26281#L1384-1 assume !(1 == ~T9_E~0); 26342#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26788#L1394-1 assume !(1 == ~T11_E~0); 26789#L1399-1 assume !(1 == ~T12_E~0); 26868#L1404-1 assume !(1 == ~E_M~0); 25720#L1409-1 assume !(1 == ~E_1~0); 25721#L1414-1 assume !(1 == ~E_2~0); 26558#L1419-1 assume !(1 == ~E_3~0); 25354#L1424-1 assume !(1 == ~E_4~0); 25355#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26289#L1434-1 assume !(1 == ~E_6~0); 26807#L1439-1 assume !(1 == ~E_7~0); 25409#L1444-1 assume !(1 == ~E_8~0); 25410#L1449-1 assume !(1 == ~E_9~0); 25825#L1454-1 assume !(1 == ~E_10~0); 25826#L1459-1 assume !(1 == ~E_11~0); 26376#L1464-1 assume !(1 == ~E_12~0); 26377#L1469-1 assume { :end_inline_reset_delta_events } true; 26424#L1815-2 [2021-11-13 18:09:41,635 INFO L793 eck$LassoCheckResult]: Loop: 26424#L1815-2 assume !false; 26578#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26247#L1181 assume !false; 26318#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26270#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25128#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25857#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 26408#L1008 assume !(0 != eval_~tmp~0#1); 26409#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25349#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25350#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26908#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26375#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25481#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25482#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26072#L1226-3 assume !(0 == ~T5_E~0); 25545#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25546#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25858#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26846#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26748#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26484#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25503#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25504#L1266-3 assume !(0 == ~E_M~0); 25543#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25544#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26016#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26017#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26554#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26555#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26897#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26865#L1306-3 assume !(0 == ~E_8~0); 26141#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25427#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25428#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25505#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 26240#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26565#L598-42 assume !(1 == ~m_pc~0); 26566#L598-44 is_master_triggered_~__retres1~0#1 := 0; 26680#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25583#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25584#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 26866#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26296#L617-42 assume 1 == ~t1_pc~0; 26069#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25933#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25934#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26348#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25648#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25649#L636-42 assume !(1 == ~t2_pc~0); 26112#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 26113#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26463#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26464#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26643#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26505#L655-42 assume !(1 == ~t3_pc~0); 26089#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 26090#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25718#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25719#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26772#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26717#L674-42 assume !(1 == ~t4_pc~0); 26491#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 26413#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25302#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25303#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26217#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26218#L693-42 assume 1 == ~t5_pc~0; 26476#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26477#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26534#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26529#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26530#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25832#L712-42 assume !(1 == ~t6_pc~0); 25833#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 26160#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26367#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26368#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25941#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25942#L731-42 assume !(1 == ~t7_pc~0); 25637#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 25638#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26708#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25849#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25850#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25550#L750-42 assume !(1 == ~t8_pc~0); 25552#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 26128#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26551#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25446#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25447#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26216#L769-42 assume 1 == ~t9_pc~0; 26036#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26037#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26722#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26787#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 25650#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25651#L788-42 assume 1 == ~t10_pc~0; 26224#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26435#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26168#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26169#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26906#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26882#L807-42 assume !(1 == ~t11_pc~0); 25254#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 25255#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25393#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 25394#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25396#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25645#L826-42 assume 1 == ~t12_pc~0; 25646#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 25838#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26630#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 25635#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25636#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26487#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26488#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26414#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25795#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25796#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26428#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26886#L1369-3 assume !(1 == ~T6_E~0); 26806#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25560#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25561#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25793#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25794#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26092#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26815#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26778#L1409-3 assume !(1 == ~E_1~0); 26779#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26844#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26624#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25461#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25462#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26427#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25399#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25400#L1449-3 assume !(1 == ~E_9~0); 25511#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26420#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 26421#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 26803#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26301#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25300#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25301#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 25917#L1834 assume !(0 == start_simulation_~tmp~3#1); 26537#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26560#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25994#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 26173#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 26385#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26793#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25286#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 25287#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 26424#L1815-2 [2021-11-13 18:09:41,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:41,636 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2021-11-13 18:09:41,637 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:41,637 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [887888182] [2021-11-13 18:09:41,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:41,637 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:41,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:41,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:41,689 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:41,690 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [887888182] [2021-11-13 18:09:41,690 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [887888182] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:41,692 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:41,692 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:41,692 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [919541857] [2021-11-13 18:09:41,693 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:41,693 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:41,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:41,694 INFO L85 PathProgramCache]: Analyzing trace with hash -1085730025, now seen corresponding path program 2 times [2021-11-13 18:09:41,694 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:41,695 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184577339] [2021-11-13 18:09:41,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:41,695 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:41,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:41,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:41,785 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:41,787 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184577339] [2021-11-13 18:09:41,790 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184577339] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:41,790 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:41,790 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:41,791 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [343421071] [2021-11-13 18:09:41,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:41,791 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:41,792 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:41,792 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:09:41,792 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:09:41,792 INFO L87 Difference]: Start difference. First operand 1790 states and 2649 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:41,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:41,847 INFO L93 Difference]: Finished difference Result 1790 states and 2648 transitions. [2021-11-13 18:09:41,847 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:09:41,851 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2648 transitions. [2021-11-13 18:09:41,869 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:41,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2648 transitions. [2021-11-13 18:09:41,889 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-13 18:09:41,892 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-13 18:09:41,892 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2648 transitions. [2021-11-13 18:09:41,896 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:41,896 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2648 transitions. [2021-11-13 18:09:41,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2648 transitions. [2021-11-13 18:09:41,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-13 18:09:41,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4793296089385475) internal successors, (2648), 1789 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:41,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2648 transitions. [2021-11-13 18:09:41,959 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2648 transitions. [2021-11-13 18:09:41,959 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2648 transitions. [2021-11-13 18:09:41,959 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-13 18:09:41,959 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2648 transitions. [2021-11-13 18:09:41,972 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:41,972 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:41,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:41,976 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:41,976 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:41,977 INFO L791 eck$LassoCheckResult]: Stem: 29556#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 29557#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 28980#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28950#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28951#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 30212#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29259#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28712#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28713#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29984#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30123#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30489#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30490#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29469#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29470#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 30010#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29930#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29931#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30083#L1206 assume !(0 == ~M_E~0); 29448#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29449#L1211-1 assume !(0 == ~T2_E~0); 30342#L1216-1 assume !(0 == ~T3_E~0); 29241#L1221-1 assume !(0 == ~T4_E~0); 29242#L1226-1 assume !(0 == ~T5_E~0); 28904#L1231-1 assume !(0 == ~T6_E~0); 28905#L1236-1 assume !(0 == ~T7_E~0); 30373#L1241-1 assume !(0 == ~T8_E~0); 29303#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29304#L1251-1 assume !(0 == ~T10_E~0); 29524#L1256-1 assume !(0 == ~T11_E~0); 28724#L1261-1 assume !(0 == ~T12_E~0); 28725#L1266-1 assume !(0 == ~E_M~0); 30476#L1271-1 assume !(0 == ~E_1~0); 30111#L1276-1 assume !(0 == ~E_2~0); 30112#L1281-1 assume !(0 == ~E_3~0); 30037#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 29145#L1291-1 assume !(0 == ~E_5~0); 29146#L1296-1 assume !(0 == ~E_6~0); 29852#L1301-1 assume !(0 == ~E_7~0); 29853#L1306-1 assume !(0 == ~E_8~0); 30285#L1311-1 assume !(0 == ~E_9~0); 29106#L1316-1 assume !(0 == ~E_10~0); 29107#L1321-1 assume !(0 == ~E_11~0); 29869#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 28970#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28971#L598 assume 1 == ~m_pc~0; 29030#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29031#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30355#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30447#L1497 assume !(0 != activate_threads_~tmp~1#1); 30448#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30404#L617 assume !(1 == ~t1_pc~0); 29326#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29327#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29186#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29187#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29947#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29948#L636 assume 1 == ~t2_pc~0; 29295#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29296#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29126#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29127#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 29983#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29646#L655 assume !(1 == ~t3_pc~0); 29647#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30360#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29000#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29001#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 30477#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30478#L674 assume 1 == ~t4_pc~0; 28820#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28821#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30118#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29128#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 29129#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29643#L693 assume !(1 == ~t5_pc~0); 29806#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 29450#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29451#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30287#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 29536#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29473#L712 assume 1 == ~t6_pc~0; 29474#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29901#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29902#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30188#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 29999#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29997#L731 assume 1 == ~t7_pc~0; 28974#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28975#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29169#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30106#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 30225#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29084#L750 assume !(1 == ~t8_pc~0); 28755#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 28754#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29270#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30300#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29407#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29408#L769 assume 1 == ~t9_pc~0; 29945#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28928#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28929#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29712#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 30164#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30245#L788 assume !(1 == ~t10_pc~0); 29820#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29821#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30052#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30053#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 29080#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29081#L807 assume 1 == ~t11_pc~0; 30254#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29832#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29985#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30396#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 30501#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30344#L826 assume !(1 == ~t12_pc~0); 29476#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29477#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30005#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 30436#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 29636#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29545#L1344 assume !(1 == ~M_E~0); 29546#L1344-2 assume !(1 == ~T1_E~0); 29687#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29859#L1354-1 assume !(1 == ~T3_E~0); 29860#L1359-1 assume !(1 == ~T4_E~0); 30234#L1364-1 assume !(1 == ~T5_E~0); 29188#L1369-1 assume !(1 == ~T6_E~0); 29189#L1374-1 assume !(1 == ~T7_E~0); 29865#L1379-1 assume !(1 == ~T8_E~0); 29866#L1384-1 assume !(1 == ~T9_E~0); 29929#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30375#L1394-1 assume !(1 == ~T11_E~0); 30376#L1399-1 assume !(1 == ~T12_E~0); 30455#L1404-1 assume !(1 == ~E_M~0); 29307#L1409-1 assume !(1 == ~E_1~0); 29308#L1414-1 assume !(1 == ~E_2~0); 30145#L1419-1 assume !(1 == ~E_3~0); 28941#L1424-1 assume !(1 == ~E_4~0); 28942#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 29876#L1434-1 assume !(1 == ~E_6~0); 30394#L1439-1 assume !(1 == ~E_7~0); 28996#L1444-1 assume !(1 == ~E_8~0); 28997#L1449-1 assume !(1 == ~E_9~0); 29412#L1454-1 assume !(1 == ~E_10~0); 29413#L1459-1 assume !(1 == ~E_11~0); 29963#L1464-1 assume !(1 == ~E_12~0); 29964#L1469-1 assume { :end_inline_reset_delta_events } true; 30011#L1815-2 [2021-11-13 18:09:41,978 INFO L793 eck$LassoCheckResult]: Loop: 30011#L1815-2 assume !false; 30165#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29834#L1181 assume !false; 29905#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29857#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28715#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29444#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 29995#L1008 assume !(0 != eval_~tmp~0#1); 29996#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28934#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28935#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30495#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29962#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29068#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29069#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29659#L1226-3 assume !(0 == ~T5_E~0); 29132#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29133#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29445#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30432#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30335#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30071#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29090#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29091#L1266-3 assume !(0 == ~E_M~0); 29130#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29131#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29603#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29604#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30141#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30142#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30484#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30452#L1306-3 assume !(0 == ~E_8~0); 29728#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29014#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29015#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29092#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29827#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30152#L598-42 assume !(1 == ~m_pc~0); 30153#L598-44 is_master_triggered_~__retres1~0#1 := 0; 30267#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29170#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29171#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 30453#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29883#L617-42 assume 1 == ~t1_pc~0; 29655#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29520#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29521#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29935#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29235#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29236#L636-42 assume !(1 == ~t2_pc~0); 29699#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 29700#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30050#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30051#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30230#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30092#L655-42 assume !(1 == ~t3_pc~0); 29672#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 29673#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29305#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29306#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30359#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30304#L674-42 assume 1 == ~t4_pc~0; 30305#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30000#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28889#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28890#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29804#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29805#L693-42 assume 1 == ~t5_pc~0; 30060#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30061#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30121#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30116#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30117#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29419#L712-42 assume !(1 == ~t6_pc~0); 29420#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 29746#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29954#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29955#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29528#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29529#L731-42 assume 1 == ~t7_pc~0; 29392#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29228#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30295#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29436#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29437#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29140#L750-42 assume 1 == ~t8_pc~0; 29141#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29715#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30138#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29033#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29034#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29803#L769-42 assume 1 == ~t9_pc~0; 29625#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29626#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30309#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30374#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 29237#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29238#L788-42 assume 1 == ~t10_pc~0; 29811#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30025#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29755#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29756#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30493#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30471#L807-42 assume 1 == ~t11_pc~0; 30160#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28842#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28981#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 28982#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28983#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29232#L826-42 assume 1 == ~t12_pc~0; 29233#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 29425#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30217#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 29222#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29223#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30074#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30075#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30001#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29382#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29383#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30015#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30473#L1369-3 assume !(1 == ~T6_E~0); 30393#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29147#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29148#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29380#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29381#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29679#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30402#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30365#L1409-3 assume !(1 == ~E_1~0); 30366#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30431#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30211#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29048#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29049#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30014#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28988#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28989#L1449-3 assume !(1 == ~E_9~0); 29098#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30008#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 30009#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 30390#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29888#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28887#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28888#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 29504#L1834 assume !(0 == start_simulation_~tmp~3#1); 30124#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 30147#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29582#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29760#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 29972#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30380#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28873#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 28874#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 30011#L1815-2 [2021-11-13 18:09:41,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:41,979 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2021-11-13 18:09:41,980 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:41,980 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [949993778] [2021-11-13 18:09:41,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:41,980 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:41,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:42,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:42,022 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:42,022 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [949993778] [2021-11-13 18:09:42,022 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [949993778] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:42,023 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:42,023 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:42,023 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [790158855] [2021-11-13 18:09:42,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:42,024 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:42,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:42,025 INFO L85 PathProgramCache]: Analyzing trace with hash -1380802157, now seen corresponding path program 2 times [2021-11-13 18:09:42,025 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:42,026 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [704822258] [2021-11-13 18:09:42,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:42,026 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:42,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:42,079 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:42,080 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:42,080 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [704822258] [2021-11-13 18:09:42,080 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [704822258] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:42,080 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:42,081 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:42,081 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [315143331] [2021-11-13 18:09:42,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:42,082 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:42,082 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:42,082 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:09:42,082 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:09:42,083 INFO L87 Difference]: Start difference. First operand 1790 states and 2648 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:42,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:42,162 INFO L93 Difference]: Finished difference Result 1790 states and 2647 transitions. [2021-11-13 18:09:42,163 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:09:42,164 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2647 transitions. [2021-11-13 18:09:42,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:42,194 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2647 transitions. [2021-11-13 18:09:42,194 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-13 18:09:42,196 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-13 18:09:42,197 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2647 transitions. [2021-11-13 18:09:42,201 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:42,201 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2647 transitions. [2021-11-13 18:09:42,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2647 transitions. [2021-11-13 18:09:42,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-13 18:09:42,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4787709497206705) internal successors, (2647), 1789 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:42,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2647 transitions. [2021-11-13 18:09:42,253 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2647 transitions. [2021-11-13 18:09:42,253 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2647 transitions. [2021-11-13 18:09:42,253 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-13 18:09:42,253 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2647 transitions. [2021-11-13 18:09:42,264 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:42,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:42,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:42,267 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:42,267 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:42,269 INFO L791 eck$LassoCheckResult]: Stem: 33143#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 33144#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 32567#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32537#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32538#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 33799#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32846#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32299#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32300#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33571#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33710#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34076#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34077#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33056#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33057#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33597#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33517#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33518#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33670#L1206 assume !(0 == ~M_E~0); 33035#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33036#L1211-1 assume !(0 == ~T2_E~0); 33929#L1216-1 assume !(0 == ~T3_E~0); 32828#L1221-1 assume !(0 == ~T4_E~0); 32829#L1226-1 assume !(0 == ~T5_E~0); 32491#L1231-1 assume !(0 == ~T6_E~0); 32492#L1236-1 assume !(0 == ~T7_E~0); 33960#L1241-1 assume !(0 == ~T8_E~0); 32890#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32891#L1251-1 assume !(0 == ~T10_E~0); 33111#L1256-1 assume !(0 == ~T11_E~0); 32311#L1261-1 assume !(0 == ~T12_E~0); 32312#L1266-1 assume !(0 == ~E_M~0); 34063#L1271-1 assume !(0 == ~E_1~0); 33698#L1276-1 assume !(0 == ~E_2~0); 33699#L1281-1 assume !(0 == ~E_3~0); 33624#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 32732#L1291-1 assume !(0 == ~E_5~0); 32733#L1296-1 assume !(0 == ~E_6~0); 33439#L1301-1 assume !(0 == ~E_7~0); 33440#L1306-1 assume !(0 == ~E_8~0); 33872#L1311-1 assume !(0 == ~E_9~0); 32693#L1316-1 assume !(0 == ~E_10~0); 32694#L1321-1 assume !(0 == ~E_11~0); 33456#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 32557#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32558#L598 assume 1 == ~m_pc~0; 32617#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32618#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33942#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34034#L1497 assume !(0 != activate_threads_~tmp~1#1); 34035#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33991#L617 assume !(1 == ~t1_pc~0); 32913#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32914#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32773#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32774#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33534#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33535#L636 assume 1 == ~t2_pc~0; 32882#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32883#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32713#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32714#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 33570#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33233#L655 assume !(1 == ~t3_pc~0); 33234#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33947#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32587#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32588#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 34064#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34065#L674 assume 1 == ~t4_pc~0; 32407#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32408#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33705#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32715#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 32716#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33230#L693 assume !(1 == ~t5_pc~0); 33393#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 33037#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33038#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33874#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 33123#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33060#L712 assume 1 == ~t6_pc~0; 33061#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33488#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33489#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33775#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 33586#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33584#L731 assume 1 == ~t7_pc~0; 32561#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32562#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32756#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33693#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 33812#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32671#L750 assume !(1 == ~t8_pc~0); 32342#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32341#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32857#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33887#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32994#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32995#L769 assume 1 == ~t9_pc~0; 33530#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32515#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32516#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33299#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 33751#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33832#L788 assume !(1 == ~t10_pc~0); 33407#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 33408#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33639#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 33640#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 32667#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32668#L807 assume 1 == ~t11_pc~0; 33841#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33419#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33572#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 33983#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 34088#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33931#L826 assume !(1 == ~t12_pc~0); 33063#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33064#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33592#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 34023#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 33223#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33132#L1344 assume !(1 == ~M_E~0); 33133#L1344-2 assume !(1 == ~T1_E~0); 33274#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33446#L1354-1 assume !(1 == ~T3_E~0); 33447#L1359-1 assume !(1 == ~T4_E~0); 33821#L1364-1 assume !(1 == ~T5_E~0); 32775#L1369-1 assume !(1 == ~T6_E~0); 32776#L1374-1 assume !(1 == ~T7_E~0); 33452#L1379-1 assume !(1 == ~T8_E~0); 33453#L1384-1 assume !(1 == ~T9_E~0); 33516#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33962#L1394-1 assume !(1 == ~T11_E~0); 33963#L1399-1 assume !(1 == ~T12_E~0); 34042#L1404-1 assume !(1 == ~E_M~0); 32894#L1409-1 assume !(1 == ~E_1~0); 32895#L1414-1 assume !(1 == ~E_2~0); 33732#L1419-1 assume !(1 == ~E_3~0); 32528#L1424-1 assume !(1 == ~E_4~0); 32529#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 33463#L1434-1 assume !(1 == ~E_6~0); 33981#L1439-1 assume !(1 == ~E_7~0); 32583#L1444-1 assume !(1 == ~E_8~0); 32584#L1449-1 assume !(1 == ~E_9~0); 32999#L1454-1 assume !(1 == ~E_10~0); 33000#L1459-1 assume !(1 == ~E_11~0); 33550#L1464-1 assume !(1 == ~E_12~0); 33551#L1469-1 assume { :end_inline_reset_delta_events } true; 33598#L1815-2 [2021-11-13 18:09:42,270 INFO L793 eck$LassoCheckResult]: Loop: 33598#L1815-2 assume !false; 33752#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33421#L1181 assume !false; 33492#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33444#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32302#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33031#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 33582#L1008 assume !(0 != eval_~tmp~0#1); 33583#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32521#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32522#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34082#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33549#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32655#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32656#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33246#L1226-3 assume !(0 == ~T5_E~0); 32719#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32720#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33032#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 34019#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33922#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33658#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32677#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32678#L1266-3 assume !(0 == ~E_M~0); 32717#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32718#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33190#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33191#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33728#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33729#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34071#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34039#L1306-3 assume !(0 == ~E_8~0); 33315#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32601#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32602#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32679#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 33414#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33739#L598-42 assume !(1 == ~m_pc~0); 33740#L598-44 is_master_triggered_~__retres1~0#1 := 0; 33854#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32757#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32758#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 34040#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33470#L617-42 assume 1 == ~t1_pc~0; 33242#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33107#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33108#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33522#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32822#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32823#L636-42 assume !(1 == ~t2_pc~0); 33286#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 33287#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33637#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33638#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33817#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33679#L655-42 assume 1 == ~t3_pc~0; 33680#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33260#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32892#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32893#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33946#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33891#L674-42 assume !(1 == ~t4_pc~0); 33665#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 33587#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32476#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32477#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33391#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33392#L693-42 assume !(1 == ~t5_pc~0); 33649#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 33648#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33708#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33703#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33704#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33006#L712-42 assume 1 == ~t6_pc~0; 33008#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33333#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33541#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33542#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33115#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33116#L731-42 assume 1 == ~t7_pc~0; 32979#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32815#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33882#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33023#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33024#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32727#L750-42 assume 1 == ~t8_pc~0; 32728#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33302#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33725#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32620#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32621#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33390#L769-42 assume 1 == ~t9_pc~0; 33212#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33213#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33896#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33961#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 32824#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32825#L788-42 assume 1 == ~t10_pc~0; 33398#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33612#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33342#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 33343#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34080#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34058#L807-42 assume 1 == ~t11_pc~0; 33747#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32429#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32568#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 32569#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32570#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32819#L826-42 assume 1 == ~t12_pc~0; 32820#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 33012#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33804#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 32809#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32810#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33661#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33662#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33588#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32969#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32970#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33602#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34060#L1369-3 assume !(1 == ~T6_E~0); 33980#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32734#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32735#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32967#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32968#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33266#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33989#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33952#L1409-3 assume !(1 == ~E_1~0); 33953#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34018#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33798#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32635#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32636#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33601#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32575#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32576#L1449-3 assume !(1 == ~E_9~0); 32685#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33595#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33596#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33977#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33475#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32474#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32475#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 33091#L1834 assume !(0 == start_simulation_~tmp~3#1); 33711#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33734#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 33168#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33347#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 33559#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33967#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32460#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 32461#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 33598#L1815-2 [2021-11-13 18:09:42,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:42,271 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2021-11-13 18:09:42,272 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:42,272 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [745461134] [2021-11-13 18:09:42,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:42,272 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:42,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:42,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:42,310 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:42,310 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [745461134] [2021-11-13 18:09:42,310 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [745461134] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:42,311 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:42,311 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:42,311 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1487043733] [2021-11-13 18:09:42,311 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:42,313 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:42,313 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:42,314 INFO L85 PathProgramCache]: Analyzing trace with hash -1098284653, now seen corresponding path program 1 times [2021-11-13 18:09:42,314 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:42,314 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [725069591] [2021-11-13 18:09:42,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:42,314 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:42,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:42,371 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:42,371 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:42,372 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [725069591] [2021-11-13 18:09:42,372 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [725069591] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:42,372 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:42,372 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:42,373 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [985991561] [2021-11-13 18:09:42,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:42,373 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:42,374 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:42,374 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:09:42,374 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:09:42,375 INFO L87 Difference]: Start difference. First operand 1790 states and 2647 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:42,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:42,427 INFO L93 Difference]: Finished difference Result 1790 states and 2646 transitions. [2021-11-13 18:09:42,427 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:09:42,428 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2646 transitions. [2021-11-13 18:09:42,442 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:42,472 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2646 transitions. [2021-11-13 18:09:42,472 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-13 18:09:42,475 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-13 18:09:42,475 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2646 transitions. [2021-11-13 18:09:42,479 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:42,479 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2646 transitions. [2021-11-13 18:09:42,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2646 transitions. [2021-11-13 18:09:42,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-13 18:09:42,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4782122905027932) internal successors, (2646), 1789 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:42,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2646 transitions. [2021-11-13 18:09:42,529 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2646 transitions. [2021-11-13 18:09:42,529 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2646 transitions. [2021-11-13 18:09:42,529 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-13 18:09:42,529 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2646 transitions. [2021-11-13 18:09:42,541 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:42,541 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:42,541 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:42,545 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:42,545 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:42,546 INFO L791 eck$LassoCheckResult]: Stem: 36730#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 36731#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 36154#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36124#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36125#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 37386#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36433#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35886#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35887#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37158#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37297#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37663#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37664#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36643#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36644#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 37184#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37104#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37105#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37257#L1206 assume !(0 == ~M_E~0); 36622#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36623#L1211-1 assume !(0 == ~T2_E~0); 37516#L1216-1 assume !(0 == ~T3_E~0); 36415#L1221-1 assume !(0 == ~T4_E~0); 36416#L1226-1 assume !(0 == ~T5_E~0); 36078#L1231-1 assume !(0 == ~T6_E~0); 36079#L1236-1 assume !(0 == ~T7_E~0); 37547#L1241-1 assume !(0 == ~T8_E~0); 36477#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36478#L1251-1 assume !(0 == ~T10_E~0); 36698#L1256-1 assume !(0 == ~T11_E~0); 35898#L1261-1 assume !(0 == ~T12_E~0); 35899#L1266-1 assume !(0 == ~E_M~0); 37650#L1271-1 assume !(0 == ~E_1~0); 37285#L1276-1 assume !(0 == ~E_2~0); 37286#L1281-1 assume !(0 == ~E_3~0); 37211#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 36319#L1291-1 assume !(0 == ~E_5~0); 36320#L1296-1 assume !(0 == ~E_6~0); 37026#L1301-1 assume !(0 == ~E_7~0); 37027#L1306-1 assume !(0 == ~E_8~0); 37459#L1311-1 assume !(0 == ~E_9~0); 36280#L1316-1 assume !(0 == ~E_10~0); 36281#L1321-1 assume !(0 == ~E_11~0); 37043#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 36144#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36145#L598 assume 1 == ~m_pc~0; 36204#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36205#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37529#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37621#L1497 assume !(0 != activate_threads_~tmp~1#1); 37622#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37578#L617 assume !(1 == ~t1_pc~0); 36500#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36501#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36360#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36361#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37121#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37122#L636 assume 1 == ~t2_pc~0; 36469#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36470#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36300#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36301#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 37157#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36820#L655 assume !(1 == ~t3_pc~0); 36821#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37534#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36174#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36175#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 37651#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37652#L674 assume 1 == ~t4_pc~0; 35994#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35995#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37292#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36302#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 36303#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36817#L693 assume !(1 == ~t5_pc~0); 36980#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36624#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36625#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37461#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 36710#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36647#L712 assume 1 == ~t6_pc~0; 36648#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37075#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37076#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37362#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 37173#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37171#L731 assume 1 == ~t7_pc~0; 36148#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36149#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36343#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37280#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 37399#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36258#L750 assume !(1 == ~t8_pc~0); 35929#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35928#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36444#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37474#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36581#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36582#L769 assume 1 == ~t9_pc~0; 37117#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36102#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36103#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36886#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 37338#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37419#L788 assume !(1 == ~t10_pc~0); 36994#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36995#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37226#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 37227#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 36254#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36255#L807 assume 1 == ~t11_pc~0; 37428#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37006#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37159#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 37570#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 37675#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37518#L826 assume !(1 == ~t12_pc~0); 36650#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 36651#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37179#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 37610#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 36810#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36719#L1344 assume !(1 == ~M_E~0); 36720#L1344-2 assume !(1 == ~T1_E~0); 36861#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37033#L1354-1 assume !(1 == ~T3_E~0); 37034#L1359-1 assume !(1 == ~T4_E~0); 37408#L1364-1 assume !(1 == ~T5_E~0); 36362#L1369-1 assume !(1 == ~T6_E~0); 36363#L1374-1 assume !(1 == ~T7_E~0); 37039#L1379-1 assume !(1 == ~T8_E~0); 37040#L1384-1 assume !(1 == ~T9_E~0); 37103#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37549#L1394-1 assume !(1 == ~T11_E~0); 37550#L1399-1 assume !(1 == ~T12_E~0); 37629#L1404-1 assume !(1 == ~E_M~0); 36481#L1409-1 assume !(1 == ~E_1~0); 36482#L1414-1 assume !(1 == ~E_2~0); 37319#L1419-1 assume !(1 == ~E_3~0); 36115#L1424-1 assume !(1 == ~E_4~0); 36116#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 37050#L1434-1 assume !(1 == ~E_6~0); 37568#L1439-1 assume !(1 == ~E_7~0); 36170#L1444-1 assume !(1 == ~E_8~0); 36171#L1449-1 assume !(1 == ~E_9~0); 36586#L1454-1 assume !(1 == ~E_10~0); 36587#L1459-1 assume !(1 == ~E_11~0); 37137#L1464-1 assume !(1 == ~E_12~0); 37138#L1469-1 assume { :end_inline_reset_delta_events } true; 37185#L1815-2 [2021-11-13 18:09:42,547 INFO L793 eck$LassoCheckResult]: Loop: 37185#L1815-2 assume !false; 37339#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37008#L1181 assume !false; 37079#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37031#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 35889#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36618#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 37169#L1008 assume !(0 != eval_~tmp~0#1); 37170#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36108#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36109#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37669#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37136#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36242#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36243#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36833#L1226-3 assume !(0 == ~T5_E~0); 36306#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36307#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36619#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37606#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37509#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37245#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36264#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 36265#L1266-3 assume !(0 == ~E_M~0); 36304#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36305#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36777#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36778#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37315#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37316#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37658#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37626#L1306-3 assume !(0 == ~E_8~0); 36902#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36188#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36189#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36266#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 37001#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37326#L598-42 assume 1 == ~m_pc~0; 37328#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37441#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36344#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36345#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 37627#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37057#L617-42 assume 1 == ~t1_pc~0; 36829#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36694#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36695#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37109#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36409#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36410#L636-42 assume !(1 == ~t2_pc~0); 36873#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 36874#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37224#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37225#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37404#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37266#L655-42 assume 1 == ~t3_pc~0; 37267#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36847#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36479#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36480#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37533#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37478#L674-42 assume !(1 == ~t4_pc~0); 37252#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 37174#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36063#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36064#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36978#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36979#L693-42 assume 1 == ~t5_pc~0; 37234#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37235#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37295#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37290#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37291#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36593#L712-42 assume !(1 == ~t6_pc~0); 36594#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 36920#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37128#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37129#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36702#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36703#L731-42 assume !(1 == ~t7_pc~0); 36401#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 36402#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37469#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36610#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36611#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36314#L750-42 assume 1 == ~t8_pc~0; 36315#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36889#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37312#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36207#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36208#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36977#L769-42 assume !(1 == ~t9_pc~0); 36801#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 36800#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37483#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37548#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 36411#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36412#L788-42 assume 1 == ~t10_pc~0; 36985#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37199#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36929#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 36930#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37667#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37645#L807-42 assume 1 == ~t11_pc~0; 37334#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36016#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36155#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 36156#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36157#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36406#L826-42 assume 1 == ~t12_pc~0; 36407#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36599#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37391#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 36396#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36397#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37248#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37249#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37175#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36556#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36557#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37189#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37647#L1369-3 assume !(1 == ~T6_E~0); 37567#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36321#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36322#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36554#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36555#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36853#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 37576#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37539#L1409-3 assume !(1 == ~E_1~0); 37540#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37605#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37385#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36222#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36223#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37188#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36162#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36163#L1449-3 assume !(1 == ~E_9~0); 36272#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37182#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37183#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37564#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37062#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36061#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36062#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 36678#L1834 assume !(0 == start_simulation_~tmp~3#1); 37298#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37321#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36755#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36934#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 37146#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37554#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36047#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 36048#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 37185#L1815-2 [2021-11-13 18:09:42,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:42,548 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2021-11-13 18:09:42,548 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:42,548 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1068807865] [2021-11-13 18:09:42,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:42,549 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:42,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:42,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:42,597 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:42,598 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1068807865] [2021-11-13 18:09:42,598 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1068807865] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:42,598 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:42,598 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:42,598 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [235430488] [2021-11-13 18:09:42,599 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:42,599 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:42,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:42,600 INFO L85 PathProgramCache]: Analyzing trace with hash -1147501804, now seen corresponding path program 1 times [2021-11-13 18:09:42,600 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:42,600 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899767645] [2021-11-13 18:09:42,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:42,601 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:42,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:42,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:42,656 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:42,656 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [899767645] [2021-11-13 18:09:42,656 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [899767645] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:42,657 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:42,657 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:42,657 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [911746146] [2021-11-13 18:09:42,657 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:42,658 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:42,658 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:42,659 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:09:42,659 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:09:42,660 INFO L87 Difference]: Start difference. First operand 1790 states and 2646 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:42,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:42,707 INFO L93 Difference]: Finished difference Result 1790 states and 2645 transitions. [2021-11-13 18:09:42,708 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:09:42,708 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2645 transitions. [2021-11-13 18:09:42,722 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:42,737 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2645 transitions. [2021-11-13 18:09:42,737 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-13 18:09:42,740 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-13 18:09:42,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2645 transitions. [2021-11-13 18:09:42,744 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:42,745 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2645 transitions. [2021-11-13 18:09:42,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2645 transitions. [2021-11-13 18:09:42,780 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-13 18:09:42,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4776536312849162) internal successors, (2645), 1789 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:42,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2645 transitions. [2021-11-13 18:09:42,811 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2645 transitions. [2021-11-13 18:09:42,811 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2645 transitions. [2021-11-13 18:09:42,811 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-13 18:09:42,811 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2645 transitions. [2021-11-13 18:09:42,822 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:42,822 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:42,822 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:42,825 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:42,826 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:42,826 INFO L791 eck$LassoCheckResult]: Stem: 40317#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 40318#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 39741#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39711#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39712#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 40973#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40020#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39473#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39474#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40745#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40884#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41250#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41251#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40230#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40231#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40771#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40691#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40692#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40844#L1206 assume !(0 == ~M_E~0); 40209#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40210#L1211-1 assume !(0 == ~T2_E~0); 41103#L1216-1 assume !(0 == ~T3_E~0); 40002#L1221-1 assume !(0 == ~T4_E~0); 40003#L1226-1 assume !(0 == ~T5_E~0); 39665#L1231-1 assume !(0 == ~T6_E~0); 39666#L1236-1 assume !(0 == ~T7_E~0); 41134#L1241-1 assume !(0 == ~T8_E~0); 40064#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40065#L1251-1 assume !(0 == ~T10_E~0); 40285#L1256-1 assume !(0 == ~T11_E~0); 39485#L1261-1 assume !(0 == ~T12_E~0); 39486#L1266-1 assume !(0 == ~E_M~0); 41237#L1271-1 assume !(0 == ~E_1~0); 40872#L1276-1 assume !(0 == ~E_2~0); 40873#L1281-1 assume !(0 == ~E_3~0); 40798#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 39906#L1291-1 assume !(0 == ~E_5~0); 39907#L1296-1 assume !(0 == ~E_6~0); 40613#L1301-1 assume !(0 == ~E_7~0); 40614#L1306-1 assume !(0 == ~E_8~0); 41046#L1311-1 assume !(0 == ~E_9~0); 39867#L1316-1 assume !(0 == ~E_10~0); 39868#L1321-1 assume !(0 == ~E_11~0); 40630#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 39731#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39732#L598 assume 1 == ~m_pc~0; 39791#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39792#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41116#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41208#L1497 assume !(0 != activate_threads_~tmp~1#1); 41209#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41165#L617 assume !(1 == ~t1_pc~0); 40087#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40088#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39947#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39948#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40708#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40709#L636 assume 1 == ~t2_pc~0; 40056#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40057#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39887#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39888#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 40744#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40407#L655 assume !(1 == ~t3_pc~0); 40408#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41121#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39761#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39762#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 41238#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41239#L674 assume 1 == ~t4_pc~0; 39581#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39582#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40879#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39889#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 39890#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40404#L693 assume !(1 == ~t5_pc~0); 40567#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 40211#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40212#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41048#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 40297#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40234#L712 assume 1 == ~t6_pc~0; 40235#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40662#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40663#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40949#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 40760#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40758#L731 assume 1 == ~t7_pc~0; 39735#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39736#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39930#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40867#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 40986#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39845#L750 assume !(1 == ~t8_pc~0); 39516#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39515#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40031#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41061#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40168#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40169#L769 assume 1 == ~t9_pc~0; 40704#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39689#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39690#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40473#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 40925#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41006#L788 assume !(1 == ~t10_pc~0); 40581#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40582#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40813#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 40814#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 39841#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39842#L807 assume 1 == ~t11_pc~0; 41015#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40593#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40746#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 41157#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 41262#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41105#L826 assume !(1 == ~t12_pc~0); 40237#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40238#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40766#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 41197#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 40397#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40306#L1344 assume !(1 == ~M_E~0); 40307#L1344-2 assume !(1 == ~T1_E~0); 40448#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40620#L1354-1 assume !(1 == ~T3_E~0); 40621#L1359-1 assume !(1 == ~T4_E~0); 40995#L1364-1 assume !(1 == ~T5_E~0); 39949#L1369-1 assume !(1 == ~T6_E~0); 39950#L1374-1 assume !(1 == ~T7_E~0); 40626#L1379-1 assume !(1 == ~T8_E~0); 40627#L1384-1 assume !(1 == ~T9_E~0); 40690#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41136#L1394-1 assume !(1 == ~T11_E~0); 41137#L1399-1 assume !(1 == ~T12_E~0); 41216#L1404-1 assume !(1 == ~E_M~0); 40068#L1409-1 assume !(1 == ~E_1~0); 40069#L1414-1 assume !(1 == ~E_2~0); 40906#L1419-1 assume !(1 == ~E_3~0); 39702#L1424-1 assume !(1 == ~E_4~0); 39703#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 40637#L1434-1 assume !(1 == ~E_6~0); 41155#L1439-1 assume !(1 == ~E_7~0); 39757#L1444-1 assume !(1 == ~E_8~0); 39758#L1449-1 assume !(1 == ~E_9~0); 40173#L1454-1 assume !(1 == ~E_10~0); 40174#L1459-1 assume !(1 == ~E_11~0); 40724#L1464-1 assume !(1 == ~E_12~0); 40725#L1469-1 assume { :end_inline_reset_delta_events } true; 40772#L1815-2 [2021-11-13 18:09:42,827 INFO L793 eck$LassoCheckResult]: Loop: 40772#L1815-2 assume !false; 40926#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40595#L1181 assume !false; 40666#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40618#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39476#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40205#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 40756#L1008 assume !(0 != eval_~tmp~0#1); 40757#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39695#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39696#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41256#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40723#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39829#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39830#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40420#L1226-3 assume !(0 == ~T5_E~0); 39893#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39894#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40206#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41193#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41096#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40832#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 39851#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39852#L1266-3 assume !(0 == ~E_M~0); 39891#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39892#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40364#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40365#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40902#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40903#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41245#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41213#L1306-3 assume !(0 == ~E_8~0); 40489#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39775#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39776#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39853#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40588#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40913#L598-42 assume !(1 == ~m_pc~0); 40914#L598-44 is_master_triggered_~__retres1~0#1 := 0; 41028#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39931#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39932#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 41214#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40644#L617-42 assume 1 == ~t1_pc~0; 40416#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40281#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40282#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40696#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39996#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39997#L636-42 assume !(1 == ~t2_pc~0); 40460#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 40461#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40811#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40812#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40991#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40853#L655-42 assume !(1 == ~t3_pc~0); 40433#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 40434#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40066#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40067#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41120#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41065#L674-42 assume !(1 == ~t4_pc~0); 40839#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 40761#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39650#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39651#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40565#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40566#L693-42 assume 1 == ~t5_pc~0; 40821#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40822#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40882#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40877#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40878#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40180#L712-42 assume !(1 == ~t6_pc~0); 40181#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 40507#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40715#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40716#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40289#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40290#L731-42 assume !(1 == ~t7_pc~0); 39988#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 39989#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41056#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40197#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40198#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39901#L750-42 assume 1 == ~t8_pc~0; 39902#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40476#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40899#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39794#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39795#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40564#L769-42 assume 1 == ~t9_pc~0; 40386#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40387#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41070#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41135#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 39998#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39999#L788-42 assume 1 == ~t10_pc~0; 40572#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 40786#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40516#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 40517#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41254#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41232#L807-42 assume !(1 == ~t11_pc~0); 39602#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 39603#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39742#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 39743#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39744#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39993#L826-42 assume 1 == ~t12_pc~0; 39994#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40186#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40978#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 39983#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 39984#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40835#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40836#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40762#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40143#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40144#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40776#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41234#L1369-3 assume !(1 == ~T6_E~0); 41154#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 39908#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 39909#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40141#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40142#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40440#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 41163#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41126#L1409-3 assume !(1 == ~E_1~0); 41127#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41192#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40972#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39809#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39810#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40775#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39749#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39750#L1449-3 assume !(1 == ~E_9~0); 39859#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40769#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40770#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41151#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40649#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39648#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39649#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 40265#L1834 assume !(0 == start_simulation_~tmp~3#1); 40885#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40908#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40342#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40521#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 40733#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41141#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39634#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 39635#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 40772#L1815-2 [2021-11-13 18:09:42,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:42,828 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2021-11-13 18:09:42,828 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:42,829 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [115942066] [2021-11-13 18:09:42,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:42,829 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:42,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:42,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:42,872 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:42,872 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [115942066] [2021-11-13 18:09:42,872 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [115942066] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:42,875 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:42,875 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:42,877 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [463197133] [2021-11-13 18:09:42,877 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:42,878 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:42,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:42,879 INFO L85 PathProgramCache]: Analyzing trace with hash 2071608406, now seen corresponding path program 1 times [2021-11-13 18:09:42,879 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:42,879 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458359813] [2021-11-13 18:09:42,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:42,880 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:42,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:42,929 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:42,930 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:42,930 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1458359813] [2021-11-13 18:09:42,930 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1458359813] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:42,930 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:42,931 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:42,931 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1089478943] [2021-11-13 18:09:42,931 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:42,932 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:42,932 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:42,932 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:09:42,932 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:09:42,933 INFO L87 Difference]: Start difference. First operand 1790 states and 2645 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:43,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:43,012 INFO L93 Difference]: Finished difference Result 1790 states and 2644 transitions. [2021-11-13 18:09:43,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:09:43,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2644 transitions. [2021-11-13 18:09:43,027 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:43,041 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2644 transitions. [2021-11-13 18:09:43,041 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-13 18:09:43,043 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-13 18:09:43,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2644 transitions. [2021-11-13 18:09:43,047 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:43,048 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2644 transitions. [2021-11-13 18:09:43,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2644 transitions. [2021-11-13 18:09:43,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-13 18:09:43,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4770949720670392) internal successors, (2644), 1789 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:43,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2644 transitions. [2021-11-13 18:09:43,092 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2644 transitions. [2021-11-13 18:09:43,092 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2644 transitions. [2021-11-13 18:09:43,092 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-13 18:09:43,093 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2644 transitions. [2021-11-13 18:09:43,102 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:43,102 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:43,103 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:43,106 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:43,106 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:43,107 INFO L791 eck$LassoCheckResult]: Stem: 43904#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 43905#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 43328#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43298#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43299#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 44560#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43607#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43060#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43061#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44332#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44471#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44837#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44838#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 43817#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43818#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44358#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44278#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 44279#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44431#L1206 assume !(0 == ~M_E~0); 43796#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 43797#L1211-1 assume !(0 == ~T2_E~0); 44690#L1216-1 assume !(0 == ~T3_E~0); 43589#L1221-1 assume !(0 == ~T4_E~0); 43590#L1226-1 assume !(0 == ~T5_E~0); 43252#L1231-1 assume !(0 == ~T6_E~0); 43253#L1236-1 assume !(0 == ~T7_E~0); 44721#L1241-1 assume !(0 == ~T8_E~0); 43651#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43652#L1251-1 assume !(0 == ~T10_E~0); 43872#L1256-1 assume !(0 == ~T11_E~0); 43072#L1261-1 assume !(0 == ~T12_E~0); 43073#L1266-1 assume !(0 == ~E_M~0); 44824#L1271-1 assume !(0 == ~E_1~0); 44459#L1276-1 assume !(0 == ~E_2~0); 44460#L1281-1 assume !(0 == ~E_3~0); 44385#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 43493#L1291-1 assume !(0 == ~E_5~0); 43494#L1296-1 assume !(0 == ~E_6~0); 44200#L1301-1 assume !(0 == ~E_7~0); 44201#L1306-1 assume !(0 == ~E_8~0); 44633#L1311-1 assume !(0 == ~E_9~0); 43454#L1316-1 assume !(0 == ~E_10~0); 43455#L1321-1 assume !(0 == ~E_11~0); 44217#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 43318#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43319#L598 assume 1 == ~m_pc~0; 43378#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43379#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44703#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44795#L1497 assume !(0 != activate_threads_~tmp~1#1); 44796#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44752#L617 assume !(1 == ~t1_pc~0); 43674#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43675#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43534#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43535#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44295#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44296#L636 assume 1 == ~t2_pc~0; 43643#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43644#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43474#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43475#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 44331#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43994#L655 assume !(1 == ~t3_pc~0); 43995#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44708#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43348#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43349#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 44825#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44826#L674 assume 1 == ~t4_pc~0; 43168#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43169#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44466#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43476#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 43477#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43991#L693 assume !(1 == ~t5_pc~0); 44154#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 43798#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43799#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44635#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 43884#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43821#L712 assume 1 == ~t6_pc~0; 43822#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44249#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44250#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44536#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 44347#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44345#L731 assume 1 == ~t7_pc~0; 43322#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43323#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43517#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44454#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 44573#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43432#L750 assume !(1 == ~t8_pc~0); 43103#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 43102#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43618#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44648#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43755#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43756#L769 assume 1 == ~t9_pc~0; 44291#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43276#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43277#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44060#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 44512#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44593#L788 assume !(1 == ~t10_pc~0); 44168#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 44169#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44400#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 44401#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 43428#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43429#L807 assume 1 == ~t11_pc~0; 44602#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 44180#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44333#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 44744#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 44849#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44692#L826 assume !(1 == ~t12_pc~0); 43824#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 43825#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44353#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 44784#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 43984#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43893#L1344 assume !(1 == ~M_E~0); 43894#L1344-2 assume !(1 == ~T1_E~0); 44035#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44207#L1354-1 assume !(1 == ~T3_E~0); 44208#L1359-1 assume !(1 == ~T4_E~0); 44582#L1364-1 assume !(1 == ~T5_E~0); 43536#L1369-1 assume !(1 == ~T6_E~0); 43537#L1374-1 assume !(1 == ~T7_E~0); 44213#L1379-1 assume !(1 == ~T8_E~0); 44214#L1384-1 assume !(1 == ~T9_E~0); 44277#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44723#L1394-1 assume !(1 == ~T11_E~0); 44724#L1399-1 assume !(1 == ~T12_E~0); 44803#L1404-1 assume !(1 == ~E_M~0); 43655#L1409-1 assume !(1 == ~E_1~0); 43656#L1414-1 assume !(1 == ~E_2~0); 44493#L1419-1 assume !(1 == ~E_3~0); 43289#L1424-1 assume !(1 == ~E_4~0); 43290#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 44224#L1434-1 assume !(1 == ~E_6~0); 44742#L1439-1 assume !(1 == ~E_7~0); 43344#L1444-1 assume !(1 == ~E_8~0); 43345#L1449-1 assume !(1 == ~E_9~0); 43760#L1454-1 assume !(1 == ~E_10~0); 43761#L1459-1 assume !(1 == ~E_11~0); 44311#L1464-1 assume !(1 == ~E_12~0); 44312#L1469-1 assume { :end_inline_reset_delta_events } true; 44359#L1815-2 [2021-11-13 18:09:43,108 INFO L793 eck$LassoCheckResult]: Loop: 44359#L1815-2 assume !false; 44513#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44182#L1181 assume !false; 44253#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44205#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43063#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43792#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 44343#L1008 assume !(0 != eval_~tmp~0#1); 44344#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43282#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43283#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44843#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44310#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 43416#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43417#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44007#L1226-3 assume !(0 == ~T5_E~0); 43480#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43481#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43793#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44780#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44683#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44419#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43438#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43439#L1266-3 assume !(0 == ~E_M~0); 43478#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43479#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43951#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43952#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44489#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44490#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44832#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44800#L1306-3 assume !(0 == ~E_8~0); 44076#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43362#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 43363#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43440#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 44175#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44500#L598-42 assume !(1 == ~m_pc~0); 44501#L598-44 is_master_triggered_~__retres1~0#1 := 0; 44615#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43518#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43519#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 44801#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44231#L617-42 assume 1 == ~t1_pc~0; 44003#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43868#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43869#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44283#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43583#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43584#L636-42 assume 1 == ~t2_pc~0; 44785#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44048#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44398#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44399#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44578#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44440#L655-42 assume !(1 == ~t3_pc~0); 44020#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 44021#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43653#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43654#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44707#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44652#L674-42 assume !(1 == ~t4_pc~0); 44426#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 44348#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43237#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43238#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44152#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44153#L693-42 assume 1 == ~t5_pc~0; 44408#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44409#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44469#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44464#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44465#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43767#L712-42 assume !(1 == ~t6_pc~0); 43768#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 44094#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44302#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44303#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43876#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43877#L731-42 assume !(1 == ~t7_pc~0); 43575#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 43576#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44643#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43784#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43785#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43488#L750-42 assume 1 == ~t8_pc~0; 43489#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44063#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44486#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43381#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43382#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44151#L769-42 assume 1 == ~t9_pc~0; 43973#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43974#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44657#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44722#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 43585#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43586#L788-42 assume !(1 == ~t10_pc~0); 44160#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 44373#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44103#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 44104#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44841#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44819#L807-42 assume !(1 == ~t11_pc~0); 43189#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 43190#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43329#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 43330#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43331#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43580#L826-42 assume 1 == ~t12_pc~0; 43581#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43773#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44565#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 43570#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43571#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44422#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44423#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44349#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43730#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43731#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44363#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44821#L1369-3 assume !(1 == ~T6_E~0); 44741#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 43495#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 43496#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 43728#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43729#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 44027#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 44750#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44713#L1409-3 assume !(1 == ~E_1~0); 44714#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44779#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44559#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43396#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43397#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44362#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43336#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43337#L1449-3 assume !(1 == ~E_9~0); 43446#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44356#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44357#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44738#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44236#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43235#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43236#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 43852#L1834 assume !(0 == start_simulation_~tmp~3#1); 44472#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44495#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43929#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44108#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 44320#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44728#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43221#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 43222#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 44359#L1815-2 [2021-11-13 18:09:43,109 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:43,110 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2021-11-13 18:09:43,110 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:43,110 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [33942129] [2021-11-13 18:09:43,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:43,111 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:43,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:43,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:43,184 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:43,184 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [33942129] [2021-11-13 18:09:43,184 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [33942129] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:43,184 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:43,185 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:09:43,185 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [556262319] [2021-11-13 18:09:43,185 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:43,186 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:43,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:43,187 INFO L85 PathProgramCache]: Analyzing trace with hash 2024415830, now seen corresponding path program 1 times [2021-11-13 18:09:43,187 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:43,187 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1741181983] [2021-11-13 18:09:43,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:43,188 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:43,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:43,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:43,236 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:43,236 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1741181983] [2021-11-13 18:09:43,237 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1741181983] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:43,237 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:43,237 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:43,237 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [701661637] [2021-11-13 18:09:43,237 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:43,238 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:43,239 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:43,239 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:09:43,239 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:09:43,240 INFO L87 Difference]: Start difference. First operand 1790 states and 2644 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:43,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:43,288 INFO L93 Difference]: Finished difference Result 1790 states and 2639 transitions. [2021-11-13 18:09:43,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:09:43,289 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2639 transitions. [2021-11-13 18:09:43,302 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:43,314 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2639 transitions. [2021-11-13 18:09:43,314 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-13 18:09:43,317 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-13 18:09:43,317 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2639 transitions. [2021-11-13 18:09:43,321 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:43,321 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2639 transitions. [2021-11-13 18:09:43,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2639 transitions. [2021-11-13 18:09:43,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-13 18:09:43,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4743016759776537) internal successors, (2639), 1789 states have internal predecessors, (2639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:43,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2639 transitions. [2021-11-13 18:09:43,369 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2639 transitions. [2021-11-13 18:09:43,369 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2639 transitions. [2021-11-13 18:09:43,370 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-13 18:09:43,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2639 transitions. [2021-11-13 18:09:43,380 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:43,380 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:43,380 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:43,384 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:43,384 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:43,384 INFO L791 eck$LassoCheckResult]: Stem: 47493#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 47494#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 46917#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46890#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46891#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 48147#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47194#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46647#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46648#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47919#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48058#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48424#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48425#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 47406#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47407#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47945#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47865#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47866#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48018#L1206 assume !(0 == ~M_E~0); 47383#L1206-2 assume !(0 == ~T1_E~0); 47384#L1211-1 assume !(0 == ~T2_E~0); 48277#L1216-1 assume !(0 == ~T3_E~0); 47176#L1221-1 assume !(0 == ~T4_E~0); 47177#L1226-1 assume !(0 == ~T5_E~0); 46841#L1231-1 assume !(0 == ~T6_E~0); 46842#L1236-1 assume !(0 == ~T7_E~0); 48308#L1241-1 assume !(0 == ~T8_E~0); 47238#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47239#L1251-1 assume !(0 == ~T10_E~0); 47459#L1256-1 assume !(0 == ~T11_E~0); 46659#L1261-1 assume !(0 == ~T12_E~0); 46660#L1266-1 assume !(0 == ~E_M~0); 48411#L1271-1 assume !(0 == ~E_1~0); 48046#L1276-1 assume !(0 == ~E_2~0); 48047#L1281-1 assume !(0 == ~E_3~0); 47974#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 47080#L1291-1 assume !(0 == ~E_5~0); 47081#L1296-1 assume !(0 == ~E_6~0); 47787#L1301-1 assume !(0 == ~E_7~0); 47788#L1306-1 assume !(0 == ~E_8~0); 48220#L1311-1 assume !(0 == ~E_9~0); 47041#L1316-1 assume !(0 == ~E_10~0); 47042#L1321-1 assume !(0 == ~E_11~0); 47804#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 46907#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46908#L598 assume 1 == ~m_pc~0; 46965#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 46966#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48290#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48382#L1497 assume !(0 != activate_threads_~tmp~1#1); 48383#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48339#L617 assume !(1 == ~t1_pc~0); 47261#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47262#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47121#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47122#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47882#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47883#L636 assume 1 == ~t2_pc~0; 47230#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47231#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47061#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47062#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 47918#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47582#L655 assume !(1 == ~t3_pc~0); 47583#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48295#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46935#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46936#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 48412#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48413#L674 assume 1 == ~t4_pc~0; 46755#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46756#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48053#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47065#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 47066#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47578#L693 assume !(1 == ~t5_pc~0); 47741#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 47388#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47389#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48222#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 47471#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47408#L712 assume 1 == ~t6_pc~0; 47409#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47836#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47837#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48123#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 47934#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47932#L731 assume 1 == ~t7_pc~0; 46909#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46910#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47106#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48042#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 48160#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47019#L750 assume !(1 == ~t8_pc~0); 46690#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46689#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47205#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48235#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47342#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47343#L769 assume 1 == ~t9_pc~0; 47880#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46863#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46864#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47647#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 48099#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48180#L788 assume !(1 == ~t10_pc~0); 47755#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 47756#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47989#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 47990#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 47017#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47018#L807 assume 1 == ~t11_pc~0; 48189#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 47767#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47920#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 48331#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 48436#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48279#L826 assume !(1 == ~t12_pc~0); 47413#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 47414#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47940#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 48371#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 47571#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47480#L1344 assume !(1 == ~M_E~0); 47481#L1344-2 assume !(1 == ~T1_E~0); 47622#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47795#L1354-1 assume !(1 == ~T3_E~0); 47796#L1359-1 assume !(1 == ~T4_E~0); 48169#L1364-1 assume !(1 == ~T5_E~0); 47123#L1369-1 assume !(1 == ~T6_E~0); 47124#L1374-1 assume !(1 == ~T7_E~0); 47802#L1379-1 assume !(1 == ~T8_E~0); 47803#L1384-1 assume !(1 == ~T9_E~0); 47864#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48310#L1394-1 assume !(1 == ~T11_E~0); 48311#L1399-1 assume !(1 == ~T12_E~0); 48390#L1404-1 assume !(1 == ~E_M~0); 47242#L1409-1 assume !(1 == ~E_1~0); 47243#L1414-1 assume !(1 == ~E_2~0); 48080#L1419-1 assume !(1 == ~E_3~0); 46876#L1424-1 assume !(1 == ~E_4~0); 46877#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 47814#L1434-1 assume !(1 == ~E_6~0); 48329#L1439-1 assume !(1 == ~E_7~0); 46931#L1444-1 assume !(1 == ~E_8~0); 46932#L1449-1 assume !(1 == ~E_9~0); 47347#L1454-1 assume !(1 == ~E_10~0); 47348#L1459-1 assume !(1 == ~E_11~0); 47898#L1464-1 assume !(1 == ~E_12~0); 47899#L1469-1 assume { :end_inline_reset_delta_events } true; 47946#L1815-2 [2021-11-13 18:09:43,385 INFO L793 eck$LassoCheckResult]: Loop: 47946#L1815-2 assume !false; 48100#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47769#L1181 assume !false; 47840#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47792#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46650#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47380#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 47930#L1008 assume !(0 != eval_~tmp~0#1); 47931#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46871#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46872#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48430#L1206-5 assume !(0 == ~T1_E~0); 47897#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47003#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47004#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47594#L1226-3 assume !(0 == ~T5_E~0); 47067#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47068#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47379#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48367#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48270#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 48006#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47025#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47026#L1266-3 assume !(0 == ~E_M~0); 47063#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47064#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47538#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47539#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48076#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 48077#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 48419#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 48387#L1306-3 assume !(0 == ~E_8~0); 47663#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46949#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 46950#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47027#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 47761#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48087#L598-42 assume !(1 == ~m_pc~0); 48088#L598-44 is_master_triggered_~__retres1~0#1 := 0; 48202#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47104#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47105#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 48388#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47818#L617-42 assume 1 == ~t1_pc~0; 47590#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47455#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47456#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47870#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47170#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47171#L636-42 assume !(1 == ~t2_pc~0); 47634#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47635#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47985#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47986#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 48165#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48027#L655-42 assume !(1 == ~t3_pc~0); 47607#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 47608#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47240#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47241#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 48294#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48239#L674-42 assume 1 == ~t4_pc~0; 48240#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47935#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46824#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46825#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47739#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47740#L693-42 assume 1 == ~t5_pc~0; 47995#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47996#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48056#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48051#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48052#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47354#L712-42 assume !(1 == ~t6_pc~0); 47355#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 47681#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47889#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47890#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47463#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47464#L731-42 assume !(1 == ~t7_pc~0); 47162#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 47163#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48230#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47371#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47372#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47075#L750-42 assume 1 == ~t8_pc~0; 47076#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47650#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48073#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46968#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46969#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47738#L769-42 assume 1 == ~t9_pc~0; 47560#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47561#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48244#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 48309#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 47172#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47173#L788-42 assume 1 == ~t10_pc~0; 47746#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 47960#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47690#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 47691#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48428#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48406#L807-42 assume !(1 == ~t11_pc~0); 46776#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 46777#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46915#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46916#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46918#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47167#L826-42 assume 1 == ~t12_pc~0; 47168#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 47360#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48152#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 47157#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47158#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48009#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48010#L1344-5 assume !(1 == ~T1_E~0); 47936#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47317#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47318#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47950#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48408#L1369-3 assume !(1 == ~T6_E~0); 48328#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47082#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47083#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47315#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47316#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47614#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 48337#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 48300#L1409-3 assume !(1 == ~E_1~0); 48301#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48366#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48146#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46983#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46984#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47949#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46923#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46924#L1449-3 assume !(1 == ~E_9~0); 47033#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47943#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 47944#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 48325#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47823#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46822#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 46823#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 47439#L1834 assume !(0 == start_simulation_~tmp~3#1); 48059#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 48082#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47516#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47695#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 47907#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48315#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46808#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 46809#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 47946#L1815-2 [2021-11-13 18:09:43,386 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:43,386 INFO L85 PathProgramCache]: Analyzing trace with hash -2089382286, now seen corresponding path program 1 times [2021-11-13 18:09:43,386 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:43,386 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2061611678] [2021-11-13 18:09:43,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:43,387 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:43,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:43,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:43,440 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:43,440 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2061611678] [2021-11-13 18:09:43,440 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2061611678] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:43,440 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:43,441 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:09:43,441 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [98815873] [2021-11-13 18:09:43,441 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:43,444 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:43,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:43,445 INFO L85 PathProgramCache]: Analyzing trace with hash 351618645, now seen corresponding path program 1 times [2021-11-13 18:09:43,445 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:43,445 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1084905223] [2021-11-13 18:09:43,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:43,447 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:43,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:43,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:43,506 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:43,506 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1084905223] [2021-11-13 18:09:43,506 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1084905223] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:43,506 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:43,507 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:43,507 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [992407330] [2021-11-13 18:09:43,507 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:43,508 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:43,508 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:43,508 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:09:43,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:09:43,509 INFO L87 Difference]: Start difference. First operand 1790 states and 2639 transitions. cyclomatic complexity: 850 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:43,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:43,557 INFO L93 Difference]: Finished difference Result 1790 states and 2634 transitions. [2021-11-13 18:09:43,558 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:09:43,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2634 transitions. [2021-11-13 18:09:43,570 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:43,592 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2634 transitions. [2021-11-13 18:09:43,592 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-13 18:09:43,594 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-13 18:09:43,595 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2634 transitions. [2021-11-13 18:09:43,598 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:43,599 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2634 transitions. [2021-11-13 18:09:43,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2634 transitions. [2021-11-13 18:09:43,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-13 18:09:43,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4715083798882682) internal successors, (2634), 1789 states have internal predecessors, (2634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:43,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2634 transitions. [2021-11-13 18:09:43,645 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2634 transitions. [2021-11-13 18:09:43,645 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2634 transitions. [2021-11-13 18:09:43,645 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-13 18:09:43,646 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2634 transitions. [2021-11-13 18:09:43,655 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:43,655 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:43,655 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:43,658 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:43,658 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:43,659 INFO L791 eck$LassoCheckResult]: Stem: 51078#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 51079#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 50504#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50474#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50475#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 51734#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50781#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50234#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50235#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51506#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 51645#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 52011#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 52012#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50993#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50994#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 51532#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 51452#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 51453#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 51605#L1206 assume !(0 == ~M_E~0); 50970#L1206-2 assume !(0 == ~T1_E~0); 50971#L1211-1 assume !(0 == ~T2_E~0); 51864#L1216-1 assume !(0 == ~T3_E~0); 50763#L1221-1 assume !(0 == ~T4_E~0); 50764#L1226-1 assume !(0 == ~T5_E~0); 50428#L1231-1 assume !(0 == ~T6_E~0); 50429#L1236-1 assume !(0 == ~T7_E~0); 51895#L1241-1 assume !(0 == ~T8_E~0); 50825#L1246-1 assume !(0 == ~T9_E~0); 50826#L1251-1 assume !(0 == ~T10_E~0); 51046#L1256-1 assume !(0 == ~T11_E~0); 50246#L1261-1 assume !(0 == ~T12_E~0); 50247#L1266-1 assume !(0 == ~E_M~0); 51998#L1271-1 assume !(0 == ~E_1~0); 51633#L1276-1 assume !(0 == ~E_2~0); 51634#L1281-1 assume !(0 == ~E_3~0); 51561#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 50667#L1291-1 assume !(0 == ~E_5~0); 50668#L1296-1 assume !(0 == ~E_6~0); 51374#L1301-1 assume !(0 == ~E_7~0); 51375#L1306-1 assume !(0 == ~E_8~0); 51807#L1311-1 assume !(0 == ~E_9~0); 50628#L1316-1 assume !(0 == ~E_10~0); 50629#L1321-1 assume !(0 == ~E_11~0); 51391#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 50494#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50495#L598 assume 1 == ~m_pc~0; 50552#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 50553#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51877#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51969#L1497 assume !(0 != activate_threads_~tmp~1#1); 51970#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51926#L617 assume !(1 == ~t1_pc~0); 50848#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50849#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50708#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50709#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51469#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51470#L636 assume 1 == ~t2_pc~0; 50817#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50818#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50648#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50649#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 51505#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51168#L655 assume !(1 == ~t3_pc~0); 51169#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 51882#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50522#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50523#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 51999#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52000#L674 assume 1 == ~t4_pc~0; 50342#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50343#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51640#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50650#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 50651#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51165#L693 assume !(1 == ~t5_pc~0); 51328#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 50975#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50976#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51809#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 51058#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50995#L712 assume 1 == ~t6_pc~0; 50996#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 51423#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51424#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51710#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 51521#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51519#L731 assume 1 == ~t7_pc~0; 50496#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50497#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50691#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 51629#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 51747#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50606#L750 assume !(1 == ~t8_pc~0); 50277#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50276#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50792#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51822#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50929#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50930#L769 assume 1 == ~t9_pc~0; 51467#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50450#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50451#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 51234#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 51686#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51767#L788 assume !(1 == ~t10_pc~0); 51342#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 51343#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51575#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 51576#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 50602#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50603#L807 assume 1 == ~t11_pc~0; 51776#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 51354#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51507#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 51918#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 52023#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51866#L826 assume !(1 == ~t12_pc~0); 51000#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 51001#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51527#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 51958#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 51158#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51067#L1344 assume !(1 == ~M_E~0); 51068#L1344-2 assume !(1 == ~T1_E~0); 51209#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 51382#L1354-1 assume !(1 == ~T3_E~0); 51383#L1359-1 assume !(1 == ~T4_E~0); 51756#L1364-1 assume !(1 == ~T5_E~0); 50710#L1369-1 assume !(1 == ~T6_E~0); 50711#L1374-1 assume !(1 == ~T7_E~0); 51389#L1379-1 assume !(1 == ~T8_E~0); 51390#L1384-1 assume !(1 == ~T9_E~0); 51451#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51897#L1394-1 assume !(1 == ~T11_E~0); 51898#L1399-1 assume !(1 == ~T12_E~0); 51977#L1404-1 assume !(1 == ~E_M~0); 50829#L1409-1 assume !(1 == ~E_1~0); 50830#L1414-1 assume !(1 == ~E_2~0); 51667#L1419-1 assume !(1 == ~E_3~0); 50463#L1424-1 assume !(1 == ~E_4~0); 50464#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 51401#L1434-1 assume !(1 == ~E_6~0); 51916#L1439-1 assume !(1 == ~E_7~0); 50518#L1444-1 assume !(1 == ~E_8~0); 50519#L1449-1 assume !(1 == ~E_9~0); 50934#L1454-1 assume !(1 == ~E_10~0); 50935#L1459-1 assume !(1 == ~E_11~0); 51485#L1464-1 assume !(1 == ~E_12~0); 51486#L1469-1 assume { :end_inline_reset_delta_events } true; 51533#L1815-2 [2021-11-13 18:09:43,659 INFO L793 eck$LassoCheckResult]: Loop: 51533#L1815-2 assume !false; 51687#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51356#L1181 assume !false; 51427#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 51379#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 50237#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 50966#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 51517#L1008 assume !(0 != eval_~tmp~0#1); 51518#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50458#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50459#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 52017#L1206-5 assume !(0 == ~T1_E~0); 51484#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50590#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50591#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51181#L1226-3 assume !(0 == ~T5_E~0); 50654#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50655#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50967#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51955#L1246-3 assume !(0 == ~T9_E~0); 51857#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51593#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 50614#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 50615#L1266-3 assume !(0 == ~E_M~0); 50652#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50653#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51125#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 51126#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51663#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51664#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 52006#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51974#L1306-3 assume !(0 == ~E_8~0); 51250#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50536#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50537#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 50616#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 51349#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51674#L598-42 assume !(1 == ~m_pc~0); 51675#L598-44 is_master_triggered_~__retres1~0#1 := 0; 51789#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50692#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50693#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 51975#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51404#L617-42 assume 1 == ~t1_pc~0; 51177#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 51042#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51043#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51457#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50757#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50758#L636-42 assume !(1 == ~t2_pc~0); 51220#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 51221#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51571#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51572#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 51752#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51611#L655-42 assume !(1 == ~t3_pc~0); 51194#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 51195#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50827#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50828#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51881#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51826#L674-42 assume !(1 == ~t4_pc~0); 51600#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 51522#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50411#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50412#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51326#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51327#L693-42 assume !(1 == ~t5_pc~0); 51584#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 51583#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51643#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51637#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 51638#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50941#L712-42 assume !(1 == ~t6_pc~0); 50942#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 51268#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51476#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51477#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 51050#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51051#L731-42 assume 1 == ~t7_pc~0; 50912#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50750#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51817#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50958#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50959#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50662#L750-42 assume 1 == ~t8_pc~0; 50663#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 51237#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51660#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50555#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50556#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51325#L769-42 assume 1 == ~t9_pc~0; 51146#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51147#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51831#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 51896#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 50759#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50760#L788-42 assume 1 == ~t10_pc~0; 51333#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 51547#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51277#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 51278#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 52015#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51992#L807-42 assume 1 == ~t11_pc~0; 51682#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 50364#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50502#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50503#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50505#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50754#L826-42 assume 1 == ~t12_pc~0; 50755#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50947#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51739#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 50744#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 50745#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51596#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 51597#L1344-5 assume !(1 == ~T1_E~0); 51523#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50904#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50905#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51537#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 51995#L1369-3 assume !(1 == ~T6_E~0); 51915#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50669#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50670#L1384-3 assume !(1 == ~T9_E~0); 50902#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50903#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 51201#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51924#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 51887#L1409-3 assume !(1 == ~E_1~0); 51888#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 51953#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 51733#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50570#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50571#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51536#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50510#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50511#L1449-3 assume !(1 == ~E_9~0); 50620#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51529#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 51530#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 51912#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 51410#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 50409#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 50410#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 51026#L1834 assume !(0 == start_simulation_~tmp~3#1); 51646#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 51669#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 51103#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 51282#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 51494#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51902#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50395#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 50396#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 51533#L1815-2 [2021-11-13 18:09:43,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:43,660 INFO L85 PathProgramCache]: Analyzing trace with hash -1227548684, now seen corresponding path program 1 times [2021-11-13 18:09:43,661 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:43,661 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [725957153] [2021-11-13 18:09:43,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:43,661 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:43,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:43,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:43,704 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:43,704 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [725957153] [2021-11-13 18:09:43,704 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [725957153] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:43,704 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:43,704 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:09:43,705 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1782609746] [2021-11-13 18:09:43,705 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:43,705 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:43,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:43,706 INFO L85 PathProgramCache]: Analyzing trace with hash -930076331, now seen corresponding path program 1 times [2021-11-13 18:09:43,706 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:43,707 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [38990883] [2021-11-13 18:09:43,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:43,707 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:43,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:43,748 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:43,748 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:43,749 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [38990883] [2021-11-13 18:09:43,749 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [38990883] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:43,750 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:43,750 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:43,750 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1543700117] [2021-11-13 18:09:43,750 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:43,751 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:43,751 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:43,751 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:09:43,752 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:09:43,752 INFO L87 Difference]: Start difference. First operand 1790 states and 2634 transitions. cyclomatic complexity: 845 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:43,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:43,883 INFO L93 Difference]: Finished difference Result 1790 states and 2614 transitions. [2021-11-13 18:09:43,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:09:43,884 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2614 transitions. [2021-11-13 18:09:43,895 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:43,908 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2614 transitions. [2021-11-13 18:09:43,908 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-13 18:09:43,910 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-13 18:09:43,911 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2614 transitions. [2021-11-13 18:09:43,914 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:43,914 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2614 transitions. [2021-11-13 18:09:43,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2614 transitions. [2021-11-13 18:09:43,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-13 18:09:43,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4603351955307262) internal successors, (2614), 1789 states have internal predecessors, (2614), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:43,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2614 transitions. [2021-11-13 18:09:43,952 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2614 transitions. [2021-11-13 18:09:43,952 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2614 transitions. [2021-11-13 18:09:43,953 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-13 18:09:43,953 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2614 transitions. [2021-11-13 18:09:43,961 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:43,961 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:43,961 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:43,964 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:43,965 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:43,965 INFO L791 eck$LassoCheckResult]: Stem: 54662#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 54663#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 54090#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54058#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54059#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 55318#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54366#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53821#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53822#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55090#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55229#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 55598#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55599#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 54578#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54579#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 55117#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 55036#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 55037#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55189#L1206 assume !(0 == ~M_E~0); 54555#L1206-2 assume !(0 == ~T1_E~0); 54556#L1211-1 assume !(0 == ~T2_E~0); 55448#L1216-1 assume !(0 == ~T3_E~0); 54348#L1221-1 assume !(0 == ~T4_E~0); 54349#L1226-1 assume !(0 == ~T5_E~0); 54012#L1231-1 assume !(0 == ~T6_E~0); 54013#L1236-1 assume !(0 == ~T7_E~0); 55480#L1241-1 assume !(0 == ~T8_E~0); 54410#L1246-1 assume !(0 == ~T9_E~0); 54411#L1251-1 assume !(0 == ~T10_E~0); 54631#L1256-1 assume !(0 == ~T11_E~0); 53833#L1261-1 assume !(0 == ~T12_E~0); 53834#L1266-1 assume !(0 == ~E_M~0); 55583#L1271-1 assume !(0 == ~E_1~0); 55217#L1276-1 assume !(0 == ~E_2~0); 55218#L1281-1 assume !(0 == ~E_3~0); 55144#L1286-1 assume !(0 == ~E_4~0); 54252#L1291-1 assume !(0 == ~E_5~0); 54253#L1296-1 assume !(0 == ~E_6~0); 54958#L1301-1 assume !(0 == ~E_7~0); 54959#L1306-1 assume !(0 == ~E_8~0); 55391#L1311-1 assume !(0 == ~E_9~0); 54214#L1316-1 assume !(0 == ~E_10~0); 54215#L1321-1 assume !(0 == ~E_11~0); 54975#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 54078#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54079#L598 assume 1 == ~m_pc~0; 54138#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 54139#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55462#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 55554#L1497 assume !(0 != activate_threads_~tmp~1#1); 55555#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55511#L617 assume !(1 == ~t1_pc~0); 54433#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54434#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54293#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54294#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55053#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55054#L636 assume 1 == ~t2_pc~0; 54402#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54403#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54234#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54235#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 55089#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54752#L655 assume !(1 == ~t3_pc~0); 54753#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 55467#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54108#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54109#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 55584#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55585#L674 assume !(1 == ~t4_pc~0); 53930#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 55451#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55224#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54236#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 54237#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54749#L693 assume !(1 == ~t5_pc~0); 54912#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 54558#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54559#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55393#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 54643#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54580#L712 assume 1 == ~t6_pc~0; 54581#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 55007#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55008#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 55294#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 55105#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 55103#L731 assume 1 == ~t7_pc~0; 54082#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 54083#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54276#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 55212#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 55331#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54192#L750 assume !(1 == ~t8_pc~0); 53864#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 53863#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54377#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55406#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 54514#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54515#L769 assume 1 == ~t9_pc~0; 55051#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54036#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54037#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54818#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 55270#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55351#L788 assume !(1 == ~t10_pc~0); 54926#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 54927#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 55160#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 55161#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 54188#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54189#L807 assume 1 == ~t11_pc~0; 55360#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54938#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 55091#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 55503#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 55610#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 55450#L826 assume !(1 == ~t12_pc~0); 54583#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 54584#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55112#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 55543#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 54742#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54651#L1344 assume !(1 == ~M_E~0); 54652#L1344-2 assume !(1 == ~T1_E~0); 54793#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54966#L1354-1 assume !(1 == ~T3_E~0); 54967#L1359-1 assume !(1 == ~T4_E~0); 55340#L1364-1 assume !(1 == ~T5_E~0); 54295#L1369-1 assume !(1 == ~T6_E~0); 54296#L1374-1 assume !(1 == ~T7_E~0); 54973#L1379-1 assume !(1 == ~T8_E~0); 54974#L1384-1 assume !(1 == ~T9_E~0); 55035#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 55482#L1394-1 assume !(1 == ~T11_E~0); 55483#L1399-1 assume !(1 == ~T12_E~0); 55562#L1404-1 assume !(1 == ~E_M~0); 54414#L1409-1 assume !(1 == ~E_1~0); 54415#L1414-1 assume !(1 == ~E_2~0); 55251#L1419-1 assume !(1 == ~E_3~0); 54049#L1424-1 assume !(1 == ~E_4~0); 54050#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54982#L1434-1 assume !(1 == ~E_6~0); 55501#L1439-1 assume !(1 == ~E_7~0); 54104#L1444-1 assume !(1 == ~E_8~0); 54105#L1449-1 assume !(1 == ~E_9~0); 54519#L1454-1 assume !(1 == ~E_10~0); 54520#L1459-1 assume !(1 == ~E_11~0); 55069#L1464-1 assume !(1 == ~E_12~0); 55070#L1469-1 assume { :end_inline_reset_delta_events } true; 55118#L1815-2 [2021-11-13 18:09:43,966 INFO L793 eck$LassoCheckResult]: Loop: 55118#L1815-2 assume !false; 55271#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54940#L1181 assume !false; 55011#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 54963#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 53824#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54551#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 55101#L1008 assume !(0 != eval_~tmp~0#1); 55102#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54044#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54045#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 55604#L1206-5 assume !(0 == ~T1_E~0); 55068#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54176#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54177#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54765#L1226-3 assume !(0 == ~T5_E~0); 54240#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 54241#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 54552#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 55540#L1246-3 assume !(0 == ~T9_E~0); 55441#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 55178#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 54198#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 54199#L1266-3 assume !(0 == ~E_M~0); 54238#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54239#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54709#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54710#L1286-3 assume !(0 == ~E_4~0); 55247#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 55248#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 55591#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 55559#L1306-3 assume !(0 == ~E_8~0); 54834#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 54122#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 54123#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 54200#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 54933#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55258#L598-42 assume !(1 == ~m_pc~0); 55259#L598-44 is_master_triggered_~__retres1~0#1 := 0; 55373#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54277#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54278#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 55560#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54989#L617-42 assume 1 == ~t1_pc~0; 54762#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 54627#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54628#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 55041#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54342#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54343#L636-42 assume !(1 == ~t2_pc~0); 54805#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 54806#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55157#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55158#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55336#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55198#L655-42 assume !(1 == ~t3_pc~0); 54782#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 54783#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54412#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54413#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 55466#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55410#L674-42 assume !(1 == ~t4_pc~0); 55184#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 55106#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53997#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53998#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54910#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54911#L693-42 assume 1 == ~t5_pc~0; 55170#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55171#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55227#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55222#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 55223#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54526#L712-42 assume 1 == ~t6_pc~0; 54528#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 54850#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55060#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 55061#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54635#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54636#L731-42 assume 1 == ~t7_pc~0; 54497#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 54332#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55401#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54543#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54544#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54244#L750-42 assume 1 == ~t8_pc~0; 54245#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54821#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55244#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54141#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 54142#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54909#L769-42 assume 1 == ~t9_pc~0; 54729#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54730#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55415#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55481#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 54344#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54345#L788-42 assume 1 == ~t10_pc~0; 54917#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 55130#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54861#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54862#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 55602#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55576#L807-42 assume 1 == ~t11_pc~0; 55266#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53950#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54088#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54089#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 54091#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54339#L826-42 assume 1 == ~t12_pc~0; 54340#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 54532#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55323#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 54329#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 54330#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55181#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 55182#L1344-5 assume !(1 == ~T1_E~0); 55107#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54489#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54490#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55122#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 55580#L1369-3 assume !(1 == ~T6_E~0); 55500#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54254#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54255#L1384-3 assume !(1 == ~T9_E~0); 54487#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54488#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54785#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 55509#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 55472#L1409-3 assume !(1 == ~E_1~0); 55473#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 55538#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 55317#L1424-3 assume !(1 == ~E_4~0); 54156#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54157#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 55121#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 54094#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 54095#L1449-3 assume !(1 == ~E_9~0); 54206#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 55114#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 55115#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 55497#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 54994#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 53995#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 53996#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 54611#L1834 assume !(0 == start_simulation_~tmp~3#1); 55230#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 55253#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 54687#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54866#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 55078#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 55487#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53981#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 53982#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 55118#L1815-2 [2021-11-13 18:09:43,966 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:43,967 INFO L85 PathProgramCache]: Analyzing trace with hash -2133589833, now seen corresponding path program 1 times [2021-11-13 18:09:43,967 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:43,967 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1988833814] [2021-11-13 18:09:43,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:43,968 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:43,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:44,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:44,006 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:44,007 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1988833814] [2021-11-13 18:09:44,007 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1988833814] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:44,007 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:44,007 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:09:44,007 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [632478315] [2021-11-13 18:09:44,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:44,008 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:44,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:44,008 INFO L85 PathProgramCache]: Analyzing trace with hash -1120480941, now seen corresponding path program 1 times [2021-11-13 18:09:44,009 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:44,009 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1528828625] [2021-11-13 18:09:44,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:44,009 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:44,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:44,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:44,048 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:44,049 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1528828625] [2021-11-13 18:09:44,049 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1528828625] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:44,049 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:44,049 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:44,049 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1249035533] [2021-11-13 18:09:44,050 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:44,050 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:44,050 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:44,051 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:09:44,051 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:09:44,051 INFO L87 Difference]: Start difference. First operand 1790 states and 2614 transitions. cyclomatic complexity: 825 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:44,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:44,137 INFO L93 Difference]: Finished difference Result 1790 states and 2594 transitions. [2021-11-13 18:09:44,138 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:09:44,138 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2594 transitions. [2021-11-13 18:09:44,148 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:44,155 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2594 transitions. [2021-11-13 18:09:44,155 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-13 18:09:44,157 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-13 18:09:44,158 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2594 transitions. [2021-11-13 18:09:44,162 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:44,162 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2594 transitions. [2021-11-13 18:09:44,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2594 transitions. [2021-11-13 18:09:44,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-13 18:09:44,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4491620111731844) internal successors, (2594), 1789 states have internal predecessors, (2594), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:44,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2594 transitions. [2021-11-13 18:09:44,202 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2594 transitions. [2021-11-13 18:09:44,202 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2594 transitions. [2021-11-13 18:09:44,202 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-13 18:09:44,202 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2594 transitions. [2021-11-13 18:09:44,214 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-13 18:09:44,214 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:44,214 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:44,218 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:44,218 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:44,219 INFO L791 eck$LassoCheckResult]: Stem: 58246#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 58247#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 57673#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 57643#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 57644#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 58905#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 57950#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 57408#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 57409#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 58675#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 58814#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59185#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59186#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 58160#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 58161#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 58702#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 58620#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 58621#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 58774#L1206 assume !(0 == ~M_E~0); 58139#L1206-2 assume !(0 == ~T1_E~0); 58140#L1211-1 assume !(0 == ~T2_E~0); 59035#L1216-1 assume !(0 == ~T3_E~0); 57932#L1221-1 assume !(0 == ~T4_E~0); 57933#L1226-1 assume !(0 == ~T5_E~0); 57598#L1231-1 assume !(0 == ~T6_E~0); 57599#L1236-1 assume !(0 == ~T7_E~0); 59066#L1241-1 assume !(0 == ~T8_E~0); 57994#L1246-1 assume !(0 == ~T9_E~0); 57995#L1251-1 assume !(0 == ~T10_E~0); 58215#L1256-1 assume !(0 == ~T11_E~0); 57420#L1261-1 assume !(0 == ~T12_E~0); 57421#L1266-1 assume !(0 == ~E_M~0); 59170#L1271-1 assume !(0 == ~E_1~0); 58802#L1276-1 assume !(0 == ~E_2~0); 58803#L1281-1 assume !(0 == ~E_3~0); 58729#L1286-1 assume !(0 == ~E_4~0); 57837#L1291-1 assume !(0 == ~E_5~0); 57838#L1296-1 assume !(0 == ~E_6~0); 58542#L1301-1 assume !(0 == ~E_7~0); 58543#L1306-1 assume !(0 == ~E_8~0); 58978#L1311-1 assume !(0 == ~E_9~0); 57799#L1316-1 assume !(0 == ~E_10~0); 57800#L1321-1 assume !(0 == ~E_11~0); 58559#L1326-1 assume !(0 == ~E_12~0); 57663#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57664#L598 assume 1 == ~m_pc~0; 57722#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 57723#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59049#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59141#L1497 assume !(0 != activate_threads_~tmp~1#1); 59142#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59097#L617 assume !(1 == ~t1_pc~0); 58017#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 58018#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57878#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57879#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58637#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58638#L636 assume 1 == ~t2_pc~0; 57986#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 57987#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57819#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 57820#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 58674#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58336#L655 assume !(1 == ~t3_pc~0); 58337#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59054#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57693#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 57694#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 59171#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59172#L674 assume !(1 == ~t4_pc~0); 57516#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 59038#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58809#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 57821#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 57822#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58333#L693 assume !(1 == ~t5_pc~0); 58496#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 58141#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58142#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58980#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 58227#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58164#L712 assume 1 == ~t6_pc~0; 58165#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 58591#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58592#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58880#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 58690#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58688#L731 assume 1 == ~t7_pc~0; 57667#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 57668#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57861#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58797#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 58918#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57776#L750 assume !(1 == ~t8_pc~0); 57451#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 57450#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57961#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58993#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 58098#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58099#L769 assume 1 == ~t9_pc~0; 58635#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 57622#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 57623#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58402#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 58856#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58938#L788 assume !(1 == ~t10_pc~0); 58510#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 58511#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58744#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 58745#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 57772#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 57773#L807 assume 1 == ~t11_pc~0; 58947#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 58522#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58676#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 59089#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 59197#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59037#L826 assume !(1 == ~t12_pc~0); 58167#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 58168#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58697#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 59129#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 58326#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58235#L1344 assume !(1 == ~M_E~0); 58236#L1344-2 assume !(1 == ~T1_E~0); 58377#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58549#L1354-1 assume !(1 == ~T3_E~0); 58550#L1359-1 assume !(1 == ~T4_E~0); 58927#L1364-1 assume !(1 == ~T5_E~0); 57880#L1369-1 assume !(1 == ~T6_E~0); 57881#L1374-1 assume !(1 == ~T7_E~0); 58555#L1379-1 assume !(1 == ~T8_E~0); 58556#L1384-1 assume !(1 == ~T9_E~0); 58619#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 59068#L1394-1 assume !(1 == ~T11_E~0); 59069#L1399-1 assume !(1 == ~T12_E~0); 59149#L1404-1 assume !(1 == ~E_M~0); 57998#L1409-1 assume !(1 == ~E_1~0); 57999#L1414-1 assume !(1 == ~E_2~0); 58836#L1419-1 assume !(1 == ~E_3~0); 57634#L1424-1 assume !(1 == ~E_4~0); 57635#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 58566#L1434-1 assume !(1 == ~E_6~0); 59087#L1439-1 assume !(1 == ~E_7~0); 57689#L1444-1 assume !(1 == ~E_8~0); 57690#L1449-1 assume !(1 == ~E_9~0); 58103#L1454-1 assume !(1 == ~E_10~0); 58104#L1459-1 assume !(1 == ~E_11~0); 58653#L1464-1 assume !(1 == ~E_12~0); 58654#L1469-1 assume { :end_inline_reset_delta_events } true; 58703#L1815-2 [2021-11-13 18:09:44,220 INFO L793 eck$LassoCheckResult]: Loop: 58703#L1815-2 assume !false; 58857#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 58524#L1181 assume !false; 58595#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 58547#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 57411#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 58135#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 58686#L1008 assume !(0 != eval_~tmp~0#1); 58687#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57628#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 57629#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 59191#L1206-5 assume !(0 == ~T1_E~0); 58652#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 57760#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57761#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 58349#L1226-3 assume !(0 == ~T5_E~0); 57825#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 57826#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 58136#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59125#L1246-3 assume !(0 == ~T9_E~0); 59028#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 58763#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 57782#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 57783#L1266-3 assume !(0 == ~E_M~0); 57823#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 57824#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 58293#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 58294#L1286-3 assume !(0 == ~E_4~0); 58832#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 58833#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 59178#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 59146#L1306-3 assume !(0 == ~E_8~0); 58418#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 57706#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 57707#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 57784#L1326-3 assume !(0 == ~E_12~0); 58517#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58844#L598-42 assume !(1 == ~m_pc~0); 58845#L598-44 is_master_triggered_~__retres1~0#1 := 0; 58960#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 57862#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57863#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 59147#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58573#L617-42 assume 1 == ~t1_pc~0; 58345#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58211#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58212#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58625#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57926#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57927#L636-42 assume !(1 == ~t2_pc~0); 58389#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 58390#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58742#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58743#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58923#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58783#L655-42 assume 1 == ~t3_pc~0; 58784#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58363#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57996#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 57997#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59053#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58997#L674-42 assume !(1 == ~t4_pc~0); 58769#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 58691#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57583#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 57584#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58494#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58495#L693-42 assume 1 == ~t5_pc~0; 58752#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58753#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58812#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58807#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 58808#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58110#L712-42 assume 1 == ~t6_pc~0; 58112#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 58436#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58644#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58645#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58219#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58220#L731-42 assume 1 == ~t7_pc~0; 58083#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 57920#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58988#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58127#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 58128#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57832#L750-42 assume 1 == ~t8_pc~0; 57833#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 58408#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58829#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 57725#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 57726#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58493#L769-42 assume !(1 == ~t9_pc~0); 58320#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 58319#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59002#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 59067#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 57928#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57929#L788-42 assume 1 == ~t10_pc~0; 58501#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 58718#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58445#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 58446#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59189#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59165#L807-42 assume 1 == ~t11_pc~0; 58852#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 57536#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 57674#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 57675#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 57676#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 57923#L826-42 assume !(1 == ~t12_pc~0); 57925#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 58116#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58910#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 57914#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 57915#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58766#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 58767#L1344-5 assume !(1 == ~T1_E~0); 58692#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58073#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58074#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58707#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 59167#L1369-3 assume !(1 == ~T6_E~0); 59086#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 57839#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 57840#L1384-3 assume !(1 == ~T9_E~0); 58071#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 58072#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 58369#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 59095#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59059#L1409-3 assume !(1 == ~E_1~0); 59060#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 59124#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 58904#L1424-3 assume !(1 == ~E_4~0); 57740#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57741#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 58706#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 57681#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 57682#L1449-3 assume !(1 == ~E_9~0); 57791#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 58700#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 58701#L1464-3 assume !(1 == ~E_12~0); 59083#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 58578#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 57581#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 57582#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 58195#L1834 assume !(0 == start_simulation_~tmp~3#1); 58815#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 58838#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 58272#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 58450#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 58662#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 59073#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57567#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 57568#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 58703#L1815-2 [2021-11-13 18:09:44,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:44,221 INFO L85 PathProgramCache]: Analyzing trace with hash 19516985, now seen corresponding path program 1 times [2021-11-13 18:09:44,221 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:44,221 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1607527788] [2021-11-13 18:09:44,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:44,222 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:44,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:44,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:44,270 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:44,270 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1607527788] [2021-11-13 18:09:44,271 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1607527788] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:44,271 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:44,271 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:09:44,271 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [264313841] [2021-11-13 18:09:44,271 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:44,272 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:44,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:44,273 INFO L85 PathProgramCache]: Analyzing trace with hash -1599752876, now seen corresponding path program 1 times [2021-11-13 18:09:44,273 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:44,273 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [830196138] [2021-11-13 18:09:44,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:44,274 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:44,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:44,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:44,321 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:44,322 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [830196138] [2021-11-13 18:09:44,322 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [830196138] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:44,322 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:44,322 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:44,322 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1198570930] [2021-11-13 18:09:44,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:44,323 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:44,323 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:44,324 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:09:44,324 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:09:44,324 INFO L87 Difference]: Start difference. First operand 1790 states and 2594 transitions. cyclomatic complexity: 805 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:44,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:44,463 INFO L93 Difference]: Finished difference Result 3393 states and 4880 transitions. [2021-11-13 18:09:44,463 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:09:44,464 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3393 states and 4880 transitions. [2021-11-13 18:09:44,482 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3230 [2021-11-13 18:09:44,496 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3393 states to 3393 states and 4880 transitions. [2021-11-13 18:09:44,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3393 [2021-11-13 18:09:44,500 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3393 [2021-11-13 18:09:44,501 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3393 states and 4880 transitions. [2021-11-13 18:09:44,507 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:44,508 INFO L681 BuchiCegarLoop]: Abstraction has 3393 states and 4880 transitions. [2021-11-13 18:09:44,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3393 states and 4880 transitions. [2021-11-13 18:09:44,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3393 to 3303. [2021-11-13 18:09:44,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3303 states, 3303 states have (on average 1.4396003633060854) internal successors, (4755), 3302 states have internal predecessors, (4755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:44,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3303 states to 3303 states and 4755 transitions. [2021-11-13 18:09:44,599 INFO L704 BuchiCegarLoop]: Abstraction has 3303 states and 4755 transitions. [2021-11-13 18:09:44,600 INFO L587 BuchiCegarLoop]: Abstraction has 3303 states and 4755 transitions. [2021-11-13 18:09:44,600 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-13 18:09:44,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3303 states and 4755 transitions. [2021-11-13 18:09:44,646 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3140 [2021-11-13 18:09:44,647 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:44,647 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:44,651 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:44,651 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:44,652 INFO L791 eck$LassoCheckResult]: Stem: 63434#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 63435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 62862#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62832#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62833#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 64112#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63137#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62598#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62599#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63876#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64019#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64443#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 64444#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 63348#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 63349#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 63904#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 63819#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 63820#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63979#L1206 assume !(0 == ~M_E~0); 63327#L1206-2 assume !(0 == ~T1_E~0); 63328#L1211-1 assume !(0 == ~T2_E~0); 64262#L1216-1 assume !(0 == ~T3_E~0); 63119#L1221-1 assume !(0 == ~T4_E~0); 63120#L1226-1 assume !(0 == ~T5_E~0); 62787#L1231-1 assume !(0 == ~T6_E~0); 62788#L1236-1 assume !(0 == ~T7_E~0); 64296#L1241-1 assume !(0 == ~T8_E~0); 63182#L1246-1 assume !(0 == ~T9_E~0); 63183#L1251-1 assume !(0 == ~T10_E~0); 63403#L1256-1 assume !(0 == ~T11_E~0); 62610#L1261-1 assume !(0 == ~T12_E~0); 62611#L1266-1 assume !(0 == ~E_M~0); 64426#L1271-1 assume !(0 == ~E_1~0); 64007#L1276-1 assume !(0 == ~E_2~0); 64008#L1281-1 assume !(0 == ~E_3~0); 63932#L1286-1 assume !(0 == ~E_4~0); 63023#L1291-1 assume !(0 == ~E_5~0); 63024#L1296-1 assume !(0 == ~E_6~0); 63736#L1301-1 assume !(0 == ~E_7~0); 63737#L1306-1 assume !(0 == ~E_8~0); 64191#L1311-1 assume !(0 == ~E_9~0); 62986#L1316-1 assume !(0 == ~E_10~0); 62987#L1321-1 assume !(0 == ~E_11~0); 63753#L1326-1 assume !(0 == ~E_12~0); 62852#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62853#L598 assume !(1 == ~m_pc~0); 63550#L598-2 is_master_triggered_~__retres1~0#1 := 0; 63551#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64278#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64384#L1497 assume !(0 != activate_threads_~tmp~1#1); 64385#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64331#L617 assume !(1 == ~t1_pc~0); 63205#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63206#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63064#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 63065#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 63836#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63837#L636 assume 1 == ~t2_pc~0; 63174#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 63175#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63005#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63006#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 63875#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63523#L655 assume !(1 == ~t3_pc~0); 63524#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 64284#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62882#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62883#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 64427#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64428#L674 assume !(1 == ~t4_pc~0); 62705#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 64267#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64014#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 63007#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 63008#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63520#L693 assume !(1 == ~t5_pc~0); 63689#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 63329#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63330#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64194#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 63415#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63352#L712 assume 1 == ~t6_pc~0; 63353#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 63785#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63786#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64086#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 63892#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63890#L731 assume 1 == ~t7_pc~0; 62856#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62857#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63047#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 64002#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 64125#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62962#L750 assume !(1 == ~t8_pc~0); 62641#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 62640#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63148#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 64207#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 63286#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63287#L769 assume 1 == ~t9_pc~0; 63832#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62811#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62812#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 63593#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 64062#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64148#L788 assume !(1 == ~t10_pc~0); 63703#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 63704#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 63947#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 63948#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 62958#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 62959#L807 assume 1 == ~t11_pc~0; 64157#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 63716#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 63877#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 64322#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 64462#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 64266#L826 assume !(1 == ~t12_pc~0); 63355#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 63356#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 63899#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 64367#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 63513#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63423#L1344 assume !(1 == ~M_E~0); 63424#L1344-2 assume !(1 == ~T1_E~0); 63568#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63743#L1354-1 assume !(1 == ~T3_E~0); 63744#L1359-1 assume !(1 == ~T4_E~0); 64137#L1364-1 assume !(1 == ~T5_E~0); 63066#L1369-1 assume !(1 == ~T6_E~0); 63067#L1374-1 assume !(1 == ~T7_E~0); 63749#L1379-1 assume !(1 == ~T8_E~0); 63750#L1384-1 assume !(1 == ~T9_E~0); 63818#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 64298#L1394-1 assume !(1 == ~T11_E~0); 64299#L1399-1 assume !(1 == ~T12_E~0); 64393#L1404-1 assume !(1 == ~E_M~0); 63186#L1409-1 assume !(1 == ~E_1~0); 63187#L1414-1 assume !(1 == ~E_2~0); 64041#L1419-1 assume !(1 == ~E_3~0); 62823#L1424-1 assume !(1 == ~E_4~0); 62824#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 63760#L1434-1 assume !(1 == ~E_6~0); 64320#L1439-1 assume !(1 == ~E_7~0); 62878#L1444-1 assume !(1 == ~E_8~0); 62879#L1449-1 assume !(1 == ~E_9~0); 63291#L1454-1 assume !(1 == ~E_10~0); 63292#L1459-1 assume !(1 == ~E_11~0); 63852#L1464-1 assume !(1 == ~E_12~0); 63853#L1469-1 assume { :end_inline_reset_delta_events } true; 63905#L1815-2 [2021-11-13 18:09:44,652 INFO L793 eck$LassoCheckResult]: Loop: 63905#L1815-2 assume !false; 64063#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63718#L1181 assume !false; 63789#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63741#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 62601#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63323#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 63888#L1008 assume !(0 != eval_~tmp~0#1); 63889#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 62817#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 62818#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 64451#L1206-5 assume !(0 == ~T1_E~0); 63851#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 62946#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62947#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 63538#L1226-3 assume !(0 == ~T5_E~0); 63011#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 63012#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 63324#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 64363#L1246-3 assume !(0 == ~T9_E~0); 64251#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 63966#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 62968#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 62969#L1266-3 assume !(0 == ~E_M~0); 63009#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 63010#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 63481#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 63482#L1286-3 assume !(0 == ~E_4~0); 64037#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 64038#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 64435#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 64389#L1306-3 assume !(0 == ~E_8~0); 64390#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 65602#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 62970#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 62971#L1326-3 assume !(0 == ~E_12~0); 64381#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64048#L598-42 assume !(1 == ~m_pc~0); 64049#L598-44 is_master_triggered_~__retres1~0#1 := 0; 65698#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65697#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65696#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 65695#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65694#L617-42 assume !(1 == ~t1_pc~0); 65693#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 65691#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65690#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65601#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65600#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65599#L636-42 assume 1 == ~t2_pc~0; 65597#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65596#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65595#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65594#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65593#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65592#L655-42 assume !(1 == ~t3_pc~0); 65591#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 65589#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65588#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65587#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 65586#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65585#L674-42 assume !(1 == ~t4_pc~0); 65583#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 65582#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65581#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65580#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 65579#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65578#L693-42 assume !(1 == ~t5_pc~0); 65577#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 65575#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65574#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65573#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65572#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65571#L712-42 assume !(1 == ~t6_pc~0); 65569#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 65568#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65567#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65566#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 65565#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65564#L731-42 assume !(1 == ~t7_pc~0); 65563#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 65561#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65560#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65559#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 65558#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65557#L750-42 assume !(1 == ~t8_pc~0); 65555#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 65554#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65553#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65552#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 65551#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65550#L769-42 assume !(1 == ~t9_pc~0); 65549#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 65547#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65546#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 65545#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 65544#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65543#L788-42 assume 1 == ~t10_pc~0; 65541#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 65540#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 65539#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 65538#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 65537#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65535#L807-42 assume !(1 == ~t11_pc~0); 62724#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 62725#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 62863#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 62864#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 62865#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 65522#L826-42 assume !(1 == ~t12_pc~0); 65520#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 65519#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 65518#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 65517#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 65514#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65512#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 65510#L1344-5 assume !(1 == ~T1_E~0); 65508#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65501#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65497#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 65491#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 65483#L1369-3 assume !(1 == ~T6_E~0); 64319#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 63025#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 63026#L1384-3 assume !(1 == ~T9_E~0); 63259#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 63260#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 63560#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 64329#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 64289#L1409-3 assume !(1 == ~E_1~0); 64290#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 64370#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 64371#L1424-3 assume !(1 == ~E_4~0); 65467#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63908#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 63909#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 62870#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 62871#L1449-3 assume !(1 == ~E_9~0); 62978#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 63902#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 63903#L1464-3 assume !(1 == ~E_12~0); 64316#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63772#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 62770#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 62771#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 63383#L1834 assume !(0 == start_simulation_~tmp~3#1); 64437#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 64043#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63459#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63641#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 63861#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 64303#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 62756#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 62757#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 63905#L1815-2 [2021-11-13 18:09:44,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:44,653 INFO L85 PathProgramCache]: Analyzing trace with hash 306976890, now seen corresponding path program 1 times [2021-11-13 18:09:44,653 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:44,654 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156526132] [2021-11-13 18:09:44,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:44,654 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:44,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:44,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:44,714 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:44,715 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1156526132] [2021-11-13 18:09:44,715 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1156526132] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:44,715 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:44,715 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 18:09:44,715 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1510917089] [2021-11-13 18:09:44,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:44,716 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:44,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:44,717 INFO L85 PathProgramCache]: Analyzing trace with hash 174908186, now seen corresponding path program 1 times [2021-11-13 18:09:44,717 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:44,717 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2084510664] [2021-11-13 18:09:44,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:44,718 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:44,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:44,763 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:44,763 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:44,763 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2084510664] [2021-11-13 18:09:44,763 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2084510664] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:44,764 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:44,764 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:44,764 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1830362261] [2021-11-13 18:09:44,764 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:44,765 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:44,765 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:44,765 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-13 18:09:44,766 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-13 18:09:44,766 INFO L87 Difference]: Start difference. First operand 3303 states and 4755 transitions. cyclomatic complexity: 1454 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:45,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:45,324 INFO L93 Difference]: Finished difference Result 9347 states and 13414 transitions. [2021-11-13 18:09:45,325 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-13 18:09:45,325 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9347 states and 13414 transitions. [2021-11-13 18:09:45,375 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 8969 [2021-11-13 18:09:45,411 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9347 states to 9347 states and 13414 transitions. [2021-11-13 18:09:45,411 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9347 [2021-11-13 18:09:45,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9347 [2021-11-13 18:09:45,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9347 states and 13414 transitions. [2021-11-13 18:09:45,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:45,434 INFO L681 BuchiCegarLoop]: Abstraction has 9347 states and 13414 transitions. [2021-11-13 18:09:45,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9347 states and 13414 transitions. [2021-11-13 18:09:45,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9347 to 3393. [2021-11-13 18:09:45,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3393 states, 3393 states have (on average 1.4279398762157383) internal successors, (4845), 3392 states have internal predecessors, (4845), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:45,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3393 states to 3393 states and 4845 transitions. [2021-11-13 18:09:45,532 INFO L704 BuchiCegarLoop]: Abstraction has 3393 states and 4845 transitions. [2021-11-13 18:09:45,532 INFO L587 BuchiCegarLoop]: Abstraction has 3393 states and 4845 transitions. [2021-11-13 18:09:45,532 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-13 18:09:45,532 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3393 states and 4845 transitions. [2021-11-13 18:09:45,546 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3227 [2021-11-13 18:09:45,547 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:45,547 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:45,551 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:45,551 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:45,552 INFO L791 eck$LassoCheckResult]: Stem: 76101#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 76102#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 75525#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 75495#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 75496#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 76814#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75803#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75261#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75262#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76565#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76715#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 77165#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 77166#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76014#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 76015#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 76594#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 76508#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 76509#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76676#L1206 assume !(0 == ~M_E~0); 75993#L1206-2 assume !(0 == ~T1_E~0); 75994#L1211-1 assume !(0 == ~T2_E~0); 76970#L1216-1 assume !(0 == ~T3_E~0); 75785#L1221-1 assume !(0 == ~T4_E~0); 75786#L1226-1 assume !(0 == ~T5_E~0); 75450#L1231-1 assume !(0 == ~T6_E~0); 75451#L1236-1 assume !(0 == ~T7_E~0); 77010#L1241-1 assume !(0 == ~T8_E~0); 75848#L1246-1 assume !(0 == ~T9_E~0); 75849#L1251-1 assume !(0 == ~T10_E~0); 76070#L1256-1 assume !(0 == ~T11_E~0); 75273#L1261-1 assume !(0 == ~T12_E~0); 75274#L1266-1 assume !(0 == ~E_M~0); 77140#L1271-1 assume !(0 == ~E_1~0); 76703#L1276-1 assume !(0 == ~E_2~0); 76704#L1281-1 assume !(0 == ~E_3~0); 76621#L1286-1 assume !(0 == ~E_4~0); 75689#L1291-1 assume !(0 == ~E_5~0); 75690#L1296-1 assume !(0 == ~E_6~0); 76418#L1301-1 assume !(0 == ~E_7~0); 76419#L1306-1 assume !(0 == ~E_8~0); 76895#L1311-1 assume !(0 == ~E_9~0); 75650#L1316-1 assume !(0 == ~E_10~0); 75651#L1321-1 assume !(0 == ~E_11~0); 76435#L1326-1 assume !(0 == ~E_12~0); 75515#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75516#L598 assume !(1 == ~m_pc~0); 76224#L598-2 is_master_triggered_~__retres1~0#1 := 0; 76225#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76989#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77098#L1497 assume !(0 != activate_threads_~tmp~1#1); 77099#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77044#L617 assume !(1 == ~t1_pc~0); 75871#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 75872#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77191#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77113#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 76527#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76528#L636 assume 1 == ~t2_pc~0; 75840#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 75841#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75671#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 75672#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 76564#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76194#L655 assume !(1 == ~t3_pc~0); 76195#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76995#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75546#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75547#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 77141#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77142#L674 assume !(1 == ~t4_pc~0); 75368#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 76977#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76710#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75673#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 75674#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76191#L693 assume !(1 == ~t5_pc~0); 76367#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 75995#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75996#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76898#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 76082#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76018#L712 assume 1 == ~t6_pc~0; 76019#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 76470#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76471#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76788#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 76581#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76579#L731 assume 1 == ~t7_pc~0; 75519#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75520#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75713#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76698#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 76827#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75627#L750 assume !(1 == ~t8_pc~0); 75304#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 75303#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 75814#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76913#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 75952#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75953#L769 assume 1 == ~t9_pc~0; 76523#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75474#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75475#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 76269#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 76761#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76852#L788 assume !(1 == ~t10_pc~0); 76383#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 76384#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76638#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 76639#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 75623#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 75624#L807 assume 1 == ~t11_pc~0; 76861#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 76398#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76566#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 77036#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 77197#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76976#L826 assume !(1 == ~t12_pc~0); 76021#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 76022#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 76589#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 77082#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 76184#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76090#L1344 assume !(1 == ~M_E~0); 76091#L1344-2 assume !(1 == ~T1_E~0); 76243#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76425#L1354-1 assume !(1 == ~T3_E~0); 76426#L1359-1 assume !(1 == ~T4_E~0); 76838#L1364-1 assume !(1 == ~T5_E~0); 75732#L1369-1 assume !(1 == ~T6_E~0); 75733#L1374-1 assume !(1 == ~T7_E~0); 76431#L1379-1 assume !(1 == ~T8_E~0); 76432#L1384-1 assume !(1 == ~T9_E~0); 76504#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 77012#L1394-1 assume !(1 == ~T11_E~0); 77013#L1399-1 assume !(1 == ~T12_E~0); 77110#L1404-1 assume !(1 == ~E_M~0); 75852#L1409-1 assume !(1 == ~E_1~0); 75853#L1414-1 assume !(1 == ~E_2~0); 76739#L1419-1 assume !(1 == ~E_3~0); 75486#L1424-1 assume !(1 == ~E_4~0); 75487#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 76442#L1434-1 assume !(1 == ~E_6~0); 77034#L1439-1 assume !(1 == ~E_7~0); 75542#L1444-1 assume !(1 == ~E_8~0); 75543#L1449-1 assume !(1 == ~E_9~0); 75957#L1454-1 assume !(1 == ~E_10~0); 75958#L1459-1 assume !(1 == ~E_11~0); 76543#L1464-1 assume !(1 == ~E_12~0); 76544#L1469-1 assume { :end_inline_reset_delta_events } true; 76595#L1815-2 [2021-11-13 18:09:45,552 INFO L793 eck$LassoCheckResult]: Loop: 76595#L1815-2 assume !false; 76763#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76474#L1181 assume !false; 76475#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 76423#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 75264#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 75989#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 76756#L1008 assume !(0 != eval_~tmp~0#1); 77234#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 78581#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78577#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 77178#L1206-5 assume !(0 == ~T1_E~0); 76542#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 75611#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 75612#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 76212#L1226-3 assume !(0 == ~T5_E~0); 75677#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 75678#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 75990#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 77198#L1246-3 assume !(0 == ~T9_E~0); 78528#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 78527#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 78526#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 78525#L1266-3 assume !(0 == ~E_M~0); 78524#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 78523#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 78522#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 78521#L1286-3 assume !(0 == ~E_4~0); 78520#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 78132#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 78131#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 78130#L1306-3 assume !(0 == ~E_8~0); 78129#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 78128#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 78127#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 78126#L1326-3 assume !(0 == ~E_12~0); 77095#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76746#L598-42 assume !(1 == ~m_pc~0); 76747#L598-44 is_master_triggered_~__retres1~0#1 := 0; 76875#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75714#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75715#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 77106#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77181#L617-42 assume 1 == ~t1_pc~0; 76205#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 76206#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76513#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76514#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 75779#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75780#L636-42 assume !(1 == ~t2_pc~0); 76256#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 76257#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76636#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76637#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 76833#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76685#L655-42 assume !(1 == ~t3_pc~0); 76227#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 76228#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75850#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75851#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76994#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76919#L674-42 assume !(1 == ~t4_pc~0); 76667#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 76582#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75435#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75436#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 76365#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76366#L693-42 assume 1 == ~t5_pc~0; 76647#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 76648#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76713#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76708#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 76709#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75964#L712-42 assume !(1 == ~t6_pc~0); 75965#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 76305#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76534#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76535#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 76074#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76075#L731-42 assume 1 == ~t7_pc~0; 75937#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75773#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76908#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 75981#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 75982#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75684#L750-42 assume 1 == ~t8_pc~0; 75685#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 76272#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76730#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 75576#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 75577#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76364#L769-42 assume 1 == ~t9_pc~0; 76172#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 76173#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76924#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 77011#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 75781#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75782#L788-42 assume !(1 == ~t10_pc~0); 76373#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 76609#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76314#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 76315#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77170#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77133#L807-42 assume 1 == ~t11_pc~0; 76757#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 75388#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 75526#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 75527#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 75528#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 75776#L826-42 assume !(1 == ~t12_pc~0); 75778#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 75970#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 76819#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 75767#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 75768#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76664#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 76665#L1344-5 assume !(1 == ~T1_E~0); 76583#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 75927#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 75928#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 76599#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77137#L1369-3 assume !(1 == ~T6_E~0); 77033#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 75691#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 75692#L1384-3 assume !(1 == ~T9_E~0); 75925#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 75926#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 76235#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 77042#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 77003#L1409-3 assume !(1 == ~E_1~0); 77004#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 77077#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 76813#L1424-3 assume !(1 == ~E_4~0); 75591#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 75592#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 76598#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 75533#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 75534#L1449-3 assume !(1 == ~E_9~0); 75642#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 76592#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 76593#L1464-3 assume !(1 == ~E_12~0); 77029#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 76457#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 75433#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 75434#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 76050#L1834 assume !(0 == start_simulation_~tmp~3#1); 76716#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 76741#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 76128#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 76319#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 76552#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77018#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 75419#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 75420#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 76595#L1815-2 [2021-11-13 18:09:45,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:45,553 INFO L85 PathProgramCache]: Analyzing trace with hash 1658362108, now seen corresponding path program 1 times [2021-11-13 18:09:45,554 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:45,554 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1848772536] [2021-11-13 18:09:45,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:45,554 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:45,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:45,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:45,600 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:45,600 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1848772536] [2021-11-13 18:09:45,601 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1848772536] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:45,601 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:45,601 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:45,601 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1227038708] [2021-11-13 18:09:45,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:45,602 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:45,602 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:45,603 INFO L85 PathProgramCache]: Analyzing trace with hash 1707980374, now seen corresponding path program 1 times [2021-11-13 18:09:45,603 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:45,603 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1421315573] [2021-11-13 18:09:45,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:45,604 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:45,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:45,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:45,648 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:45,648 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1421315573] [2021-11-13 18:09:45,649 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1421315573] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:45,649 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:45,649 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:45,649 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1427697525] [2021-11-13 18:09:45,650 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:45,650 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:45,650 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:45,651 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:09:45,651 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:09:45,651 INFO L87 Difference]: Start difference. First operand 3393 states and 4845 transitions. cyclomatic complexity: 1454 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:46,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:46,047 INFO L93 Difference]: Finished difference Result 8091 states and 11463 transitions. [2021-11-13 18:09:46,048 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:09:46,048 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8091 states and 11463 transitions. [2021-11-13 18:09:46,085 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 7825 [2021-11-13 18:09:46,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8091 states to 8091 states and 11463 transitions. [2021-11-13 18:09:46,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8091 [2021-11-13 18:09:46,126 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8091 [2021-11-13 18:09:46,126 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8091 states and 11463 transitions. [2021-11-13 18:09:46,134 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:46,134 INFO L681 BuchiCegarLoop]: Abstraction has 8091 states and 11463 transitions. [2021-11-13 18:09:46,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8091 states and 11463 transitions. [2021-11-13 18:09:46,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8091 to 6396. [2021-11-13 18:09:46,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6396 states, 6396 states have (on average 1.4210444027517197) internal successors, (9089), 6395 states have internal predecessors, (9089), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:46,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6396 states to 6396 states and 9089 transitions. [2021-11-13 18:09:46,271 INFO L704 BuchiCegarLoop]: Abstraction has 6396 states and 9089 transitions. [2021-11-13 18:09:46,271 INFO L587 BuchiCegarLoop]: Abstraction has 6396 states and 9089 transitions. [2021-11-13 18:09:46,271 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-13 18:09:46,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6396 states and 9089 transitions. [2021-11-13 18:09:46,294 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6230 [2021-11-13 18:09:46,294 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:46,294 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:46,297 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:46,297 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:46,298 INFO L791 eck$LassoCheckResult]: Stem: 87588#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 87589#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 87019#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86992#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86993#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 88278#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 87293#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86755#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86756#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 88044#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 88184#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 88622#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 88623#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 87502#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 87503#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 88074#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 87985#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 87986#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 88145#L1206 assume !(0 == ~M_E~0); 87479#L1206-2 assume !(0 == ~T1_E~0); 87480#L1211-1 assume !(0 == ~T2_E~0); 88432#L1216-1 assume !(0 == ~T3_E~0); 87275#L1221-1 assume !(0 == ~T4_E~0); 87276#L1226-1 assume !(0 == ~T5_E~0); 86945#L1231-1 assume !(0 == ~T6_E~0); 86946#L1236-1 assume !(0 == ~T7_E~0); 88470#L1241-1 assume !(0 == ~T8_E~0); 87334#L1246-1 assume !(0 == ~T9_E~0); 87335#L1251-1 assume !(0 == ~T10_E~0); 87555#L1256-1 assume !(0 == ~T11_E~0); 86767#L1261-1 assume !(0 == ~T12_E~0); 86768#L1266-1 assume !(0 == ~E_M~0); 88606#L1271-1 assume !(0 == ~E_1~0); 88172#L1276-1 assume !(0 == ~E_2~0); 88173#L1281-1 assume !(0 == ~E_3~0); 88102#L1286-1 assume !(0 == ~E_4~0); 87178#L1291-1 assume !(0 == ~E_5~0); 87179#L1296-1 assume !(0 == ~E_6~0); 87901#L1301-1 assume !(0 == ~E_7~0); 87902#L1306-1 assume !(0 == ~E_8~0); 88362#L1311-1 assume !(0 == ~E_9~0); 87141#L1316-1 assume !(0 == ~E_10~0); 87142#L1321-1 assume !(0 == ~E_11~0); 87918#L1326-1 assume !(0 == ~E_12~0); 87009#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87010#L598 assume !(1 == ~m_pc~0); 87707#L598-2 is_master_triggered_~__retres1~0#1 := 0; 87708#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88451#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 88568#L1497 assume !(0 != activate_threads_~tmp~1#1); 88569#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88503#L617 assume !(1 == ~t1_pc~0); 87357#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 87358#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88654#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 88580#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 88003#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88004#L636 assume !(1 == ~t2_pc~0); 88520#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 87777#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87160#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 87161#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 88043#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87679#L655 assume !(1 == ~t3_pc~0); 87680#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 88456#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87037#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 87038#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 88607#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88608#L674 assume !(1 == ~t4_pc~0); 86861#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 88439#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88179#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 87164#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 87165#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87673#L693 assume !(1 == ~t5_pc~0); 87853#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 87484#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87485#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 88364#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 87567#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87504#L712 assume 1 == ~t6_pc~0; 87505#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 87951#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 87952#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 88250#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 88061#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 88058#L731 assume 1 == ~t7_pc~0; 87011#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 87012#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 87204#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 88168#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 88292#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 87118#L750 assume !(1 == ~t8_pc~0); 86798#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 86797#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 87304#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 88378#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 87437#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 87438#L769 assume 1 == ~t9_pc~0; 88001#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 86966#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86967#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 87752#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 88225#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 88316#L788 assume !(1 == ~t10_pc~0); 87867#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 87868#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 88117#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 88118#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 87114#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 87115#L807 assume 1 == ~t11_pc~0; 88325#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 87880#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 88045#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 88494#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 88650#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 88438#L826 assume !(1 == ~t12_pc~0); 87509#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 87510#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 88069#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 88546#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 87666#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87575#L1344 assume !(1 == ~M_E~0); 87576#L1344-2 assume !(1 == ~T1_E~0); 87725#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87909#L1354-1 assume !(1 == ~T3_E~0); 87910#L1359-1 assume !(1 == ~T4_E~0); 88304#L1364-1 assume !(1 == ~T5_E~0); 87221#L1369-1 assume !(1 == ~T6_E~0); 87222#L1374-1 assume !(1 == ~T7_E~0); 87916#L1379-1 assume !(1 == ~T8_E~0); 87917#L1384-1 assume !(1 == ~T9_E~0); 87984#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 88472#L1394-1 assume !(1 == ~T11_E~0); 88473#L1399-1 assume !(1 == ~T12_E~0); 88577#L1404-1 assume !(1 == ~E_M~0); 87338#L1409-1 assume !(1 == ~E_1~0); 87339#L1414-1 assume !(1 == ~E_2~0); 88206#L1419-1 assume !(1 == ~E_3~0); 86978#L1424-1 assume !(1 == ~E_4~0); 86979#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 87928#L1434-1 assume !(1 == ~E_6~0); 88492#L1439-1 assume !(1 == ~E_7~0); 87033#L1444-1 assume !(1 == ~E_8~0); 87034#L1449-1 assume !(1 == ~E_9~0); 87442#L1454-1 assume !(1 == ~E_10~0); 87443#L1459-1 assume !(1 == ~E_11~0); 88021#L1464-1 assume !(1 == ~E_12~0); 88022#L1469-1 assume { :end_inline_reset_delta_events } true; 88075#L1815-2 [2021-11-13 18:09:46,298 INFO L793 eck$LassoCheckResult]: Loop: 88075#L1815-2 assume !false; 88226#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 87882#L1181 assume !false; 87955#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 87906#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 86758#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 87475#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 88056#L1008 assume !(0 != eval_~tmp~0#1); 88057#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 86972#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 86973#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 88634#L1206-5 assume !(0 == ~T1_E~0); 88020#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 87102#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 87103#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 87694#L1226-3 assume !(0 == ~T5_E~0); 87166#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 87167#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 87476#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 88543#L1246-3 assume !(0 == ~T9_E~0); 88424#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 88134#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 87124#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 87125#L1266-3 assume !(0 == ~E_M~0); 87162#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 87163#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 87634#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 87635#L1286-3 assume !(0 == ~E_4~0); 88203#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 88204#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 88614#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 88573#L1306-3 assume !(0 == ~E_8~0); 87770#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 87050#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 87051#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 87126#L1326-3 assume !(0 == ~E_12~0); 87875#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88214#L598-42 assume !(1 == ~m_pc~0); 88215#L598-44 is_master_triggered_~__retres1~0#1 := 0; 88343#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87202#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87203#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 88574#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 87933#L617-42 assume 1 == ~t1_pc~0; 87687#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 87688#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92999#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 92998#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 87269#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87270#L636-42 assume !(1 == ~t2_pc~0); 87740#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 87741#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88112#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 88113#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 88298#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88154#L655-42 assume !(1 == ~t3_pc~0); 87714#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 87715#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87336#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 87337#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 88455#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88384#L674-42 assume !(1 == ~t4_pc~0); 88140#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 88062#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86928#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 86929#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87851#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87852#L693-42 assume 1 == ~t5_pc~0; 88123#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 88124#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88181#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 88176#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 88177#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87446#L712-42 assume !(1 == ~t6_pc~0); 87447#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 87787#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88012#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 88013#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 87559#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87560#L731-42 assume !(1 == ~t7_pc~0); 87259#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 87260#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 88373#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 87467#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 87468#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 87170#L750-42 assume 1 == ~t8_pc~0; 87171#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 87755#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 88199#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 87066#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 87067#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 87847#L769-42 assume 1 == ~t9_pc~0; 87653#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 87654#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 88391#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 88471#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 87271#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 87272#L788-42 assume !(1 == ~t10_pc~0); 87859#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 88084#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 87798#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 87799#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 88626#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 88599#L807-42 assume !(1 == ~t11_pc~0); 86880#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 86881#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 87017#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 87018#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 87020#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 87266#L826-42 assume !(1 == ~t12_pc~0); 87268#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 87455#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 88283#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 87257#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 87258#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88137#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 88138#L1344-5 assume !(1 == ~T1_E~0); 88063#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87412#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 87413#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 88079#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 88603#L1369-3 assume !(1 == ~T6_E~0); 88491#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 87180#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 87181#L1384-3 assume !(1 == ~T9_E~0); 87410#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 87411#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 87717#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 88501#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 88463#L1409-3 assume !(1 == ~E_1~0); 88464#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 88541#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 88277#L1424-3 assume !(1 == ~E_4~0); 87081#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 87082#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 88078#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 87025#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 87026#L1449-3 assume !(1 == ~E_9~0); 87133#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 88072#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 88073#L1464-3 assume !(1 == ~E_12~0); 88488#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 87938#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 86926#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 86927#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 87535#L1834 assume !(0 == start_simulation_~tmp~3#1); 88185#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 88208#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 87611#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 87803#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 88028#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 88478#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86912#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 86913#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 88075#L1815-2 [2021-11-13 18:09:46,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:46,299 INFO L85 PathProgramCache]: Analyzing trace with hash -1519420227, now seen corresponding path program 1 times [2021-11-13 18:09:46,300 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:46,300 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1501253623] [2021-11-13 18:09:46,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:46,300 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:46,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:46,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:46,357 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:46,357 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1501253623] [2021-11-13 18:09:46,357 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1501253623] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:46,357 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:46,358 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:46,358 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1778009061] [2021-11-13 18:09:46,361 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:46,362 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:46,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:46,363 INFO L85 PathProgramCache]: Analyzing trace with hash -251761320, now seen corresponding path program 1 times [2021-11-13 18:09:46,363 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:46,363 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1719434083] [2021-11-13 18:09:46,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:46,364 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:46,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:46,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:46,405 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:46,405 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1719434083] [2021-11-13 18:09:46,406 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1719434083] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:46,406 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:46,406 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:46,406 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [512430624] [2021-11-13 18:09:46,406 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:46,407 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:46,407 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:46,407 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:09:46,408 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:09:46,408 INFO L87 Difference]: Start difference. First operand 6396 states and 9089 transitions. cyclomatic complexity: 2695 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:46,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:46,778 INFO L93 Difference]: Finished difference Result 15351 states and 21662 transitions. [2021-11-13 18:09:46,778 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:09:46,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15351 states and 21662 transitions. [2021-11-13 18:09:46,857 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 14985 [2021-11-13 18:09:47,035 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15351 states to 15351 states and 21662 transitions. [2021-11-13 18:09:47,036 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15351 [2021-11-13 18:09:47,051 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15351 [2021-11-13 18:09:47,051 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15351 states and 21662 transitions. [2021-11-13 18:09:47,064 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:47,064 INFO L681 BuchiCegarLoop]: Abstraction has 15351 states and 21662 transitions. [2021-11-13 18:09:47,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15351 states and 21662 transitions. [2021-11-13 18:09:47,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15351 to 12183. [2021-11-13 18:09:47,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12183 states, 12183 states have (on average 1.4150865960765) internal successors, (17240), 12182 states have internal predecessors, (17240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:47,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12183 states to 12183 states and 17240 transitions. [2021-11-13 18:09:47,284 INFO L704 BuchiCegarLoop]: Abstraction has 12183 states and 17240 transitions. [2021-11-13 18:09:47,284 INFO L587 BuchiCegarLoop]: Abstraction has 12183 states and 17240 transitions. [2021-11-13 18:09:47,284 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-13 18:09:47,285 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12183 states and 17240 transitions. [2021-11-13 18:09:47,324 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12016 [2021-11-13 18:09:47,324 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:47,324 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:47,328 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:47,328 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:47,329 INFO L791 eck$LassoCheckResult]: Stem: 109342#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 109343#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 108775#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 108748#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 108749#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 110040#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 109049#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 108512#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 108513#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 109800#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 109944#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 110425#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 110426#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 109257#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 109258#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 109830#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 109743#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 109744#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 109904#L1206 assume !(0 == ~M_E~0); 109233#L1206-2 assume !(0 == ~T1_E~0); 109234#L1211-1 assume !(0 == ~T2_E~0); 110213#L1216-1 assume !(0 == ~T3_E~0); 109031#L1221-1 assume !(0 == ~T4_E~0); 109032#L1226-1 assume !(0 == ~T5_E~0); 108701#L1231-1 assume !(0 == ~T6_E~0); 108702#L1236-1 assume !(0 == ~T7_E~0); 110256#L1241-1 assume !(0 == ~T8_E~0); 109090#L1246-1 assume !(0 == ~T9_E~0); 109091#L1251-1 assume !(0 == ~T10_E~0); 109309#L1256-1 assume !(0 == ~T11_E~0); 108524#L1261-1 assume !(0 == ~T12_E~0); 108525#L1266-1 assume !(0 == ~E_M~0); 110404#L1271-1 assume !(0 == ~E_1~0); 109932#L1276-1 assume !(0 == ~E_2~0); 109933#L1281-1 assume !(0 == ~E_3~0); 109859#L1286-1 assume !(0 == ~E_4~0); 108936#L1291-1 assume !(0 == ~E_5~0); 108937#L1296-1 assume !(0 == ~E_6~0); 109654#L1301-1 assume !(0 == ~E_7~0); 109655#L1306-1 assume !(0 == ~E_8~0); 110131#L1311-1 assume !(0 == ~E_9~0); 108899#L1316-1 assume !(0 == ~E_10~0); 108900#L1321-1 assume !(0 == ~E_11~0); 109671#L1326-1 assume !(0 == ~E_12~0); 108765#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 108766#L598 assume !(1 == ~m_pc~0); 109459#L598-2 is_master_triggered_~__retres1~0#1 := 0; 109460#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 110229#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 110360#L1497 assume !(0 != activate_threads_~tmp~1#1); 110361#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 110296#L617 assume !(1 == ~t1_pc~0); 109112#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 109113#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 110464#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 110374#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 109760#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 109761#L636 assume !(1 == ~t2_pc~0); 110316#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 109527#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 108918#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 108919#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 109799#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 109434#L655 assume !(1 == ~t3_pc~0); 109435#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 110238#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 108793#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 108794#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 110405#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 110406#L674 assume !(1 == ~t4_pc~0); 108617#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 110217#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 109939#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 108922#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 108923#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 109428#L693 assume !(1 == ~t5_pc~0); 109605#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 109238#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 109239#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 110133#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 109321#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 109259#L712 assume !(1 == ~t6_pc~0); 109260#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 109705#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 109706#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 110015#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 109816#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 109814#L731 assume 1 == ~t7_pc~0; 108767#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 108768#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 108961#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 109928#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 110058#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 108875#L750 assume !(1 == ~t8_pc~0); 108555#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 108554#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 109060#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 110147#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 109192#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 109193#L769 assume 1 == ~t9_pc~0; 109758#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 108722#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 108723#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 109502#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 109988#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 110084#L788 assume !(1 == ~t10_pc~0); 109620#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 109621#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 109876#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 109877#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 108873#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 108874#L807 assume 1 == ~t11_pc~0; 110093#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 109634#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 109801#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 110283#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 110463#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 110216#L826 assume !(1 == ~t12_pc~0); 109263#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 109264#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 109824#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 110336#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 109421#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 109329#L1344 assume !(1 == ~M_E~0); 109330#L1344-2 assume !(1 == ~T1_E~0); 109476#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 109662#L1354-1 assume !(1 == ~T3_E~0); 109663#L1359-1 assume !(1 == ~T4_E~0); 110072#L1364-1 assume !(1 == ~T5_E~0); 108978#L1369-1 assume !(1 == ~T6_E~0); 108979#L1374-1 assume !(1 == ~T7_E~0); 109669#L1379-1 assume !(1 == ~T8_E~0); 109670#L1384-1 assume !(1 == ~T9_E~0); 109742#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 110259#L1394-1 assume !(1 == ~T11_E~0); 110260#L1399-1 assume !(1 == ~T12_E~0); 110371#L1404-1 assume !(1 == ~E_M~0); 109094#L1409-1 assume !(1 == ~E_1~0); 109095#L1414-1 assume !(1 == ~E_2~0); 109967#L1419-1 assume !(1 == ~E_3~0); 108734#L1424-1 assume !(1 == ~E_4~0); 108735#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 109680#L1434-1 assume !(1 == ~E_6~0); 110281#L1439-1 assume !(1 == ~E_7~0); 108789#L1444-1 assume !(1 == ~E_8~0); 108790#L1449-1 assume !(1 == ~E_9~0); 109198#L1454-1 assume !(1 == ~E_10~0); 109199#L1459-1 assume !(1 == ~E_11~0); 109778#L1464-1 assume !(1 == ~E_12~0); 109779#L1469-1 assume { :end_inline_reset_delta_events } true; 109831#L1815-2 [2021-11-13 18:09:47,329 INFO L793 eck$LassoCheckResult]: Loop: 109831#L1815-2 assume !false; 109989#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 109636#L1181 assume !false; 109709#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 109659#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 108515#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 109229#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 109812#L1008 assume !(0 != eval_~tmp~0#1); 109813#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 120658#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 120657#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 120656#L1206-5 assume !(0 == ~T1_E~0); 120655#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 120654#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 120653#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 120652#L1226-3 assume !(0 == ~T5_E~0); 120651#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 120650#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 120649#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 110333#L1246-3 assume !(0 == ~T9_E~0); 110200#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 109893#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 108881#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 108882#L1266-3 assume !(0 == ~E_M~0); 108920#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 108921#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 109389#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 109390#L1286-3 assume !(0 == ~E_4~0); 110237#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 120607#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 120606#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 120605#L1306-3 assume !(0 == ~E_8~0); 109520#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 109521#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 108883#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 108884#L1326-3 assume !(0 == ~E_12~0); 109628#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 109977#L598-42 assume !(1 == ~m_pc~0); 109978#L598-44 is_master_triggered_~__retres1~0#1 := 0; 110111#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 108959#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 108960#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 110369#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 109685#L617-42 assume !(1 == ~t1_pc~0); 109443#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 110151#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 120608#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 110364#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 109025#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 109026#L636-42 assume !(1 == ~t2_pc~0); 110358#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 119958#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119957#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 119956#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 119955#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119954#L655-42 assume !(1 == ~t3_pc~0); 119953#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 119951#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119950#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 119949#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 119948#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119947#L674-42 assume !(1 == ~t4_pc~0); 119945#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 119944#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 119943#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 119941#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 119939#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119937#L693-42 assume !(1 == ~t5_pc~0); 119935#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 119932#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 119929#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 119927#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 119925#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 119923#L712-42 assume !(1 == ~t6_pc~0); 114894#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 119919#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 119917#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 119915#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 119914#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 119913#L731-42 assume 1 == ~t7_pc~0; 119911#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 119910#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 110141#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 109221#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 109222#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 108928#L750-42 assume 1 == ~t8_pc~0; 108929#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 109506#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 109959#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 108822#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 108823#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 109599#L769-42 assume 1 == ~t9_pc~0; 109408#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 109409#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 110160#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 110257#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 109027#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 109028#L788-42 assume !(1 == ~t10_pc~0); 109611#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 109840#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 109549#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 109550#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 110431#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 110397#L807-42 assume 1 == ~t11_pc~0; 109984#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 108637#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 108773#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 108774#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 108776#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 109022#L826-42 assume !(1 == ~t12_pc~0); 109024#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 109210#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 110045#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 109013#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 109014#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 109896#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 109897#L1344-5 assume !(1 == ~T1_E~0); 109818#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 109167#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 109168#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 109835#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 110401#L1369-3 assume !(1 == ~T6_E~0); 110280#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 108938#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 108939#L1384-3 assume !(1 == ~T9_E~0); 109165#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 109166#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 109469#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 110294#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 110249#L1409-3 assume !(1 == ~E_1~0); 110250#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 110331#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 110039#L1424-3 assume !(1 == ~E_4~0); 108837#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 108838#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 109834#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 108781#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 108782#L1449-3 assume !(1 == ~E_9~0); 108891#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 109828#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 109829#L1464-3 assume !(1 == ~E_12~0); 110276#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 109690#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 108682#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 108683#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 109289#L1834 assume !(0 == start_simulation_~tmp~3#1); 109945#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 109969#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 109366#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 109554#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 109785#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 110265#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 108668#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 108669#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 109831#L1815-2 [2021-11-13 18:09:47,330 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:47,330 INFO L85 PathProgramCache]: Analyzing trace with hash -381791362, now seen corresponding path program 1 times [2021-11-13 18:09:47,331 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:47,331 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [97677066] [2021-11-13 18:09:47,331 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:47,331 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:47,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:47,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:47,376 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:47,376 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [97677066] [2021-11-13 18:09:47,376 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [97677066] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:47,377 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:47,377 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:47,377 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [785177388] [2021-11-13 18:09:47,377 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:47,378 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:47,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:47,378 INFO L85 PathProgramCache]: Analyzing trace with hash -1194040870, now seen corresponding path program 1 times [2021-11-13 18:09:47,378 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:47,379 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [971038229] [2021-11-13 18:09:47,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:47,379 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:47,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:47,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:47,417 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:47,417 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [971038229] [2021-11-13 18:09:47,417 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [971038229] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:47,417 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:47,418 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:47,418 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1019854133] [2021-11-13 18:09:47,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:47,418 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:47,419 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:47,419 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:09:47,419 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:09:47,419 INFO L87 Difference]: Start difference. First operand 12183 states and 17240 transitions. cyclomatic complexity: 5059 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:47,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:47,935 INFO L93 Difference]: Finished difference Result 29384 states and 41307 transitions. [2021-11-13 18:09:47,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:09:47,936 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29384 states and 41307 transitions. [2021-11-13 18:09:48,094 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 28818 [2021-11-13 18:09:48,219 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29384 states to 29384 states and 41307 transitions. [2021-11-13 18:09:48,219 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29384 [2021-11-13 18:09:48,237 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29384 [2021-11-13 18:09:48,238 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29384 states and 41307 transitions. [2021-11-13 18:09:48,258 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:48,258 INFO L681 BuchiCegarLoop]: Abstraction has 29384 states and 41307 transitions. [2021-11-13 18:09:48,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29384 states and 41307 transitions. [2021-11-13 18:09:48,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29384 to 23322. [2021-11-13 18:09:48,826 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23322 states, 23322 states have (on average 1.4096989966555185) internal successors, (32877), 23321 states have internal predecessors, (32877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:49,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23322 states to 23322 states and 32877 transitions. [2021-11-13 18:09:49,077 INFO L704 BuchiCegarLoop]: Abstraction has 23322 states and 32877 transitions. [2021-11-13 18:09:49,077 INFO L587 BuchiCegarLoop]: Abstraction has 23322 states and 32877 transitions. [2021-11-13 18:09:49,077 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-13 18:09:49,077 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23322 states and 32877 transitions. [2021-11-13 18:09:49,236 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 23152 [2021-11-13 18:09:49,237 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:49,237 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:49,241 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:49,242 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:49,242 INFO L791 eck$LassoCheckResult]: Stem: 150928#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 150929#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 150348#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 150325#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 150326#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 151641#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 150623#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 150089#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 150090#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 151397#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 151545#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 152028#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 152029#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 150839#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 150840#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 151427#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 151336#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 151337#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 151502#L1206 assume !(0 == ~M_E~0); 150815#L1206-2 assume !(0 == ~T1_E~0); 150816#L1211-1 assume !(0 == ~T2_E~0); 151801#L1216-1 assume !(0 == ~T3_E~0); 150605#L1221-1 assume !(0 == ~T4_E~0); 150606#L1226-1 assume !(0 == ~T5_E~0); 150278#L1231-1 assume !(0 == ~T6_E~0); 150279#L1236-1 assume !(0 == ~T7_E~0); 151847#L1241-1 assume !(0 == ~T8_E~0); 150667#L1246-1 assume !(0 == ~T9_E~0); 150668#L1251-1 assume !(0 == ~T10_E~0); 150894#L1256-1 assume !(0 == ~T11_E~0); 150101#L1261-1 assume !(0 == ~T12_E~0); 150102#L1266-1 assume !(0 == ~E_M~0); 152009#L1271-1 assume !(0 == ~E_1~0); 151532#L1276-1 assume !(0 == ~E_2~0); 151533#L1281-1 assume !(0 == ~E_3~0); 151456#L1286-1 assume !(0 == ~E_4~0); 150508#L1291-1 assume !(0 == ~E_5~0); 150509#L1296-1 assume !(0 == ~E_6~0); 151248#L1301-1 assume !(0 == ~E_7~0); 151249#L1306-1 assume !(0 == ~E_8~0); 151731#L1311-1 assume !(0 == ~E_9~0); 150469#L1316-1 assume !(0 == ~E_10~0); 150470#L1321-1 assume !(0 == ~E_11~0); 151266#L1326-1 assume !(0 == ~E_12~0); 150342#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 150343#L598 assume !(1 == ~m_pc~0); 151047#L598-2 is_master_triggered_~__retres1~0#1 := 0; 151048#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 151820#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 151965#L1497 assume !(0 != activate_threads_~tmp~1#1); 151966#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 151890#L617 assume !(1 == ~t1_pc~0); 150690#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 150691#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 152063#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 151977#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 151354#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 151355#L636 assume !(1 == ~t2_pc~0); 151913#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 151117#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 150490#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 150491#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 151396#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 151021#L655 assume !(1 == ~t3_pc~0); 151022#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 151828#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 150366#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 150367#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 152010#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 152011#L674 assume !(1 == ~t4_pc~0); 150194#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 151806#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 151539#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 150494#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 150495#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 151015#L693 assume !(1 == ~t5_pc~0); 151199#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 150820#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 150821#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 151733#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 150907#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 150841#L712 assume !(1 == ~t6_pc~0); 150842#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 151300#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 151301#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 151614#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 151414#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 151411#L731 assume !(1 == ~t7_pc~0); 151412#L731-2 is_transmit7_triggered_~__retres1~7#1 := 0; 150533#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 150534#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 151528#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 151658#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 150446#L750 assume !(1 == ~t8_pc~0); 150132#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 150131#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 150634#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 151747#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 150773#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 150774#L769 assume 1 == ~t9_pc~0; 151352#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 150299#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 150300#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 151093#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 151589#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 151682#L788 assume !(1 == ~t10_pc~0); 151213#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 151214#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 151474#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 151475#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 150444#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 150445#L807 assume 1 == ~t11_pc~0; 151692#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 151228#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 151398#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 151879#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 152062#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 151805#L826 assume !(1 == ~t12_pc~0); 150845#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 150846#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 151422#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 151937#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 151008#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 150915#L1344 assume !(1 == ~M_E~0); 150916#L1344-2 assume !(1 == ~T1_E~0); 151065#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 151257#L1354-1 assume !(1 == ~T3_E~0); 151258#L1359-1 assume !(1 == ~T4_E~0); 151670#L1364-1 assume !(1 == ~T5_E~0); 150551#L1369-1 assume !(1 == ~T6_E~0); 150552#L1374-1 assume !(1 == ~T7_E~0); 151264#L1379-1 assume !(1 == ~T8_E~0); 151265#L1384-1 assume !(1 == ~T9_E~0); 151335#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 151852#L1394-1 assume !(1 == ~T11_E~0); 151853#L1399-1 assume !(1 == ~T12_E~0); 151975#L1404-1 assume !(1 == ~E_M~0); 150671#L1409-1 assume !(1 == ~E_1~0); 150672#L1414-1 assume !(1 == ~E_2~0); 151568#L1419-1 assume !(1 == ~E_3~0); 150311#L1424-1 assume !(1 == ~E_4~0); 150312#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 151276#L1434-1 assume !(1 == ~E_6~0); 151877#L1439-1 assume !(1 == ~E_7~0); 150362#L1444-1 assume !(1 == ~E_8~0); 150363#L1449-1 assume !(1 == ~E_9~0); 150779#L1454-1 assume !(1 == ~E_10~0); 150780#L1459-1 assume !(1 == ~E_11~0); 151372#L1464-1 assume !(1 == ~E_12~0); 151373#L1469-1 assume { :end_inline_reset_delta_events } true; 151428#L1815-2 [2021-11-13 18:09:49,243 INFO L793 eck$LassoCheckResult]: Loop: 151428#L1815-2 assume !false; 151590#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 151230#L1181 assume !false; 151304#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 168652#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 168640#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 168638#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 168635#L1008 assume !(0 != eval_~tmp~0#1); 168636#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 173396#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 173394#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 173392#L1206-5 assume !(0 == ~T1_E~0); 173390#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 173388#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 173386#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 173384#L1226-3 assume !(0 == ~T5_E~0); 173382#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 173380#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 173378#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 173376#L1246-3 assume !(0 == ~T9_E~0); 173374#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 173372#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 173370#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 173368#L1266-3 assume !(0 == ~E_M~0); 173366#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 173364#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 173362#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 173360#L1286-3 assume !(0 == ~E_4~0); 173358#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 173355#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 173352#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 173348#L1306-3 assume !(0 == ~E_8~0); 173343#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 173341#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 173340#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 173339#L1326-3 assume !(0 == ~E_12~0); 173337#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 173335#L598-42 assume !(1 == ~m_pc~0); 173333#L598-44 is_master_triggered_~__retres1~0#1 := 0; 173331#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 173330#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 173329#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 173328#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 173327#L617-42 assume !(1 == ~t1_pc~0); 173326#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 173324#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 173322#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 173320#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 173318#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 151961#L636-42 assume !(1 == ~t2_pc~0); 151962#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 172628#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 172621#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 172613#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 172608#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 172603#L655-42 assume 1 == ~t3_pc~0; 172595#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 172589#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 172582#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 172576#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 172568#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 172561#L674-42 assume !(1 == ~t4_pc~0); 172553#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 172547#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 172541#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 172534#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 172529#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 172523#L693-42 assume 1 == ~t5_pc~0; 172516#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 172511#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 172506#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 172502#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 172499#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 150783#L712-42 assume !(1 == ~t6_pc~0); 150784#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 173018#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 173016#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 173014#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 173012#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 173010#L731-42 assume !(1 == ~t7_pc~0); 172098#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 173006#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 173005#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 173004#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 173003#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 173002#L750-42 assume !(1 == ~t8_pc~0); 173000#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 172999#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 172998#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 172997#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 152047#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 151193#L769-42 assume 1 == ~t9_pc~0; 150995#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 150996#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 151758#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 151848#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 150601#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 150602#L788-42 assume 1 == ~t10_pc~0; 151204#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 151438#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 151142#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 151143#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 152032#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 152002#L807-42 assume !(1 == ~t11_pc~0); 150210#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 150211#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 150346#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 150347#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 150349#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 150596#L826-42 assume !(1 == ~t12_pc~0); 150598#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 150791#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 151646#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 150587#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 150588#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 151494#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 151495#L1344-5 assume !(1 == ~T1_E~0); 151416#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 150747#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 150748#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 151432#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 152006#L1369-3 assume !(1 == ~T6_E~0); 151876#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 150510#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 150511#L1384-3 assume !(1 == ~T9_E~0); 150745#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 150746#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 151058#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 151888#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 151840#L1409-3 assume !(1 == ~E_1~0); 151841#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 151930#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 151640#L1424-3 assume !(1 == ~E_4~0); 150410#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 150411#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 151431#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 150354#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 150355#L1449-3 assume !(1 == ~E_9~0); 150461#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 151425#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 151426#L1464-3 assume !(1 == ~E_12~0); 151871#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 151286#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 150259#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 150260#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 150872#L1834 assume !(0 == start_simulation_~tmp~3#1); 151546#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 151570#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 150951#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 151148#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 151379#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 151858#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 150245#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 150246#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 151428#L1815-2 [2021-11-13 18:09:49,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:49,244 INFO L85 PathProgramCache]: Analyzing trace with hash 195137279, now seen corresponding path program 1 times [2021-11-13 18:09:49,244 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:49,244 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [951190307] [2021-11-13 18:09:49,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:49,245 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:49,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:49,299 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:49,299 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:49,301 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [951190307] [2021-11-13 18:09:49,301 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [951190307] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:49,302 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:49,302 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 18:09:49,302 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [121654958] [2021-11-13 18:09:49,302 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:49,305 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:49,306 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:49,306 INFO L85 PathProgramCache]: Analyzing trace with hash 1339385818, now seen corresponding path program 1 times [2021-11-13 18:09:49,306 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:49,306 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021552765] [2021-11-13 18:09:49,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:49,307 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:49,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:49,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:49,352 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:49,352 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021552765] [2021-11-13 18:09:49,352 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1021552765] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:49,353 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:49,353 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:49,353 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [458850940] [2021-11-13 18:09:49,353 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:49,354 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:49,354 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:49,354 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-13 18:09:49,354 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-13 18:09:49,355 INFO L87 Difference]: Start difference. First operand 23322 states and 32877 transitions. cyclomatic complexity: 9557 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:50,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:50,252 INFO L93 Difference]: Finished difference Result 56005 states and 79338 transitions. [2021-11-13 18:09:50,252 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-13 18:09:50,253 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56005 states and 79338 transitions. [2021-11-13 18:09:50,664 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 55704 [2021-11-13 18:09:50,916 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56005 states to 56005 states and 79338 transitions. [2021-11-13 18:09:50,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 56005 [2021-11-13 18:09:50,954 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 56005 [2021-11-13 18:09:50,954 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56005 states and 79338 transitions. [2021-11-13 18:09:50,999 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:51,000 INFO L681 BuchiCegarLoop]: Abstraction has 56005 states and 79338 transitions. [2021-11-13 18:09:51,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56005 states and 79338 transitions. [2021-11-13 18:09:51,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56005 to 23949. [2021-11-13 18:09:51,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23949 states, 23949 states have (on average 1.3989728172366278) internal successors, (33504), 23948 states have internal predecessors, (33504), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:51,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23949 states to 23949 states and 33504 transitions. [2021-11-13 18:09:51,562 INFO L704 BuchiCegarLoop]: Abstraction has 23949 states and 33504 transitions. [2021-11-13 18:09:51,562 INFO L587 BuchiCegarLoop]: Abstraction has 23949 states and 33504 transitions. [2021-11-13 18:09:51,562 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-13 18:09:51,562 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23949 states and 33504 transitions. [2021-11-13 18:09:51,650 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 23776 [2021-11-13 18:09:51,650 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:51,651 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:51,656 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:51,656 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:51,657 INFO L791 eck$LassoCheckResult]: Stem: 230267#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 230268#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 229689#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 229663#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 229664#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 231015#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 229964#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 229429#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 229430#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 230757#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 230910#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 231440#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 231441#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 230177#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 230178#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 230792#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 230697#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 230698#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 230868#L1206 assume !(0 == ~M_E~0); 230156#L1206-2 assume !(0 == ~T1_E~0); 230157#L1211-1 assume !(0 == ~T2_E~0); 231195#L1216-1 assume !(0 == ~T3_E~0); 229946#L1221-1 assume !(0 == ~T4_E~0); 229947#L1226-1 assume !(0 == ~T5_E~0); 229618#L1231-1 assume !(0 == ~T6_E~0); 229619#L1236-1 assume !(0 == ~T7_E~0); 231244#L1241-1 assume !(0 == ~T8_E~0); 230007#L1246-1 assume !(0 == ~T9_E~0); 230008#L1251-1 assume !(0 == ~T10_E~0); 230235#L1256-1 assume !(0 == ~T11_E~0); 229441#L1261-1 assume !(0 == ~T12_E~0); 229442#L1266-1 assume !(0 == ~E_M~0); 231420#L1271-1 assume !(0 == ~E_1~0); 230898#L1276-1 assume !(0 == ~E_2~0); 230899#L1281-1 assume !(0 == ~E_3~0); 230820#L1286-1 assume !(0 == ~E_4~0); 229849#L1291-1 assume !(0 == ~E_5~0); 229850#L1296-1 assume !(0 == ~E_6~0); 230603#L1301-1 assume !(0 == ~E_7~0); 230604#L1306-1 assume !(0 == ~E_8~0); 231116#L1311-1 assume !(0 == ~E_9~0); 229812#L1316-1 assume !(0 == ~E_10~0); 229813#L1321-1 assume !(0 == ~E_11~0); 230621#L1326-1 assume !(0 == ~E_12~0); 229683#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 229684#L598 assume !(1 == ~m_pc~0); 230392#L598-2 is_master_triggered_~__retres1~0#1 := 0; 230393#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 231216#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 231368#L1497 assume !(0 != activate_threads_~tmp~1#1); 231369#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 231286#L617 assume !(1 == ~t1_pc~0); 230029#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 230030#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 231489#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 231387#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 230714#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 230715#L636 assume !(1 == ~t2_pc~0); 231307#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 230465#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 229831#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 229832#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 230756#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 230362#L655 assume !(1 == ~t3_pc~0); 230363#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 231225#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 229709#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 229710#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 231421#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 231422#L674 assume !(1 == ~t4_pc~0); 229534#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 231201#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 230905#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 229833#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 229834#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 230359#L693 assume !(1 == ~t5_pc~0); 230548#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 230158#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 230159#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 231121#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 230248#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 230182#L712 assume !(1 == ~t6_pc~0); 230183#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 230659#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 230660#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 230985#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 230777#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 230772#L731 assume !(1 == ~t7_pc~0); 230773#L731-2 is_transmit7_triggered_~__retres1~7#1 := 0; 229872#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 229873#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 230893#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 231030#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 229789#L750 assume !(1 == ~t8_pc~0); 229472#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 229975#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 229976#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 231135#L1561 assume !(0 != activate_threads_~tmp___7~0#1); 230114#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 230115#L769 assume 1 == ~t9_pc~0; 230710#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 229641#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 229642#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 230437#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 230955#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 231060#L788 assume !(1 == ~t10_pc~0); 230564#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 230565#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 230838#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 230839#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 229785#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 229786#L807 assume 1 == ~t11_pc~0; 231070#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 230581#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 230758#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 231276#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 231486#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 231200#L826 assume !(1 == ~t12_pc~0); 230184#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 230185#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 230787#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 231330#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 230352#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 230256#L1344 assume !(1 == ~M_E~0); 230257#L1344-2 assume !(1 == ~T1_E~0); 230409#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 230610#L1354-1 assume !(1 == ~T3_E~0); 230611#L1359-1 assume !(1 == ~T4_E~0); 231043#L1364-1 assume !(1 == ~T5_E~0); 229892#L1369-1 assume !(1 == ~T6_E~0); 229893#L1374-1 assume !(1 == ~T7_E~0); 230617#L1379-1 assume !(1 == ~T8_E~0); 230618#L1384-1 assume !(1 == ~T9_E~0); 230696#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 231247#L1394-1 assume !(1 == ~T11_E~0); 231248#L1399-1 assume !(1 == ~T12_E~0); 231385#L1404-1 assume !(1 == ~E_M~0); 230011#L1409-1 assume !(1 == ~E_1~0); 230012#L1414-1 assume !(1 == ~E_2~0); 230934#L1419-1 assume !(1 == ~E_3~0); 229654#L1424-1 assume !(1 == ~E_4~0); 229655#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 230628#L1434-1 assume !(1 == ~E_6~0); 231274#L1439-1 assume !(1 == ~E_7~0); 229705#L1444-1 assume !(1 == ~E_8~0); 229706#L1449-1 assume !(1 == ~E_9~0); 230120#L1454-1 assume !(1 == ~E_10~0); 230121#L1459-1 assume !(1 == ~E_11~0); 230732#L1464-1 assume !(1 == ~E_12~0); 230733#L1469-1 assume { :end_inline_reset_delta_events } true; 230793#L1815-2 [2021-11-13 18:09:51,658 INFO L793 eck$LassoCheckResult]: Loop: 230793#L1815-2 assume !false; 245359#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 245353#L1181 assume !false; 245351#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 245208#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 244987#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 244981#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 244979#L1008 assume !(0 != eval_~tmp~0#1); 231481#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 229648#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 229649#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 231459#L1206-5 assume !(0 == ~T1_E~0); 230731#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 229773#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 229774#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 230379#L1226-3 assume !(0 == ~T5_E~0); 229837#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 229838#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 230153#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 231325#L1246-3 assume !(0 == ~T9_E~0); 231180#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 230857#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 229795#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 229796#L1266-3 assume !(0 == ~E_M~0); 230447#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 252624#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 252623#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 252622#L1286-3 assume !(0 == ~E_4~0); 252620#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 252617#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 252615#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 252613#L1306-3 assume !(0 == ~E_8~0); 252607#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 252525#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 252524#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 252523#L1326-3 assume !(0 == ~E_12~0); 252052#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 252050#L598-42 assume !(1 == ~m_pc~0); 252049#L598-44 is_master_triggered_~__retres1~0#1 := 0; 252045#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 252043#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 252041#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 252039#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 252036#L617-42 assume 1 == ~t1_pc~0; 252034#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 252035#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 252061#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 252026#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 252024#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 252022#L636-42 assume !(1 == ~t2_pc~0); 249430#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 252019#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 252016#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 252014#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 252012#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 252010#L655-42 assume 1 == ~t3_pc~0; 252007#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 252004#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 252002#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 252000#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 251998#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 251996#L674-42 assume !(1 == ~t4_pc~0); 251993#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 251992#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 251991#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 251614#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 251611#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 251609#L693-42 assume !(1 == ~t5_pc~0); 251607#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 251604#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 251602#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 251599#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 251215#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 248012#L712-42 assume !(1 == ~t6_pc~0); 248008#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 248000#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 247995#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 247990#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 247985#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 247980#L731-42 assume !(1 == ~t7_pc~0); 247758#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 247968#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 247962#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 247957#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 247952#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 247951#L750-42 assume !(1 == ~t8_pc~0); 247947#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 247944#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 247943#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 247942#L1561-42 assume !(0 != activate_threads_~tmp___7~0#1); 247938#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 247936#L769-42 assume !(1 == ~t9_pc~0); 247934#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 247931#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 247929#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 247927#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 247924#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 247922#L788-42 assume !(1 == ~t10_pc~0); 247920#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 247917#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 247915#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 247912#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 247910#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 247908#L807-42 assume 1 == ~t11_pc~0; 247906#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 247903#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 247901#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 246438#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 246436#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 246434#L826-42 assume !(1 == ~t12_pc~0); 246430#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 246428#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 246426#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 246424#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 246422#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 246420#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 246417#L1344-5 assume !(1 == ~T1_E~0); 246415#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 246413#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 246411#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 246409#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 246407#L1369-3 assume !(1 == ~T6_E~0); 246404#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 246402#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 246400#L1384-3 assume !(1 == ~T9_E~0); 246398#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 246396#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 246393#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 246391#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 246389#L1409-3 assume !(1 == ~E_1~0); 246387#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 246385#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 246383#L1424-3 assume !(1 == ~E_4~0); 246382#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 246378#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 246376#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 246059#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 246057#L1449-3 assume !(1 == ~E_9~0); 246055#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 246052#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 246050#L1464-3 assume !(1 == ~E_12~0); 246048#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 246043#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 246029#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 246027#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 246024#L1834 assume !(0 == start_simulation_~tmp~3#1); 246021#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 246008#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 245998#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 245997#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 245996#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 245995#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 245365#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 245363#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 230793#L1815-2 [2021-11-13 18:09:51,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:51,659 INFO L85 PathProgramCache]: Analyzing trace with hash 639037953, now seen corresponding path program 1 times [2021-11-13 18:09:51,659 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:51,660 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2122016277] [2021-11-13 18:09:51,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:51,660 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:51,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:51,915 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:51,915 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:51,916 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2122016277] [2021-11-13 18:09:51,916 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2122016277] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:51,916 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:51,916 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:51,916 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1876516471] [2021-11-13 18:09:51,917 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:51,917 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:51,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:51,918 INFO L85 PathProgramCache]: Analyzing trace with hash -1792183269, now seen corresponding path program 1 times [2021-11-13 18:09:51,918 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:51,918 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1831693500] [2021-11-13 18:09:51,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:51,918 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:51,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:51,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:51,959 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:51,959 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1831693500] [2021-11-13 18:09:51,959 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1831693500] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:51,959 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:51,960 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:51,960 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497601270] [2021-11-13 18:09:51,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:51,961 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:51,961 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:51,961 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:09:51,961 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:09:51,962 INFO L87 Difference]: Start difference. First operand 23949 states and 33504 transitions. cyclomatic complexity: 9557 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:52,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:52,608 INFO L93 Difference]: Finished difference Result 57708 states and 80229 transitions. [2021-11-13 18:09:52,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:09:52,610 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57708 states and 80229 transitions. [2021-11-13 18:09:52,891 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 56716 [2021-11-13 18:09:53,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57708 states to 57708 states and 80229 transitions. [2021-11-13 18:09:53,266 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57708 [2021-11-13 18:09:53,304 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57708 [2021-11-13 18:09:53,304 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57708 states and 80229 transitions. [2021-11-13 18:09:53,373 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:53,373 INFO L681 BuchiCegarLoop]: Abstraction has 57708 states and 80229 transitions. [2021-11-13 18:09:53,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57708 states and 80229 transitions. [2021-11-13 18:09:53,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57708 to 45940. [2021-11-13 18:09:54,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45940 states, 45940 states have (on average 1.3941010013060513) internal successors, (64045), 45939 states have internal predecessors, (64045), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:54,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45940 states to 45940 states and 64045 transitions. [2021-11-13 18:09:54,318 INFO L704 BuchiCegarLoop]: Abstraction has 45940 states and 64045 transitions. [2021-11-13 18:09:54,318 INFO L587 BuchiCegarLoop]: Abstraction has 45940 states and 64045 transitions. [2021-11-13 18:09:54,318 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-13 18:09:54,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45940 states and 64045 transitions. [2021-11-13 18:09:54,426 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 45760 [2021-11-13 18:09:54,426 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:54,426 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:54,432 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:54,433 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:54,433 INFO L791 eck$LassoCheckResult]: Stem: 311938#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 311939#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 311357#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 311334#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 311335#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 312682#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 311632#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 311096#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 311097#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 312420#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 312574#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 313119#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 313120#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 311848#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 311849#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 312453#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 312359#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 312360#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 312530#L1206 assume !(0 == ~M_E~0); 311824#L1206-2 assume !(0 == ~T1_E~0); 311825#L1211-1 assume !(0 == ~T2_E~0); 312861#L1216-1 assume !(0 == ~T3_E~0); 311614#L1221-1 assume !(0 == ~T4_E~0); 311615#L1226-1 assume !(0 == ~T5_E~0); 311287#L1231-1 assume !(0 == ~T6_E~0); 311288#L1236-1 assume !(0 == ~T7_E~0); 312911#L1241-1 assume !(0 == ~T8_E~0); 311676#L1246-1 assume !(0 == ~T9_E~0); 311677#L1251-1 assume !(0 == ~T10_E~0); 311903#L1256-1 assume !(0 == ~T11_E~0); 311108#L1261-1 assume !(0 == ~T12_E~0); 311109#L1266-1 assume !(0 == ~E_M~0); 313092#L1271-1 assume !(0 == ~E_1~0); 312562#L1276-1 assume !(0 == ~E_2~0); 312563#L1281-1 assume !(0 == ~E_3~0); 312485#L1286-1 assume !(0 == ~E_4~0); 311516#L1291-1 assume !(0 == ~E_5~0); 311517#L1296-1 assume !(0 == ~E_6~0); 312271#L1301-1 assume !(0 == ~E_7~0); 312272#L1306-1 assume !(0 == ~E_8~0); 312780#L1311-1 assume !(0 == ~E_9~0); 311479#L1316-1 assume !(0 == ~E_10~0); 311480#L1321-1 assume !(0 == ~E_11~0); 312290#L1326-1 assume !(0 == ~E_12~0); 311351#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 311352#L598 assume !(1 == ~m_pc~0); 312060#L598-2 is_master_triggered_~__retres1~0#1 := 0; 312061#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 312881#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 313033#L1497 assume !(0 != activate_threads_~tmp~1#1); 313034#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 312948#L617 assume !(1 == ~t1_pc~0); 311698#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 311699#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 313184#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 313045#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 312374#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 312375#L636 assume !(1 == ~t2_pc~0); 312971#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 312133#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 311498#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 311499#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 312419#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 312033#L655 assume !(1 == ~t3_pc~0); 312034#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 312889#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 311375#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 311376#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 313093#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 313094#L674 assume !(1 == ~t4_pc~0); 311201#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 312865#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 312569#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 311502#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 311503#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 312027#L693 assume !(1 == ~t5_pc~0); 312219#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 311829#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 311830#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 312782#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 311916#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 311850#L712 assume !(1 == ~t6_pc~0); 311851#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 312326#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 312327#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 312651#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 312438#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 312434#L731 assume !(1 == ~t7_pc~0); 312435#L731-2 is_transmit7_triggered_~__retres1~7#1 := 0; 311542#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 311543#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 312558#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 312698#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 311456#L750 assume !(1 == ~t8_pc~0); 311139#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 311643#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 311644#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 312803#L1561 assume !(0 != activate_threads_~tmp___7~0#1); 311782#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 311783#L769 assume !(1 == ~t9_pc~0); 312373#L769-2 is_transmit9_triggered_~__retres1~9#1 := 0; 311308#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 311309#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 312108#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 312622#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 312726#L788 assume !(1 == ~t10_pc~0); 312234#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 312235#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 312502#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 312503#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 311454#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 311455#L807 assume 1 == ~t11_pc~0; 312736#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 312249#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 312421#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 312936#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 313178#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 312864#L826 assume !(1 == ~t12_pc~0); 311854#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 311855#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 312448#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 313001#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 312020#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 311924#L1344 assume !(1 == ~M_E~0); 311925#L1344-2 assume !(1 == ~T1_E~0); 312079#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 312281#L1354-1 assume !(1 == ~T3_E~0); 312282#L1359-1 assume !(1 == ~T4_E~0); 312712#L1364-1 assume !(1 == ~T5_E~0); 311560#L1369-1 assume !(1 == ~T6_E~0); 311561#L1374-1 assume !(1 == ~T7_E~0); 312288#L1379-1 assume !(1 == ~T8_E~0); 312289#L1384-1 assume !(1 == ~T9_E~0); 312357#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 312913#L1394-1 assume !(1 == ~T11_E~0); 312914#L1399-1 assume !(1 == ~T12_E~0); 313043#L1404-1 assume !(1 == ~E_M~0); 311680#L1409-1 assume !(1 == ~E_1~0); 311681#L1414-1 assume !(1 == ~E_2~0); 312599#L1419-1 assume !(1 == ~E_3~0); 311321#L1424-1 assume !(1 == ~E_4~0); 311322#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 312300#L1434-1 assume !(1 == ~E_6~0); 312935#L1439-1 assume !(1 == ~E_7~0); 311371#L1444-1 assume !(1 == ~E_8~0); 311372#L1449-1 assume !(1 == ~E_9~0); 311788#L1454-1 assume !(1 == ~E_10~0); 311789#L1459-1 assume !(1 == ~E_11~0); 312394#L1464-1 assume !(1 == ~E_12~0); 312395#L1469-1 assume { :end_inline_reset_delta_events } true; 312454#L1815-2 [2021-11-13 18:09:54,434 INFO L793 eck$LassoCheckResult]: Loop: 312454#L1815-2 assume !false; 312623#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 312251#L1181 assume !false; 312330#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 312276#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 311099#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 311820#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 312432#L1008 assume !(0 != eval_~tmp~0#1); 312433#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 311317#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 311318#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 313135#L1206-5 assume !(0 == ~T1_E~0); 312393#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 311439#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 311440#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 312047#L1226-3 assume !(0 == ~T5_E~0); 311504#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 311505#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 311821#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 312996#L1246-3 assume !(0 == ~T9_E~0); 312850#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 312519#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 311465#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 311466#L1266-3 assume !(0 == ~E_M~0); 311500#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 311501#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 311987#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 311988#L1286-3 assume !(0 == ~E_4~0); 312596#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 312597#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 313103#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 313039#L1306-3 assume !(0 == ~E_8~0); 312127#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 311388#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 311389#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 311462#L1326-3 assume !(0 == ~E_12~0); 312243#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 312606#L598-42 assume !(1 == ~m_pc~0); 312607#L598-44 is_master_triggered_~__retres1~0#1 := 0; 312756#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 311540#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 311541#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 313040#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 312303#L617-42 assume 1 == ~t1_pc~0; 312041#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 312042#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 357035#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 357034#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 311608#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 311609#L636-42 assume !(1 == ~t2_pc~0); 312093#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 312094#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 312496#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 312497#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 312706#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 312538#L655-42 assume !(1 == ~t3_pc~0); 312062#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 312063#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 311678#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 311679#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 312888#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 312807#L674-42 assume !(1 == ~t4_pc~0); 312525#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 312439#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 311270#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 311271#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 312217#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 312218#L693-42 assume 1 == ~t5_pc~0; 312508#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 312509#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 312571#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 312567#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 312568#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 311795#L712-42 assume !(1 == ~t6_pc~0); 311796#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 312699#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 312385#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 312386#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 311907#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 311908#L731-42 assume !(1 == ~t7_pc~0); 311601#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 311602#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 312796#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 311812#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 311813#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 312765#L750-42 assume !(1 == ~t8_pc~0); 355860#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 355858#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 355856#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 355854#L1561-42 assume !(0 != activate_threads_~tmp___7~0#1); 355851#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 355849#L769-42 assume !(1 == ~t9_pc~0); 340203#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 355847#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 355844#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 355842#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 355840#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 355838#L788-42 assume !(1 == ~t10_pc~0); 355835#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 355832#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 355830#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 355828#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 355827#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 354628#L807-42 assume !(1 == ~t11_pc~0); 354625#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 354626#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 354618#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 354617#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 354616#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 354615#L826-42 assume !(1 == ~t12_pc~0); 354613#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 354612#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 354494#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 354486#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 354485#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 354484#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 354464#L1344-5 assume !(1 == ~T1_E~0); 354459#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 311755#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 311756#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 312458#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 313087#L1369-3 assume !(1 == ~T6_E~0); 312934#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 311518#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 311519#L1384-3 assume !(1 == ~T9_E~0); 312854#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 355781#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 354775#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 312945#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 312946#L1409-3 assume !(1 == ~E_1~0); 312993#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 312994#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 312678#L1424-3 assume !(1 == ~E_4~0); 311419#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 311420#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 312457#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 311363#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 311364#L1449-3 assume !(1 == ~E_9~0); 311471#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 312451#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 312452#L1464-3 assume !(1 == ~E_12~0); 312929#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 312311#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 311268#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 311269#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 311881#L1834 assume !(0 == start_simulation_~tmp~3#1); 312576#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 312601#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 311961#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 312163#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 312403#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 312919#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 311253#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 311254#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 312454#L1815-2 [2021-11-13 18:09:54,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:54,435 INFO L85 PathProgramCache]: Analyzing trace with hash -1461803262, now seen corresponding path program 1 times [2021-11-13 18:09:54,435 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:54,435 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2017079656] [2021-11-13 18:09:54,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:54,436 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:54,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:54,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:54,489 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:54,489 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2017079656] [2021-11-13 18:09:54,489 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2017079656] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:54,489 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:54,490 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:54,490 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [960694024] [2021-11-13 18:09:54,490 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:54,490 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:54,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:54,491 INFO L85 PathProgramCache]: Analyzing trace with hash -223383652, now seen corresponding path program 1 times [2021-11-13 18:09:54,491 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:54,492 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409259273] [2021-11-13 18:09:54,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:54,492 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:54,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:54,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:54,532 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:54,533 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [409259273] [2021-11-13 18:09:54,533 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [409259273] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:54,533 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:54,533 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:54,533 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [712410923] [2021-11-13 18:09:54,534 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:54,534 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:54,534 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:54,535 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:09:54,535 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:09:54,535 INFO L87 Difference]: Start difference. First operand 45940 states and 64045 transitions. cyclomatic complexity: 18107 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:55,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:55,353 INFO L93 Difference]: Finished difference Result 110371 states and 152906 transitions. [2021-11-13 18:09:55,353 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:09:55,354 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 110371 states and 152906 transitions. [2021-11-13 18:09:56,168 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 108560 [2021-11-13 18:09:56,460 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 110371 states to 110371 states and 152906 transitions. [2021-11-13 18:09:56,461 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 110371 [2021-11-13 18:09:56,521 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 110371 [2021-11-13 18:09:56,522 INFO L73 IsDeterministic]: Start isDeterministic. Operand 110371 states and 152906 transitions. [2021-11-13 18:09:56,596 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:09:56,596 INFO L681 BuchiCegarLoop]: Abstraction has 110371 states and 152906 transitions. [2021-11-13 18:09:56,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110371 states and 152906 transitions. [2021-11-13 18:09:57,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110371 to 88163. [2021-11-13 18:09:58,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 88163 states, 88163 states have (on average 1.3891768655785306) internal successors, (122474), 88162 states have internal predecessors, (122474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:58,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88163 states to 88163 states and 122474 transitions. [2021-11-13 18:09:58,668 INFO L704 BuchiCegarLoop]: Abstraction has 88163 states and 122474 transitions. [2021-11-13 18:09:58,668 INFO L587 BuchiCegarLoop]: Abstraction has 88163 states and 122474 transitions. [2021-11-13 18:09:58,668 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-11-13 18:09:58,668 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88163 states and 122474 transitions. [2021-11-13 18:09:58,998 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 87968 [2021-11-13 18:09:58,998 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:09:58,999 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:09:59,011 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:59,012 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:09:59,013 INFO L791 eck$LassoCheckResult]: Stem: 468258#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 468259#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 467675#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 467650#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 467651#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 469016#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 467954#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 467417#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 467418#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 468744#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 468905#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 469470#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 469471#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 468166#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 468167#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 468778#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 468684#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 468685#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 468858#L1206 assume !(0 == ~M_E~0); 468145#L1206-2 assume !(0 == ~T1_E~0); 468146#L1211-1 assume !(0 == ~T2_E~0); 469197#L1216-1 assume !(0 == ~T3_E~0); 467936#L1221-1 assume !(0 == ~T4_E~0); 467937#L1226-1 assume !(0 == ~T5_E~0); 467605#L1231-1 assume !(0 == ~T6_E~0); 467606#L1236-1 assume !(0 == ~T7_E~0); 469242#L1241-1 assume !(0 == ~T8_E~0); 467997#L1246-1 assume !(0 == ~T9_E~0); 467998#L1251-1 assume !(0 == ~T10_E~0); 468225#L1256-1 assume !(0 == ~T11_E~0); 467429#L1261-1 assume !(0 == ~T12_E~0); 467430#L1266-1 assume !(0 == ~E_M~0); 469442#L1271-1 assume !(0 == ~E_1~0); 468892#L1276-1 assume !(0 == ~E_2~0); 468893#L1281-1 assume !(0 == ~E_3~0); 468810#L1286-1 assume !(0 == ~E_4~0); 467838#L1291-1 assume !(0 == ~E_5~0); 467839#L1296-1 assume !(0 == ~E_6~0); 468594#L1301-1 assume !(0 == ~E_7~0); 468595#L1306-1 assume !(0 == ~E_8~0); 469109#L1311-1 assume !(0 == ~E_9~0); 467801#L1316-1 assume !(0 == ~E_10~0); 467802#L1321-1 assume !(0 == ~E_11~0); 468613#L1326-1 assume !(0 == ~E_12~0); 467669#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 467670#L598 assume !(1 == ~m_pc~0); 468383#L598-2 is_master_triggered_~__retres1~0#1 := 0; 468384#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 469217#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 469380#L1497 assume !(0 != activate_threads_~tmp~1#1); 469381#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 469283#L617 assume !(1 == ~t1_pc~0); 468020#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 468021#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 469524#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 469397#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 468700#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 468701#L636 assume !(1 == ~t2_pc~0); 469304#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 468455#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 467820#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 467821#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 468743#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 468351#L655 assume !(1 == ~t3_pc~0); 468352#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 469225#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 467694#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 467695#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 469443#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 469444#L674 assume !(1 == ~t4_pc~0); 467522#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 469203#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 468899#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 467822#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 467823#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 468348#L693 assume !(1 == ~t5_pc~0); 468543#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 468147#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 468148#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 469114#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 468238#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 468171#L712 assume !(1 == ~t6_pc~0); 468172#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 468649#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 468650#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 468984#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 468762#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 468758#L731 assume !(1 == ~t7_pc~0); 468759#L731-2 is_transmit7_triggered_~__retres1~7#1 := 0; 467862#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 467863#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 468887#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 469033#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 467777#L750 assume !(1 == ~t8_pc~0); 467460#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 468878#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 469523#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 469130#L1561 assume !(0 != activate_threads_~tmp___7~0#1); 468103#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 468104#L769 assume !(1 == ~t9_pc~0); 468697#L769-2 is_transmit9_triggered_~__retres1~9#1 := 0; 467629#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 467630#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 468428#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 468957#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 469061#L788 assume !(1 == ~t10_pc~0); 468558#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 468559#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 468827#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 468828#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 467773#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 467774#L807 assume !(1 == ~t11_pc~0); 468572#L807-2 is_transmit11_triggered_~__retres1~11#1 := 0; 468573#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 468745#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 469273#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 469520#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 469202#L826 assume !(1 == ~t12_pc~0); 468173#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 468174#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 468773#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 469337#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 468341#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 468247#L1344 assume !(1 == ~M_E~0); 468248#L1344-2 assume !(1 == ~T1_E~0); 468400#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 468601#L1354-1 assume !(1 == ~T3_E~0); 468602#L1359-1 assume !(1 == ~T4_E~0); 469047#L1364-1 assume !(1 == ~T5_E~0); 467882#L1369-1 assume !(1 == ~T6_E~0); 467883#L1374-1 assume !(1 == ~T7_E~0); 468609#L1379-1 assume !(1 == ~T8_E~0); 468610#L1384-1 assume !(1 == ~T9_E~0); 468683#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 469246#L1394-1 assume !(1 == ~T11_E~0); 469247#L1399-1 assume !(1 == ~T12_E~0); 469396#L1404-1 assume !(1 == ~E_M~0); 468001#L1409-1 assume !(1 == ~E_1~0); 468002#L1414-1 assume !(1 == ~E_2~0); 468933#L1419-1 assume !(1 == ~E_3~0); 467641#L1424-1 assume !(1 == ~E_4~0); 467642#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 468620#L1434-1 assume !(1 == ~E_6~0); 469271#L1439-1 assume !(1 == ~E_7~0); 467690#L1444-1 assume !(1 == ~E_8~0); 467691#L1449-1 assume !(1 == ~E_9~0); 468109#L1454-1 assume !(1 == ~E_10~0); 468110#L1459-1 assume !(1 == ~E_11~0); 468718#L1464-1 assume !(1 == ~E_12~0); 468719#L1469-1 assume { :end_inline_reset_delta_events } true; 468779#L1815-2 [2021-11-13 18:09:59,013 INFO L793 eck$LassoCheckResult]: Loop: 468779#L1815-2 assume !false; 468959#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 468575#L1181 assume !false; 468653#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 468599#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 467420#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 468140#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 468756#L1008 assume !(0 != eval_~tmp~0#1); 468757#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 555579#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 555578#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 555577#L1206-5 assume !(0 == ~T1_E~0); 555576#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 555575#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 555574#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 555573#L1226-3 assume !(0 == ~T5_E~0); 555572#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 468141#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 468142#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 469332#L1246-3 assume !(0 == ~T9_E~0); 469183#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 468846#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 467783#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 467784#L1266-3 assume !(0 == ~E_M~0); 468437#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 555565#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 468309#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 468310#L1286-3 assume !(0 == ~E_4~0); 468929#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 468930#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 469456#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 469457#L1306-3 assume !(0 == ~E_8~0); 555560#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 555559#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 467785#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 467786#L1326-3 assume !(0 == ~E_12~0); 468566#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 468940#L598-42 assume !(1 == ~m_pc~0); 468941#L598-44 is_master_triggered_~__retres1~0#1 := 0; 469086#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 467864#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 467865#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 469389#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 468629#L617-42 assume !(1 == ~t1_pc~0); 468366#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 468221#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 468222#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 469384#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 469385#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 469376#L636-42 assume !(1 == ~t2_pc~0); 468415#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 468416#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 468823#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 468824#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 469041#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 468872#L655-42 assume 1 == ~t3_pc~0; 468873#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 468387#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 555056#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 555055#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 555054#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 553827#L674-42 assume !(1 == ~t4_pc~0); 553822#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 553820#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 553818#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 553816#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 553813#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 552519#L693-42 assume 1 == ~t5_pc~0; 552515#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 552513#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 552511#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 552509#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 552507#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 552505#L712-42 assume !(1 == ~t6_pc~0); 549400#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 552503#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 552501#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 552499#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 552497#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 469348#L731-42 assume !(1 == ~t7_pc~0); 467923#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 467924#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 469124#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 468132#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 468133#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 467833#L750-42 assume !(1 == ~t8_pc~0); 467835#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 469194#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 468923#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 467723#L1561-42 assume !(0 != activate_threads_~tmp___7~0#1); 467724#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 468540#L769-42 assume !(1 == ~t9_pc~0); 468522#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 468523#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 469146#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 469243#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 467932#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 467933#L788-42 assume !(1 == ~t10_pc~0); 468549#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 553769#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 553767#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 553765#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 553764#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 553761#L807-42 assume !(1 == ~t11_pc~0); 494564#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 553741#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 467676#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 467677#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 467678#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 467927#L826-42 assume !(1 == ~t12_pc~0); 467929#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 468121#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 469021#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 467918#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 467919#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 468849#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 468850#L1344-5 assume !(1 == ~T1_E~0); 468764#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 468077#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 468078#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 468783#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 469437#L1369-3 assume !(1 == ~T6_E~0); 469270#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 467840#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 467841#L1384-3 assume !(1 == ~T9_E~0); 468075#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 468076#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 468393#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 469281#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 469234#L1409-3 assume !(1 == ~E_1~0); 469235#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 469331#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 469012#L1424-3 assume !(1 == ~E_4~0); 467738#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 467739#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 468782#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 467683#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 467684#L1449-3 assume !(1 == ~E_9~0); 467793#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 468776#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 468777#L1464-3 assume !(1 == ~E_12~0); 469266#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 468634#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 467588#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 467589#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 468203#L1834 assume !(0 == start_simulation_~tmp~3#1); 468906#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 468935#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 468285#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 468487#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 468727#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 469253#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 467573#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 467574#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 468779#L1815-2 [2021-11-13 18:09:59,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:59,014 INFO L85 PathProgramCache]: Analyzing trace with hash 1876235651, now seen corresponding path program 1 times [2021-11-13 18:09:59,015 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:59,015 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1194388888] [2021-11-13 18:09:59,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:59,016 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:59,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:59,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:59,094 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:59,095 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1194388888] [2021-11-13 18:09:59,095 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1194388888] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:59,095 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:59,095 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:09:59,095 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [814581347] [2021-11-13 18:09:59,096 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:59,096 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:09:59,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:09:59,097 INFO L85 PathProgramCache]: Analyzing trace with hash 470401950, now seen corresponding path program 1 times [2021-11-13 18:09:59,097 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:09:59,097 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [450413022] [2021-11-13 18:09:59,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:09:59,097 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:09:59,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:09:59,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:09:59,138 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:09:59,139 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [450413022] [2021-11-13 18:09:59,139 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [450413022] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:09:59,139 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:09:59,139 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:09:59,140 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [897079275] [2021-11-13 18:09:59,140 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:09:59,140 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:09:59,141 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:09:59,141 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:09:59,141 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:09:59,142 INFO L87 Difference]: Start difference. First operand 88163 states and 122474 transitions. cyclomatic complexity: 34313 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:09:59,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:09:59,949 INFO L93 Difference]: Finished difference Result 88163 states and 122280 transitions. [2021-11-13 18:09:59,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:09:59,952 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88163 states and 122280 transitions. [2021-11-13 18:10:00,287 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 87968 [2021-11-13 18:10:00,468 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88163 states to 88163 states and 122280 transitions. [2021-11-13 18:10:00,468 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88163 [2021-11-13 18:10:00,503 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88163 [2021-11-13 18:10:00,503 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88163 states and 122280 transitions. [2021-11-13 18:10:00,536 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:10:00,537 INFO L681 BuchiCegarLoop]: Abstraction has 88163 states and 122280 transitions. [2021-11-13 18:10:00,593 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88163 states and 122280 transitions. [2021-11-13 18:10:01,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88163 to 88163. [2021-11-13 18:10:01,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 88163 states, 88163 states have (on average 1.3869763959937842) internal successors, (122280), 88162 states have internal predecessors, (122280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:10:02,029 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88163 states to 88163 states and 122280 transitions. [2021-11-13 18:10:02,029 INFO L704 BuchiCegarLoop]: Abstraction has 88163 states and 122280 transitions. [2021-11-13 18:10:02,029 INFO L587 BuchiCegarLoop]: Abstraction has 88163 states and 122280 transitions. [2021-11-13 18:10:02,030 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-11-13 18:10:02,030 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88163 states and 122280 transitions. [2021-11-13 18:10:02,343 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 87968 [2021-11-13 18:10:02,344 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:10:02,344 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:10:02,357 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:10:02,357 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:10:02,358 INFO L791 eck$LassoCheckResult]: Stem: 644578#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 644579#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 644007#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 643982#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 643983#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 645330#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 644284#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 643750#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 643751#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 645064#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 645223#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 645794#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 645795#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 644491#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 644492#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 645099#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 645003#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 645004#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 645177#L1206 assume !(0 == ~M_E~0); 644469#L1206-2 assume !(0 == ~T1_E~0); 644470#L1211-1 assume !(0 == ~T2_E~0); 645507#L1216-1 assume !(0 == ~T3_E~0); 644265#L1221-1 assume !(0 == ~T4_E~0); 644266#L1226-1 assume !(0 == ~T5_E~0); 643938#L1231-1 assume !(0 == ~T6_E~0); 643939#L1236-1 assume !(0 == ~T7_E~0); 645562#L1241-1 assume !(0 == ~T8_E~0); 644325#L1246-1 assume !(0 == ~T9_E~0); 644326#L1251-1 assume !(0 == ~T10_E~0); 644546#L1256-1 assume !(0 == ~T11_E~0); 643762#L1261-1 assume !(0 == ~T12_E~0); 643763#L1266-1 assume !(0 == ~E_M~0); 645769#L1271-1 assume !(0 == ~E_1~0); 645210#L1276-1 assume !(0 == ~E_2~0); 645211#L1281-1 assume !(0 == ~E_3~0); 645129#L1286-1 assume !(0 == ~E_4~0); 644168#L1291-1 assume !(0 == ~E_5~0); 644169#L1296-1 assume !(0 == ~E_6~0); 644911#L1301-1 assume !(0 == ~E_7~0); 644912#L1306-1 assume !(0 == ~E_8~0); 645424#L1311-1 assume !(0 == ~E_9~0); 644131#L1316-1 assume !(0 == ~E_10~0); 644132#L1321-1 assume !(0 == ~E_11~0); 644929#L1326-1 assume !(0 == ~E_12~0); 644001#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 644002#L598 assume !(1 == ~m_pc~0); 644699#L598-2 is_master_triggered_~__retres1~0#1 := 0; 644700#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 645530#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 645692#L1497 assume !(0 != activate_threads_~tmp~1#1); 645693#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 645605#L617 assume !(1 == ~t1_pc~0); 644347#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 644348#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 645852#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 645713#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 645019#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 645020#L636 assume !(1 == ~t2_pc~0); 645627#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 644770#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 644150#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 644151#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 645063#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 644670#L655 assume !(1 == ~t3_pc~0); 644671#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 645538#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 644026#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 644027#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 645770#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 645771#L674 assume !(1 == ~t4_pc~0); 643856#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 645515#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 645217#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 644152#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 644153#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 644667#L693 assume !(1 == ~t5_pc~0); 644859#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 644471#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 644472#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 645428#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 644558#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 644496#L712 assume !(1 == ~t6_pc~0); 644497#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 644966#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 644967#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 645299#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 645083#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 645078#L731 assume !(1 == ~t7_pc~0); 645079#L731-2 is_transmit7_triggered_~__retres1~7#1 := 0; 644193#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 644194#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 645205#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 645346#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 644108#L750 assume !(1 == ~t8_pc~0); 643793#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 645195#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 645851#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 645446#L1561 assume !(0 != activate_threads_~tmp___7~0#1); 644427#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 644428#L769 assume !(1 == ~t9_pc~0); 645016#L769-2 is_transmit9_triggered_~__retres1~9#1 := 0; 643961#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 643962#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 644744#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 645272#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 645372#L788 assume !(1 == ~t10_pc~0); 644874#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 644875#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 645146#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 645147#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 644104#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 644105#L807 assume !(1 == ~t11_pc~0); 644889#L807-2 is_transmit11_triggered_~__retres1~11#1 := 0; 644890#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 645065#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 645592#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 645848#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 645514#L826 assume !(1 == ~t12_pc~0); 644498#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 644499#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 645093#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 645657#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 644660#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 644566#L1344 assume !(1 == ~M_E~0); 644567#L1344-2 assume !(1 == ~T1_E~0); 644716#L1349-1 assume !(1 == ~T2_E~0); 644918#L1354-1 assume !(1 == ~T3_E~0); 644919#L1359-1 assume !(1 == ~T4_E~0); 645358#L1364-1 assume !(1 == ~T5_E~0); 644213#L1369-1 assume !(1 == ~T6_E~0); 644214#L1374-1 assume !(1 == ~T7_E~0); 644925#L1379-1 assume !(1 == ~T8_E~0); 644926#L1384-1 assume !(1 == ~T9_E~0); 645002#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 645565#L1394-1 assume !(1 == ~T11_E~0); 645566#L1399-1 assume !(1 == ~T12_E~0); 645711#L1404-1 assume !(1 == ~E_M~0); 644329#L1409-1 assume !(1 == ~E_1~0); 644330#L1414-1 assume !(1 == ~E_2~0); 645248#L1419-1 assume !(1 == ~E_3~0); 643973#L1424-1 assume !(1 == ~E_4~0); 643974#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 644935#L1434-1 assume !(1 == ~E_6~0); 645589#L1439-1 assume !(1 == ~E_7~0); 644022#L1444-1 assume !(1 == ~E_8~0); 644023#L1449-1 assume !(1 == ~E_9~0); 644432#L1454-1 assume !(1 == ~E_10~0); 644433#L1459-1 assume !(1 == ~E_11~0); 645039#L1464-1 assume !(1 == ~E_12~0); 645040#L1469-1 assume { :end_inline_reset_delta_events } true; 645100#L1815-2 [2021-11-13 18:10:02,359 INFO L793 eck$LassoCheckResult]: Loop: 645100#L1815-2 assume !false; 695944#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 695939#L1181 assume !false; 695938#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 695931#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 695918#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 695916#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 695913#L1008 assume !(0 != eval_~tmp~0#1); 695914#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 729449#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 729447#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 729445#L1206-5 assume !(0 == ~T1_E~0); 729443#L1211-3 assume !(0 == ~T2_E~0); 729440#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 729438#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 729436#L1226-3 assume !(0 == ~T5_E~0); 729435#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 729433#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 729431#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 729429#L1246-3 assume !(0 == ~T9_E~0); 729427#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 729425#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 727522#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 727521#L1266-3 assume !(0 == ~E_M~0); 727520#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 727519#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 727518#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 726202#L1286-3 assume !(0 == ~E_4~0); 726071#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 726070#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 726068#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 726066#L1306-3 assume !(0 == ~E_8~0); 726065#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 726064#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 726062#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 726060#L1326-3 assume !(0 == ~E_12~0); 725697#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 725039#L598-42 assume !(1 == ~m_pc~0); 725038#L598-44 is_master_triggered_~__retres1~0#1 := 0; 725037#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 725036#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 725034#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 725033#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 725031#L617-42 assume !(1 == ~t1_pc~0); 725029#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 725026#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 725022#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 725018#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 725014#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 717332#L636-42 assume !(1 == ~t2_pc~0); 717330#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 717326#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 717324#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 717322#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 717320#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 717317#L655-42 assume !(1 == ~t3_pc~0); 717314#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 717311#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 717309#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 717307#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 717305#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 717303#L674-42 assume !(1 == ~t4_pc~0); 717300#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 717297#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 717295#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 717293#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 717291#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 717289#L693-42 assume 1 == ~t5_pc~0; 717286#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 717284#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 717283#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 717282#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 717280#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 696146#L712-42 assume !(1 == ~t6_pc~0); 696144#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 696142#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 696140#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 696138#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 696136#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 696135#L731-42 assume !(1 == ~t7_pc~0); 687708#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 696131#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 696129#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 696127#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 696125#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 696124#L750-42 assume !(1 == ~t8_pc~0); 696122#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 696120#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 696118#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 696117#L1561-42 assume !(0 != activate_threads_~tmp___7~0#1); 696112#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 696110#L769-42 assume !(1 == ~t9_pc~0); 681501#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 696107#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 696104#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 696102#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 696100#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 696099#L788-42 assume 1 == ~t10_pc~0; 696095#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 696093#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 696091#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 696089#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 696087#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 696085#L807-42 assume !(1 == ~t11_pc~0); 671048#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 696081#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 696079#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 696077#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 696075#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 696073#L826-42 assume !(1 == ~t12_pc~0); 696070#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 696068#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 696066#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 696064#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 696062#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 696060#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 696057#L1344-5 assume !(1 == ~T1_E~0); 696055#L1349-3 assume !(1 == ~T2_E~0); 696053#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 696051#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 696049#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 696046#L1369-3 assume !(1 == ~T6_E~0); 696044#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 696042#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 696040#L1384-3 assume !(1 == ~T9_E~0); 696038#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 696036#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 696034#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 696031#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 696029#L1409-3 assume !(1 == ~E_1~0); 696027#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 696025#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 696023#L1424-3 assume !(1 == ~E_4~0); 696021#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 696020#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 696018#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 696016#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 696014#L1449-3 assume !(1 == ~E_9~0); 696012#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 696010#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 696009#L1464-3 assume !(1 == ~E_12~0); 696007#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 696002#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 695987#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 695985#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 695982#L1834 assume !(0 == start_simulation_~tmp~3#1); 695979#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 695968#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 695958#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 695956#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 695954#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 695951#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 695949#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 695947#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 645100#L1815-2 [2021-11-13 18:10:02,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:10:02,360 INFO L85 PathProgramCache]: Analyzing trace with hash 2016784261, now seen corresponding path program 1 times [2021-11-13 18:10:02,361 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:10:02,361 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [301681680] [2021-11-13 18:10:02,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:10:02,361 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:10:02,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:10:02,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:10:02,432 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:10:02,432 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [301681680] [2021-11-13 18:10:02,433 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [301681680] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:10:02,433 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:10:02,433 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:10:02,433 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1382369740] [2021-11-13 18:10:02,434 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:10:02,434 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:10:02,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:10:02,435 INFO L85 PathProgramCache]: Analyzing trace with hash -1761330018, now seen corresponding path program 1 times [2021-11-13 18:10:02,435 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:10:02,435 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911636623] [2021-11-13 18:10:02,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:10:02,436 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:10:02,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:10:02,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:10:02,962 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:10:02,962 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1911636623] [2021-11-13 18:10:02,962 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1911636623] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:10:02,962 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:10:02,963 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:10:02,963 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [493895098] [2021-11-13 18:10:02,963 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:10:02,964 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:10:02,964 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:10:02,965 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:10:02,965 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:10:02,965 INFO L87 Difference]: Start difference. First operand 88163 states and 122280 transitions. cyclomatic complexity: 34119 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:10:03,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:10:03,329 INFO L93 Difference]: Finished difference Result 88163 states and 122086 transitions. [2021-11-13 18:10:03,329 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:10:03,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88163 states and 122086 transitions. [2021-11-13 18:10:03,682 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 87968 [2021-11-13 18:10:03,902 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88163 states to 88163 states and 122086 transitions. [2021-11-13 18:10:03,903 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88163 [2021-11-13 18:10:03,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88163 [2021-11-13 18:10:03,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88163 states and 122086 transitions. [2021-11-13 18:10:03,988 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:10:03,988 INFO L681 BuchiCegarLoop]: Abstraction has 88163 states and 122086 transitions. [2021-11-13 18:10:04,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88163 states and 122086 transitions. [2021-11-13 18:10:05,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88163 to 88163. [2021-11-13 18:10:05,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 88163 states, 88163 states have (on average 1.3847759264090378) internal successors, (122086), 88162 states have internal predecessors, (122086), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:10:05,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88163 states to 88163 states and 122086 transitions. [2021-11-13 18:10:05,442 INFO L704 BuchiCegarLoop]: Abstraction has 88163 states and 122086 transitions. [2021-11-13 18:10:05,442 INFO L587 BuchiCegarLoop]: Abstraction has 88163 states and 122086 transitions. [2021-11-13 18:10:05,442 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-11-13 18:10:05,442 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88163 states and 122086 transitions. [2021-11-13 18:10:05,688 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 87968 [2021-11-13 18:10:05,688 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:10:05,689 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:10:05,695 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:10:05,695 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:10:05,695 INFO L791 eck$LassoCheckResult]: Stem: 820920#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 820921#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 820342#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 820317#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 820318#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 821689#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 820620#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 820083#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 820084#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 821407#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 821569#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 822171#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 822172#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 820832#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 820833#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 821439#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 821348#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 821349#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 821520#L1206 assume !(0 == ~M_E~0); 820809#L1206-2 assume !(0 == ~T1_E~0); 820810#L1211-1 assume !(0 == ~T2_E~0); 821882#L1216-1 assume !(0 == ~T3_E~0); 820602#L1221-1 assume !(0 == ~T4_E~0); 820603#L1226-1 assume !(0 == ~T5_E~0); 820273#L1231-1 assume !(0 == ~T6_E~0); 820274#L1236-1 assume !(0 == ~T7_E~0); 821932#L1241-1 assume !(0 == ~T8_E~0); 820661#L1246-1 assume !(0 == ~T9_E~0); 820662#L1251-1 assume !(0 == ~T10_E~0); 820886#L1256-1 assume !(0 == ~T11_E~0); 820095#L1261-1 assume !(0 == ~T12_E~0); 820096#L1266-1 assume !(0 == ~E_M~0); 822142#L1271-1 assume !(0 == ~E_1~0); 821556#L1276-1 assume !(0 == ~E_2~0); 821557#L1281-1 assume !(0 == ~E_3~0); 821474#L1286-1 assume !(0 == ~E_4~0); 820503#L1291-1 assume !(0 == ~E_5~0); 820504#L1296-1 assume !(0 == ~E_6~0); 821257#L1301-1 assume !(0 == ~E_7~0); 821258#L1306-1 assume !(0 == ~E_8~0); 821791#L1311-1 assume !(0 == ~E_9~0); 820466#L1316-1 assume !(0 == ~E_10~0); 820467#L1321-1 assume !(0 == ~E_11~0); 821277#L1326-1 assume !(0 == ~E_12~0); 820336#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 820337#L598 assume !(1 == ~m_pc~0); 821043#L598-2 is_master_triggered_~__retres1~0#1 := 0; 821044#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 821902#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 822072#L1497 assume !(0 != activate_threads_~tmp~1#1); 822073#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 821981#L617 assume !(1 == ~t1_pc~0); 820683#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 820684#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 822243#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 822093#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 821363#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 821364#L636 assume !(1 == ~t2_pc~0); 822004#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 821113#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 820485#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 820486#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 821406#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 821015#L655 assume !(1 == ~t3_pc~0); 821016#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 821911#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 820359#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 820360#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 822143#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 822144#L674 assume !(1 == ~t4_pc~0); 820189#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 821887#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 821563#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 820487#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 820488#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 821012#L693 assume !(1 == ~t5_pc~0); 821202#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 820814#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 820815#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 821797#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 820898#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 820834#L712 assume !(1 == ~t6_pc~0); 820835#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 821311#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 821312#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 821654#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 821426#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 821422#L731 assume !(1 == ~t7_pc~0); 821423#L731-2 is_transmit7_triggered_~__retres1~7#1 := 0; 820530#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 820531#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 821552#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 821707#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 820443#L750 assume !(1 == ~t8_pc~0); 820126#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 821541#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 822242#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 821815#L1561 assume !(0 != activate_threads_~tmp___7~0#1); 820767#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 820768#L769 assume !(1 == ~t9_pc~0); 821362#L769-2 is_transmit9_triggered_~__retres1~9#1 := 0; 820294#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 820295#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 821088#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 821621#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 821740#L788 assume !(1 == ~t10_pc~0); 821217#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 821218#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 821490#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 821491#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 820439#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 820440#L807 assume !(1 == ~t11_pc~0); 821235#L807-2 is_transmit11_triggered_~__retres1~11#1 := 0; 821236#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 821408#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 821969#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 822236#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 821886#L826 assume !(1 == ~t12_pc~0); 820838#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 820839#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 821434#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 822035#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 821005#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 820906#L1344 assume !(1 == ~M_E~0); 820907#L1344-2 assume !(1 == ~T1_E~0); 821061#L1349-1 assume !(1 == ~T2_E~0); 821265#L1354-1 assume !(1 == ~T3_E~0); 821266#L1359-1 assume !(1 == ~T4_E~0); 821725#L1364-1 assume !(1 == ~T5_E~0); 820548#L1369-1 assume !(1 == ~T6_E~0); 820549#L1374-1 assume !(1 == ~T7_E~0); 821275#L1379-1 assume !(1 == ~T8_E~0); 821276#L1384-1 assume !(1 == ~T9_E~0); 821347#L1389-1 assume !(1 == ~T10_E~0); 821940#L1394-1 assume !(1 == ~T11_E~0); 821941#L1399-1 assume !(1 == ~T12_E~0); 822091#L1404-1 assume !(1 == ~E_M~0); 820665#L1409-1 assume !(1 == ~E_1~0); 820666#L1414-1 assume !(1 == ~E_2~0); 821597#L1419-1 assume !(1 == ~E_3~0); 820306#L1424-1 assume !(1 == ~E_4~0); 820307#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 821286#L1434-1 assume !(1 == ~E_6~0); 821966#L1439-1 assume !(1 == ~E_7~0); 820355#L1444-1 assume !(1 == ~E_8~0); 820356#L1449-1 assume !(1 == ~E_9~0); 820773#L1454-1 assume !(1 == ~E_10~0); 820774#L1459-1 assume !(1 == ~E_11~0); 821381#L1464-1 assume !(1 == ~E_12~0); 821382#L1469-1 assume { :end_inline_reset_delta_events } true; 821440#L1815-2 [2021-11-13 18:10:05,696 INFO L793 eck$LassoCheckResult]: Loop: 821440#L1815-2 assume !false; 879281#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 879274#L1181 assume !false; 879272#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 879261#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 879249#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 879248#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 879246#L1008 assume !(0 != eval_~tmp~0#1); 879247#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 906898#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 906897#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 906896#L1206-5 assume !(0 == ~T1_E~0); 906894#L1211-3 assume !(0 == ~T2_E~0); 906893#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 906892#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 906891#L1226-3 assume !(0 == ~T5_E~0); 906890#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 906889#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 906888#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 906887#L1246-3 assume !(0 == ~T9_E~0); 906886#L1251-3 assume !(0 == ~T10_E~0); 906885#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 906884#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 906883#L1266-3 assume !(0 == ~E_M~0); 906882#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 906881#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 906880#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 906879#L1286-3 assume !(0 == ~E_4~0); 906877#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 906876#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 906875#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 906873#L1306-3 assume !(0 == ~E_8~0); 906871#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 906869#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 906867#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 906865#L1326-3 assume !(0 == ~E_12~0); 906863#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 906861#L598-42 assume !(1 == ~m_pc~0); 906859#L598-44 is_master_triggered_~__retres1~0#1 := 0; 906857#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 906855#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 906853#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 906851#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 906849#L617-42 assume !(1 == ~t1_pc~0); 906847#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 907816#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 906793#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 906791#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 906788#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 906785#L636-42 assume !(1 == ~t2_pc~0); 906786#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 907841#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 907840#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 907839#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 907838#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 907837#L655-42 assume !(1 == ~t3_pc~0); 906775#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 906773#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 906771#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 906767#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 906765#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 906763#L674-42 assume !(1 == ~t4_pc~0); 906760#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 906757#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 906755#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 906753#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 906752#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 906749#L693-42 assume !(1 == ~t5_pc~0); 906743#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 906740#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 906738#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 821561#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 821562#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 821867#L712-42 assume !(1 == ~t6_pc~0); 890894#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 821708#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 821709#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 822237#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 822238#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 822043#L731-42 assume !(1 == ~t7_pc~0); 820589#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 820590#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 821806#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 820797#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 820798#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 821778#L750-42 assume !(1 == ~t8_pc~0); 821876#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 821877#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 907227#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 907225#L1561-42 assume !(0 != activate_threads_~tmp___7~0#1); 903907#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 879438#L769-42 assume !(1 == ~t9_pc~0); 879436#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 879434#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 879432#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 879430#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 879428#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 879426#L788-42 assume 1 == ~t10_pc~0; 879423#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 879421#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 879419#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 879417#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 879415#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 879413#L807-42 assume !(1 == ~t11_pc~0); 856743#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 879410#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 879408#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 879406#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 879404#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 879402#L826-42 assume !(1 == ~t12_pc~0); 879399#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 879397#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 879395#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 879393#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 879391#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 879389#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 879387#L1344-5 assume !(1 == ~T1_E~0); 879385#L1349-3 assume !(1 == ~T2_E~0); 879383#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 879381#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 879379#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 879378#L1369-3 assume !(1 == ~T6_E~0); 879377#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 879376#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 879375#L1384-3 assume !(1 == ~T9_E~0); 879374#L1389-3 assume !(1 == ~T10_E~0); 879373#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 879372#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 879371#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 879370#L1409-3 assume !(1 == ~E_1~0); 879369#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 879368#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 879366#L1424-3 assume !(1 == ~E_4~0); 879364#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 879362#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 879360#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 879358#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 879356#L1449-3 assume !(1 == ~E_9~0); 879354#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 879353#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 879351#L1464-3 assume !(1 == ~E_12~0); 879349#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 879336#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 879323#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 879321#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 879319#L1834 assume !(0 == start_simulation_~tmp~3#1); 879316#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 879303#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 879293#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 879291#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 879289#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 879288#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 879286#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 879284#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 821440#L1815-2 [2021-11-13 18:10:05,697 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:10:05,697 INFO L85 PathProgramCache]: Analyzing trace with hash 428436359, now seen corresponding path program 1 times [2021-11-13 18:10:05,697 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:10:05,698 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [415309175] [2021-11-13 18:10:05,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:10:05,698 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:10:05,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:10:05,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:10:05,753 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:10:05,753 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [415309175] [2021-11-13 18:10:05,754 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [415309175] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:10:05,754 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:10:05,754 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:10:05,754 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [58967901] [2021-11-13 18:10:05,755 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:10:05,755 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:10:05,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:10:05,756 INFO L85 PathProgramCache]: Analyzing trace with hash 817160031, now seen corresponding path program 1 times [2021-11-13 18:10:05,756 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:10:05,756 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [614208143] [2021-11-13 18:10:05,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:10:05,757 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:10:05,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:10:05,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:10:05,801 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:10:05,801 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [614208143] [2021-11-13 18:10:05,801 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [614208143] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:10:05,801 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:10:05,801 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:10:05,802 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [59565627] [2021-11-13 18:10:05,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:10:05,803 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:10:05,803 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:10:05,803 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:10:05,803 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:10:05,804 INFO L87 Difference]: Start difference. First operand 88163 states and 122086 transitions. cyclomatic complexity: 33925 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:10:06,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:10:06,779 INFO L93 Difference]: Finished difference Result 88163 states and 121187 transitions. [2021-11-13 18:10:06,780 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:10:06,780 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88163 states and 121187 transitions. [2021-11-13 18:10:07,158 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 87968 [2021-11-13 18:10:07,373 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88163 states to 88163 states and 121187 transitions. [2021-11-13 18:10:07,373 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88163 [2021-11-13 18:10:07,419 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88163 [2021-11-13 18:10:07,419 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88163 states and 121187 transitions. [2021-11-13 18:10:07,457 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:10:07,457 INFO L681 BuchiCegarLoop]: Abstraction has 88163 states and 121187 transitions. [2021-11-13 18:10:07,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88163 states and 121187 transitions. [2021-11-13 18:10:08,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88163 to 88163. [2021-11-13 18:10:08,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 88163 states, 88163 states have (on average 1.3745789049828159) internal successors, (121187), 88162 states have internal predecessors, (121187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:10:09,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88163 states to 88163 states and 121187 transitions. [2021-11-13 18:10:09,100 INFO L704 BuchiCegarLoop]: Abstraction has 88163 states and 121187 transitions. [2021-11-13 18:10:09,100 INFO L587 BuchiCegarLoop]: Abstraction has 88163 states and 121187 transitions. [2021-11-13 18:10:09,100 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-11-13 18:10:09,100 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88163 states and 121187 transitions. [2021-11-13 18:10:09,389 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 87968 [2021-11-13 18:10:09,389 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:10:09,390 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:10:09,396 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:10:09,396 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:10:09,397 INFO L791 eck$LassoCheckResult]: Stem: 997265#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 997266#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 996676#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 996653#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 996654#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 998015#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 996957#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 996416#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 996417#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 997747#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 997903#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 998496#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 998497#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 997173#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 997174#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 997776#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 997685#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 997686#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 997854#L1206 assume !(0 == ~M_E~0); 997149#L1206-2 assume !(0 == ~T1_E~0); 997150#L1211-1 assume !(0 == ~T2_E~0); 998209#L1216-1 assume !(0 == ~T3_E~0); 996939#L1221-1 assume !(0 == ~T4_E~0); 996940#L1226-1 assume !(0 == ~T5_E~0); 996607#L1231-1 assume !(0 == ~T6_E~0); 996608#L1236-1 assume !(0 == ~T7_E~0); 998259#L1241-1 assume !(0 == ~T8_E~0); 997003#L1246-1 assume !(0 == ~T9_E~0); 997004#L1251-1 assume !(0 == ~T10_E~0); 997231#L1256-1 assume !(0 == ~T11_E~0); 996428#L1261-1 assume !(0 == ~T12_E~0); 996429#L1266-1 assume !(0 == ~E_M~0); 998466#L1271-1 assume !(0 == ~E_1~0); 997889#L1276-1 assume !(0 == ~E_2~0); 997890#L1281-1 assume !(0 == ~E_3~0); 997808#L1286-1 assume !(0 == ~E_4~0); 996841#L1291-1 assume !(0 == ~E_5~0); 996842#L1296-1 assume !(0 == ~E_6~0); 997598#L1301-1 assume !(0 == ~E_7~0); 997599#L1306-1 assume !(0 == ~E_8~0); 998123#L1311-1 assume !(0 == ~E_9~0); 996804#L1316-1 assume !(0 == ~E_10~0); 996805#L1321-1 assume !(0 == ~E_11~0); 997618#L1326-1 assume !(0 == ~E_12~0); 996670#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 996671#L598 assume !(1 == ~m_pc~0); 997381#L598-2 is_master_triggered_~__retres1~0#1 := 0; 997382#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 998234#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 998391#L1497 assume !(0 != activate_threads_~tmp~1#1); 998392#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 998304#L617 assume !(1 == ~t1_pc~0); 997025#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 997026#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 998569#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 998409#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 997702#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 997703#L636 assume !(1 == ~t2_pc~0); 998325#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 997456#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 996823#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 996824#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 997746#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 997355#L655 assume !(1 == ~t3_pc~0); 997356#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 998240#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 996694#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 996695#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 998467#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 998468#L674 assume !(1 == ~t4_pc~0); 996521#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 998214#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 997896#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 996827#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 996828#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 997351#L693 assume !(1 == ~t5_pc~0); 997546#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 997154#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 997155#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 998125#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 997243#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 997175#L712 assume !(1 == ~t6_pc~0); 997176#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 997653#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 997654#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 997985#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 997764#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 997760#L731 assume !(1 == ~t7_pc~0); 997761#L731-2 is_transmit7_triggered_~__retres1~7#1 := 0; 996868#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 996869#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 997885#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 998035#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 996781#L750 assume !(1 == ~t8_pc~0); 996459#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 996968#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 996969#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 998142#L1561 assume !(0 != activate_threads_~tmp___7~0#1); 997106#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 997107#L769 assume !(1 == ~t9_pc~0); 997701#L769-2 is_transmit9_triggered_~__retres1~9#1 := 0; 996628#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 996629#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 997427#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 997956#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 998061#L788 assume !(1 == ~t10_pc~0); 997562#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 997563#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 997824#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 997825#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 996779#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 996780#L807 assume !(1 == ~t11_pc~0); 997576#L807-2 is_transmit11_triggered_~__retres1~11#1 := 0; 997577#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 997748#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 998291#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 998566#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 998213#L826 assume !(1 == ~t12_pc~0); 997179#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 997180#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 997771#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 998353#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 997344#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 997251#L1344 assume !(1 == ~M_E~0); 997252#L1344-2 assume !(1 == ~T1_E~0); 997399#L1349-1 assume !(1 == ~T2_E~0); 997609#L1354-1 assume !(1 == ~T3_E~0); 997610#L1359-1 assume !(1 == ~T4_E~0); 998046#L1364-1 assume !(1 == ~T5_E~0); 996886#L1369-1 assume !(1 == ~T6_E~0); 996887#L1374-1 assume !(1 == ~T7_E~0); 997616#L1379-1 assume !(1 == ~T8_E~0); 997617#L1384-1 assume !(1 == ~T9_E~0); 997684#L1389-1 assume !(1 == ~T10_E~0); 998264#L1394-1 assume !(1 == ~T11_E~0); 998265#L1399-1 assume !(1 == ~T12_E~0); 998407#L1404-1 assume !(1 == ~E_M~0); 997007#L1409-1 assume !(1 == ~E_1~0); 997008#L1414-1 assume !(1 == ~E_2~0); 997928#L1419-1 assume !(1 == ~E_3~0); 996640#L1424-1 assume !(1 == ~E_4~0); 996641#L1429-1 assume !(1 == ~E_5~0); 997628#L1434-1 assume !(1 == ~E_6~0); 998289#L1439-1 assume !(1 == ~E_7~0); 996690#L1444-1 assume !(1 == ~E_8~0); 996691#L1449-1 assume !(1 == ~E_9~0); 997112#L1454-1 assume !(1 == ~E_10~0); 997113#L1459-1 assume !(1 == ~E_11~0); 997720#L1464-1 assume !(1 == ~E_12~0); 997721#L1469-1 assume { :end_inline_reset_delta_events } true; 997777#L1815-2 [2021-11-13 18:10:09,398 INFO L793 eck$LassoCheckResult]: Loop: 997777#L1815-2 assume !false; 1062789#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1062784#L1181 assume !false; 1062781#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1062774#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1062762#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1062759#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1062757#L1008 assume !(0 != eval_~tmp~0#1); 998559#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 996636#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 996637#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 998521#L1206-5 assume !(0 == ~T1_E~0); 997719#L1211-3 assume !(0 == ~T2_E~0); 996763#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 996764#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 997369#L1226-3 assume !(0 == ~T5_E~0); 996829#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 996830#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 997145#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 998348#L1246-3 assume !(0 == ~T9_E~0); 998197#L1251-3 assume !(0 == ~T10_E~0); 997841#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 996789#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 996790#L1266-3 assume !(0 == ~E_M~0); 996825#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 996826#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 997313#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 997314#L1286-3 assume !(0 == ~E_4~0); 997925#L1291-3 assume !(0 == ~E_5~0); 997926#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 998482#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 998398#L1306-3 assume !(0 == ~E_8~0); 997450#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 996707#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 996708#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 996791#L1326-3 assume !(0 == ~E_12~0); 997570#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 997935#L598-42 assume !(1 == ~m_pc~0); 997936#L598-44 is_master_triggered_~__retres1~0#1 := 0; 998092#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 996866#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 996867#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 998399#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 997633#L617-42 assume !(1 == ~t1_pc~0); 997365#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 998149#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 997690#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 997691#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 996933#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 996934#L636-42 assume !(1 == ~t2_pc~0); 1075595#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1075596#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1084174#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1084172#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1084170#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1084168#L655-42 assume 1 == ~t3_pc~0; 1075572#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1075569#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1075567#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1075565#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1075561#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1075562#L674-42 assume !(1 == ~t4_pc~0); 1084118#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1084117#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1084116#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1084114#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1084112#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1075539#L693-42 assume !(1 == ~t5_pc~0); 1075538#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1075531#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1075532#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1075523#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1075524#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1063360#L712-42 assume !(1 == ~t6_pc~0); 1063359#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1063357#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1063355#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1063353#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1063351#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1062953#L731-42 assume !(1 == ~t7_pc~0); 1062952#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1062951#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1062950#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1062949#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1062948#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1062947#L750-42 assume !(1 == ~t8_pc~0); 1062945#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1062943#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1062941#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1062940#L1561-42 assume !(0 != activate_threads_~tmp___7~0#1); 1062938#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1062937#L769-42 assume !(1 == ~t9_pc~0); 1058821#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1062936#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1062935#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1062934#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 1062933#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1062932#L788-42 assume 1 == ~t10_pc~0; 1062929#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1062927#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1062925#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1062923#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1062921#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1062919#L807-42 assume !(1 == ~t11_pc~0); 1045374#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1062915#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1062913#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1062911#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1062909#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1062907#L826-42 assume !(1 == ~t12_pc~0); 1062904#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 1062903#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1062901#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 1062899#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1062897#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1062895#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1062892#L1344-5 assume !(1 == ~T1_E~0); 1062890#L1349-3 assume !(1 == ~T2_E~0); 1062888#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1062886#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1062884#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1062882#L1369-3 assume !(1 == ~T6_E~0); 1062880#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1062878#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1062876#L1384-3 assume !(1 == ~T9_E~0); 1062874#L1389-3 assume !(1 == ~T10_E~0); 1062872#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1062870#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1062868#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1062866#L1409-3 assume !(1 == ~E_1~0); 1062864#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1062862#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1062860#L1424-3 assume !(1 == ~E_4~0); 1062858#L1429-3 assume !(1 == ~E_5~0); 1062856#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1062854#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1062852#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1062850#L1449-3 assume !(1 == ~E_9~0); 1062848#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1062846#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1062844#L1464-3 assume !(1 == ~E_12~0); 1062842#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1062836#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1062823#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1062821#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1062819#L1834 assume !(0 == start_simulation_~tmp~3#1); 1062817#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1062812#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1062803#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1062800#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 1062798#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1062796#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1062794#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 1062792#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 997777#L1815-2 [2021-11-13 18:10:09,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:10:09,399 INFO L85 PathProgramCache]: Analyzing trace with hash 1108494729, now seen corresponding path program 1 times [2021-11-13 18:10:09,400 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:10:09,400 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [446848323] [2021-11-13 18:10:09,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:10:09,400 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:10:09,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-13 18:10:09,423 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-13 18:10:09,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-13 18:10:09,620 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-13 18:10:09,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:10:09,621 INFO L85 PathProgramCache]: Analyzing trace with hash -1374197090, now seen corresponding path program 1 times [2021-11-13 18:10:09,622 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:10:09,622 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039676284] [2021-11-13 18:10:09,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:10:09,622 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:10:09,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:10:09,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:10:09,673 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:10:09,673 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2039676284] [2021-11-13 18:10:09,673 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2039676284] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:10:09,673 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:10:09,674 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:10:09,674 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1612072874] [2021-11-13 18:10:09,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:10:09,675 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:10:09,675 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:10:09,676 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:10:09,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:10:09,676 INFO L87 Difference]: Start difference. First operand 88163 states and 121187 transitions. cyclomatic complexity: 33026 Second operand has 3 states, 3 states have (on average 51.333333333333336) internal successors, (154), 3 states have internal predecessors, (154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:10:10,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:10:10,717 INFO L93 Difference]: Finished difference Result 96025 states and 132163 transitions. [2021-11-13 18:10:10,723 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:10:10,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 96025 states and 132163 transitions. [2021-11-13 18:10:11,126 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 95712 [2021-11-13 18:10:11,327 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 96025 states to 96025 states and 132163 transitions. [2021-11-13 18:10:11,327 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 96025 [2021-11-13 18:10:11,372 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 96025 [2021-11-13 18:10:11,372 INFO L73 IsDeterministic]: Start isDeterministic. Operand 96025 states and 132163 transitions. [2021-11-13 18:10:11,407 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:10:11,407 INFO L681 BuchiCegarLoop]: Abstraction has 96025 states and 132163 transitions. [2021-11-13 18:10:11,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96025 states and 132163 transitions. [2021-11-13 18:10:12,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96025 to 96025. [2021-11-13 18:10:12,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 96025 states, 96025 states have (on average 1.376339494923197) internal successors, (132163), 96024 states have internal predecessors, (132163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:10:12,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96025 states to 96025 states and 132163 transitions. [2021-11-13 18:10:12,850 INFO L704 BuchiCegarLoop]: Abstraction has 96025 states and 132163 transitions. [2021-11-13 18:10:12,850 INFO L587 BuchiCegarLoop]: Abstraction has 96025 states and 132163 transitions. [2021-11-13 18:10:12,850 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-11-13 18:10:12,850 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 96025 states and 132163 transitions. [2021-11-13 18:10:13,111 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 95712 [2021-11-13 18:10:13,111 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:10:13,111 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:10:13,119 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:10:13,119 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:10:13,120 INFO L791 eck$LassoCheckResult]: Stem: 1181453#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1181454#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1180868#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1180843#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1180844#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 1182207#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1181147#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1180610#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1180611#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1181940#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1182099#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1182700#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1182701#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1181361#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1181362#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1181976#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1181881#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1181882#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1182051#L1206 assume !(0 == ~M_E~0); 1181340#L1206-2 assume !(0 == ~T1_E~0); 1181341#L1211-1 assume !(0 == ~T2_E~0); 1182402#L1216-1 assume !(0 == ~T3_E~0); 1181128#L1221-1 assume !(0 == ~T4_E~0); 1181129#L1226-1 assume !(0 == ~T5_E~0); 1180798#L1231-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1180799#L1236-1 assume !(0 == ~T7_E~0); 1182461#L1241-1 assume !(0 == ~T8_E~0); 1182462#L1246-1 assume !(0 == ~T9_E~0); 1181418#L1251-1 assume !(0 == ~T10_E~0); 1181419#L1256-1 assume !(0 == ~T11_E~0); 1180622#L1261-1 assume !(0 == ~T12_E~0); 1180623#L1266-1 assume !(0 == ~E_M~0); 1182668#L1271-1 assume !(0 == ~E_1~0); 1182669#L1276-1 assume !(0 == ~E_2~0); 1182664#L1281-1 assume !(0 == ~E_3~0); 1182665#L1286-1 assume !(0 == ~E_4~0); 1181031#L1291-1 assume !(0 == ~E_5~0); 1181032#L1296-1 assume !(0 == ~E_6~0); 1181793#L1301-1 assume !(0 == ~E_7~0); 1181794#L1306-1 assume !(0 == ~E_8~0); 1182308#L1311-1 assume !(0 == ~E_9~0); 1182309#L1316-1 assume !(0 == ~E_10~0); 1182629#L1321-1 assume !(0 == ~E_11~0); 1182630#L1326-1 assume !(0 == ~E_12~0); 1182820#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1182776#L598 assume !(1 == ~m_pc~0); 1181576#L598-2 is_master_triggered_~__retres1~0#1 := 0; 1181577#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1182762#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1182763#L1497 assume !(0 != activate_threads_~tmp~1#1); 1182733#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1182734#L617 assume !(1 == ~t1_pc~0); 1181215#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1181216#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1182790#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1182791#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 1181898#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1181899#L636 assume !(1 == ~t2_pc~0); 1182816#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1181648#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1181649#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1182619#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 1182620#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1182815#L655 assume !(1 == ~t3_pc~0); 1182442#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1182443#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1180887#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1180888#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 1182779#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1182691#L674 assume !(1 == ~t4_pc~0); 1180715#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1182729#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1182092#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1182093#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 1182811#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1182547#L693 assume !(1 == ~t5_pc~0); 1181950#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1181342#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1181343#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1182314#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 1182315#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1181366#L712 assume !(1 == ~t6_pc~0); 1181367#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1181847#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1181848#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1182176#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 1181960#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1181961#L731 assume !(1 == ~t7_pc~0); 1182682#L731-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1181055#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1181056#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1182319#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 1182225#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1182226#L750 assume !(1 == ~t8_pc~0); 1182069#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1182070#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1182787#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1182788#L1561 assume !(0 != activate_threads_~tmp___7~0#1); 1181298#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1181299#L769 assume !(1 == ~t9_pc~0); 1182523#L769-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1180822#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1180823#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1182799#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 1182561#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1182254#L788 assume !(1 == ~t10_pc~0); 1182255#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1182464#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1182465#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1182373#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 1182374#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1182797#L807 assume !(1 == ~t11_pc~0); 1181771#L807-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1181772#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1182496#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1182497#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 1182777#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1182778#L826 assume !(1 == ~t12_pc~0); 1181368#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1181369#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1182698#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 1182699#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 1182793#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1182792#L1344 assume !(1 == ~M_E~0); 1181592#L1344-2 assume !(1 == ~T1_E~0); 1181593#L1349-1 assume !(1 == ~T2_E~0); 1181801#L1354-1 assume !(1 == ~T3_E~0); 1181802#L1359-1 assume !(1 == ~T4_E~0); 1182241#L1364-1 assume !(1 == ~T5_E~0); 1181075#L1369-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1181076#L1374-1 assume !(1 == ~T7_E~0); 1181808#L1379-1 assume !(1 == ~T8_E~0); 1181809#L1384-1 assume !(1 == ~T9_E~0); 1181880#L1389-1 assume !(1 == ~T10_E~0); 1182470#L1394-1 assume !(1 == ~T11_E~0); 1182471#L1399-1 assume !(1 == ~T12_E~0); 1182621#L1404-1 assume !(1 == ~E_M~0); 1181197#L1409-1 assume !(1 == ~E_1~0); 1181198#L1414-1 assume !(1 == ~E_2~0); 1182123#L1419-1 assume !(1 == ~E_3~0); 1180834#L1424-1 assume !(1 == ~E_4~0); 1180835#L1429-1 assume !(1 == ~E_5~0); 1181819#L1434-1 assume !(1 == ~E_6~0); 1182495#L1439-1 assume !(1 == ~E_7~0); 1180883#L1444-1 assume !(1 == ~E_8~0); 1180884#L1449-1 assume !(1 == ~E_9~0); 1181304#L1454-1 assume !(1 == ~E_10~0); 1181305#L1459-1 assume !(1 == ~E_11~0); 1181915#L1464-1 assume !(1 == ~E_12~0); 1181916#L1469-1 assume { :end_inline_reset_delta_events } true; 1181977#L1815-2 [2021-11-13 18:10:13,121 INFO L793 eck$LassoCheckResult]: Loop: 1181977#L1815-2 assume !false; 1182149#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1181774#L1181 assume !false; 1181851#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1181798#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1180613#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1181335#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1181954#L1008 assume !(0 != eval_~tmp~0#1); 1181955#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1272740#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1272739#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1272738#L1206-5 assume !(0 == ~T1_E~0); 1272737#L1211-3 assume !(0 == ~T2_E~0); 1272736#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1272735#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1272734#L1226-3 assume !(0 == ~T5_E~0); 1272732#L1231-3 assume !(0 == ~T6_E~0); 1272731#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1272730#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1272729#L1246-3 assume !(0 == ~T9_E~0); 1272728#L1251-3 assume !(0 == ~T10_E~0); 1272727#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1272726#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1272725#L1266-3 assume !(0 == ~E_M~0); 1272724#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1272723#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1272722#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1272721#L1286-3 assume !(0 == ~E_4~0); 1272720#L1291-3 assume !(0 == ~E_5~0); 1272719#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1272718#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1272717#L1306-3 assume !(0 == ~E_8~0); 1272716#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1272715#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1272714#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1272713#L1326-3 assume !(0 == ~E_12~0); 1272712#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1272711#L598-42 assume !(1 == ~m_pc~0); 1272710#L598-44 is_master_triggered_~__retres1~0#1 := 0; 1272709#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1272708#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1272707#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 1272706#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1272705#L617-42 assume !(1 == ~t1_pc~0); 1272703#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1272701#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1272699#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1272698#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 1272696#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1272695#L636-42 assume !(1 == ~t2_pc~0); 1269373#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1272694#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1272692#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1272690#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1272688#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1272686#L655-42 assume 1 == ~t3_pc~0; 1272683#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1272681#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1272679#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1272677#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1272675#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1272673#L674-42 assume !(1 == ~t4_pc~0); 1272670#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1272668#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1272666#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1272664#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1272662#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1272660#L693-42 assume !(1 == ~t5_pc~0); 1272657#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1272655#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1272653#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1272651#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1272648#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1272646#L712-42 assume !(1 == ~t6_pc~0); 1265635#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1272643#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1272641#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1272637#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1272635#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1272633#L731-42 assume !(1 == ~t7_pc~0); 1270190#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1272629#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1272627#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1272625#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1272624#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1272623#L750-42 assume !(1 == ~t8_pc~0); 1272618#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1272616#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1272614#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1272612#L1561-42 assume !(0 != activate_threads_~tmp___7~0#1); 1272609#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1272607#L769-42 assume !(1 == ~t9_pc~0); 1259263#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1272603#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1272601#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1272599#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 1272597#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1272594#L788-42 assume !(1 == ~t10_pc~0); 1272592#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1272589#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1272587#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1272585#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1269811#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1265071#L807-42 assume !(1 == ~t11_pc~0); 1250834#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1265020#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1265018#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1265016#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1265015#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1265014#L826-42 assume !(1 == ~t12_pc~0); 1265010#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 1265008#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1265006#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 1265004#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1265002#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1265000#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1264997#L1344-5 assume !(1 == ~T1_E~0); 1264996#L1349-3 assume !(1 == ~T2_E~0); 1264993#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1264991#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1264989#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1264987#L1369-3 assume !(1 == ~T6_E~0); 1182494#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1181033#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1181034#L1384-3 assume !(1 == ~T9_E~0); 1181270#L1389-3 assume !(1 == ~T10_E~0); 1181271#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1181586#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1182509#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1182454#L1409-3 assume !(1 == ~E_1~0); 1182455#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1182558#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1182203#L1424-3 assume !(1 == ~E_4~0); 1180931#L1429-3 assume !(1 == ~E_5~0); 1180932#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1181980#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1180876#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1180877#L1449-3 assume !(1 == ~E_9~0); 1180985#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1181974#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1181975#L1464-3 assume !(1 == ~E_12~0); 1182488#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1181833#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1180781#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1180782#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1181396#L1834 assume !(0 == start_simulation_~tmp~3#1); 1182100#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1182125#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1181479#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1181685#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 1181924#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1182476#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1180767#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 1180768#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 1181977#L1815-2 [2021-11-13 18:10:13,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:10:13,122 INFO L85 PathProgramCache]: Analyzing trace with hash 1115451209, now seen corresponding path program 1 times [2021-11-13 18:10:13,122 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:10:13,122 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1757088012] [2021-11-13 18:10:13,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:10:13,123 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:10:13,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:10:13,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:10:13,159 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:10:13,160 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1757088012] [2021-11-13 18:10:13,160 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1757088012] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:10:13,160 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:10:13,160 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:10:13,161 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [497018501] [2021-11-13 18:10:13,161 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:10:13,161 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:10:13,162 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:10:13,162 INFO L85 PathProgramCache]: Analyzing trace with hash 1025154333, now seen corresponding path program 1 times [2021-11-13 18:10:13,162 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:10:13,163 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1434126801] [2021-11-13 18:10:13,163 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:10:13,163 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:10:13,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:10:13,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:10:13,212 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:10:13,212 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1434126801] [2021-11-13 18:10:13,213 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1434126801] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:10:13,213 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:10:13,213 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:10:13,213 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1081601552] [2021-11-13 18:10:13,214 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:10:13,214 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:10:13,214 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:10:13,215 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:10:13,215 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:10:13,215 INFO L87 Difference]: Start difference. First operand 96025 states and 132163 transitions. cyclomatic complexity: 36140 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:10:13,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:10:13,535 INFO L93 Difference]: Finished difference Result 88163 states and 120993 transitions. [2021-11-13 18:10:13,535 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:10:13,536 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88163 states and 120993 transitions. [2021-11-13 18:10:13,890 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 87968 [2021-11-13 18:10:14,808 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88163 states to 88163 states and 120993 transitions. [2021-11-13 18:10:14,809 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88163 [2021-11-13 18:10:14,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88163 [2021-11-13 18:10:14,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88163 states and 120993 transitions. [2021-11-13 18:10:14,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:10:14,876 INFO L681 BuchiCegarLoop]: Abstraction has 88163 states and 120993 transitions. [2021-11-13 18:10:14,917 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88163 states and 120993 transitions. [2021-11-13 18:10:15,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88163 to 88163. [2021-11-13 18:10:15,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 88163 states, 88163 states have (on average 1.3723784353980695) internal successors, (120993), 88162 states have internal predecessors, (120993), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:10:15,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88163 states to 88163 states and 120993 transitions. [2021-11-13 18:10:15,720 INFO L704 BuchiCegarLoop]: Abstraction has 88163 states and 120993 transitions. [2021-11-13 18:10:15,720 INFO L587 BuchiCegarLoop]: Abstraction has 88163 states and 120993 transitions. [2021-11-13 18:10:15,720 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-11-13 18:10:15,720 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88163 states and 120993 transitions. [2021-11-13 18:10:16,507 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 87968 [2021-11-13 18:10:16,507 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:10:16,507 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:10:16,513 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:10:16,514 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:10:16,514 INFO L791 eck$LassoCheckResult]: Stem: 1365647#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1365648#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1365064#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1365041#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1365042#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 1366418#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1365340#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1364805#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1364806#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1366147#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1366305#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1366922#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1366923#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1365556#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1365557#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1366180#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1366087#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1366088#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1366258#L1206 assume !(0 == ~M_E~0); 1365532#L1206-2 assume !(0 == ~T1_E~0); 1365533#L1211-1 assume !(0 == ~T2_E~0); 1366609#L1216-1 assume !(0 == ~T3_E~0); 1365321#L1221-1 assume !(0 == ~T4_E~0); 1365322#L1226-1 assume !(0 == ~T5_E~0); 1364994#L1231-1 assume !(0 == ~T6_E~0); 1364995#L1236-1 assume !(0 == ~T7_E~0); 1366668#L1241-1 assume !(0 == ~T8_E~0); 1365383#L1246-1 assume !(0 == ~T9_E~0); 1365384#L1251-1 assume !(0 == ~T10_E~0); 1365612#L1256-1 assume !(0 == ~T11_E~0); 1364817#L1261-1 assume !(0 == ~T12_E~0); 1364818#L1266-1 assume !(0 == ~E_M~0); 1366892#L1271-1 assume !(0 == ~E_1~0); 1366292#L1276-1 assume !(0 == ~E_2~0); 1366293#L1281-1 assume !(0 == ~E_3~0); 1366212#L1286-1 assume !(0 == ~E_4~0); 1365224#L1291-1 assume !(0 == ~E_5~0); 1365225#L1296-1 assume !(0 == ~E_6~0); 1365988#L1301-1 assume !(0 == ~E_7~0); 1365989#L1306-1 assume !(0 == ~E_8~0); 1366526#L1311-1 assume !(0 == ~E_9~0); 1365186#L1316-1 assume !(0 == ~E_10~0); 1365187#L1321-1 assume !(0 == ~E_11~0); 1366008#L1326-1 assume !(0 == ~E_12~0); 1365058#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1365059#L598 assume !(1 == ~m_pc~0); 1365770#L598-2 is_master_triggered_~__retres1~0#1 := 0; 1365771#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1366637#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1366807#L1497 assume !(0 != activate_threads_~tmp~1#1); 1366808#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1366715#L617 assume !(1 == ~t1_pc~0); 1365405#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1365406#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1366993#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1366839#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 1366103#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1366104#L636 assume !(1 == ~t2_pc~0); 1366736#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1365845#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1365206#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1365207#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 1366146#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1365743#L655 assume !(1 == ~t3_pc~0); 1365744#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1366644#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1365081#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1365082#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 1366893#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1366894#L674 assume !(1 == ~t4_pc~0); 1364910#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1366618#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1366299#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1365210#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 1365211#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1365739#L693 assume !(1 == ~t5_pc~0); 1365935#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1365537#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1365538#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1366528#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 1365625#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1365558#L712 assume !(1 == ~t6_pc~0); 1365559#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1366045#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1366046#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1366383#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 1366166#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1366161#L731 assume !(1 == ~t7_pc~0); 1366162#L731-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1365250#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1365251#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1366288#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 1366439#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1365163#L750 assume !(1 == ~t8_pc~0); 1364848#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1366277#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1366992#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1366546#L1561 assume !(0 != activate_threads_~tmp___7~0#1); 1365486#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1365487#L769 assume !(1 == ~t9_pc~0); 1366102#L769-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1365015#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1365016#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1365817#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 1366355#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1366467#L788 assume !(1 == ~t10_pc~0); 1365950#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1365951#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1366229#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1366230#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 1365159#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1365160#L807 assume !(1 == ~t11_pc~0); 1365966#L807-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1365967#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1366148#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1366699#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 1366987#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1366617#L826 assume !(1 == ~t12_pc~0); 1365562#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1365563#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1366174#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 1366763#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 1365732#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1365633#L1344 assume !(1 == ~M_E~0); 1365634#L1344-2 assume !(1 == ~T1_E~0); 1365789#L1349-1 assume !(1 == ~T2_E~0); 1365999#L1354-1 assume !(1 == ~T3_E~0); 1366000#L1359-1 assume !(1 == ~T4_E~0); 1366452#L1364-1 assume !(1 == ~T5_E~0); 1365268#L1369-1 assume !(1 == ~T6_E~0); 1365269#L1374-1 assume !(1 == ~T7_E~0); 1366006#L1379-1 assume !(1 == ~T8_E~0); 1366007#L1384-1 assume !(1 == ~T9_E~0); 1366086#L1389-1 assume !(1 == ~T10_E~0); 1366671#L1394-1 assume !(1 == ~T11_E~0); 1366672#L1399-1 assume !(1 == ~T12_E~0); 1366831#L1404-1 assume !(1 == ~E_M~0); 1365387#L1409-1 assume !(1 == ~E_1~0); 1365388#L1414-1 assume !(1 == ~E_2~0); 1366330#L1419-1 assume !(1 == ~E_3~0); 1365028#L1424-1 assume !(1 == ~E_4~0); 1365029#L1429-1 assume !(1 == ~E_5~0); 1366019#L1434-1 assume !(1 == ~E_6~0); 1366696#L1439-1 assume !(1 == ~E_7~0); 1365077#L1444-1 assume !(1 == ~E_8~0); 1365078#L1449-1 assume !(1 == ~E_9~0); 1365492#L1454-1 assume !(1 == ~E_10~0); 1365493#L1459-1 assume !(1 == ~E_11~0); 1366121#L1464-1 assume !(1 == ~E_12~0); 1366122#L1469-1 assume { :end_inline_reset_delta_events } true; 1366181#L1815-2 [2021-11-13 18:10:16,515 INFO L793 eck$LassoCheckResult]: Loop: 1366181#L1815-2 assume !false; 1406632#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1406625#L1181 assume !false; 1406622#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1406615#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1406601#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1406599#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1406596#L1008 assume !(0 != eval_~tmp~0#1); 1406597#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1447951#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1447948#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1447943#L1206-5 assume !(0 == ~T1_E~0); 1447940#L1211-3 assume !(0 == ~T2_E~0); 1447937#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1447935#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1447933#L1226-3 assume !(0 == ~T5_E~0); 1447931#L1231-3 assume !(0 == ~T6_E~0); 1447928#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1447925#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1447922#L1246-3 assume !(0 == ~T9_E~0); 1447919#L1251-3 assume !(0 == ~T10_E~0); 1447917#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1447915#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1447913#L1266-3 assume !(0 == ~E_M~0); 1447911#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1447909#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1447907#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1447905#L1286-3 assume !(0 == ~E_4~0); 1447903#L1291-3 assume !(0 == ~E_5~0); 1447901#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1447899#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1447897#L1306-3 assume !(0 == ~E_8~0); 1447895#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1447893#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1447890#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1447888#L1326-3 assume !(0 == ~E_12~0); 1447886#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1447885#L598-42 assume !(1 == ~m_pc~0); 1447884#L598-44 is_master_triggered_~__retres1~0#1 := 0; 1447883#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1447881#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1447880#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 1447879#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1447878#L617-42 assume 1 == ~t1_pc~0; 1447876#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1447874#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1447872#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1447870#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1447869#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1447868#L636-42 assume !(1 == ~t2_pc~0); 1442624#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1447865#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1447863#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1447861#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1447859#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1447851#L655-42 assume !(1 == ~t3_pc~0); 1447844#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1447839#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1447836#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1447833#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1447829#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1447825#L674-42 assume !(1 == ~t4_pc~0); 1447818#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1447812#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1447806#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1447800#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1447793#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1447788#L693-42 assume !(1 == ~t5_pc~0); 1447783#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1447777#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1447772#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1447765#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1447760#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1447755#L712-42 assume !(1 == ~t6_pc~0); 1439121#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1447744#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1447739#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1447732#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1447727#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1447721#L731-42 assume !(1 == ~t7_pc~0); 1441427#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1447711#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1447705#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1447701#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1447696#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1447695#L750-42 assume !(1 == ~t8_pc~0); 1447694#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1447660#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1447658#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1447656#L1561-42 assume !(0 != activate_threads_~tmp___7~0#1); 1445650#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1424509#L769-42 assume !(1 == ~t9_pc~0); 1424508#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1424507#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1424506#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1424505#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 1424504#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1424502#L788-42 assume !(1 == ~t10_pc~0); 1424500#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1424497#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1424495#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1424493#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1424491#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1424489#L807-42 assume !(1 == ~t11_pc~0); 1415910#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1424485#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1424483#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1424481#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1424479#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1424477#L826-42 assume !(1 == ~t12_pc~0); 1424475#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 1424473#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1424471#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 1424469#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1424467#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1424464#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1424462#L1344-5 assume !(1 == ~T1_E~0); 1424460#L1349-3 assume !(1 == ~T2_E~0); 1424458#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1424456#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1424454#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1424452#L1369-3 assume !(1 == ~T6_E~0); 1424450#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1424448#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1424446#L1384-3 assume !(1 == ~T9_E~0); 1424444#L1389-3 assume !(1 == ~T10_E~0); 1424442#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1424440#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1424438#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1424436#L1409-3 assume !(1 == ~E_1~0); 1424434#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1424432#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1424430#L1424-3 assume !(1 == ~E_4~0); 1424428#L1429-3 assume !(1 == ~E_5~0); 1424426#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1424424#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1424422#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1424420#L1449-3 assume !(1 == ~E_9~0); 1424418#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1424416#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1424414#L1464-3 assume !(1 == ~E_12~0); 1424412#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1424407#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1424394#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1424392#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1424390#L1834 assume !(0 == start_simulation_~tmp~3#1); 1424388#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1406656#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1406646#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1406643#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 1406642#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1406639#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1406637#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 1406635#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 1366181#L1815-2 [2021-11-13 18:10:16,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:10:16,516 INFO L85 PathProgramCache]: Analyzing trace with hash 1108494729, now seen corresponding path program 2 times [2021-11-13 18:10:16,516 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:10:16,516 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500878860] [2021-11-13 18:10:16,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:10:16,517 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:10:16,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-13 18:10:16,535 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-13 18:10:16,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-13 18:10:16,669 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-13 18:10:16,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:10:16,670 INFO L85 PathProgramCache]: Analyzing trace with hash 331368731, now seen corresponding path program 1 times [2021-11-13 18:10:16,671 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:10:16,672 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1650844034] [2021-11-13 18:10:16,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:10:16,673 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:10:16,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:10:16,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:10:16,765 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:10:16,766 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1650844034] [2021-11-13 18:10:16,766 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1650844034] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:10:16,766 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:10:16,766 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:10:16,767 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1372991811] [2021-11-13 18:10:16,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:10:16,768 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:10:16,768 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:10:16,768 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:10:16,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:10:16,769 INFO L87 Difference]: Start difference. First operand 88163 states and 120993 transitions. cyclomatic complexity: 32832 Second operand has 3 states, 3 states have (on average 51.333333333333336) internal successors, (154), 3 states have internal predecessors, (154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:10:17,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:10:17,496 INFO L93 Difference]: Finished difference Result 166118 states and 226059 transitions. [2021-11-13 18:10:17,496 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:10:17,497 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 166118 states and 226059 transitions. [2021-11-13 18:10:18,305 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 165776 [2021-11-13 18:10:19,661 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 166118 states to 166118 states and 226059 transitions. [2021-11-13 18:10:19,661 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 166118 [2021-11-13 18:10:19,732 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 166118 [2021-11-13 18:10:19,732 INFO L73 IsDeterministic]: Start isDeterministic. Operand 166118 states and 226059 transitions. [2021-11-13 18:10:19,796 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:10:19,796 INFO L681 BuchiCegarLoop]: Abstraction has 166118 states and 226059 transitions. [2021-11-13 18:10:19,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166118 states and 226059 transitions. [2021-11-13 18:10:21,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166118 to 165702. [2021-11-13 18:10:21,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 165702 states, 165702 states have (on average 1.3605810430773315) internal successors, (225451), 165701 states have internal predecessors, (225451), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:10:22,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165702 states to 165702 states and 225451 transitions. [2021-11-13 18:10:22,097 INFO L704 BuchiCegarLoop]: Abstraction has 165702 states and 225451 transitions. [2021-11-13 18:10:22,098 INFO L587 BuchiCegarLoop]: Abstraction has 165702 states and 225451 transitions. [2021-11-13 18:10:22,098 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-11-13 18:10:22,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 165702 states and 225451 transitions. [2021-11-13 18:10:22,573 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 165392 [2021-11-13 18:10:22,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:10:22,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:10:22,583 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:10:22,583 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:10:22,583 INFO L791 eck$LassoCheckResult]: Stem: 1619927#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1619928#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1619351#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret37#1, start_simulation_#t~ret38#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1619328#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1619329#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 1620716#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1619633#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1619092#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1619093#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1620428#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1620598#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1621246#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1621247#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1619842#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1619843#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1620465#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1620368#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1620369#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1620546#L1206 assume !(0 == ~M_E~0); 1619818#L1206-2 assume !(0 == ~T1_E~0); 1619819#L1211-1 assume !(0 == ~T2_E~0); 1620918#L1216-1 assume !(0 == ~T3_E~0); 1619615#L1221-1 assume !(0 == ~T4_E~0); 1619616#L1226-1 assume !(0 == ~T5_E~0); 1619282#L1231-1 assume !(0 == ~T6_E~0); 1619283#L1236-1 assume !(0 == ~T7_E~0); 1620975#L1241-1 assume !(0 == ~T8_E~0); 1619676#L1246-1 assume !(0 == ~T9_E~0); 1619677#L1251-1 assume !(0 == ~T10_E~0); 1619894#L1256-1 assume !(0 == ~T11_E~0); 1619104#L1261-1 assume !(0 == ~T12_E~0); 1619105#L1266-1 assume !(0 == ~E_M~0); 1621209#L1271-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1620583#L1276-1 assume !(0 == ~E_2~0); 1620584#L1281-1 assume !(0 == ~E_3~0); 1621204#L1286-1 assume !(0 == ~E_4~0); 1619518#L1291-1 assume !(0 == ~E_5~0); 1619519#L1296-1 assume !(0 == ~E_6~0); 1620277#L1301-1 assume !(0 == ~E_7~0); 1620278#L1306-1 assume !(0 == ~E_8~0); 1620817#L1311-1 assume !(0 == ~E_9~0); 1620818#L1316-1 assume !(0 == ~E_10~0); 1621162#L1321-1 assume !(0 == ~E_11~0); 1621163#L1326-1 assume !(0 == ~E_12~0); 1621357#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1621356#L598 assume !(1 == ~m_pc~0); 1621355#L598-2 is_master_triggered_~__retres1~0#1 := 0; 1621354#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1621300#L610 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1621137#L1497 assume !(0 != activate_threads_~tmp~1#1); 1621138#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1621032#L617 assume !(1 == ~t1_pc~0); 1619698#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1619699#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1621352#L629 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1621353#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 1620384#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1620385#L636 assume !(1 == ~t2_pc~0); 1621313#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1621314#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1619500#L648 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1619501#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 1620426#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1620427#L655 assume !(1 == ~t3_pc~0); 1620951#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1620952#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1619369#L667 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1619370#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 1621211#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1621212#L674 assume !(1 == ~t4_pc~0); 1620926#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1620927#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1620590#L686 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1620591#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 1620017#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1620018#L693 assume !(1 == ~t5_pc~0); 1620220#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1620221#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1620854#L705 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1620855#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 1619906#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1619907#L712 assume !(1 == ~t6_pc~0); 1620932#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1620933#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1620680#L724 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1620681#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 1620449#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1620450#L731 assume !(1 == ~t7_pc~0); 1621223#L731-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1621224#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1620578#L743 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1620579#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 1621370#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1619454#L750 assume !(1 == ~t8_pc~0); 1619455#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1621361#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1621362#L762 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1620841#L1561 assume !(0 != activate_threads_~tmp___7~0#1); 1620842#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1620382#L769 assume !(1 == ~t9_pc~0); 1620383#L769-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1619303#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1619304#L781 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1621369#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 1621087#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1620760#L788 assume !(1 == ~t10_pc~0); 1620761#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1620977#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1620978#L800 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1620881#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 1620882#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1621367#L807 assume !(1 == ~t11_pc~0); 1620255#L807-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1620256#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1621015#L819 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1621016#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 1621320#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1621321#L826 assume !(1 == ~t12_pc~0); 1619848#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1619849#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1621244#L838 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 1621245#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 1621363#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1619915#L1344 assume !(1 == ~M_E~0); 1619916#L1344-2 assume !(1 == ~T1_E~0); 1621302#L1349-1 assume !(1 == ~T2_E~0); 1620285#L1354-1 assume !(1 == ~T3_E~0); 1620286#L1359-1 assume !(1 == ~T4_E~0); 1620746#L1364-1 assume !(1 == ~T5_E~0); 1619562#L1369-1 assume !(1 == ~T6_E~0); 1619563#L1374-1 assume !(1 == ~T7_E~0); 1620293#L1379-1 assume !(1 == ~T8_E~0); 1620294#L1384-1 assume !(1 == ~T9_E~0); 1620367#L1389-1 assume !(1 == ~T10_E~0); 1620983#L1394-1 assume !(1 == ~T11_E~0); 1620984#L1399-1 assume !(1 == ~T12_E~0); 1621155#L1404-1 assume !(1 == ~E_M~0); 1619680#L1409-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1619681#L1414-1 assume !(1 == ~E_2~0); 1620629#L1419-1 assume !(1 == ~E_3~0); 1619315#L1424-1 assume !(1 == ~E_4~0); 1619316#L1429-1 assume !(1 == ~E_5~0); 1620305#L1434-1 assume !(1 == ~E_6~0); 1621012#L1439-1 assume !(1 == ~E_7~0); 1619365#L1444-1 assume !(1 == ~E_8~0); 1619366#L1449-1 assume !(1 == ~E_9~0); 1619783#L1454-1 assume !(1 == ~E_10~0); 1619784#L1459-1 assume !(1 == ~E_11~0); 1620403#L1464-1 assume !(1 == ~E_12~0); 1620404#L1469-1 assume { :end_inline_reset_delta_events } true; 1620466#L1815-2 [2021-11-13 18:10:22,583 INFO L793 eck$LassoCheckResult]: Loop: 1620466#L1815-2 assume !false; 1668658#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet22#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1668649#L1181 assume !false; 1668642#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1666665#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1666652#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1666650#L994 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1666647#L1008 assume !(0 != eval_~tmp~0#1); 1666648#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1700278#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1700277#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1700276#L1206-5 assume !(0 == ~T1_E~0); 1700275#L1211-3 assume !(0 == ~T2_E~0); 1700274#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1700273#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1700272#L1226-3 assume !(0 == ~T5_E~0); 1700271#L1231-3 assume !(0 == ~T6_E~0); 1700270#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1700269#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1700268#L1246-3 assume !(0 == ~T9_E~0); 1700267#L1251-3 assume !(0 == ~T10_E~0); 1700266#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1700265#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1700264#L1266-3 assume !(0 == ~E_M~0); 1700246#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1700245#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1700244#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1700243#L1286-3 assume !(0 == ~E_4~0); 1700242#L1291-3 assume !(0 == ~E_5~0); 1700241#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1700240#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1700239#L1306-3 assume !(0 == ~E_8~0); 1700238#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1700237#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1700236#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1700235#L1326-3 assume !(0 == ~E_12~0); 1700234#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_#t~ret35#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1700233#L598-42 assume !(1 == ~m_pc~0); 1700232#L598-44 is_master_triggered_~__retres1~0#1 := 0; 1700231#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1700230#L610-14 activate_threads_#t~ret23#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1700229#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 1700228#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1700226#L617-42 assume !(1 == ~t1_pc~0); 1700225#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1700224#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1700223#L629-14 activate_threads_#t~ret24#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1700222#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 1700220#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1700219#L636-42 assume !(1 == ~t2_pc~0); 1699586#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1700218#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1700217#L648-14 activate_threads_#t~ret25#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1700216#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1700215#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1700214#L655-42 assume !(1 == ~t3_pc~0); 1700213#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1700211#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1700210#L667-14 activate_threads_#t~ret26#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1700209#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1700208#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1700207#L674-42 assume !(1 == ~t4_pc~0); 1700205#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1700204#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1700203#L686-14 activate_threads_#t~ret27#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1700202#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1700201#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1700200#L693-42 assume !(1 == ~t5_pc~0); 1700198#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1700197#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1700196#L705-14 activate_threads_#t~ret28#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1700195#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1700194#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1700193#L712-42 assume !(1 == ~t6_pc~0); 1676831#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1700192#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1689807#L724-14 activate_threads_#t~ret29#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1689803#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1689800#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1678854#L731-42 assume !(1 == ~t7_pc~0); 1678855#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1678849#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1678850#L743-14 activate_threads_#t~ret30#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1678843#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1678844#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1678838#L750-42 assume !(1 == ~t8_pc~0); 1678840#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1678828#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1678829#L762-14 activate_threads_#t~ret31#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1678823#L1561-42 assume !(0 != activate_threads_~tmp___7~0#1); 1678822#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1669038#L769-42 assume !(1 == ~t9_pc~0); 1669032#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1669026#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1669020#L781-14 activate_threads_#t~ret32#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1669013#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 1669007#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1669002#L788-42 assume !(1 == ~t10_pc~0); 1668997#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1668992#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1668975#L800-14 activate_threads_#t~ret33#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1668972#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1668970#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1668968#L807-42 assume !(1 == ~t11_pc~0); 1662418#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1668965#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1668963#L819-14 activate_threads_#t~ret34#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1668962#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1668960#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1668958#L826-42 assume !(1 == ~t12_pc~0); 1668955#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 1668953#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1668950#L838-14 activate_threads_#t~ret35#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret35#1;havoc activate_threads_#t~ret35#1; 1668948#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1668946#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1668944#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1668942#L1344-5 assume !(1 == ~T1_E~0); 1668940#L1349-3 assume !(1 == ~T2_E~0); 1668938#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1668936#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1668934#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1668932#L1369-3 assume !(1 == ~T6_E~0); 1668930#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1668928#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1668926#L1384-3 assume !(1 == ~T9_E~0); 1668924#L1389-3 assume !(1 == ~T10_E~0); 1668922#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1668920#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1668918#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1668916#L1409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1668913#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1668911#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1668908#L1424-3 assume !(1 == ~E_4~0); 1668906#L1429-3 assume !(1 == ~E_5~0); 1668904#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1668902#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1668900#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1668898#L1449-3 assume !(1 == ~E_9~0); 1668896#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1668894#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1668892#L1464-3 assume !(1 == ~E_12~0); 1668890#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1668863#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1668848#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1668842#L994-1 start_simulation_#t~ret37#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1668835#L1834 assume !(0 == start_simulation_~tmp~3#1); 1668832#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret36#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1668721#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1668706#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1668699#L994-2 stop_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret36#1;havoc stop_simulation_#t~ret36#1; 1668694#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1668689#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1668682#L1797 start_simulation_#t~ret38#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret38#1;havoc start_simulation_#t~ret38#1; 1668673#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 1620466#L1815-2 [2021-11-13 18:10:22,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:10:22,584 INFO L85 PathProgramCache]: Analyzing trace with hash -757190839, now seen corresponding path program 1 times [2021-11-13 18:10:22,584 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:10:22,584 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [491448415] [2021-11-13 18:10:22,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:10:22,585 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:10:22,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:10:22,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:10:22,639 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:10:22,639 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [491448415] [2021-11-13 18:10:22,639 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [491448415] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:10:22,640 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:10:22,640 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:10:22,640 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1139419868] [2021-11-13 18:10:22,640 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:10:22,640 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:10:22,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:10:22,640 INFO L85 PathProgramCache]: Analyzing trace with hash -1225960932, now seen corresponding path program 1 times [2021-11-13 18:10:22,641 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:10:22,641 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412630270] [2021-11-13 18:10:22,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:10:22,641 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:10:22,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:10:22,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:10:22,688 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:10:22,688 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1412630270] [2021-11-13 18:10:22,688 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1412630270] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:10:22,688 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:10:22,689 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:10:22,689 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1710619681] [2021-11-13 18:10:22,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:10:22,689 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:10:22,689 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:10:22,690 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:10:22,690 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:10:22,690 INFO L87 Difference]: Start difference. First operand 165702 states and 225451 transitions. cyclomatic complexity: 59751 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:10:24,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:10:24,513 INFO L93 Difference]: Finished difference Result 246390 states and 334526 transitions. [2021-11-13 18:10:24,514 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:10:24,514 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 246390 states and 334526 transitions. [2021-11-13 18:10:25,571 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 238496 [2021-11-13 18:10:27,298 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 246390 states to 246390 states and 334526 transitions. [2021-11-13 18:10:27,298 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 246390 [2021-11-13 18:10:27,432 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 246390 [2021-11-13 18:10:27,432 INFO L73 IsDeterministic]: Start isDeterministic. Operand 246390 states and 334526 transitions. [2021-11-13 18:10:27,549 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:10:27,549 INFO L681 BuchiCegarLoop]: Abstraction has 246390 states and 334526 transitions. [2021-11-13 18:10:27,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246390 states and 334526 transitions.