./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.11.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 63182f13 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/bin/uautomizer-YU5uOKAj3y/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/bin/uautomizer-YU5uOKAj3y/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/bin/uautomizer-YU5uOKAj3y/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/bin/uautomizer-YU5uOKAj3y/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.11.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/bin/uautomizer-YU5uOKAj3y/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/bin/uautomizer-YU5uOKAj3y --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-63182f1 [2021-11-13 18:15:39,521 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-13 18:15:39,524 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-13 18:15:39,580 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-13 18:15:39,581 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-13 18:15:39,582 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-13 18:15:39,584 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-13 18:15:39,587 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-13 18:15:39,589 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-13 18:15:39,591 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-13 18:15:39,592 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-13 18:15:39,594 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-13 18:15:39,595 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-13 18:15:39,597 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-13 18:15:39,599 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-13 18:15:39,601 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-13 18:15:39,602 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-13 18:15:39,604 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-13 18:15:39,607 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-13 18:15:39,610 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-13 18:15:39,622 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-13 18:15:39,625 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-13 18:15:39,627 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-13 18:15:39,629 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-13 18:15:39,633 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-13 18:15:39,634 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-13 18:15:39,634 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-13 18:15:39,636 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-13 18:15:39,644 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-13 18:15:39,646 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-13 18:15:39,648 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-13 18:15:39,649 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-13 18:15:39,652 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-13 18:15:39,653 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-13 18:15:39,660 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-13 18:15:39,660 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-13 18:15:39,661 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-13 18:15:39,661 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-13 18:15:39,661 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-13 18:15:39,662 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-13 18:15:39,663 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-13 18:15:39,664 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/bin/uautomizer-YU5uOKAj3y/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-13 18:15:39,695 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-13 18:15:39,696 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-13 18:15:39,696 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-13 18:15:39,697 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-13 18:15:39,698 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-13 18:15:39,698 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-13 18:15:39,698 INFO L138 SettingsManager]: * Use SBE=true [2021-11-13 18:15:39,699 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-13 18:15:39,699 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-13 18:15:39,699 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-13 18:15:39,699 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-13 18:15:39,700 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-13 18:15:39,700 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-13 18:15:39,700 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-13 18:15:39,701 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-13 18:15:39,701 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-13 18:15:39,701 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-13 18:15:39,701 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-13 18:15:39,702 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-13 18:15:39,702 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-13 18:15:39,702 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-13 18:15:39,702 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-13 18:15:39,703 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-13 18:15:39,703 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-13 18:15:39,703 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-13 18:15:39,703 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-13 18:15:39,704 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-13 18:15:39,704 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-13 18:15:39,704 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-13 18:15:39,704 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-13 18:15:39,705 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-13 18:15:39,705 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-13 18:15:39,706 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-13 18:15:39,706 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/bin/uautomizer-YU5uOKAj3y/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/bin/uautomizer-YU5uOKAj3y Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 [2021-11-13 18:15:39,968 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-13 18:15:39,990 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-13 18:15:40,002 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-13 18:15:40,003 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-13 18:15:40,004 INFO L275 PluginConnector]: CDTParser initialized [2021-11-13 18:15:40,006 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/bin/uautomizer-YU5uOKAj3y/../../sv-benchmarks/c/systemc/transmitter.11.cil.c [2021-11-13 18:15:40,096 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/bin/uautomizer-YU5uOKAj3y/data/b94d2854c/4bd345982f5948ea97fbfe7510aae995/FLAG790981e84 [2021-11-13 18:15:40,704 INFO L306 CDTParser]: Found 1 translation units. [2021-11-13 18:15:40,705 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/sv-benchmarks/c/systemc/transmitter.11.cil.c [2021-11-13 18:15:40,728 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/bin/uautomizer-YU5uOKAj3y/data/b94d2854c/4bd345982f5948ea97fbfe7510aae995/FLAG790981e84 [2021-11-13 18:15:40,991 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/bin/uautomizer-YU5uOKAj3y/data/b94d2854c/4bd345982f5948ea97fbfe7510aae995 [2021-11-13 18:15:40,994 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-13 18:15:40,996 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-13 18:15:41,013 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-13 18:15:41,013 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-13 18:15:41,018 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-13 18:15:41,019 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 06:15:40" (1/1) ... [2021-11-13 18:15:41,020 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@53287373 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:15:41, skipping insertion in model container [2021-11-13 18:15:41,020 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 06:15:40" (1/1) ... [2021-11-13 18:15:41,029 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-13 18:15:41,114 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-13 18:15:41,328 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/sv-benchmarks/c/systemc/transmitter.11.cil.c[706,719] [2021-11-13 18:15:41,546 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-13 18:15:41,570 INFO L203 MainTranslator]: Completed pre-run [2021-11-13 18:15:41,584 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/sv-benchmarks/c/systemc/transmitter.11.cil.c[706,719] [2021-11-13 18:15:41,646 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-13 18:15:41,667 INFO L208 MainTranslator]: Completed translation [2021-11-13 18:15:41,667 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:15:41 WrapperNode [2021-11-13 18:15:41,668 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-13 18:15:41,669 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-13 18:15:41,669 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-13 18:15:41,669 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-13 18:15:41,677 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:15:41" (1/1) ... [2021-11-13 18:15:41,691 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:15:41" (1/1) ... [2021-11-13 18:15:41,791 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-13 18:15:41,793 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-13 18:15:41,793 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-13 18:15:41,793 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-13 18:15:41,803 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:15:41" (1/1) ... [2021-11-13 18:15:41,804 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:15:41" (1/1) ... [2021-11-13 18:15:41,825 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:15:41" (1/1) ... [2021-11-13 18:15:41,826 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:15:41" (1/1) ... [2021-11-13 18:15:41,904 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:15:41" (1/1) ... [2021-11-13 18:15:41,980 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:15:41" (1/1) ... [2021-11-13 18:15:41,989 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:15:41" (1/1) ... [2021-11-13 18:15:42,009 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-13 18:15:42,011 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-13 18:15:42,011 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-13 18:15:42,011 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-13 18:15:42,012 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:15:41" (1/1) ... [2021-11-13 18:15:42,021 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-13 18:15:42,036 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/bin/uautomizer-YU5uOKAj3y/z3 [2021-11-13 18:15:42,051 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/bin/uautomizer-YU5uOKAj3y/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-13 18:15:42,067 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9675aa36-1812-4a2f-92b2-9540d014ff4c/bin/uautomizer-YU5uOKAj3y/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-13 18:15:42,117 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-13 18:15:42,117 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-13 18:15:42,118 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-13 18:15:42,118 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-13 18:15:44,600 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-13 18:15:44,600 INFO L299 CfgBuilder]: Removed 15 assume(true) statements. [2021-11-13 18:15:44,604 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 06:15:44 BoogieIcfgContainer [2021-11-13 18:15:44,604 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-13 18:15:44,605 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-13 18:15:44,605 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-13 18:15:44,624 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-13 18:15:44,624 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-13 18:15:44,625 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 06:15:40" (1/3) ... [2021-11-13 18:15:44,627 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1c77f1c9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 06:15:44, skipping insertion in model container [2021-11-13 18:15:44,627 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-13 18:15:44,627 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:15:41" (2/3) ... [2021-11-13 18:15:44,628 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1c77f1c9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 06:15:44, skipping insertion in model container [2021-11-13 18:15:44,629 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-13 18:15:44,629 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 06:15:44" (3/3) ... [2021-11-13 18:15:44,630 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.11.cil.c [2021-11-13 18:15:44,673 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-13 18:15:44,673 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-13 18:15:44,673 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-13 18:15:44,673 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-13 18:15:44,673 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-13 18:15:44,673 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-13 18:15:44,673 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-13 18:15:44,673 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-13 18:15:44,725 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1483 states, 1482 states have (on average 1.5053981106612686) internal successors, (2231), 1482 states have internal predecessors, (2231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:44,810 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1330 [2021-11-13 18:15:44,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:44,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:44,829 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:44,829 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:44,829 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-13 18:15:44,833 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1483 states, 1482 states have (on average 1.5053981106612686) internal successors, (2231), 1482 states have internal predecessors, (2231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:44,851 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1330 [2021-11-13 18:15:44,851 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:44,851 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:44,857 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:44,857 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:44,867 INFO L791 eck$LassoCheckResult]: Stem: 715#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1355#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 725#L1607true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1298#L754true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 511#L761true assume !(1 == ~m_i~0);~m_st~0 := 2; 527#L761-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 424#L766-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 366#L771-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 204#L776-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 21#L781-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1462#L786-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 44#L791-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 646#L796-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 612#L801-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 655#L806-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1335#L811-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 262#L816-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1145#L1090true assume !(0 == ~M_E~0); 288#L1090-2true assume !(0 == ~T1_E~0); 1306#L1095-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 785#L1100-1true assume !(0 == ~T3_E~0); 811#L1105-1true assume !(0 == ~T4_E~0); 157#L1110-1true assume !(0 == ~T5_E~0); 386#L1115-1true assume !(0 == ~T6_E~0); 595#L1120-1true assume !(0 == ~T7_E~0); 1343#L1125-1true assume !(0 == ~T8_E~0); 1336#L1130-1true assume !(0 == ~T9_E~0); 809#L1135-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 265#L1140-1true assume !(0 == ~T11_E~0); 739#L1145-1true assume !(0 == ~E_1~0); 781#L1150-1true assume !(0 == ~E_2~0); 374#L1155-1true assume !(0 == ~E_3~0); 1315#L1160-1true assume !(0 == ~E_4~0); 430#L1165-1true assume !(0 == ~E_5~0); 1070#L1170-1true assume !(0 == ~E_6~0); 1255#L1175-1true assume 0 == ~E_7~0;~E_7~0 := 1; 480#L1180-1true assume !(0 == ~E_8~0); 895#L1185-1true assume !(0 == ~E_9~0); 263#L1190-1true assume !(0 == ~E_10~0); 490#L1195-1true assume !(0 == ~E_11~0); 1013#L1200-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 381#L525true assume !(1 == ~m_pc~0); 62#L525-2true is_master_triggered_~__retres1~0#1 := 0; 1009#L536true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 492#L537true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 874#L1350true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 254#L1350-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 531#L544true assume 1 == ~t1_pc~0; 412#L545true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 736#L555true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1466#L556true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 168#L1358true assume !(0 != activate_threads_~tmp___0~0#1); 574#L1358-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1004#L563true assume !(1 == ~t2_pc~0); 726#L563-2true is_transmit2_triggered_~__retres1~2#1 := 0; 73#L574true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 570#L575true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 304#L1366true assume !(0 != activate_threads_~tmp___1~0#1); 634#L1366-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 737#L582true assume 1 == ~t3_pc~0; 141#L583true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1214#L593true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1427#L594true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1082#L1374true assume !(0 != activate_threads_~tmp___2~0#1); 108#L1374-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1378#L601true assume !(1 == ~t4_pc~0); 829#L601-2true is_transmit4_triggered_~__retres1~4#1 := 0; 387#L612true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 791#L613true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 748#L1382true assume !(0 != activate_threads_~tmp___3~0#1); 1387#L1382-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1186#L620true assume 1 == ~t5_pc~0; 87#L621true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 652#L631true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 592#L632true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1460#L1390true assume !(0 != activate_threads_~tmp___4~0#1); 1244#L1390-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1348#L639true assume !(1 == ~t6_pc~0); 593#L639-2true is_transmit6_triggered_~__retres1~6#1 := 0; 325#L650true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1086#L651true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1239#L1398true assume !(0 != activate_threads_~tmp___5~0#1); 391#L1398-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 940#L658true assume 1 == ~t7_pc~0; 594#L659true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1262#L669true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 621#L670true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 687#L1406true assume !(0 != activate_threads_~tmp___6~0#1); 259#L1406-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 394#L677true assume 1 == ~t8_pc~0; 864#L678true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 148#L688true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1034#L689true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 302#L1414true assume !(0 != activate_threads_~tmp___7~0#1); 865#L1414-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 972#L696true assume !(1 == ~t9_pc~0); 582#L696-2true is_transmit9_triggered_~__retres1~9#1 := 0; 662#L707true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 755#L708true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 598#L1422true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 789#L1422-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1123#L715true assume 1 == ~t10_pc~0; 797#L716true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 677#L726true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 576#L727true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 766#L1430true assume !(0 != activate_threads_~tmp___9~0#1); 475#L1430-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 145#L734true assume !(1 == ~t11_pc~0); 432#L734-2true is_transmit11_triggered_~__retres1~11#1 := 0; 483#L745true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 496#L746true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15#L1438true assume !(0 != activate_threads_~tmp___10~0#1); 653#L1438-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1182#L1213true assume !(1 == ~M_E~0); 473#L1213-2true assume !(1 == ~T1_E~0); 958#L1218-1true assume !(1 == ~T2_E~0); 33#L1223-1true assume !(1 == ~T3_E~0); 458#L1228-1true assume !(1 == ~T4_E~0); 1245#L1233-1true assume !(1 == ~T5_E~0); 1440#L1238-1true assume !(1 == ~T6_E~0); 747#L1243-1true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1393#L1248-1true assume !(1 == ~T8_E~0); 795#L1253-1true assume !(1 == ~T9_E~0); 1087#L1258-1true assume !(1 == ~T10_E~0); 773#L1263-1true assume !(1 == ~T11_E~0); 1129#L1268-1true assume !(1 == ~E_1~0); 611#L1273-1true assume !(1 == ~E_2~0); 1225#L1278-1true assume !(1 == ~E_3~0); 324#L1283-1true assume 1 == ~E_4~0;~E_4~0 := 2; 1276#L1288-1true assume !(1 == ~E_5~0); 916#L1293-1true assume !(1 == ~E_6~0); 870#L1298-1true assume !(1 == ~E_7~0); 637#L1303-1true assume !(1 == ~E_8~0); 331#L1308-1true assume !(1 == ~E_9~0); 268#L1313-1true assume !(1 == ~E_10~0); 1361#L1318-1true assume !(1 == ~E_11~0); 274#L1323-1true assume { :end_inline_reset_delta_events } true; 1135#L1644-2true [2021-11-13 18:15:44,870 INFO L793 eck$LassoCheckResult]: Loop: 1135#L1644-2true assume !false; 685#L1645true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 765#L1065true assume !true; 867#L1080true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 762#L754-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 946#L1090-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1025#L1090-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1364#L1095-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 975#L1100-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1237#L1105-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 201#L1110-3true assume !(0 == ~T5_E~0); 1075#L1115-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 367#L1120-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 744#L1125-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1115#L1130-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1273#L1135-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 318#L1140-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 49#L1145-3true assume 0 == ~E_1~0;~E_1~0 := 1; 498#L1150-3true assume !(0 == ~E_2~0); 109#L1155-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1421#L1160-3true assume 0 == ~E_4~0;~E_4~0 := 1; 308#L1165-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1480#L1170-3true assume 0 == ~E_6~0;~E_6~0 := 1; 567#L1175-3true assume 0 == ~E_7~0;~E_7~0 := 1; 256#L1180-3true assume 0 == ~E_8~0;~E_8~0 := 1; 124#L1185-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1278#L1190-3true assume !(0 == ~E_10~0); 1095#L1195-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1478#L1200-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 447#L525-36true assume !(1 == ~m_pc~0); 1132#L525-38true is_master_triggered_~__retres1~0#1 := 0; 174#L536-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1351#L537-12true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 339#L1350-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 566#L1350-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 290#L544-36true assume 1 == ~t1_pc~0; 792#L545-12true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 667#L555-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 221#L556-12true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1257#L1358-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1066#L1358-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 906#L563-36true assume 1 == ~t2_pc~0; 167#L564-12true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47#L574-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 752#L575-12true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1254#L1366-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 457#L1366-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1363#L582-36true assume 1 == ~t3_pc~0; 361#L583-12true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 510#L593-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1366#L594-12true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 660#L1374-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 482#L1374-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 444#L601-36true assume 1 == ~t4_pc~0; 378#L602-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1456#L612-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1265#L613-12true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1035#L1382-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1177#L1382-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 891#L620-36true assume !(1 == ~t5_pc~0); 1453#L620-38true is_transmit5_triggered_~__retres1~5#1 := 0; 729#L631-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 953#L632-12true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 393#L1390-36true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 180#L1390-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70#L639-36true assume 1 == ~t6_pc~0; 717#L640-12true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 89#L650-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1005#L651-12true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 212#L1398-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 597#L1398-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1176#L658-36true assume !(1 == ~t7_pc~0); 75#L658-38true is_transmit7_triggered_~__retres1~7#1 := 0; 1006#L669-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1046#L670-12true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 64#L1406-36true assume !(0 != activate_threads_~tmp___6~0#1); 712#L1406-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 927#L677-36true assume !(1 == ~t8_pc~0); 534#L677-38true is_transmit8_triggered_~__retres1~8#1 := 0; 635#L688-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1187#L689-12true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1174#L1414-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 555#L1414-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1092#L696-36true assume 1 == ~t9_pc~0; 471#L697-12true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 827#L707-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 98#L708-12true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1007#L1422-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 568#L1422-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1251#L715-36true assume !(1 == ~t10_pc~0); 543#L715-38true is_transmit10_triggered_~__retres1~10#1 := 0; 16#L726-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 127#L727-12true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4#L1430-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1052#L1430-38true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 206#L734-36true assume 1 == ~t11_pc~0; 799#L735-12true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 216#L745-12true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 460#L746-12true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12#L1438-36true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 616#L1438-38true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1098#L1213-3true assume 1 == ~M_E~0;~M_E~0 := 2; 372#L1213-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 710#L1218-3true assume !(1 == ~T2_E~0); 233#L1223-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 753#L1228-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 345#L1233-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1263#L1238-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 508#L1243-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1033#L1248-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1400#L1253-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1042#L1258-3true assume !(1 == ~T10_E~0); 222#L1263-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 989#L1268-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1012#L1273-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1454#L1278-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1015#L1283-3true assume 1 == ~E_4~0;~E_4~0 := 2; 428#L1288-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1285#L1293-3true assume 1 == ~E_6~0;~E_6~0 := 2; 338#L1298-3true assume !(1 == ~E_7~0); 1136#L1303-3true assume 1 == ~E_8~0;~E_8~0 := 2; 683#L1308-3true assume 1 == ~E_9~0;~E_9~0 := 2; 336#L1313-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1037#L1318-3true assume 1 == ~E_11~0;~E_11~0 := 2; 223#L1323-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1428#L829-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 440#L891-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 836#L892-1true start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1429#L1663true assume !(0 == start_simulation_~tmp~3#1); 1329#L1663-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 596#L829-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 526#L891-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 703#L892-2true stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 80#L1618true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 261#L1625true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1299#L1626true start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1164#L1676true assume !(0 != start_simulation_~tmp___0~1#1); 1135#L1644-2true [2021-11-13 18:15:44,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:44,877 INFO L85 PathProgramCache]: Analyzing trace with hash -92888918, now seen corresponding path program 1 times [2021-11-13 18:15:44,886 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:44,886 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1091871161] [2021-11-13 18:15:44,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:44,888 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:45,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:45,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:45,192 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:45,192 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1091871161] [2021-11-13 18:15:45,193 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1091871161] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:45,193 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:45,194 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:45,195 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [449771634] [2021-11-13 18:15:45,196 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:45,201 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:45,217 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:45,217 INFO L85 PathProgramCache]: Analyzing trace with hash 862291405, now seen corresponding path program 1 times [2021-11-13 18:15:45,218 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:45,218 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248778537] [2021-11-13 18:15:45,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:45,218 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:45,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:45,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:45,311 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:45,312 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248778537] [2021-11-13 18:15:45,313 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1248778537] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:45,313 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:45,313 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:15:45,314 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [172520195] [2021-11-13 18:15:45,314 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:45,315 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:45,317 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:45,355 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-11-13 18:15:45,356 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-11-13 18:15:45,362 INFO L87 Difference]: Start difference. First operand has 1483 states, 1482 states have (on average 1.5053981106612686) internal successors, (2231), 1482 states have internal predecessors, (2231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 68.5) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:45,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:45,433 INFO L93 Difference]: Finished difference Result 1482 states and 2199 transitions. [2021-11-13 18:15:45,434 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-11-13 18:15:45,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1482 states and 2199 transitions. [2021-11-13 18:15:45,454 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:45,471 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1482 states to 1476 states and 2193 transitions. [2021-11-13 18:15:45,472 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-13 18:15:45,475 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-13 18:15:45,475 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2193 transitions. [2021-11-13 18:15:45,482 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:45,483 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2193 transitions. [2021-11-13 18:15:45,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2193 transitions. [2021-11-13 18:15:45,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-13 18:15:45,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4857723577235773) internal successors, (2193), 1475 states have internal predecessors, (2193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:45,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2193 transitions. [2021-11-13 18:15:45,594 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2193 transitions. [2021-11-13 18:15:45,594 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2193 transitions. [2021-11-13 18:15:45,595 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-13 18:15:45,595 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2193 transitions. [2021-11-13 18:15:45,605 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:45,605 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:45,605 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:45,609 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:45,609 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:45,610 INFO L791 eck$LassoCheckResult]: Stem: 4096#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 4097#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4106#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4107#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3872#L761 assume !(1 == ~m_i~0);~m_st~0 := 2; 3873#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3742#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3654#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3377#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3012#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3013#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3061#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3062#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3990#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3991#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4029#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3477#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3478#L1090 assume !(0 == ~M_E~0); 3523#L1090-2 assume !(0 == ~T1_E~0); 3524#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4167#L1100-1 assume !(0 == ~T3_E~0); 4168#L1105-1 assume !(0 == ~T4_E~0); 3296#L1110-1 assume !(0 == ~T5_E~0); 3297#L1115-1 assume !(0 == ~T6_E~0); 3692#L1120-1 assume !(0 == ~T7_E~0); 3969#L1125-1 assume !(0 == ~T8_E~0); 4438#L1130-1 assume !(0 == ~T9_E~0); 4187#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3482#L1140-1 assume !(0 == ~T11_E~0); 3483#L1145-1 assume !(0 == ~E_1~0); 4121#L1150-1 assume !(0 == ~E_2~0); 3667#L1155-1 assume !(0 == ~E_3~0); 3668#L1160-1 assume !(0 == ~E_4~0); 3750#L1165-1 assume !(0 == ~E_5~0); 3751#L1170-1 assume !(0 == ~E_6~0); 4359#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3828#L1180-1 assume !(0 == ~E_8~0); 3829#L1185-1 assume !(0 == ~E_9~0); 3479#L1190-1 assume !(0 == ~E_10~0); 3480#L1195-1 assume !(0 == ~E_11~0); 3842#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3689#L525 assume !(1 == ~m_pc~0); 3100#L525-2 is_master_triggered_~__retres1~0#1 := 0; 3101#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3846#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3847#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3466#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3467#L544 assume 1 == ~t1_pc~0; 3727#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3691#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4119#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3317#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 3318#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3940#L563 assume !(1 == ~t2_pc~0); 4108#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3121#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3122#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3553#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 3554#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4013#L582 assume 1 == ~t3_pc~0; 3261#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3262#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4410#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4368#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 3195#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3196#L601 assume !(1 == ~t4_pc~0); 4136#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3693#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3694#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4130#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 4131#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4402#L620 assume 1 == ~t5_pc~0; 3154#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3155#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3965#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3966#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 4417#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4418#L639 assume !(1 == ~t6_pc~0); 3967#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3590#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3591#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4371#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 3701#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3702#L658 assume 1 == ~t7_pc~0; 3968#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3895#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4000#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4001#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 3473#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3474#L677 assume 1 == ~t8_pc~0; 3706#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3276#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3277#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3547#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 3548#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4226#L696 assume !(1 == ~t9_pc~0); 3953#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3954#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4044#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3973#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3974#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4171#L715 assume 1 == ~t10_pc~0; 4175#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4058#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3943#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3944#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 3820#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3270#L734 assume !(1 == ~t11_pc~0); 3271#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 3754#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3833#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3002#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 3003#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4028#L1213 assume !(1 == ~M_E~0); 3818#L1213-2 assume !(1 == ~T1_E~0); 3819#L1218-1 assume !(1 == ~T2_E~0); 3037#L1223-1 assume !(1 == ~T3_E~0); 3038#L1228-1 assume !(1 == ~T4_E~0); 3797#L1233-1 assume !(1 == ~T5_E~0); 4419#L1238-1 assume !(1 == ~T6_E~0); 4128#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4129#L1248-1 assume !(1 == ~T8_E~0); 4173#L1253-1 assume !(1 == ~T9_E~0); 4174#L1258-1 assume !(1 == ~T10_E~0); 4152#L1263-1 assume !(1 == ~T11_E~0); 4153#L1268-1 assume !(1 == ~E_1~0); 3988#L1273-1 assume !(1 == ~E_2~0); 3989#L1278-1 assume !(1 == ~E_3~0); 3588#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3589#L1288-1 assume !(1 == ~E_5~0); 4266#L1293-1 assume !(1 == ~E_6~0); 4230#L1298-1 assume !(1 == ~E_7~0); 4016#L1303-1 assume !(1 == ~E_8~0); 3599#L1308-1 assume !(1 == ~E_9~0); 3488#L1313-1 assume !(1 == ~E_10~0); 3489#L1318-1 assume !(1 == ~E_11~0); 3501#L1323-1 assume { :end_inline_reset_delta_events } true; 3502#L1644-2 [2021-11-13 18:15:45,611 INFO L793 eck$LassoCheckResult]: Loop: 3502#L1644-2 assume !false; 4069#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4070#L1065 assume !false; 4145#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4415#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3119#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4331#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 3604#L906 assume !(0 != eval_~tmp~0#1); 3606#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4143#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4144#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4283#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4335#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4298#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4299#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3372#L1110-3 assume !(0 == ~T5_E~0); 3373#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3655#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3656#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4126#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4380#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3580#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3075#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3076#L1150-3 assume !(0 == ~E_2~0); 3198#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3199#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3559#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3560#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3932#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3469#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3230#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3231#L1190-3 assume !(0 == ~E_10~0); 4374#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4375#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3782#L525-36 assume !(1 == ~m_pc~0); 3783#L525-38 is_master_triggered_~__retres1~0#1 := 0; 3333#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3334#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3614#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3615#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3520#L544-36 assume 1 == ~t1_pc~0; 3521#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4047#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3412#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3413#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4356#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4259#L563-36 assume 1 == ~t2_pc~0; 3315#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3071#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3072#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4134#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3795#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3796#L582-36 assume !(1 == ~t3_pc~0); 3648#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3647#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3871#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4038#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3832#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3776#L601-36 assume 1 == ~t4_pc~0; 3675#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3676#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4423#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4341#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4342#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4247#L620-36 assume 1 == ~t5_pc~0; 3715#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3716#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4109#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3703#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3337#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3115#L639-36 assume 1 == ~t6_pc~0; 3116#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3152#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3153#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3393#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3394#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3972#L658-36 assume 1 == ~t7_pc~0; 3232#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3127#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4326#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3102#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 3103#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4093#L677-36 assume !(1 == ~t8_pc~0); 3897#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 3898#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4014#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4398#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3920#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3921#L696-36 assume 1 == ~t9_pc~0; 3814#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3816#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3175#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3176#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3933#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3934#L715-36 assume !(1 == ~t10_pc~0); 3904#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3000#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3001#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2976#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2977#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3381#L734-36 assume 1 == ~t11_pc~0; 3382#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3081#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3403#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 2994#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2995#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3994#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3661#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3662#L1218-3 assume !(1 == ~T2_E~0); 3432#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3433#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3622#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3623#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3867#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3868#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4339#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4344#L1258-3 assume !(1 == ~T10_E~0); 3414#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3415#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4310#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4328#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4330#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3746#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3747#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3612#L1298-3 assume !(1 == ~E_7~0); 3613#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4068#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3609#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3610#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3416#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3417#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3356#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3767#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 4206#L1663 assume !(0 == start_simulation_~tmp~3#1); 3249#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3970#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3193#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3889#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 3137#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3138#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3476#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4395#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 3502#L1644-2 [2021-11-13 18:15:45,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:45,613 INFO L85 PathProgramCache]: Analyzing trace with hash -92888918, now seen corresponding path program 2 times [2021-11-13 18:15:45,613 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:45,613 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1742411651] [2021-11-13 18:15:45,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:45,614 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:45,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:45,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:45,757 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:45,757 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1742411651] [2021-11-13 18:15:45,758 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1742411651] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:45,758 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:45,759 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:45,763 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1675112907] [2021-11-13 18:15:45,764 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:45,765 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:45,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:45,777 INFO L85 PathProgramCache]: Analyzing trace with hash -852141939, now seen corresponding path program 1 times [2021-11-13 18:15:45,778 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:45,779 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1678013316] [2021-11-13 18:15:45,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:45,780 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:45,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:45,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:45,970 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:45,971 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1678013316] [2021-11-13 18:15:45,971 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1678013316] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:45,971 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:45,971 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:45,972 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1658806392] [2021-11-13 18:15:45,972 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:45,972 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:45,973 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:45,973 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:15:45,973 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:15:45,974 INFO L87 Difference]: Start difference. First operand 1476 states and 2193 transitions. cyclomatic complexity: 718 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:46,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:46,033 INFO L93 Difference]: Finished difference Result 1476 states and 2192 transitions. [2021-11-13 18:15:46,034 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:15:46,035 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2192 transitions. [2021-11-13 18:15:46,052 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:46,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2192 transitions. [2021-11-13 18:15:46,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-13 18:15:46,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-13 18:15:46,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2192 transitions. [2021-11-13 18:15:46,071 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:46,071 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2192 transitions. [2021-11-13 18:15:46,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2192 transitions. [2021-11-13 18:15:46,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-13 18:15:46,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4850948509485096) internal successors, (2192), 1475 states have internal predecessors, (2192), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:46,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2192 transitions. [2021-11-13 18:15:46,109 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2192 transitions. [2021-11-13 18:15:46,109 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2192 transitions. [2021-11-13 18:15:46,109 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-13 18:15:46,110 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2192 transitions. [2021-11-13 18:15:46,121 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:46,121 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:46,121 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:46,128 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:46,128 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:46,130 INFO L791 eck$LassoCheckResult]: Stem: 7055#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 7056#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7063#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7064#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6831#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 6832#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6701#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 6613#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6336#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5971#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5972#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6020#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6021#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6949#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6950#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6988#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 6436#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6437#L1090 assume !(0 == ~M_E~0); 6479#L1090-2 assume !(0 == ~T1_E~0); 6480#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7125#L1100-1 assume !(0 == ~T3_E~0); 7126#L1105-1 assume !(0 == ~T4_E~0); 6254#L1110-1 assume !(0 == ~T5_E~0); 6255#L1115-1 assume !(0 == ~T6_E~0); 6651#L1120-1 assume !(0 == ~T7_E~0); 6928#L1125-1 assume !(0 == ~T8_E~0); 7397#L1130-1 assume !(0 == ~T9_E~0); 7146#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6441#L1140-1 assume !(0 == ~T11_E~0); 6442#L1145-1 assume !(0 == ~E_1~0); 7080#L1150-1 assume !(0 == ~E_2~0); 6626#L1155-1 assume !(0 == ~E_3~0); 6627#L1160-1 assume !(0 == ~E_4~0); 6709#L1165-1 assume !(0 == ~E_5~0); 6710#L1170-1 assume !(0 == ~E_6~0); 7318#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6787#L1180-1 assume !(0 == ~E_8~0); 6788#L1185-1 assume !(0 == ~E_9~0); 6438#L1190-1 assume !(0 == ~E_10~0); 6439#L1195-1 assume !(0 == ~E_11~0); 6801#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6641#L525 assume !(1 == ~m_pc~0); 6059#L525-2 is_master_triggered_~__retres1~0#1 := 0; 6060#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6805#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6806#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6425#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6426#L544 assume 1 == ~t1_pc~0; 6686#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6650#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7078#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6276#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 6277#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6899#L563 assume !(1 == ~t2_pc~0); 7065#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6080#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6081#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6509#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 6510#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6972#L582 assume 1 == ~t3_pc~0; 6218#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6219#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7369#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7327#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 6154#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6155#L601 assume !(1 == ~t4_pc~0); 7095#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6652#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6653#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7089#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 7090#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7361#L620 assume 1 == ~t5_pc~0; 6109#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6110#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6924#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6925#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 7376#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7377#L639 assume !(1 == ~t6_pc~0); 6926#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6549#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6550#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7330#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 6660#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6661#L658 assume 1 == ~t7_pc~0; 6927#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6852#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6959#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6960#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 6432#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6433#L677 assume 1 == ~t8_pc~0; 6663#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6235#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6236#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6506#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 6507#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7185#L696 assume !(1 == ~t9_pc~0); 6910#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6911#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7000#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 6932#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6933#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7130#L715 assume 1 == ~t10_pc~0; 7134#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7017#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6902#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 6903#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 6779#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6227#L734 assume !(1 == ~t11_pc~0); 6228#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 6713#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6792#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5959#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 5960#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6987#L1213 assume !(1 == ~M_E~0); 6776#L1213-2 assume !(1 == ~T1_E~0); 6777#L1218-1 assume !(1 == ~T2_E~0); 5996#L1223-1 assume !(1 == ~T3_E~0); 5997#L1228-1 assume !(1 == ~T4_E~0); 6756#L1233-1 assume !(1 == ~T5_E~0); 7378#L1238-1 assume !(1 == ~T6_E~0); 7087#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7088#L1248-1 assume !(1 == ~T8_E~0); 7132#L1253-1 assume !(1 == ~T9_E~0); 7133#L1258-1 assume !(1 == ~T10_E~0); 7111#L1263-1 assume !(1 == ~T11_E~0); 7112#L1268-1 assume !(1 == ~E_1~0); 6947#L1273-1 assume !(1 == ~E_2~0); 6948#L1278-1 assume !(1 == ~E_3~0); 6547#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6548#L1288-1 assume !(1 == ~E_5~0); 7225#L1293-1 assume !(1 == ~E_6~0); 7189#L1298-1 assume !(1 == ~E_7~0); 6975#L1303-1 assume !(1 == ~E_8~0); 6558#L1308-1 assume !(1 == ~E_9~0); 6447#L1313-1 assume !(1 == ~E_10~0); 6448#L1318-1 assume !(1 == ~E_11~0); 6457#L1323-1 assume { :end_inline_reset_delta_events } true; 6458#L1644-2 [2021-11-13 18:15:46,131 INFO L793 eck$LassoCheckResult]: Loop: 6458#L1644-2 assume !false; 7028#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7029#L1065 assume !false; 7104#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7374#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6078#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7290#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 6563#L906 assume !(0 != eval_~tmp~0#1); 6565#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7101#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7102#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7242#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7294#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7257#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7258#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6331#L1110-3 assume !(0 == ~T5_E~0); 6332#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6614#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6615#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7085#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7339#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6537#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 6032#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6033#L1150-3 assume !(0 == ~E_2~0); 6156#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6157#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6518#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6519#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6891#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6428#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6186#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6187#L1190-3 assume !(0 == ~E_10~0); 7333#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7334#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6741#L525-36 assume !(1 == ~m_pc~0); 6742#L525-38 is_master_triggered_~__retres1~0#1 := 0; 6287#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6288#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6573#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6574#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6482#L544-36 assume 1 == ~t1_pc~0; 6483#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7006#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6371#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6372#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7315#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7218#L563-36 assume 1 == ~t2_pc~0; 6274#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6030#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6031#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7093#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6754#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6755#L582-36 assume 1 == ~t3_pc~0; 6605#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6606#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6830#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6997#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6791#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6735#L601-36 assume 1 == ~t4_pc~0; 6634#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6635#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7382#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7300#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7301#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7206#L620-36 assume 1 == ~t5_pc~0; 6676#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6677#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7068#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6662#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6296#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6074#L639-36 assume 1 == ~t6_pc~0; 6075#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6114#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6115#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6354#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6355#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6931#L658-36 assume 1 == ~t7_pc~0; 6193#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6086#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7285#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6061#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 6062#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7052#L677-36 assume !(1 == ~t8_pc~0); 6856#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 6857#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6973#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7357#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6879#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6880#L696-36 assume 1 == ~t9_pc~0; 6773#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6775#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6134#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 6135#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6892#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6893#L715-36 assume 1 == ~t10_pc~0; 7026#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5961#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5962#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5935#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5936#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6340#L734-36 assume 1 == ~t11_pc~0; 6341#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 6040#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6362#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5953#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5954#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6953#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6622#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6623#L1218-3 assume !(1 == ~T2_E~0); 6391#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6392#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6581#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6582#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6826#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6827#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7299#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7304#L1258-3 assume !(1 == ~T10_E~0); 6373#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 6374#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7269#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7287#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7289#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6705#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6706#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6571#L1298-3 assume !(1 == ~E_7~0); 6572#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7027#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6568#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6569#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 6375#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6376#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6315#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6726#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 7165#L1663 assume !(0 == start_simulation_~tmp~3#1); 6208#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6929#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6152#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6850#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 6096#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6097#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6435#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 7354#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 6458#L1644-2 [2021-11-13 18:15:46,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:46,135 INFO L85 PathProgramCache]: Analyzing trace with hash -456355416, now seen corresponding path program 1 times [2021-11-13 18:15:46,135 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:46,136 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1587384886] [2021-11-13 18:15:46,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:46,137 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:46,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:46,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:46,222 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:46,222 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1587384886] [2021-11-13 18:15:46,222 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1587384886] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:46,223 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:46,223 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:46,223 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1982463530] [2021-11-13 18:15:46,223 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:46,224 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:46,224 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:46,224 INFO L85 PathProgramCache]: Analyzing trace with hash 2047437327, now seen corresponding path program 1 times [2021-11-13 18:15:46,225 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:46,225 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10522468] [2021-11-13 18:15:46,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:46,226 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:46,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:46,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:46,324 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:46,325 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10522468] [2021-11-13 18:15:46,326 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10522468] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:46,326 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:46,326 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:46,326 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [792947018] [2021-11-13 18:15:46,327 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:46,328 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:46,328 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:46,328 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:15:46,329 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:15:46,329 INFO L87 Difference]: Start difference. First operand 1476 states and 2192 transitions. cyclomatic complexity: 717 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:46,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:46,370 INFO L93 Difference]: Finished difference Result 1476 states and 2191 transitions. [2021-11-13 18:15:46,370 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:15:46,372 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2191 transitions. [2021-11-13 18:15:46,385 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:46,397 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2191 transitions. [2021-11-13 18:15:46,398 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-13 18:15:46,399 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-13 18:15:46,400 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2191 transitions. [2021-11-13 18:15:46,402 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:46,402 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2191 transitions. [2021-11-13 18:15:46,405 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2191 transitions. [2021-11-13 18:15:46,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-13 18:15:46,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4844173441734418) internal successors, (2191), 1475 states have internal predecessors, (2191), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:46,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2191 transitions. [2021-11-13 18:15:46,479 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2191 transitions. [2021-11-13 18:15:46,479 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2191 transitions. [2021-11-13 18:15:46,480 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-13 18:15:46,480 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2191 transitions. [2021-11-13 18:15:46,495 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:46,495 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:46,495 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:46,504 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:46,504 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:46,504 INFO L791 eck$LassoCheckResult]: Stem: 10014#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 10015#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10024#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10025#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9790#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 9791#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9660#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9572#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9295#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8930#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8931#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8979#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8980#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9908#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9909#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9947#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9395#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9396#L1090 assume !(0 == ~M_E~0); 9438#L1090-2 assume !(0 == ~T1_E~0); 9439#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10085#L1100-1 assume !(0 == ~T3_E~0); 10086#L1105-1 assume !(0 == ~T4_E~0); 9214#L1110-1 assume !(0 == ~T5_E~0); 9215#L1115-1 assume !(0 == ~T6_E~0); 9610#L1120-1 assume !(0 == ~T7_E~0); 9887#L1125-1 assume !(0 == ~T8_E~0); 10356#L1130-1 assume !(0 == ~T9_E~0); 10105#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9400#L1140-1 assume !(0 == ~T11_E~0); 9401#L1145-1 assume !(0 == ~E_1~0); 10039#L1150-1 assume !(0 == ~E_2~0); 9585#L1155-1 assume !(0 == ~E_3~0); 9586#L1160-1 assume !(0 == ~E_4~0); 9668#L1165-1 assume !(0 == ~E_5~0); 9669#L1170-1 assume !(0 == ~E_6~0); 10277#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9746#L1180-1 assume !(0 == ~E_8~0); 9747#L1185-1 assume !(0 == ~E_9~0); 9397#L1190-1 assume !(0 == ~E_10~0); 9398#L1195-1 assume !(0 == ~E_11~0); 9760#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9607#L525 assume !(1 == ~m_pc~0); 9018#L525-2 is_master_triggered_~__retres1~0#1 := 0; 9019#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9764#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9765#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9384#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9385#L544 assume 1 == ~t1_pc~0; 9645#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9609#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10037#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9235#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 9236#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9858#L563 assume !(1 == ~t2_pc~0); 10026#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9039#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9040#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9468#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 9469#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9931#L582 assume 1 == ~t3_pc~0; 9179#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9180#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10328#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10286#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 9113#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9114#L601 assume !(1 == ~t4_pc~0); 10054#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9611#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9612#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10048#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 10049#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10320#L620 assume 1 == ~t5_pc~0; 9070#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9071#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9883#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9884#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 10335#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10336#L639 assume !(1 == ~t6_pc~0); 9885#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9508#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9509#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10289#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 9619#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9620#L658 assume 1 == ~t7_pc~0; 9886#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9813#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9918#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9919#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 9391#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9392#L677 assume 1 == ~t8_pc~0; 9624#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9194#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9195#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9465#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 9466#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10144#L696 assume !(1 == ~t9_pc~0); 9871#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9872#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9959#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9891#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9892#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10089#L715 assume 1 == ~t10_pc~0; 10093#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 9976#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9861#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9862#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 9738#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9188#L734 assume !(1 == ~t11_pc~0); 9189#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 9672#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9751#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8920#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 8921#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9946#L1213 assume !(1 == ~M_E~0); 9736#L1213-2 assume !(1 == ~T1_E~0); 9737#L1218-1 assume !(1 == ~T2_E~0); 8955#L1223-1 assume !(1 == ~T3_E~0); 8956#L1228-1 assume !(1 == ~T4_E~0); 9715#L1233-1 assume !(1 == ~T5_E~0); 10337#L1238-1 assume !(1 == ~T6_E~0); 10046#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10047#L1248-1 assume !(1 == ~T8_E~0); 10091#L1253-1 assume !(1 == ~T9_E~0); 10092#L1258-1 assume !(1 == ~T10_E~0); 10070#L1263-1 assume !(1 == ~T11_E~0); 10071#L1268-1 assume !(1 == ~E_1~0); 9906#L1273-1 assume !(1 == ~E_2~0); 9907#L1278-1 assume !(1 == ~E_3~0); 9506#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9507#L1288-1 assume !(1 == ~E_5~0); 10184#L1293-1 assume !(1 == ~E_6~0); 10148#L1298-1 assume !(1 == ~E_7~0); 9934#L1303-1 assume !(1 == ~E_8~0); 9517#L1308-1 assume !(1 == ~E_9~0); 9406#L1313-1 assume !(1 == ~E_10~0); 9407#L1318-1 assume !(1 == ~E_11~0); 9419#L1323-1 assume { :end_inline_reset_delta_events } true; 9420#L1644-2 [2021-11-13 18:15:46,505 INFO L793 eck$LassoCheckResult]: Loop: 9420#L1644-2 assume !false; 9987#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9988#L1065 assume !false; 10063#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10333#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9037#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10249#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 9522#L906 assume !(0 != eval_~tmp~0#1); 9524#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10061#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10062#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10201#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10253#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10216#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10217#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9290#L1110-3 assume !(0 == ~T5_E~0); 9291#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9573#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9574#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10044#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10298#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9498#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8993#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8994#L1150-3 assume !(0 == ~E_2~0); 9116#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9117#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9477#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9478#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9850#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9387#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9146#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9147#L1190-3 assume !(0 == ~E_10~0); 10292#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10293#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9700#L525-36 assume !(1 == ~m_pc~0); 9701#L525-38 is_master_triggered_~__retres1~0#1 := 0; 9251#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9252#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9533#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9534#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9441#L544-36 assume 1 == ~t1_pc~0; 9442#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9965#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9336#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9337#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10275#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10177#L563-36 assume 1 == ~t2_pc~0; 9233#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8989#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8990#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10052#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9713#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9714#L582-36 assume 1 == ~t3_pc~0; 9564#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9565#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9789#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9956#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9750#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9691#L601-36 assume 1 == ~t4_pc~0; 9593#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9594#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10341#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10259#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10260#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10163#L620-36 assume 1 == ~t5_pc~0; 9633#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9634#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10027#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9621#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9255#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9033#L639-36 assume 1 == ~t6_pc~0; 9034#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9068#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9069#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9311#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9312#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9890#L658-36 assume !(1 == ~t7_pc~0); 9044#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 9045#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10244#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9020#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 9021#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10011#L677-36 assume !(1 == ~t8_pc~0); 9815#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 9816#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9932#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10316#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9838#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9839#L696-36 assume 1 == ~t9_pc~0; 9732#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9734#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9090#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9091#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9851#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9852#L715-36 assume 1 == ~t10_pc~0; 9985#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8918#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8919#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8894#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8895#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9299#L734-36 assume 1 == ~t11_pc~0; 9300#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8999#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9321#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8912#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8913#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9912#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9579#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9580#L1218-3 assume !(1 == ~T2_E~0); 9350#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9351#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9540#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9541#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9785#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9786#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10257#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10262#L1258-3 assume !(1 == ~T10_E~0); 9330#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9331#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10228#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10246#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10248#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9664#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9665#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9530#L1298-3 assume !(1 == ~E_7~0); 9531#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9986#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9527#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9528#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9332#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9333#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9274#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9685#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 10124#L1663 assume !(0 == start_simulation_~tmp~3#1); 9162#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9888#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9111#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9807#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 9052#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9053#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9394#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 10313#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 9420#L1644-2 [2021-11-13 18:15:46,507 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:46,507 INFO L85 PathProgramCache]: Analyzing trace with hash 88517158, now seen corresponding path program 1 times [2021-11-13 18:15:46,507 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:46,508 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522446418] [2021-11-13 18:15:46,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:46,508 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:46,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:46,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:46,558 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:46,559 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [522446418] [2021-11-13 18:15:46,560 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [522446418] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:46,560 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:46,560 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:46,560 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1067797767] [2021-11-13 18:15:46,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:46,562 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:46,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:46,566 INFO L85 PathProgramCache]: Analyzing trace with hash 869462766, now seen corresponding path program 1 times [2021-11-13 18:15:46,566 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:46,570 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2018483531] [2021-11-13 18:15:46,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:46,571 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:46,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:46,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:46,643 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:46,644 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2018483531] [2021-11-13 18:15:46,650 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2018483531] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:46,651 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:46,651 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:46,651 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1014991966] [2021-11-13 18:15:46,651 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:46,652 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:46,652 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:46,653 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:15:46,653 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:15:46,654 INFO L87 Difference]: Start difference. First operand 1476 states and 2191 transitions. cyclomatic complexity: 716 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:46,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:46,694 INFO L93 Difference]: Finished difference Result 1476 states and 2190 transitions. [2021-11-13 18:15:46,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:15:46,695 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2190 transitions. [2021-11-13 18:15:46,708 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:46,720 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2190 transitions. [2021-11-13 18:15:46,720 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-13 18:15:46,722 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-13 18:15:46,722 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2190 transitions. [2021-11-13 18:15:46,726 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:46,726 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2190 transitions. [2021-11-13 18:15:46,729 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2190 transitions. [2021-11-13 18:15:46,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-13 18:15:46,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.483739837398374) internal successors, (2190), 1475 states have internal predecessors, (2190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:46,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2190 transitions. [2021-11-13 18:15:46,761 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2190 transitions. [2021-11-13 18:15:46,761 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2190 transitions. [2021-11-13 18:15:46,761 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-13 18:15:46,761 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2190 transitions. [2021-11-13 18:15:46,771 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:46,771 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:46,772 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:46,774 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:46,774 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:46,775 INFO L791 eck$LassoCheckResult]: Stem: 12973#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 12974#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 12981#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12982#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12749#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 12750#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12619#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12531#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12254#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11889#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11890#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11938#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11939#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12867#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12868#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12906#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12354#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12355#L1090 assume !(0 == ~M_E~0); 12397#L1090-2 assume !(0 == ~T1_E~0); 12398#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13043#L1100-1 assume !(0 == ~T3_E~0); 13044#L1105-1 assume !(0 == ~T4_E~0); 12172#L1110-1 assume !(0 == ~T5_E~0); 12173#L1115-1 assume !(0 == ~T6_E~0); 12569#L1120-1 assume !(0 == ~T7_E~0); 12846#L1125-1 assume !(0 == ~T8_E~0); 13315#L1130-1 assume !(0 == ~T9_E~0); 13064#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12359#L1140-1 assume !(0 == ~T11_E~0); 12360#L1145-1 assume !(0 == ~E_1~0); 12998#L1150-1 assume !(0 == ~E_2~0); 12544#L1155-1 assume !(0 == ~E_3~0); 12545#L1160-1 assume !(0 == ~E_4~0); 12627#L1165-1 assume !(0 == ~E_5~0); 12628#L1170-1 assume !(0 == ~E_6~0); 13236#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 12705#L1180-1 assume !(0 == ~E_8~0); 12706#L1185-1 assume !(0 == ~E_9~0); 12356#L1190-1 assume !(0 == ~E_10~0); 12357#L1195-1 assume !(0 == ~E_11~0); 12719#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12559#L525 assume !(1 == ~m_pc~0); 11977#L525-2 is_master_triggered_~__retres1~0#1 := 0; 11978#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12723#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12724#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12343#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12344#L544 assume 1 == ~t1_pc~0; 12604#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12568#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12996#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12194#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 12195#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12817#L563 assume !(1 == ~t2_pc~0); 12983#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11998#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11999#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12427#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 12428#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12890#L582 assume 1 == ~t3_pc~0; 12136#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12137#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13287#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13245#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 12072#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12073#L601 assume !(1 == ~t4_pc~0); 13013#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12570#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12571#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13007#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 13008#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13279#L620 assume 1 == ~t5_pc~0; 12027#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12028#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12842#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12843#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 13294#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13295#L639 assume !(1 == ~t6_pc~0); 12844#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12467#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12468#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13248#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 12578#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12579#L658 assume 1 == ~t7_pc~0; 12845#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12770#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12877#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12878#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 12350#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12351#L677 assume 1 == ~t8_pc~0; 12581#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12153#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12154#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12424#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 12425#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13103#L696 assume !(1 == ~t9_pc~0); 12828#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 12829#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12918#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12850#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12851#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13048#L715 assume 1 == ~t10_pc~0; 13052#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12935#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12820#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12821#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 12697#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12145#L734 assume !(1 == ~t11_pc~0); 12146#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 12631#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12710#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11877#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 11878#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12905#L1213 assume !(1 == ~M_E~0); 12694#L1213-2 assume !(1 == ~T1_E~0); 12695#L1218-1 assume !(1 == ~T2_E~0); 11914#L1223-1 assume !(1 == ~T3_E~0); 11915#L1228-1 assume !(1 == ~T4_E~0); 12674#L1233-1 assume !(1 == ~T5_E~0); 13296#L1238-1 assume !(1 == ~T6_E~0); 13005#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13006#L1248-1 assume !(1 == ~T8_E~0); 13050#L1253-1 assume !(1 == ~T9_E~0); 13051#L1258-1 assume !(1 == ~T10_E~0); 13029#L1263-1 assume !(1 == ~T11_E~0); 13030#L1268-1 assume !(1 == ~E_1~0); 12865#L1273-1 assume !(1 == ~E_2~0); 12866#L1278-1 assume !(1 == ~E_3~0); 12465#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12466#L1288-1 assume !(1 == ~E_5~0); 13143#L1293-1 assume !(1 == ~E_6~0); 13107#L1298-1 assume !(1 == ~E_7~0); 12893#L1303-1 assume !(1 == ~E_8~0); 12476#L1308-1 assume !(1 == ~E_9~0); 12365#L1313-1 assume !(1 == ~E_10~0); 12366#L1318-1 assume !(1 == ~E_11~0); 12375#L1323-1 assume { :end_inline_reset_delta_events } true; 12376#L1644-2 [2021-11-13 18:15:46,775 INFO L793 eck$LassoCheckResult]: Loop: 12376#L1644-2 assume !false; 12946#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12947#L1065 assume !false; 13022#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13292#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 11996#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13208#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 12481#L906 assume !(0 != eval_~tmp~0#1); 12483#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13019#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13020#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13160#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13212#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13175#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13176#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12249#L1110-3 assume !(0 == ~T5_E~0); 12250#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12532#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12533#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13003#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13257#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12455#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11950#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11951#L1150-3 assume !(0 == ~E_2~0); 12074#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12075#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12436#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12437#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12809#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12346#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12104#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12105#L1190-3 assume !(0 == ~E_10~0); 13251#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13252#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12659#L525-36 assume !(1 == ~m_pc~0); 12660#L525-38 is_master_triggered_~__retres1~0#1 := 0; 12205#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12206#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12491#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12492#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12400#L544-36 assume 1 == ~t1_pc~0; 12401#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12924#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12289#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12290#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13233#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13136#L563-36 assume 1 == ~t2_pc~0; 12192#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11948#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11949#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13011#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12672#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12673#L582-36 assume 1 == ~t3_pc~0; 12523#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12524#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12748#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12915#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12709#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12653#L601-36 assume 1 == ~t4_pc~0; 12552#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12553#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13300#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13218#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13219#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13124#L620-36 assume 1 == ~t5_pc~0; 12594#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12595#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12986#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12580#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12214#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11992#L639-36 assume 1 == ~t6_pc~0; 11993#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12032#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12033#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12272#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12273#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12849#L658-36 assume !(1 == ~t7_pc~0); 12003#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 12004#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13203#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11979#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 11980#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12970#L677-36 assume !(1 == ~t8_pc~0); 12774#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 12775#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12891#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13275#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12797#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12798#L696-36 assume 1 == ~t9_pc~0; 12691#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12693#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12052#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12053#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12810#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12811#L715-36 assume 1 == ~t10_pc~0; 12944#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11879#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11880#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11853#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11854#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12258#L734-36 assume 1 == ~t11_pc~0; 12259#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11958#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12280#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11871#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11872#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12871#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12540#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12541#L1218-3 assume !(1 == ~T2_E~0); 12309#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12310#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12499#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12500#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12744#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12745#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13217#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13222#L1258-3 assume !(1 == ~T10_E~0); 12291#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12292#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13187#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13205#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13207#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12623#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12624#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12489#L1298-3 assume !(1 == ~E_7~0); 12490#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12945#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12486#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12487#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12293#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12294#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12233#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12644#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 13083#L1663 assume !(0 == start_simulation_~tmp~3#1); 12126#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12847#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12070#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12768#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 12014#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12015#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12353#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 13272#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 12376#L1644-2 [2021-11-13 18:15:46,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:46,776 INFO L85 PathProgramCache]: Analyzing trace with hash -586642968, now seen corresponding path program 1 times [2021-11-13 18:15:46,777 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:46,777 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156119646] [2021-11-13 18:15:46,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:46,777 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:46,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:46,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:46,824 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:46,824 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1156119646] [2021-11-13 18:15:46,825 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1156119646] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:46,825 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:46,825 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:46,825 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [883669295] [2021-11-13 18:15:46,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:46,826 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:46,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:46,827 INFO L85 PathProgramCache]: Analyzing trace with hash 869462766, now seen corresponding path program 2 times [2021-11-13 18:15:46,827 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:46,827 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899474976] [2021-11-13 18:15:46,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:46,827 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:46,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:46,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:46,875 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:46,875 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [899474976] [2021-11-13 18:15:46,875 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [899474976] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:46,875 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:46,875 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:46,876 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [880976221] [2021-11-13 18:15:46,876 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:46,876 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:46,877 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:46,877 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:15:46,877 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:15:46,877 INFO L87 Difference]: Start difference. First operand 1476 states and 2190 transitions. cyclomatic complexity: 715 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:46,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:46,917 INFO L93 Difference]: Finished difference Result 1476 states and 2189 transitions. [2021-11-13 18:15:46,917 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:15:46,920 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2189 transitions. [2021-11-13 18:15:46,952 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:46,965 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2189 transitions. [2021-11-13 18:15:46,965 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-13 18:15:46,967 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-13 18:15:46,968 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2189 transitions. [2021-11-13 18:15:46,970 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:46,971 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2189 transitions. [2021-11-13 18:15:46,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2189 transitions. [2021-11-13 18:15:47,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-13 18:15:47,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4830623306233062) internal successors, (2189), 1475 states have internal predecessors, (2189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:47,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2189 transitions. [2021-11-13 18:15:47,010 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2189 transitions. [2021-11-13 18:15:47,010 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2189 transitions. [2021-11-13 18:15:47,011 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-13 18:15:47,011 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2189 transitions. [2021-11-13 18:15:47,022 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:47,022 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:47,022 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:47,025 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:47,025 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:47,026 INFO L791 eck$LassoCheckResult]: Stem: 15932#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 15933#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 15942#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15943#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15708#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 15709#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15578#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15490#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15213#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14848#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 14849#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14897#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14898#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15826#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15827#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15865#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15313#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15314#L1090 assume !(0 == ~M_E~0); 15356#L1090-2 assume !(0 == ~T1_E~0); 15357#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16003#L1100-1 assume !(0 == ~T3_E~0); 16004#L1105-1 assume !(0 == ~T4_E~0); 15132#L1110-1 assume !(0 == ~T5_E~0); 15133#L1115-1 assume !(0 == ~T6_E~0); 15528#L1120-1 assume !(0 == ~T7_E~0); 15805#L1125-1 assume !(0 == ~T8_E~0); 16274#L1130-1 assume !(0 == ~T9_E~0); 16023#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15318#L1140-1 assume !(0 == ~T11_E~0); 15319#L1145-1 assume !(0 == ~E_1~0); 15957#L1150-1 assume !(0 == ~E_2~0); 15503#L1155-1 assume !(0 == ~E_3~0); 15504#L1160-1 assume !(0 == ~E_4~0); 15586#L1165-1 assume !(0 == ~E_5~0); 15587#L1170-1 assume !(0 == ~E_6~0); 16195#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 15664#L1180-1 assume !(0 == ~E_8~0); 15665#L1185-1 assume !(0 == ~E_9~0); 15315#L1190-1 assume !(0 == ~E_10~0); 15316#L1195-1 assume !(0 == ~E_11~0); 15678#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15525#L525 assume !(1 == ~m_pc~0); 14936#L525-2 is_master_triggered_~__retres1~0#1 := 0; 14937#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15682#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15683#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15302#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15303#L544 assume 1 == ~t1_pc~0; 15563#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15527#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15955#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15153#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 15154#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15776#L563 assume !(1 == ~t2_pc~0); 15944#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14957#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14958#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15386#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 15387#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15849#L582 assume 1 == ~t3_pc~0; 15097#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15098#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16246#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16204#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 15031#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15032#L601 assume !(1 == ~t4_pc~0); 15972#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15529#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15530#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15966#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 15967#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16238#L620 assume 1 == ~t5_pc~0; 14988#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14989#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15801#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15802#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 16253#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16254#L639 assume !(1 == ~t6_pc~0); 15803#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15426#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15427#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16207#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 15537#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15538#L658 assume 1 == ~t7_pc~0; 15804#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15729#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15836#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15837#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 15309#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15310#L677 assume 1 == ~t8_pc~0; 15540#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15112#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15113#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15383#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 15384#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16062#L696 assume !(1 == ~t9_pc~0); 15789#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 15790#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15877#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 15809#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15810#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16007#L715 assume 1 == ~t10_pc~0; 16011#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15894#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15779#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15780#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 15656#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15106#L734 assume !(1 == ~t11_pc~0); 15107#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 15590#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15669#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14838#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 14839#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15864#L1213 assume !(1 == ~M_E~0); 15654#L1213-2 assume !(1 == ~T1_E~0); 15655#L1218-1 assume !(1 == ~T2_E~0); 14873#L1223-1 assume !(1 == ~T3_E~0); 14874#L1228-1 assume !(1 == ~T4_E~0); 15633#L1233-1 assume !(1 == ~T5_E~0); 16255#L1238-1 assume !(1 == ~T6_E~0); 15964#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15965#L1248-1 assume !(1 == ~T8_E~0); 16009#L1253-1 assume !(1 == ~T9_E~0); 16010#L1258-1 assume !(1 == ~T10_E~0); 15988#L1263-1 assume !(1 == ~T11_E~0); 15989#L1268-1 assume !(1 == ~E_1~0); 15824#L1273-1 assume !(1 == ~E_2~0); 15825#L1278-1 assume !(1 == ~E_3~0); 15424#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15425#L1288-1 assume !(1 == ~E_5~0); 16102#L1293-1 assume !(1 == ~E_6~0); 16066#L1298-1 assume !(1 == ~E_7~0); 15852#L1303-1 assume !(1 == ~E_8~0); 15435#L1308-1 assume !(1 == ~E_9~0); 15324#L1313-1 assume !(1 == ~E_10~0); 15325#L1318-1 assume !(1 == ~E_11~0); 15337#L1323-1 assume { :end_inline_reset_delta_events } true; 15338#L1644-2 [2021-11-13 18:15:47,027 INFO L793 eck$LassoCheckResult]: Loop: 15338#L1644-2 assume !false; 15905#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15906#L1065 assume !false; 15981#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16251#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 14955#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16167#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 15440#L906 assume !(0 != eval_~tmp~0#1); 15442#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15978#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15979#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16119#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16171#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16134#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16135#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15208#L1110-3 assume !(0 == ~T5_E~0); 15209#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15491#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15492#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15962#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16216#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15414#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14911#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14912#L1150-3 assume !(0 == ~E_2~0); 15034#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15035#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15395#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15396#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15768#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15305#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15064#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15065#L1190-3 assume !(0 == ~E_10~0); 16210#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16211#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15618#L525-36 assume !(1 == ~m_pc~0); 15619#L525-38 is_master_triggered_~__retres1~0#1 := 0; 15169#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15170#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15451#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15452#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15359#L544-36 assume 1 == ~t1_pc~0; 15360#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15883#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15254#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15255#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16193#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16095#L563-36 assume !(1 == ~t2_pc~0); 15152#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 14907#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14908#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15970#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15631#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15632#L582-36 assume 1 == ~t3_pc~0; 15482#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15483#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15707#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15874#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15668#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15612#L601-36 assume 1 == ~t4_pc~0; 15511#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15512#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16259#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16177#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16178#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16083#L620-36 assume 1 == ~t5_pc~0; 15554#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15555#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15947#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15539#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15173#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14948#L639-36 assume 1 == ~t6_pc~0; 14949#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14986#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14987#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15227#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15228#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15808#L658-36 assume 1 == ~t7_pc~0; 15068#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14960#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16162#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14938#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 14939#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15929#L677-36 assume !(1 == ~t8_pc~0); 15732#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 15733#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15850#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16234#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15756#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15757#L696-36 assume 1 == ~t9_pc~0; 15650#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15652#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15008#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 15009#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15769#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15770#L715-36 assume !(1 == ~t10_pc~0); 15740#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 14836#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14837#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14812#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14813#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15217#L734-36 assume 1 == ~t11_pc~0; 15218#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14917#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15239#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14830#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14831#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15830#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15497#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15498#L1218-3 assume !(1 == ~T2_E~0); 15268#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15269#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15458#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15459#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15703#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15704#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16175#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16180#L1258-3 assume !(1 == ~T10_E~0); 15248#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15249#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16146#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16164#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16166#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15582#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15583#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15447#L1298-3 assume !(1 == ~E_7~0); 15448#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15904#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15445#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15446#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 15250#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15251#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15192#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15603#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 16042#L1663 assume !(0 == start_simulation_~tmp~3#1); 15078#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15806#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15029#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15725#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 14970#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14971#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15312#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 16231#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 15338#L1644-2 [2021-11-13 18:15:47,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:47,028 INFO L85 PathProgramCache]: Analyzing trace with hash 361408998, now seen corresponding path program 1 times [2021-11-13 18:15:47,028 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:47,029 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [34625136] [2021-11-13 18:15:47,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:47,029 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:47,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:47,068 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:47,068 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:47,069 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [34625136] [2021-11-13 18:15:47,069 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [34625136] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:47,069 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:47,069 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:47,070 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [967571059] [2021-11-13 18:15:47,070 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:47,070 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:47,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:47,071 INFO L85 PathProgramCache]: Analyzing trace with hash -459098803, now seen corresponding path program 1 times [2021-11-13 18:15:47,071 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:47,076 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221053111] [2021-11-13 18:15:47,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:47,077 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:47,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:47,126 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:47,126 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:47,127 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221053111] [2021-11-13 18:15:47,127 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1221053111] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:47,127 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:47,127 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:47,129 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2099834691] [2021-11-13 18:15:47,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:47,130 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:47,130 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:47,131 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:15:47,131 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:15:47,131 INFO L87 Difference]: Start difference. First operand 1476 states and 2189 transitions. cyclomatic complexity: 714 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:47,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:47,177 INFO L93 Difference]: Finished difference Result 1476 states and 2188 transitions. [2021-11-13 18:15:47,177 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:15:47,179 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2188 transitions. [2021-11-13 18:15:47,195 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:47,208 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2188 transitions. [2021-11-13 18:15:47,209 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-13 18:15:47,210 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-13 18:15:47,211 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2188 transitions. [2021-11-13 18:15:47,213 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:47,213 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2188 transitions. [2021-11-13 18:15:47,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2188 transitions. [2021-11-13 18:15:47,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-13 18:15:47,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4823848238482384) internal successors, (2188), 1475 states have internal predecessors, (2188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:47,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2188 transitions. [2021-11-13 18:15:47,256 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2188 transitions. [2021-11-13 18:15:47,256 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2188 transitions. [2021-11-13 18:15:47,256 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-13 18:15:47,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2188 transitions. [2021-11-13 18:15:47,267 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:47,267 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:47,267 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:47,270 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:47,271 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:47,271 INFO L791 eck$LassoCheckResult]: Stem: 18891#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 18892#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 18901#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18902#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18667#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 18668#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18537#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18449#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18172#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17807#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17808#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17856#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17857#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18787#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18788#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18831#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 18272#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18273#L1090 assume !(0 == ~M_E~0); 18319#L1090-2 assume !(0 == ~T1_E~0); 18320#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18962#L1100-1 assume !(0 == ~T3_E~0); 18963#L1105-1 assume !(0 == ~T4_E~0); 18091#L1110-1 assume !(0 == ~T5_E~0); 18092#L1115-1 assume !(0 == ~T6_E~0); 18490#L1120-1 assume !(0 == ~T7_E~0); 18764#L1125-1 assume !(0 == ~T8_E~0); 19233#L1130-1 assume !(0 == ~T9_E~0); 18982#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18279#L1140-1 assume !(0 == ~T11_E~0); 18280#L1145-1 assume !(0 == ~E_1~0); 18916#L1150-1 assume !(0 == ~E_2~0); 18462#L1155-1 assume !(0 == ~E_3~0); 18463#L1160-1 assume !(0 == ~E_4~0); 18545#L1165-1 assume !(0 == ~E_5~0); 18546#L1170-1 assume !(0 == ~E_6~0); 19154#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 18623#L1180-1 assume !(0 == ~E_8~0); 18624#L1185-1 assume !(0 == ~E_9~0); 18274#L1190-1 assume !(0 == ~E_10~0); 18275#L1195-1 assume !(0 == ~E_11~0); 18637#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18484#L525 assume !(1 == ~m_pc~0); 17895#L525-2 is_master_triggered_~__retres1~0#1 := 0; 17896#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18641#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18642#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18262#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18263#L544 assume 1 == ~t1_pc~0; 18522#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18486#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18914#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18112#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 18113#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18735#L563 assume !(1 == ~t2_pc~0); 18903#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17916#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17917#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18348#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 18349#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18808#L582 assume 1 == ~t3_pc~0; 18056#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18057#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19205#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19164#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 17990#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17991#L601 assume !(1 == ~t4_pc~0); 18931#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18491#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18492#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18925#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 18926#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19197#L620 assume 1 == ~t5_pc~0; 17949#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17950#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18761#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18762#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 19212#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19213#L639 assume !(1 == ~t6_pc~0); 18763#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 18385#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18386#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19166#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 18496#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18497#L658 assume 1 == ~t7_pc~0; 18760#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18688#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18795#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18796#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 18268#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18269#L677 assume 1 == ~t8_pc~0; 18499#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18071#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18072#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18342#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 18343#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19021#L696 assume !(1 == ~t9_pc~0); 18746#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 18747#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18836#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18768#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18769#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18966#L715 assume 1 == ~t10_pc~0; 18970#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18853#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18738#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18739#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 18615#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18063#L734 assume !(1 == ~t11_pc~0); 18064#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 18549#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18628#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17795#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 17796#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18823#L1213 assume !(1 == ~M_E~0); 18612#L1213-2 assume !(1 == ~T1_E~0); 18613#L1218-1 assume !(1 == ~T2_E~0); 17832#L1223-1 assume !(1 == ~T3_E~0); 17833#L1228-1 assume !(1 == ~T4_E~0); 18592#L1233-1 assume !(1 == ~T5_E~0); 19214#L1238-1 assume !(1 == ~T6_E~0); 18923#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18924#L1248-1 assume !(1 == ~T8_E~0); 18968#L1253-1 assume !(1 == ~T9_E~0); 18969#L1258-1 assume !(1 == ~T10_E~0); 18947#L1263-1 assume !(1 == ~T11_E~0); 18948#L1268-1 assume !(1 == ~E_1~0); 18783#L1273-1 assume !(1 == ~E_2~0); 18784#L1278-1 assume !(1 == ~E_3~0); 18383#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18384#L1288-1 assume !(1 == ~E_5~0); 19061#L1293-1 assume !(1 == ~E_6~0); 19025#L1298-1 assume !(1 == ~E_7~0); 18811#L1303-1 assume !(1 == ~E_8~0); 18394#L1308-1 assume !(1 == ~E_9~0); 18283#L1313-1 assume !(1 == ~E_10~0); 18284#L1318-1 assume !(1 == ~E_11~0); 18293#L1323-1 assume { :end_inline_reset_delta_events } true; 18294#L1644-2 [2021-11-13 18:15:47,272 INFO L793 eck$LassoCheckResult]: Loop: 18294#L1644-2 assume !false; 18864#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18865#L1065 assume !false; 18940#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19210#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 17914#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19126#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 18399#L906 assume !(0 != eval_~tmp~0#1); 18401#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18937#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18938#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19078#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19130#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19093#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19094#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18167#L1110-3 assume !(0 == ~T5_E~0); 18168#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18450#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18451#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18921#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19175#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18373#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17868#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17869#L1150-3 assume !(0 == ~E_2~0); 17992#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17993#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18354#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18355#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18727#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18264#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18022#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18023#L1190-3 assume !(0 == ~E_10~0); 19169#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19170#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18577#L525-36 assume !(1 == ~m_pc~0); 18578#L525-38 is_master_triggered_~__retres1~0#1 := 0; 18123#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18124#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18409#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18410#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18316#L544-36 assume 1 == ~t1_pc~0; 18317#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18842#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18207#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18208#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19151#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19054#L563-36 assume 1 == ~t2_pc~0; 18110#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17866#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17867#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18929#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18590#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18591#L582-36 assume 1 == ~t3_pc~0; 18441#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18442#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18666#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18833#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18627#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18571#L601-36 assume 1 == ~t4_pc~0; 18470#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18471#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19218#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19136#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19137#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19042#L620-36 assume 1 == ~t5_pc~0; 18512#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18513#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18904#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18498#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18132#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17910#L639-36 assume 1 == ~t6_pc~0; 17911#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17947#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17948#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18190#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18191#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18767#L658-36 assume !(1 == ~t7_pc~0); 17921#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 17922#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19121#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17897#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 17898#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18888#L677-36 assume !(1 == ~t8_pc~0); 18692#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 18693#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18809#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19193#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18715#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18716#L696-36 assume 1 == ~t9_pc~0; 18609#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18611#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17970#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17971#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18728#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18729#L715-36 assume !(1 == ~t10_pc~0); 18699#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 17797#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17798#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17771#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17772#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18176#L734-36 assume 1 == ~t11_pc~0; 18177#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17876#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18198#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17789#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17790#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18789#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18458#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18459#L1218-3 assume !(1 == ~T2_E~0); 18227#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18228#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18417#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18418#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18662#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18663#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19135#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19140#L1258-3 assume !(1 == ~T10_E~0); 18209#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18210#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19105#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19123#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19125#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18541#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18542#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18407#L1298-3 assume !(1 == ~E_7~0); 18408#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18863#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18404#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18405#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 18211#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 18212#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 18151#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18562#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 19001#L1663 assume !(0 == start_simulation_~tmp~3#1); 18044#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 18765#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 17988#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18686#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 17932#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17933#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18271#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 19190#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 18294#L1644-2 [2021-11-13 18:15:47,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:47,273 INFO L85 PathProgramCache]: Analyzing trace with hash 946180648, now seen corresponding path program 1 times [2021-11-13 18:15:47,274 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:47,274 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1977653397] [2021-11-13 18:15:47,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:47,274 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:47,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:47,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:47,308 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:47,309 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1977653397] [2021-11-13 18:15:47,309 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1977653397] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:47,309 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:47,309 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:47,309 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [491449584] [2021-11-13 18:15:47,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:47,310 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:47,310 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:47,311 INFO L85 PathProgramCache]: Analyzing trace with hash -1992669811, now seen corresponding path program 1 times [2021-11-13 18:15:47,311 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:47,311 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1844977579] [2021-11-13 18:15:47,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:47,311 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:47,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:47,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:47,389 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:47,389 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1844977579] [2021-11-13 18:15:47,389 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1844977579] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:47,390 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:47,390 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:47,390 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1348673688] [2021-11-13 18:15:47,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:47,391 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:47,391 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:47,391 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:15:47,391 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:15:47,391 INFO L87 Difference]: Start difference. First operand 1476 states and 2188 transitions. cyclomatic complexity: 713 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:47,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:47,437 INFO L93 Difference]: Finished difference Result 1476 states and 2187 transitions. [2021-11-13 18:15:47,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:15:47,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2187 transitions. [2021-11-13 18:15:47,451 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:47,464 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2187 transitions. [2021-11-13 18:15:47,464 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-13 18:15:47,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-13 18:15:47,466 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2187 transitions. [2021-11-13 18:15:47,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:47,469 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2187 transitions. [2021-11-13 18:15:47,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2187 transitions. [2021-11-13 18:15:47,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-13 18:15:47,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4817073170731707) internal successors, (2187), 1475 states have internal predecessors, (2187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:47,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2187 transitions. [2021-11-13 18:15:47,504 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2187 transitions. [2021-11-13 18:15:47,505 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2187 transitions. [2021-11-13 18:15:47,505 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-13 18:15:47,505 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2187 transitions. [2021-11-13 18:15:47,512 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:47,512 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:47,512 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:47,515 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:47,515 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:47,515 INFO L791 eck$LassoCheckResult]: Stem: 21850#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 21851#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 21858#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21859#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21626#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 21627#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21496#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21408#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21131#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20766#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20767#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20815#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20816#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21744#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21745#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21783#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21231#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21232#L1090 assume !(0 == ~M_E~0); 21274#L1090-2 assume !(0 == ~T1_E~0); 21275#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21920#L1100-1 assume !(0 == ~T3_E~0); 21921#L1105-1 assume !(0 == ~T4_E~0); 21049#L1110-1 assume !(0 == ~T5_E~0); 21050#L1115-1 assume !(0 == ~T6_E~0); 21446#L1120-1 assume !(0 == ~T7_E~0); 21723#L1125-1 assume !(0 == ~T8_E~0); 22192#L1130-1 assume !(0 == ~T9_E~0); 21941#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21236#L1140-1 assume !(0 == ~T11_E~0); 21237#L1145-1 assume !(0 == ~E_1~0); 21875#L1150-1 assume !(0 == ~E_2~0); 21421#L1155-1 assume !(0 == ~E_3~0); 21422#L1160-1 assume !(0 == ~E_4~0); 21504#L1165-1 assume !(0 == ~E_5~0); 21505#L1170-1 assume !(0 == ~E_6~0); 22113#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 21582#L1180-1 assume !(0 == ~E_8~0); 21583#L1185-1 assume !(0 == ~E_9~0); 21233#L1190-1 assume !(0 == ~E_10~0); 21234#L1195-1 assume !(0 == ~E_11~0); 21596#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21438#L525 assume !(1 == ~m_pc~0); 20854#L525-2 is_master_triggered_~__retres1~0#1 := 0; 20855#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21600#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21601#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21220#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21221#L544 assume 1 == ~t1_pc~0; 21481#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21445#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21873#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21071#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 21072#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21694#L563 assume !(1 == ~t2_pc~0); 21860#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20875#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20876#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21304#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 21305#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21767#L582 assume 1 == ~t3_pc~0; 21013#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21014#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22164#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22122#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 20949#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20950#L601 assume !(1 == ~t4_pc~0); 21890#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21447#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21448#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21884#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 21885#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22156#L620 assume 1 == ~t5_pc~0; 20904#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20905#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21719#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21720#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 22171#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22172#L639 assume !(1 == ~t6_pc~0); 21721#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21344#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21345#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22125#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 21455#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21456#L658 assume 1 == ~t7_pc~0; 21722#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21647#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21754#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21755#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 21227#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21228#L677 assume 1 == ~t8_pc~0; 21458#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21030#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21031#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21301#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 21302#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21980#L696 assume !(1 == ~t9_pc~0); 21705#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21706#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21795#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21727#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21728#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21925#L715 assume 1 == ~t10_pc~0; 21929#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21812#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21697#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21698#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 21574#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21022#L734 assume !(1 == ~t11_pc~0); 21023#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 21508#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21587#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20756#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 20757#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21782#L1213 assume !(1 == ~M_E~0); 21571#L1213-2 assume !(1 == ~T1_E~0); 21572#L1218-1 assume !(1 == ~T2_E~0); 20791#L1223-1 assume !(1 == ~T3_E~0); 20792#L1228-1 assume !(1 == ~T4_E~0); 21551#L1233-1 assume !(1 == ~T5_E~0); 22173#L1238-1 assume !(1 == ~T6_E~0); 21882#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21883#L1248-1 assume !(1 == ~T8_E~0); 21927#L1253-1 assume !(1 == ~T9_E~0); 21928#L1258-1 assume !(1 == ~T10_E~0); 21906#L1263-1 assume !(1 == ~T11_E~0); 21907#L1268-1 assume !(1 == ~E_1~0); 21742#L1273-1 assume !(1 == ~E_2~0); 21743#L1278-1 assume !(1 == ~E_3~0); 21342#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21343#L1288-1 assume !(1 == ~E_5~0); 22020#L1293-1 assume !(1 == ~E_6~0); 21984#L1298-1 assume !(1 == ~E_7~0); 21770#L1303-1 assume !(1 == ~E_8~0); 21353#L1308-1 assume !(1 == ~E_9~0); 21242#L1313-1 assume !(1 == ~E_10~0); 21243#L1318-1 assume !(1 == ~E_11~0); 21252#L1323-1 assume { :end_inline_reset_delta_events } true; 21253#L1644-2 [2021-11-13 18:15:47,516 INFO L793 eck$LassoCheckResult]: Loop: 21253#L1644-2 assume !false; 21823#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21824#L1065 assume !false; 21899#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22169#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 20873#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22085#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 21358#L906 assume !(0 != eval_~tmp~0#1); 21360#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21896#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21897#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22037#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22089#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22052#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22053#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21126#L1110-3 assume !(0 == ~T5_E~0); 21127#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21409#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21410#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21880#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22134#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21332#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20827#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20828#L1150-3 assume !(0 == ~E_2~0); 20952#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20953#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21313#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21314#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21686#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21223#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20981#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20982#L1190-3 assume !(0 == ~E_10~0); 22128#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22129#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21536#L525-36 assume !(1 == ~m_pc~0); 21537#L525-38 is_master_triggered_~__retres1~0#1 := 0; 21082#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21083#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21368#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21369#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21277#L544-36 assume 1 == ~t1_pc~0; 21278#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21801#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21172#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21173#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22111#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22013#L563-36 assume 1 == ~t2_pc~0; 21069#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20825#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20826#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21888#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21549#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21550#L582-36 assume 1 == ~t3_pc~0; 21400#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21401#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21625#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21792#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21586#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21530#L601-36 assume 1 == ~t4_pc~0; 21429#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21430#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22177#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22095#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22096#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22001#L620-36 assume 1 == ~t5_pc~0; 21472#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21473#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21865#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21457#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21091#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20869#L639-36 assume 1 == ~t6_pc~0; 20870#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20909#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20910#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21149#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21150#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21726#L658-36 assume !(1 == ~t7_pc~0); 20880#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 20881#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22080#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20856#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 20857#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21847#L677-36 assume !(1 == ~t8_pc~0); 21651#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 21652#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21768#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22152#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21674#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21675#L696-36 assume 1 == ~t9_pc~0; 21568#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21570#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20926#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20927#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21687#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21688#L715-36 assume !(1 == ~t10_pc~0); 21658#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 20754#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20755#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20730#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20731#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21132#L734-36 assume !(1 == ~t11_pc~0); 20834#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 20835#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21157#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20748#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20749#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21748#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21415#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21416#L1218-3 assume !(1 == ~T2_E~0); 21186#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21187#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21376#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21377#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21621#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21622#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22093#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22098#L1258-3 assume !(1 == ~T10_E~0); 21166#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21167#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22064#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22082#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22083#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21500#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21501#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21365#L1298-3 assume !(1 == ~E_7~0); 21366#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21822#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21363#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 21364#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21168#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 21169#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 21110#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 21521#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 21960#L1663 assume !(0 == start_simulation_~tmp~3#1); 20996#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 21724#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 20947#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 21643#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 20888#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20889#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21230#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 22149#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 21253#L1644-2 [2021-11-13 18:15:47,517 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:47,517 INFO L85 PathProgramCache]: Analyzing trace with hash 1380686246, now seen corresponding path program 1 times [2021-11-13 18:15:47,521 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:47,521 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1268296623] [2021-11-13 18:15:47,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:47,522 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:47,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:47,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:47,555 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:47,555 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1268296623] [2021-11-13 18:15:47,555 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1268296623] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:47,556 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:47,557 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:47,557 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1677321442] [2021-11-13 18:15:47,557 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:47,558 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:47,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:47,558 INFO L85 PathProgramCache]: Analyzing trace with hash 146783084, now seen corresponding path program 1 times [2021-11-13 18:15:47,558 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:47,559 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1822746314] [2021-11-13 18:15:47,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:47,559 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:47,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:47,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:47,631 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:47,631 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1822746314] [2021-11-13 18:15:47,633 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1822746314] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:47,633 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:47,633 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:47,633 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1066462508] [2021-11-13 18:15:47,636 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:47,637 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:47,637 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:47,637 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:15:47,638 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:15:47,638 INFO L87 Difference]: Start difference. First operand 1476 states and 2187 transitions. cyclomatic complexity: 712 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:47,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:47,678 INFO L93 Difference]: Finished difference Result 1476 states and 2186 transitions. [2021-11-13 18:15:47,679 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:15:47,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2186 transitions. [2021-11-13 18:15:47,691 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:47,724 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2186 transitions. [2021-11-13 18:15:47,725 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-13 18:15:47,729 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-13 18:15:47,729 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2186 transitions. [2021-11-13 18:15:47,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:47,731 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2186 transitions. [2021-11-13 18:15:47,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2186 transitions. [2021-11-13 18:15:47,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-13 18:15:47,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.481029810298103) internal successors, (2186), 1475 states have internal predecessors, (2186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:47,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2186 transitions. [2021-11-13 18:15:47,765 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2186 transitions. [2021-11-13 18:15:47,765 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2186 transitions. [2021-11-13 18:15:47,765 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-13 18:15:47,765 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2186 transitions. [2021-11-13 18:15:47,772 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:47,773 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:47,773 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:47,775 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:47,775 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:47,776 INFO L791 eck$LassoCheckResult]: Stem: 24809#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 24810#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 24819#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24820#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24585#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 24586#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24455#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24367#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24090#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23725#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23726#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23774#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 23775#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24705#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24706#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24749#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24190#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24191#L1090 assume !(0 == ~M_E~0); 24237#L1090-2 assume !(0 == ~T1_E~0); 24238#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24880#L1100-1 assume !(0 == ~T3_E~0); 24881#L1105-1 assume !(0 == ~T4_E~0); 24009#L1110-1 assume !(0 == ~T5_E~0); 24010#L1115-1 assume !(0 == ~T6_E~0); 24408#L1120-1 assume !(0 == ~T7_E~0); 24682#L1125-1 assume !(0 == ~T8_E~0); 25151#L1130-1 assume !(0 == ~T9_E~0); 24900#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24197#L1140-1 assume !(0 == ~T11_E~0); 24198#L1145-1 assume !(0 == ~E_1~0); 24834#L1150-1 assume !(0 == ~E_2~0); 24380#L1155-1 assume !(0 == ~E_3~0); 24381#L1160-1 assume !(0 == ~E_4~0); 24463#L1165-1 assume !(0 == ~E_5~0); 24464#L1170-1 assume !(0 == ~E_6~0); 25072#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 24541#L1180-1 assume !(0 == ~E_8~0); 24542#L1185-1 assume !(0 == ~E_9~0); 24192#L1190-1 assume !(0 == ~E_10~0); 24193#L1195-1 assume !(0 == ~E_11~0); 24555#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24402#L525 assume !(1 == ~m_pc~0); 23813#L525-2 is_master_triggered_~__retres1~0#1 := 0; 23814#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24559#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24560#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24179#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24180#L544 assume 1 == ~t1_pc~0; 24440#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24404#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24832#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24030#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 24031#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24653#L563 assume !(1 == ~t2_pc~0); 24821#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23834#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23835#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24266#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 24267#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24726#L582 assume 1 == ~t3_pc~0; 23974#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23975#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25123#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25081#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 23908#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23909#L601 assume !(1 == ~t4_pc~0); 24849#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24409#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24410#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24843#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 24844#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25115#L620 assume 1 == ~t5_pc~0; 23867#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23868#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24678#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24679#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 25130#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25131#L639 assume !(1 == ~t6_pc~0); 24680#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24303#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24304#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25084#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 24414#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24415#L658 assume 1 == ~t7_pc~0; 24681#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24608#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24713#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24714#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 24186#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24187#L677 assume 1 == ~t8_pc~0; 24419#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23992#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23993#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24260#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 24261#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24939#L696 assume !(1 == ~t9_pc~0); 24667#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 24668#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24757#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24688#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24689#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24884#L715 assume 1 == ~t10_pc~0; 24888#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24771#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24656#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24657#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 24533#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23983#L734 assume !(1 == ~t11_pc~0); 23984#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 24467#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24546#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23715#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 23716#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24741#L1213 assume !(1 == ~M_E~0); 24531#L1213-2 assume !(1 == ~T1_E~0); 24532#L1218-1 assume !(1 == ~T2_E~0); 23750#L1223-1 assume !(1 == ~T3_E~0); 23751#L1228-1 assume !(1 == ~T4_E~0); 24510#L1233-1 assume !(1 == ~T5_E~0); 25132#L1238-1 assume !(1 == ~T6_E~0); 24841#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24842#L1248-1 assume !(1 == ~T8_E~0); 24886#L1253-1 assume !(1 == ~T9_E~0); 24887#L1258-1 assume !(1 == ~T10_E~0); 24865#L1263-1 assume !(1 == ~T11_E~0); 24866#L1268-1 assume !(1 == ~E_1~0); 24701#L1273-1 assume !(1 == ~E_2~0); 24702#L1278-1 assume !(1 == ~E_3~0); 24301#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 24302#L1288-1 assume !(1 == ~E_5~0); 24979#L1293-1 assume !(1 == ~E_6~0); 24943#L1298-1 assume !(1 == ~E_7~0); 24729#L1303-1 assume !(1 == ~E_8~0); 24312#L1308-1 assume !(1 == ~E_9~0); 24201#L1313-1 assume !(1 == ~E_10~0); 24202#L1318-1 assume !(1 == ~E_11~0); 24214#L1323-1 assume { :end_inline_reset_delta_events } true; 24215#L1644-2 [2021-11-13 18:15:47,777 INFO L793 eck$LassoCheckResult]: Loop: 24215#L1644-2 assume !false; 24782#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24783#L1065 assume !false; 24858#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25128#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 23832#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25044#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 24317#L906 assume !(0 != eval_~tmp~0#1); 24319#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24856#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24857#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24996#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25048#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25011#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25012#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24085#L1110-3 assume !(0 == ~T5_E~0); 24086#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24368#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24369#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24839#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25093#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24291#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 23786#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23787#L1150-3 assume !(0 == ~E_2~0); 23910#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23911#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24272#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24273#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24645#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24182#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23940#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23941#L1190-3 assume !(0 == ~E_10~0); 25087#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25088#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24492#L525-36 assume !(1 == ~m_pc~0); 24493#L525-38 is_master_triggered_~__retres1~0#1 := 0; 24041#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24042#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24327#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24328#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24234#L544-36 assume 1 == ~t1_pc~0; 24235#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24760#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24125#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24126#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25069#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24972#L563-36 assume 1 == ~t2_pc~0; 24028#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23784#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23785#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24847#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24508#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24509#L582-36 assume 1 == ~t3_pc~0; 24359#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24360#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24584#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24751#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24545#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24489#L601-36 assume 1 == ~t4_pc~0; 24388#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24389#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25136#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25054#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25055#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24960#L620-36 assume 1 == ~t5_pc~0; 24428#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24429#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24822#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24416#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24050#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23828#L639-36 assume 1 == ~t6_pc~0; 23829#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23865#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23866#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24106#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24107#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24685#L658-36 assume 1 == ~t7_pc~0; 23947#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23840#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25039#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23815#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 23816#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24806#L677-36 assume !(1 == ~t8_pc~0); 24610#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 24611#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24727#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25111#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24633#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24634#L696-36 assume !(1 == ~t9_pc~0); 24528#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 24529#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23888#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23889#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24646#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24647#L715-36 assume !(1 == ~t10_pc~0); 24617#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 23713#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23714#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23689#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23690#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24094#L734-36 assume !(1 == ~t11_pc~0); 23793#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 23794#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24116#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23707#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23708#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24707#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24374#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24375#L1218-3 assume !(1 == ~T2_E~0); 24145#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24146#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24335#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24336#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24580#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24581#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25052#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25057#L1258-3 assume !(1 == ~T10_E~0); 24127#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24128#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25023#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25041#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25043#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24459#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24460#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24325#L1298-3 assume !(1 == ~E_7~0); 24326#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24781#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24322#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24323#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24129#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 24130#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 24069#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 24480#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 24919#L1663 assume !(0 == start_simulation_~tmp~3#1); 23962#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 24683#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 23906#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 24602#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 23850#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23851#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24189#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 25108#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 24215#L1644-2 [2021-11-13 18:15:47,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:47,778 INFO L85 PathProgramCache]: Analyzing trace with hash 1810344552, now seen corresponding path program 1 times [2021-11-13 18:15:47,778 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:47,778 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487168931] [2021-11-13 18:15:47,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:47,779 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:47,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:47,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:47,812 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:47,812 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487168931] [2021-11-13 18:15:47,812 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487168931] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:47,813 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:47,813 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:47,813 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [239122462] [2021-11-13 18:15:47,813 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:47,814 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:47,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:47,814 INFO L85 PathProgramCache]: Analyzing trace with hash 1427558892, now seen corresponding path program 1 times [2021-11-13 18:15:47,815 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:47,815 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1074196262] [2021-11-13 18:15:47,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:47,815 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:47,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:47,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:47,856 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:47,856 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1074196262] [2021-11-13 18:15:47,857 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1074196262] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:47,857 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:47,857 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:47,857 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1299545516] [2021-11-13 18:15:47,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:47,858 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:47,858 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:47,858 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:15:47,859 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:15:47,859 INFO L87 Difference]: Start difference. First operand 1476 states and 2186 transitions. cyclomatic complexity: 711 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:47,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:47,897 INFO L93 Difference]: Finished difference Result 1476 states and 2185 transitions. [2021-11-13 18:15:47,898 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:15:47,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2185 transitions. [2021-11-13 18:15:47,908 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:47,920 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2185 transitions. [2021-11-13 18:15:47,920 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-13 18:15:47,922 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-13 18:15:47,922 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2185 transitions. [2021-11-13 18:15:47,924 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:47,924 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2185 transitions. [2021-11-13 18:15:47,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2185 transitions. [2021-11-13 18:15:47,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-13 18:15:47,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4803523035230353) internal successors, (2185), 1475 states have internal predecessors, (2185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:47,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2185 transitions. [2021-11-13 18:15:47,957 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2185 transitions. [2021-11-13 18:15:47,958 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2185 transitions. [2021-11-13 18:15:47,958 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-13 18:15:47,958 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2185 transitions. [2021-11-13 18:15:47,964 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:47,965 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:47,965 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:47,967 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:47,968 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:47,968 INFO L791 eck$LassoCheckResult]: Stem: 27768#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 27769#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 27776#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27777#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27544#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 27545#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27414#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27326#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27049#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26684#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26685#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26733#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26734#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27662#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27663#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 27701#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 27149#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27150#L1090 assume !(0 == ~M_E~0); 27192#L1090-2 assume !(0 == ~T1_E~0); 27193#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27838#L1100-1 assume !(0 == ~T3_E~0); 27839#L1105-1 assume !(0 == ~T4_E~0); 26967#L1110-1 assume !(0 == ~T5_E~0); 26968#L1115-1 assume !(0 == ~T6_E~0); 27364#L1120-1 assume !(0 == ~T7_E~0); 27641#L1125-1 assume !(0 == ~T8_E~0); 28110#L1130-1 assume !(0 == ~T9_E~0); 27859#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27154#L1140-1 assume !(0 == ~T11_E~0); 27155#L1145-1 assume !(0 == ~E_1~0); 27793#L1150-1 assume !(0 == ~E_2~0); 27339#L1155-1 assume !(0 == ~E_3~0); 27340#L1160-1 assume !(0 == ~E_4~0); 27422#L1165-1 assume !(0 == ~E_5~0); 27423#L1170-1 assume !(0 == ~E_6~0); 28031#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 27500#L1180-1 assume !(0 == ~E_8~0); 27501#L1185-1 assume !(0 == ~E_9~0); 27151#L1190-1 assume !(0 == ~E_10~0); 27152#L1195-1 assume !(0 == ~E_11~0); 27514#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27354#L525 assume !(1 == ~m_pc~0); 26772#L525-2 is_master_triggered_~__retres1~0#1 := 0; 26773#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27518#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27519#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27138#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27139#L544 assume 1 == ~t1_pc~0; 27399#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27363#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27791#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26989#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 26990#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27612#L563 assume !(1 == ~t2_pc~0); 27778#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26793#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26794#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27222#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 27223#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27685#L582 assume 1 == ~t3_pc~0; 26931#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26932#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28082#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28040#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 26867#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26868#L601 assume !(1 == ~t4_pc~0); 27808#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27365#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27366#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27802#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 27803#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28074#L620 assume 1 == ~t5_pc~0; 26822#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26823#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27637#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27638#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 28089#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28090#L639 assume !(1 == ~t6_pc~0); 27639#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27262#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27263#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28043#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 27373#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27374#L658 assume 1 == ~t7_pc~0; 27640#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27565#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27672#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27673#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 27145#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27146#L677 assume 1 == ~t8_pc~0; 27376#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26948#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26949#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 27219#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 27220#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27898#L696 assume !(1 == ~t9_pc~0); 27623#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27624#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27713#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27645#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27646#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27843#L715 assume 1 == ~t10_pc~0; 27847#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27730#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27615#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27616#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 27492#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26940#L734 assume !(1 == ~t11_pc~0); 26941#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 27426#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27505#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26672#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 26673#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27700#L1213 assume !(1 == ~M_E~0); 27489#L1213-2 assume !(1 == ~T1_E~0); 27490#L1218-1 assume !(1 == ~T2_E~0); 26709#L1223-1 assume !(1 == ~T3_E~0); 26710#L1228-1 assume !(1 == ~T4_E~0); 27469#L1233-1 assume !(1 == ~T5_E~0); 28091#L1238-1 assume !(1 == ~T6_E~0); 27800#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27801#L1248-1 assume !(1 == ~T8_E~0); 27845#L1253-1 assume !(1 == ~T9_E~0); 27846#L1258-1 assume !(1 == ~T10_E~0); 27824#L1263-1 assume !(1 == ~T11_E~0); 27825#L1268-1 assume !(1 == ~E_1~0); 27660#L1273-1 assume !(1 == ~E_2~0); 27661#L1278-1 assume !(1 == ~E_3~0); 27260#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 27261#L1288-1 assume !(1 == ~E_5~0); 27938#L1293-1 assume !(1 == ~E_6~0); 27902#L1298-1 assume !(1 == ~E_7~0); 27688#L1303-1 assume !(1 == ~E_8~0); 27271#L1308-1 assume !(1 == ~E_9~0); 27160#L1313-1 assume !(1 == ~E_10~0); 27161#L1318-1 assume !(1 == ~E_11~0); 27170#L1323-1 assume { :end_inline_reset_delta_events } true; 27171#L1644-2 [2021-11-13 18:15:47,969 INFO L793 eck$LassoCheckResult]: Loop: 27171#L1644-2 assume !false; 27741#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27742#L1065 assume !false; 27817#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28087#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 26791#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28003#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 27276#L906 assume !(0 != eval_~tmp~0#1); 27278#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27814#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27815#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27955#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28007#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27970#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27971#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27044#L1110-3 assume !(0 == ~T5_E~0); 27045#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27327#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27328#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27798#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28052#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27250#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26745#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26746#L1150-3 assume !(0 == ~E_2~0); 26869#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26870#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27231#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27232#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27604#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27141#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26899#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26900#L1190-3 assume !(0 == ~E_10~0); 28046#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28047#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27454#L525-36 assume 1 == ~m_pc~0; 27456#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27000#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27001#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27286#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27287#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27195#L544-36 assume 1 == ~t1_pc~0; 27196#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27719#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27084#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27085#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28028#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27931#L563-36 assume 1 == ~t2_pc~0; 26987#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26743#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26744#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27806#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27467#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27468#L582-36 assume 1 == ~t3_pc~0; 27318#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27319#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27543#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27710#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27504#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27448#L601-36 assume 1 == ~t4_pc~0; 27347#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27348#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28095#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28013#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28014#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27919#L620-36 assume 1 == ~t5_pc~0; 27389#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27390#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27781#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27375#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27009#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26787#L639-36 assume 1 == ~t6_pc~0; 26788#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26827#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26828#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27067#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27068#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27644#L658-36 assume 1 == ~t7_pc~0; 26906#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26799#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27998#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26774#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 26775#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27765#L677-36 assume !(1 == ~t8_pc~0); 27569#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 27570#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27686#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28070#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27592#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27593#L696-36 assume 1 == ~t9_pc~0; 27486#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27488#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26847#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26848#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27605#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27606#L715-36 assume !(1 == ~t10_pc~0); 27576#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 26674#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26675#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26648#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26649#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27053#L734-36 assume !(1 == ~t11_pc~0); 26752#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 26753#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27075#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26666#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26667#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27666#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27335#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27336#L1218-3 assume !(1 == ~T2_E~0); 27104#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27105#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27294#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27295#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27539#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27540#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28012#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28017#L1258-3 assume !(1 == ~T10_E~0); 27086#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27087#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27982#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28000#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28002#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27418#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27419#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27284#L1298-3 assume !(1 == ~E_7~0); 27285#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27740#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27281#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 27282#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 27088#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 27089#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 27028#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 27439#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 27878#L1663 assume !(0 == start_simulation_~tmp~3#1); 26914#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 27642#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 26865#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 27563#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 26809#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26810#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27148#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 28067#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 27171#L1644-2 [2021-11-13 18:15:47,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:47,970 INFO L85 PathProgramCache]: Analyzing trace with hash -1778026138, now seen corresponding path program 1 times [2021-11-13 18:15:47,970 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:47,970 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290469] [2021-11-13 18:15:47,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:47,971 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:47,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:48,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:48,004 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:48,004 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1290469] [2021-11-13 18:15:48,004 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1290469] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:48,004 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:48,004 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:48,004 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1051053882] [2021-11-13 18:15:48,005 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:48,006 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:48,006 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:48,007 INFO L85 PathProgramCache]: Analyzing trace with hash 1771516014, now seen corresponding path program 1 times [2021-11-13 18:15:48,007 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:48,007 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [460312501] [2021-11-13 18:15:48,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:48,007 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:48,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:48,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:48,055 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:48,055 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [460312501] [2021-11-13 18:15:48,055 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [460312501] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:48,055 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:48,055 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:48,056 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1479887664] [2021-11-13 18:15:48,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:48,056 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:48,056 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:48,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:15:48,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:15:48,057 INFO L87 Difference]: Start difference. First operand 1476 states and 2185 transitions. cyclomatic complexity: 710 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:48,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:48,093 INFO L93 Difference]: Finished difference Result 1476 states and 2184 transitions. [2021-11-13 18:15:48,094 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:15:48,094 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2184 transitions. [2021-11-13 18:15:48,103 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:48,122 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2184 transitions. [2021-11-13 18:15:48,123 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-13 18:15:48,124 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-13 18:15:48,124 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2184 transitions. [2021-11-13 18:15:48,127 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:48,127 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2184 transitions. [2021-11-13 18:15:48,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2184 transitions. [2021-11-13 18:15:48,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-13 18:15:48,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4796747967479675) internal successors, (2184), 1475 states have internal predecessors, (2184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:48,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2184 transitions. [2021-11-13 18:15:48,160 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2184 transitions. [2021-11-13 18:15:48,160 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2184 transitions. [2021-11-13 18:15:48,160 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-13 18:15:48,160 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2184 transitions. [2021-11-13 18:15:48,167 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:48,167 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:48,167 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:48,170 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:48,170 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:48,170 INFO L791 eck$LassoCheckResult]: Stem: 30727#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 30728#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 30737#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30738#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30503#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 30504#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30373#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30285#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30008#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29643#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29644#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29692#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29693#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 30621#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30622#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 30660#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 30108#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30109#L1090 assume !(0 == ~M_E~0); 30154#L1090-2 assume !(0 == ~T1_E~0); 30155#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30798#L1100-1 assume !(0 == ~T3_E~0); 30799#L1105-1 assume !(0 == ~T4_E~0); 29927#L1110-1 assume !(0 == ~T5_E~0); 29928#L1115-1 assume !(0 == ~T6_E~0); 30323#L1120-1 assume !(0 == ~T7_E~0); 30600#L1125-1 assume !(0 == ~T8_E~0); 31069#L1130-1 assume !(0 == ~T9_E~0); 30818#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30113#L1140-1 assume !(0 == ~T11_E~0); 30114#L1145-1 assume !(0 == ~E_1~0); 30752#L1150-1 assume !(0 == ~E_2~0); 30298#L1155-1 assume !(0 == ~E_3~0); 30299#L1160-1 assume !(0 == ~E_4~0); 30381#L1165-1 assume !(0 == ~E_5~0); 30382#L1170-1 assume !(0 == ~E_6~0); 30990#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 30459#L1180-1 assume !(0 == ~E_8~0); 30460#L1185-1 assume !(0 == ~E_9~0); 30110#L1190-1 assume !(0 == ~E_10~0); 30111#L1195-1 assume !(0 == ~E_11~0); 30473#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30320#L525 assume !(1 == ~m_pc~0); 29731#L525-2 is_master_triggered_~__retres1~0#1 := 0; 29732#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30477#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30478#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30097#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30098#L544 assume 1 == ~t1_pc~0; 30358#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30322#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30750#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29948#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 29949#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30571#L563 assume !(1 == ~t2_pc~0); 30739#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29752#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29753#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30184#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 30185#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30644#L582 assume 1 == ~t3_pc~0; 29892#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29893#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31041#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30999#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 29826#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29827#L601 assume !(1 == ~t4_pc~0); 30767#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30324#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30325#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30761#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 30762#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31033#L620 assume 1 == ~t5_pc~0; 29785#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29786#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30596#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30597#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 31048#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31049#L639 assume !(1 == ~t6_pc~0); 30598#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30221#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30222#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31002#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 30332#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30333#L658 assume 1 == ~t7_pc~0; 30599#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30526#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30631#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30632#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 30104#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30105#L677 assume 1 == ~t8_pc~0; 30337#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29907#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29908#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30178#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 30179#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30857#L696 assume !(1 == ~t9_pc~0); 30584#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 30585#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30675#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30604#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30605#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30802#L715 assume 1 == ~t10_pc~0; 30806#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30689#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30574#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30575#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 30451#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29901#L734 assume !(1 == ~t11_pc~0); 29902#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 30385#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30464#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29633#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 29634#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30659#L1213 assume !(1 == ~M_E~0); 30449#L1213-2 assume !(1 == ~T1_E~0); 30450#L1218-1 assume !(1 == ~T2_E~0); 29668#L1223-1 assume !(1 == ~T3_E~0); 29669#L1228-1 assume !(1 == ~T4_E~0); 30428#L1233-1 assume !(1 == ~T5_E~0); 31050#L1238-1 assume !(1 == ~T6_E~0); 30759#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30760#L1248-1 assume !(1 == ~T8_E~0); 30804#L1253-1 assume !(1 == ~T9_E~0); 30805#L1258-1 assume !(1 == ~T10_E~0); 30783#L1263-1 assume !(1 == ~T11_E~0); 30784#L1268-1 assume !(1 == ~E_1~0); 30619#L1273-1 assume !(1 == ~E_2~0); 30620#L1278-1 assume !(1 == ~E_3~0); 30219#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 30220#L1288-1 assume !(1 == ~E_5~0); 30897#L1293-1 assume !(1 == ~E_6~0); 30861#L1298-1 assume !(1 == ~E_7~0); 30647#L1303-1 assume !(1 == ~E_8~0); 30230#L1308-1 assume !(1 == ~E_9~0); 30119#L1313-1 assume !(1 == ~E_10~0); 30120#L1318-1 assume !(1 == ~E_11~0); 30132#L1323-1 assume { :end_inline_reset_delta_events } true; 30133#L1644-2 [2021-11-13 18:15:48,171 INFO L793 eck$LassoCheckResult]: Loop: 30133#L1644-2 assume !false; 30700#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30701#L1065 assume !false; 30776#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31046#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29750#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30962#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 30235#L906 assume !(0 != eval_~tmp~0#1); 30237#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30774#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30775#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30914#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30966#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30929#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30930#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30003#L1110-3 assume !(0 == ~T5_E~0); 30004#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30286#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30287#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30757#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 31011#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30211#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29706#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29707#L1150-3 assume !(0 == ~E_2~0); 29829#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29830#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30190#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30191#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30563#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30100#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29861#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29862#L1190-3 assume !(0 == ~E_10~0); 31005#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31006#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30413#L525-36 assume !(1 == ~m_pc~0); 30414#L525-38 is_master_triggered_~__retres1~0#1 := 0; 29964#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29965#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30245#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30246#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30151#L544-36 assume 1 == ~t1_pc~0; 30152#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30678#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30043#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30044#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30987#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30890#L563-36 assume 1 == ~t2_pc~0; 29946#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29702#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29703#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30765#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30426#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30427#L582-36 assume 1 == ~t3_pc~0; 30277#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30278#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30502#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30669#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30463#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30407#L601-36 assume 1 == ~t4_pc~0; 30306#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30307#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31054#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30972#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30973#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30878#L620-36 assume 1 == ~t5_pc~0; 30346#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30347#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30740#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30334#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29968#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29746#L639-36 assume 1 == ~t6_pc~0; 29747#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29783#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29784#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30024#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30025#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30603#L658-36 assume 1 == ~t7_pc~0; 29863#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29758#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30957#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29733#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 29734#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30724#L677-36 assume !(1 == ~t8_pc~0); 30528#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 30529#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30645#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31029#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30551#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30552#L696-36 assume 1 == ~t9_pc~0; 30445#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30447#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29806#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29807#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30564#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30565#L715-36 assume !(1 == ~t10_pc~0); 30535#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 29631#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29632#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29607#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29608#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30012#L734-36 assume 1 == ~t11_pc~0; 30013#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29712#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30034#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29625#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29626#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30625#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30292#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30293#L1218-3 assume !(1 == ~T2_E~0); 30063#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30064#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30253#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30254#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30498#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30499#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30970#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30975#L1258-3 assume !(1 == ~T10_E~0); 30045#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30046#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30941#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30959#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30961#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30377#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30378#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30243#L1298-3 assume !(1 == ~E_7~0); 30244#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30699#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30240#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30241#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 30047#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 30048#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29987#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30398#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 30837#L1663 assume !(0 == start_simulation_~tmp~3#1); 29880#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 30601#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29824#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30520#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 29768#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29769#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30107#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 31026#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 30133#L1644-2 [2021-11-13 18:15:48,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:48,172 INFO L85 PathProgramCache]: Analyzing trace with hash 1655107556, now seen corresponding path program 1 times [2021-11-13 18:15:48,172 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:48,172 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335577987] [2021-11-13 18:15:48,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:48,172 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:48,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:48,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:48,217 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:48,217 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335577987] [2021-11-13 18:15:48,217 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [335577987] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:48,217 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:48,217 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:48,217 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [806630376] [2021-11-13 18:15:48,218 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:48,218 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:48,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:48,219 INFO L85 PathProgramCache]: Analyzing trace with hash -814695250, now seen corresponding path program 1 times [2021-11-13 18:15:48,219 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:48,219 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113196180] [2021-11-13 18:15:48,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:48,219 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:48,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:48,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:48,264 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:48,264 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1113196180] [2021-11-13 18:15:48,264 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1113196180] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:48,264 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:48,264 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:48,264 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2130253717] [2021-11-13 18:15:48,265 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:48,265 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:48,265 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:48,266 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:15:48,266 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:15:48,266 INFO L87 Difference]: Start difference. First operand 1476 states and 2184 transitions. cyclomatic complexity: 709 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:48,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:48,301 INFO L93 Difference]: Finished difference Result 1476 states and 2183 transitions. [2021-11-13 18:15:48,301 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:15:48,302 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2183 transitions. [2021-11-13 18:15:48,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:48,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2183 transitions. [2021-11-13 18:15:48,321 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-13 18:15:48,322 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-13 18:15:48,322 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2183 transitions. [2021-11-13 18:15:48,325 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:48,325 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2183 transitions. [2021-11-13 18:15:48,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2183 transitions. [2021-11-13 18:15:48,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-13 18:15:48,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4789972899728998) internal successors, (2183), 1475 states have internal predecessors, (2183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:48,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2183 transitions. [2021-11-13 18:15:48,356 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2183 transitions. [2021-11-13 18:15:48,356 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2183 transitions. [2021-11-13 18:15:48,356 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-13 18:15:48,356 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2183 transitions. [2021-11-13 18:15:48,362 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:48,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:48,363 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:48,365 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:48,366 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:48,366 INFO L791 eck$LassoCheckResult]: Stem: 33686#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 33687#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 33694#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33695#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33462#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 33463#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33332#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33244#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32967#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32602#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32603#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32651#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32652#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33580#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33581#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 33619#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 33067#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33068#L1090 assume !(0 == ~M_E~0); 33110#L1090-2 assume !(0 == ~T1_E~0); 33111#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33756#L1100-1 assume !(0 == ~T3_E~0); 33757#L1105-1 assume !(0 == ~T4_E~0); 32885#L1110-1 assume !(0 == ~T5_E~0); 32886#L1115-1 assume !(0 == ~T6_E~0); 33282#L1120-1 assume !(0 == ~T7_E~0); 33559#L1125-1 assume !(0 == ~T8_E~0); 34028#L1130-1 assume !(0 == ~T9_E~0); 33777#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33072#L1140-1 assume !(0 == ~T11_E~0); 33073#L1145-1 assume !(0 == ~E_1~0); 33711#L1150-1 assume !(0 == ~E_2~0); 33257#L1155-1 assume !(0 == ~E_3~0); 33258#L1160-1 assume !(0 == ~E_4~0); 33340#L1165-1 assume !(0 == ~E_5~0); 33341#L1170-1 assume !(0 == ~E_6~0); 33949#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 33418#L1180-1 assume !(0 == ~E_8~0); 33419#L1185-1 assume !(0 == ~E_9~0); 33069#L1190-1 assume !(0 == ~E_10~0); 33070#L1195-1 assume !(0 == ~E_11~0); 33432#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33272#L525 assume !(1 == ~m_pc~0); 32690#L525-2 is_master_triggered_~__retres1~0#1 := 0; 32691#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33436#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33437#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33056#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33057#L544 assume 1 == ~t1_pc~0; 33317#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33281#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33709#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32907#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 32908#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33530#L563 assume !(1 == ~t2_pc~0); 33696#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32711#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32712#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33140#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 33141#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33603#L582 assume 1 == ~t3_pc~0; 32849#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32850#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34000#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33958#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 32785#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32786#L601 assume !(1 == ~t4_pc~0); 33726#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33283#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33284#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33720#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 33721#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33992#L620 assume 1 == ~t5_pc~0; 32740#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32741#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33555#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33556#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 34007#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34008#L639 assume !(1 == ~t6_pc~0); 33557#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33180#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33181#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33961#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 33291#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33292#L658 assume 1 == ~t7_pc~0; 33558#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33483#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33590#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33591#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 33063#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33064#L677 assume 1 == ~t8_pc~0; 33294#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32866#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32867#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33137#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 33138#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33816#L696 assume !(1 == ~t9_pc~0); 33541#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 33542#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33631#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33563#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33564#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33761#L715 assume 1 == ~t10_pc~0; 33765#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33648#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33533#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33534#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 33410#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32858#L734 assume !(1 == ~t11_pc~0); 32859#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 33344#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33423#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32590#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 32591#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33618#L1213 assume !(1 == ~M_E~0); 33407#L1213-2 assume !(1 == ~T1_E~0); 33408#L1218-1 assume !(1 == ~T2_E~0); 32627#L1223-1 assume !(1 == ~T3_E~0); 32628#L1228-1 assume !(1 == ~T4_E~0); 33387#L1233-1 assume !(1 == ~T5_E~0); 34009#L1238-1 assume !(1 == ~T6_E~0); 33718#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33719#L1248-1 assume !(1 == ~T8_E~0); 33763#L1253-1 assume !(1 == ~T9_E~0); 33764#L1258-1 assume !(1 == ~T10_E~0); 33742#L1263-1 assume !(1 == ~T11_E~0); 33743#L1268-1 assume !(1 == ~E_1~0); 33578#L1273-1 assume !(1 == ~E_2~0); 33579#L1278-1 assume !(1 == ~E_3~0); 33178#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 33179#L1288-1 assume !(1 == ~E_5~0); 33856#L1293-1 assume !(1 == ~E_6~0); 33820#L1298-1 assume !(1 == ~E_7~0); 33606#L1303-1 assume !(1 == ~E_8~0); 33189#L1308-1 assume !(1 == ~E_9~0); 33078#L1313-1 assume !(1 == ~E_10~0); 33079#L1318-1 assume !(1 == ~E_11~0); 33088#L1323-1 assume { :end_inline_reset_delta_events } true; 33089#L1644-2 [2021-11-13 18:15:48,367 INFO L793 eck$LassoCheckResult]: Loop: 33089#L1644-2 assume !false; 33659#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33660#L1065 assume !false; 33735#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 34005#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32709#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33921#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 33194#L906 assume !(0 != eval_~tmp~0#1); 33196#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33732#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33733#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33873#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33925#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33888#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33889#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32962#L1110-3 assume !(0 == ~T5_E~0); 32963#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33245#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33246#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33716#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33970#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33168#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32663#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32664#L1150-3 assume !(0 == ~E_2~0); 32787#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32788#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33149#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33150#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33522#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33059#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32817#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32818#L1190-3 assume !(0 == ~E_10~0); 33964#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 33965#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33372#L525-36 assume !(1 == ~m_pc~0); 33373#L525-38 is_master_triggered_~__retres1~0#1 := 0; 32918#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32919#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33204#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33205#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33113#L544-36 assume 1 == ~t1_pc~0; 33114#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33637#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33002#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33003#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33946#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33849#L563-36 assume 1 == ~t2_pc~0; 32905#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32661#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32662#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33724#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33385#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33386#L582-36 assume 1 == ~t3_pc~0; 33236#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33237#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33461#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33628#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33422#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33366#L601-36 assume 1 == ~t4_pc~0; 33265#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33266#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34013#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33931#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33932#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33837#L620-36 assume 1 == ~t5_pc~0; 33307#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33308#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33699#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33293#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32927#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32705#L639-36 assume 1 == ~t6_pc~0; 32706#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32745#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32746#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32985#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32986#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33562#L658-36 assume 1 == ~t7_pc~0; 32824#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32717#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33916#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32692#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 32693#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33683#L677-36 assume 1 == ~t8_pc~0; 33861#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33488#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33604#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33988#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33510#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33511#L696-36 assume 1 == ~t9_pc~0; 33404#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33406#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32765#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32766#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33523#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33524#L715-36 assume !(1 == ~t10_pc~0); 33494#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 32592#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32593#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32566#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32567#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32971#L734-36 assume 1 == ~t11_pc~0; 32972#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32671#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32993#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32584#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32585#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33584#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33253#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33254#L1218-3 assume !(1 == ~T2_E~0); 33022#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33023#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33212#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33213#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33457#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33458#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33930#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33935#L1258-3 assume !(1 == ~T10_E~0); 33004#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33005#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33900#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33918#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33920#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33336#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33337#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33202#L1298-3 assume !(1 == ~E_7~0); 33203#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33658#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33199#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33200#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33006#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 33007#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32946#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33357#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 33796#L1663 assume !(0 == start_simulation_~tmp~3#1); 32839#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 33560#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32783#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33481#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 32727#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32728#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33066#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 33985#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 33089#L1644-2 [2021-11-13 18:15:48,367 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:48,367 INFO L85 PathProgramCache]: Analyzing trace with hash -589450842, now seen corresponding path program 1 times [2021-11-13 18:15:48,368 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:48,368 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1119549791] [2021-11-13 18:15:48,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:48,368 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:48,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:48,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:48,407 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:48,407 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1119549791] [2021-11-13 18:15:48,408 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1119549791] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:48,410 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:48,410 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:15:48,410 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [587038598] [2021-11-13 18:15:48,410 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:48,411 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:48,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:48,411 INFO L85 PathProgramCache]: Analyzing trace with hash 1091788943, now seen corresponding path program 1 times [2021-11-13 18:15:48,411 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:48,412 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475823791] [2021-11-13 18:15:48,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:48,412 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:48,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:48,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:48,482 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:48,483 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [475823791] [2021-11-13 18:15:48,483 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [475823791] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:48,483 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:48,483 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:48,483 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1465772222] [2021-11-13 18:15:48,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:48,484 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:48,484 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:48,484 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:15:48,484 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:15:48,485 INFO L87 Difference]: Start difference. First operand 1476 states and 2183 transitions. cyclomatic complexity: 708 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:48,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:48,523 INFO L93 Difference]: Finished difference Result 1476 states and 2178 transitions. [2021-11-13 18:15:48,524 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:15:48,524 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2178 transitions. [2021-11-13 18:15:48,532 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:48,542 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2178 transitions. [2021-11-13 18:15:48,543 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-13 18:15:48,544 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-13 18:15:48,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2178 transitions. [2021-11-13 18:15:48,547 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:48,547 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2178 transitions. [2021-11-13 18:15:48,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2178 transitions. [2021-11-13 18:15:48,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-13 18:15:48,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.475609756097561) internal successors, (2178), 1475 states have internal predecessors, (2178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:48,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2178 transitions. [2021-11-13 18:15:48,579 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2178 transitions. [2021-11-13 18:15:48,579 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2178 transitions. [2021-11-13 18:15:48,580 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-13 18:15:48,580 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2178 transitions. [2021-11-13 18:15:48,587 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:48,587 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:48,587 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:48,590 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:48,590 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:48,591 INFO L791 eck$LassoCheckResult]: Stem: 36645#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 36646#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 36655#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36656#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36421#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 36422#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36291#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36203#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35926#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35561#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35562#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35610#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35611#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36539#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36540#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36578#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 36026#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36027#L1090 assume !(0 == ~M_E~0); 36069#L1090-2 assume !(0 == ~T1_E~0); 36070#L1095-1 assume !(0 == ~T2_E~0); 36716#L1100-1 assume !(0 == ~T3_E~0); 36717#L1105-1 assume !(0 == ~T4_E~0); 35845#L1110-1 assume !(0 == ~T5_E~0); 35846#L1115-1 assume !(0 == ~T6_E~0); 36241#L1120-1 assume !(0 == ~T7_E~0); 36518#L1125-1 assume !(0 == ~T8_E~0); 36987#L1130-1 assume !(0 == ~T9_E~0); 36736#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36031#L1140-1 assume !(0 == ~T11_E~0); 36032#L1145-1 assume !(0 == ~E_1~0); 36670#L1150-1 assume !(0 == ~E_2~0); 36216#L1155-1 assume !(0 == ~E_3~0); 36217#L1160-1 assume !(0 == ~E_4~0); 36299#L1165-1 assume !(0 == ~E_5~0); 36300#L1170-1 assume !(0 == ~E_6~0); 36908#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 36377#L1180-1 assume !(0 == ~E_8~0); 36378#L1185-1 assume !(0 == ~E_9~0); 36028#L1190-1 assume !(0 == ~E_10~0); 36029#L1195-1 assume !(0 == ~E_11~0); 36391#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36238#L525 assume !(1 == ~m_pc~0); 35649#L525-2 is_master_triggered_~__retres1~0#1 := 0; 35650#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36395#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36396#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36015#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36016#L544 assume 1 == ~t1_pc~0; 36276#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36240#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36668#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35866#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 35867#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36489#L563 assume !(1 == ~t2_pc~0); 36657#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35670#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35671#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36099#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 36100#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36562#L582 assume 1 == ~t3_pc~0; 35810#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35811#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36959#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36917#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 35744#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35745#L601 assume !(1 == ~t4_pc~0); 36685#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36242#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36243#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36679#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 36680#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36951#L620 assume 1 == ~t5_pc~0; 35701#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35702#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36514#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36515#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 36966#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36967#L639 assume !(1 == ~t6_pc~0); 36516#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36139#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36140#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36920#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 36250#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36251#L658 assume 1 == ~t7_pc~0; 36517#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36444#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36549#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36550#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 36022#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36023#L677 assume 1 == ~t8_pc~0; 36255#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35825#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35826#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36096#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 36097#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36775#L696 assume !(1 == ~t9_pc~0); 36502#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 36503#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36590#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36522#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36523#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36720#L715 assume 1 == ~t10_pc~0; 36724#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36607#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36492#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36493#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 36369#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35819#L734 assume !(1 == ~t11_pc~0); 35820#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 36303#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36382#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35551#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 35552#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36577#L1213 assume !(1 == ~M_E~0); 36367#L1213-2 assume !(1 == ~T1_E~0); 36368#L1218-1 assume !(1 == ~T2_E~0); 35586#L1223-1 assume !(1 == ~T3_E~0); 35587#L1228-1 assume !(1 == ~T4_E~0); 36346#L1233-1 assume !(1 == ~T5_E~0); 36968#L1238-1 assume !(1 == ~T6_E~0); 36677#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36678#L1248-1 assume !(1 == ~T8_E~0); 36722#L1253-1 assume !(1 == ~T9_E~0); 36723#L1258-1 assume !(1 == ~T10_E~0); 36701#L1263-1 assume !(1 == ~T11_E~0); 36702#L1268-1 assume !(1 == ~E_1~0); 36537#L1273-1 assume !(1 == ~E_2~0); 36538#L1278-1 assume !(1 == ~E_3~0); 36137#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 36138#L1288-1 assume !(1 == ~E_5~0); 36815#L1293-1 assume !(1 == ~E_6~0); 36779#L1298-1 assume !(1 == ~E_7~0); 36565#L1303-1 assume !(1 == ~E_8~0); 36148#L1308-1 assume !(1 == ~E_9~0); 36037#L1313-1 assume !(1 == ~E_10~0); 36038#L1318-1 assume !(1 == ~E_11~0); 36050#L1323-1 assume { :end_inline_reset_delta_events } true; 36051#L1644-2 [2021-11-13 18:15:48,591 INFO L793 eck$LassoCheckResult]: Loop: 36051#L1644-2 assume !false; 36618#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36619#L1065 assume !false; 36694#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36964#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35668#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36880#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 36153#L906 assume !(0 != eval_~tmp~0#1); 36155#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36692#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36693#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36832#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36884#L1095-3 assume !(0 == ~T2_E~0); 36847#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36848#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35921#L1110-3 assume !(0 == ~T5_E~0); 35922#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36204#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36205#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36675#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36929#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36129#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 35624#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35625#L1150-3 assume !(0 == ~E_2~0); 35747#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35748#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36108#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36109#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36481#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36018#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35777#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35778#L1190-3 assume !(0 == ~E_10~0); 36923#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36924#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36331#L525-36 assume !(1 == ~m_pc~0); 36332#L525-38 is_master_triggered_~__retres1~0#1 := 0; 35882#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35883#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36164#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36165#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36072#L544-36 assume 1 == ~t1_pc~0; 36073#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36596#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35967#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35968#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36906#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36808#L563-36 assume 1 == ~t2_pc~0; 35864#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35620#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35621#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36683#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36344#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36345#L582-36 assume 1 == ~t3_pc~0; 36195#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36196#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36420#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36587#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36381#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36322#L601-36 assume 1 == ~t4_pc~0; 36224#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36225#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36972#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36890#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36891#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36794#L620-36 assume 1 == ~t5_pc~0; 36264#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36265#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36658#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36252#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35886#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35664#L639-36 assume 1 == ~t6_pc~0; 35665#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35699#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35700#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35942#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35943#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36521#L658-36 assume 1 == ~t7_pc~0; 35781#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35676#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36875#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35651#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 35652#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36642#L677-36 assume 1 == ~t8_pc~0; 36820#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36447#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36563#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36947#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36469#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36470#L696-36 assume 1 == ~t9_pc~0; 36363#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36365#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35721#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35722#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36482#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36483#L715-36 assume !(1 == ~t10_pc~0); 36453#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 35549#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35550#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35525#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35526#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35930#L734-36 assume 1 == ~t11_pc~0; 35931#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35630#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35952#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35543#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35544#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36543#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36210#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36211#L1218-3 assume !(1 == ~T2_E~0); 35981#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35982#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36171#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36172#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36416#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36417#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36888#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36893#L1258-3 assume !(1 == ~T10_E~0); 35961#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35962#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36859#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36877#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36879#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36295#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36296#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36161#L1298-3 assume !(1 == ~E_7~0); 36162#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36617#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36158#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36159#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35963#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35964#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35905#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36316#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 36755#L1663 assume !(0 == start_simulation_~tmp~3#1); 35793#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36519#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35742#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36438#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 35683#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35684#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36025#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 36944#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 36051#L1644-2 [2021-11-13 18:15:48,592 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:48,592 INFO L85 PathProgramCache]: Analyzing trace with hash 1863040740, now seen corresponding path program 1 times [2021-11-13 18:15:48,592 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:48,593 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1879576432] [2021-11-13 18:15:48,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:48,593 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:48,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:48,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:48,663 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:48,664 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1879576432] [2021-11-13 18:15:48,664 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1879576432] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:48,664 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:48,664 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:15:48,664 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [922941247] [2021-11-13 18:15:48,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:48,665 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:48,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:48,665 INFO L85 PathProgramCache]: Analyzing trace with hash 1766949069, now seen corresponding path program 1 times [2021-11-13 18:15:48,666 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:48,666 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972990192] [2021-11-13 18:15:48,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:48,666 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:48,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:48,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:48,713 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:48,713 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1972990192] [2021-11-13 18:15:48,713 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1972990192] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:48,713 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:48,713 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:48,714 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1193033182] [2021-11-13 18:15:48,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:48,714 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:48,715 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:48,715 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:15:48,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:15:48,715 INFO L87 Difference]: Start difference. First operand 1476 states and 2178 transitions. cyclomatic complexity: 703 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:48,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:48,755 INFO L93 Difference]: Finished difference Result 1476 states and 2173 transitions. [2021-11-13 18:15:48,755 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:15:48,756 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2173 transitions. [2021-11-13 18:15:48,765 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:48,783 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2173 transitions. [2021-11-13 18:15:48,783 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-13 18:15:48,785 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-13 18:15:48,785 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2173 transitions. [2021-11-13 18:15:48,787 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:48,788 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2173 transitions. [2021-11-13 18:15:48,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2173 transitions. [2021-11-13 18:15:48,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-13 18:15:48,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4722222222222223) internal successors, (2173), 1475 states have internal predecessors, (2173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:48,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2173 transitions. [2021-11-13 18:15:48,834 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2173 transitions. [2021-11-13 18:15:48,835 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2173 transitions. [2021-11-13 18:15:48,835 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-13 18:15:48,835 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2173 transitions. [2021-11-13 18:15:48,841 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:48,841 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:48,841 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:48,844 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:48,844 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:48,844 INFO L791 eck$LassoCheckResult]: Stem: 39604#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 39605#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 39612#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39613#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39380#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 39381#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39250#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39162#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38885#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38520#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38521#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38569#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38570#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 39498#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39499#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39537#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 38985#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38986#L1090 assume !(0 == ~M_E~0); 39028#L1090-2 assume !(0 == ~T1_E~0); 39029#L1095-1 assume !(0 == ~T2_E~0); 39674#L1100-1 assume !(0 == ~T3_E~0); 39675#L1105-1 assume !(0 == ~T4_E~0); 38803#L1110-1 assume !(0 == ~T5_E~0); 38804#L1115-1 assume !(0 == ~T6_E~0); 39200#L1120-1 assume !(0 == ~T7_E~0); 39477#L1125-1 assume !(0 == ~T8_E~0); 39946#L1130-1 assume !(0 == ~T9_E~0); 39695#L1135-1 assume !(0 == ~T10_E~0); 38990#L1140-1 assume !(0 == ~T11_E~0); 38991#L1145-1 assume !(0 == ~E_1~0); 39629#L1150-1 assume !(0 == ~E_2~0); 39175#L1155-1 assume !(0 == ~E_3~0); 39176#L1160-1 assume !(0 == ~E_4~0); 39258#L1165-1 assume !(0 == ~E_5~0); 39259#L1170-1 assume !(0 == ~E_6~0); 39867#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 39336#L1180-1 assume !(0 == ~E_8~0); 39337#L1185-1 assume !(0 == ~E_9~0); 38987#L1190-1 assume !(0 == ~E_10~0); 38988#L1195-1 assume !(0 == ~E_11~0); 39350#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39190#L525 assume !(1 == ~m_pc~0); 38608#L525-2 is_master_triggered_~__retres1~0#1 := 0; 38609#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39354#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39355#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38974#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38975#L544 assume 1 == ~t1_pc~0; 39235#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 39199#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39627#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38825#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 38826#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39448#L563 assume !(1 == ~t2_pc~0); 39614#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38629#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38630#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39058#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 39059#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39521#L582 assume 1 == ~t3_pc~0; 38767#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38768#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39918#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39876#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 38703#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38704#L601 assume !(1 == ~t4_pc~0); 39644#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 39201#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39202#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39638#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 39639#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39910#L620 assume 1 == ~t5_pc~0; 38658#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38659#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39473#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39474#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 39925#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39926#L639 assume !(1 == ~t6_pc~0); 39475#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 39098#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39099#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39879#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 39209#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39210#L658 assume 1 == ~t7_pc~0; 39476#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39401#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39508#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39509#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 38981#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38982#L677 assume 1 == ~t8_pc~0; 39212#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38784#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38785#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39055#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 39056#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39734#L696 assume !(1 == ~t9_pc~0); 39459#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 39460#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39549#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39481#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39482#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39679#L715 assume 1 == ~t10_pc~0; 39683#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 39566#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39451#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39452#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 39328#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38776#L734 assume !(1 == ~t11_pc~0); 38777#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 39262#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39341#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38508#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 38509#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39536#L1213 assume !(1 == ~M_E~0); 39325#L1213-2 assume !(1 == ~T1_E~0); 39326#L1218-1 assume !(1 == ~T2_E~0); 38545#L1223-1 assume !(1 == ~T3_E~0); 38546#L1228-1 assume !(1 == ~T4_E~0); 39305#L1233-1 assume !(1 == ~T5_E~0); 39927#L1238-1 assume !(1 == ~T6_E~0); 39636#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 39637#L1248-1 assume !(1 == ~T8_E~0); 39681#L1253-1 assume !(1 == ~T9_E~0); 39682#L1258-1 assume !(1 == ~T10_E~0); 39660#L1263-1 assume !(1 == ~T11_E~0); 39661#L1268-1 assume !(1 == ~E_1~0); 39496#L1273-1 assume !(1 == ~E_2~0); 39497#L1278-1 assume !(1 == ~E_3~0); 39096#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 39097#L1288-1 assume !(1 == ~E_5~0); 39774#L1293-1 assume !(1 == ~E_6~0); 39738#L1298-1 assume !(1 == ~E_7~0); 39524#L1303-1 assume !(1 == ~E_8~0); 39107#L1308-1 assume !(1 == ~E_9~0); 38996#L1313-1 assume !(1 == ~E_10~0); 38997#L1318-1 assume !(1 == ~E_11~0); 39006#L1323-1 assume { :end_inline_reset_delta_events } true; 39007#L1644-2 [2021-11-13 18:15:48,845 INFO L793 eck$LassoCheckResult]: Loop: 39007#L1644-2 assume !false; 39577#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39578#L1065 assume !false; 39653#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 39923#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 38627#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 39839#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 39112#L906 assume !(0 != eval_~tmp~0#1); 39114#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39650#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39651#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 39791#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39843#L1095-3 assume !(0 == ~T2_E~0); 39806#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39807#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38880#L1110-3 assume !(0 == ~T5_E~0); 38881#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39163#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 39164#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 39634#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39888#L1135-3 assume !(0 == ~T10_E~0); 39086#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 38581#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38582#L1150-3 assume !(0 == ~E_2~0); 38705#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38706#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 39067#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39068#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 39440#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38977#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38735#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38736#L1190-3 assume !(0 == ~E_10~0); 39882#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39883#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39290#L525-36 assume !(1 == ~m_pc~0); 39291#L525-38 is_master_triggered_~__retres1~0#1 := 0; 38836#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38837#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39122#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39123#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39031#L544-36 assume 1 == ~t1_pc~0; 39032#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 39555#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38920#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38921#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39864#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39767#L563-36 assume 1 == ~t2_pc~0; 38823#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38579#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38580#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39642#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39303#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39304#L582-36 assume 1 == ~t3_pc~0; 39154#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39155#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39379#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39546#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39340#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39284#L601-36 assume !(1 == ~t4_pc~0); 39185#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 39184#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39931#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39849#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39850#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39755#L620-36 assume 1 == ~t5_pc~0; 39225#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39226#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39617#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39211#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38845#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38623#L639-36 assume 1 == ~t6_pc~0; 38624#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38663#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38664#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38903#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38904#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39480#L658-36 assume 1 == ~t7_pc~0; 38742#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38635#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39834#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38610#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 38611#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39601#L677-36 assume 1 == ~t8_pc~0; 39779#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 39406#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39522#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39906#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39428#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39429#L696-36 assume 1 == ~t9_pc~0; 39322#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39324#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38683#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38684#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39441#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39442#L715-36 assume !(1 == ~t10_pc~0); 39412#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 38510#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38511#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38484#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38485#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38889#L734-36 assume 1 == ~t11_pc~0; 38890#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38589#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38911#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38502#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38503#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39502#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39171#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39172#L1218-3 assume !(1 == ~T2_E~0); 38940#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38941#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39130#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39131#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 39375#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 39376#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 39848#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 39853#L1258-3 assume !(1 == ~T10_E~0); 38922#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38923#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 39818#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 39836#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39838#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39254#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39255#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 39120#L1298-3 assume !(1 == ~E_7~0); 39121#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39576#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39117#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 39118#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 38924#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 38925#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 38864#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 39275#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 39714#L1663 assume !(0 == start_simulation_~tmp~3#1); 38757#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 39478#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 38701#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 39399#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 38645#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38646#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38984#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 39903#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 39007#L1644-2 [2021-11-13 18:15:48,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:48,846 INFO L85 PathProgramCache]: Analyzing trace with hash -268309982, now seen corresponding path program 1 times [2021-11-13 18:15:48,846 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:48,846 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815061169] [2021-11-13 18:15:48,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:48,846 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:48,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:48,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:48,886 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:48,887 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [815061169] [2021-11-13 18:15:48,887 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [815061169] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:48,887 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:48,887 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:15:48,887 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [136946932] [2021-11-13 18:15:48,887 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:48,889 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:48,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:48,890 INFO L85 PathProgramCache]: Analyzing trace with hash -738365910, now seen corresponding path program 1 times [2021-11-13 18:15:48,890 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:48,890 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135145905] [2021-11-13 18:15:48,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:48,891 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:48,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:48,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:48,939 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:48,939 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135145905] [2021-11-13 18:15:48,939 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2135145905] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:48,940 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:48,940 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:48,940 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2044485358] [2021-11-13 18:15:48,940 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:48,941 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:48,941 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:48,941 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:15:48,941 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:15:48,942 INFO L87 Difference]: Start difference. First operand 1476 states and 2173 transitions. cyclomatic complexity: 698 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:49,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:49,015 INFO L93 Difference]: Finished difference Result 1476 states and 2155 transitions. [2021-11-13 18:15:49,015 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:15:49,017 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2155 transitions. [2021-11-13 18:15:49,025 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:49,033 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2155 transitions. [2021-11-13 18:15:49,033 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-11-13 18:15:49,035 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-11-13 18:15:49,035 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2155 transitions. [2021-11-13 18:15:49,037 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:49,037 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2155 transitions. [2021-11-13 18:15:49,040 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2155 transitions. [2021-11-13 18:15:49,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-11-13 18:15:49,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4600271002710028) internal successors, (2155), 1475 states have internal predecessors, (2155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:49,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2155 transitions. [2021-11-13 18:15:49,066 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2155 transitions. [2021-11-13 18:15:49,066 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2155 transitions. [2021-11-13 18:15:49,066 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-13 18:15:49,066 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2155 transitions. [2021-11-13 18:15:49,073 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-11-13 18:15:49,073 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:49,073 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:49,076 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:49,076 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:49,076 INFO L791 eck$LassoCheckResult]: Stem: 42563#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 42564#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 42573#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42574#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42338#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 42339#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42209#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42121#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41844#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41479#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41480#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41528#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41529#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42457#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 42458#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 42496#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 41944#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41945#L1090 assume !(0 == ~M_E~0); 41987#L1090-2 assume !(0 == ~T1_E~0); 41988#L1095-1 assume !(0 == ~T2_E~0); 42634#L1100-1 assume !(0 == ~T3_E~0); 42635#L1105-1 assume !(0 == ~T4_E~0); 41763#L1110-1 assume !(0 == ~T5_E~0); 41764#L1115-1 assume !(0 == ~T6_E~0); 42159#L1120-1 assume !(0 == ~T7_E~0); 42435#L1125-1 assume !(0 == ~T8_E~0); 42905#L1130-1 assume !(0 == ~T9_E~0); 42654#L1135-1 assume !(0 == ~T10_E~0); 41949#L1140-1 assume !(0 == ~T11_E~0); 41950#L1145-1 assume !(0 == ~E_1~0); 42588#L1150-1 assume !(0 == ~E_2~0); 42134#L1155-1 assume !(0 == ~E_3~0); 42135#L1160-1 assume !(0 == ~E_4~0); 42217#L1165-1 assume !(0 == ~E_5~0); 42218#L1170-1 assume !(0 == ~E_6~0); 42826#L1175-1 assume !(0 == ~E_7~0); 42294#L1180-1 assume !(0 == ~E_8~0); 42295#L1185-1 assume !(0 == ~E_9~0); 41946#L1190-1 assume !(0 == ~E_10~0); 41947#L1195-1 assume !(0 == ~E_11~0); 42308#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42156#L525 assume !(1 == ~m_pc~0); 41567#L525-2 is_master_triggered_~__retres1~0#1 := 0; 41568#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42312#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42313#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41933#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41934#L544 assume 1 == ~t1_pc~0; 42194#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42158#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42586#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41784#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 41785#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42406#L563 assume !(1 == ~t2_pc~0); 42575#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41588#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41589#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42017#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 42018#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42480#L582 assume 1 == ~t3_pc~0; 41728#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41729#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42877#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42835#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 41662#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41663#L601 assume !(1 == ~t4_pc~0); 42603#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 42160#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42161#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42597#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 42598#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42869#L620 assume 1 == ~t5_pc~0; 41619#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41620#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42431#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42432#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 42884#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42885#L639 assume !(1 == ~t6_pc~0); 42433#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 42057#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42058#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42838#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 42168#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42169#L658 assume !(1 == ~t7_pc~0); 42358#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 42359#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42467#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42468#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 41940#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41941#L677 assume 1 == ~t8_pc~0; 42171#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41743#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41744#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42014#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 42015#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 42693#L696 assume !(1 == ~t9_pc~0); 42419#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 42420#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42508#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42439#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42440#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42638#L715 assume 1 == ~t10_pc~0; 42642#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 42525#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42409#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42410#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 42286#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41737#L734 assume !(1 == ~t11_pc~0); 41738#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 42221#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42299#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41469#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 41470#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42495#L1213 assume !(1 == ~M_E~0); 42284#L1213-2 assume !(1 == ~T1_E~0); 42285#L1218-1 assume !(1 == ~T2_E~0); 41504#L1223-1 assume !(1 == ~T3_E~0); 41505#L1228-1 assume !(1 == ~T4_E~0); 42263#L1233-1 assume !(1 == ~T5_E~0); 42886#L1238-1 assume !(1 == ~T6_E~0); 42595#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42596#L1248-1 assume !(1 == ~T8_E~0); 42640#L1253-1 assume !(1 == ~T9_E~0); 42641#L1258-1 assume !(1 == ~T10_E~0); 42619#L1263-1 assume !(1 == ~T11_E~0); 42620#L1268-1 assume !(1 == ~E_1~0); 42455#L1273-1 assume !(1 == ~E_2~0); 42456#L1278-1 assume !(1 == ~E_3~0); 42055#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 42056#L1288-1 assume !(1 == ~E_5~0); 42733#L1293-1 assume !(1 == ~E_6~0); 42697#L1298-1 assume !(1 == ~E_7~0); 42483#L1303-1 assume !(1 == ~E_8~0); 42066#L1308-1 assume !(1 == ~E_9~0); 41955#L1313-1 assume !(1 == ~E_10~0); 41956#L1318-1 assume !(1 == ~E_11~0); 41968#L1323-1 assume { :end_inline_reset_delta_events } true; 41969#L1644-2 [2021-11-13 18:15:49,077 INFO L793 eck$LassoCheckResult]: Loop: 41969#L1644-2 assume !false; 42536#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 42537#L1065 assume !false; 42612#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 42882#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 41586#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 42798#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 42071#L906 assume !(0 != eval_~tmp~0#1); 42073#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42609#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42610#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42750#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42802#L1095-3 assume !(0 == ~T2_E~0); 42765#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42766#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41839#L1110-3 assume !(0 == ~T5_E~0); 41840#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42122#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42123#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 42593#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42847#L1135-3 assume !(0 == ~T10_E~0); 42045#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41542#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41543#L1150-3 assume !(0 == ~E_2~0); 41665#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41666#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42026#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42027#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42398#L1175-3 assume !(0 == ~E_7~0); 41936#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41695#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 41696#L1190-3 assume !(0 == ~E_10~0); 42841#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 42842#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42248#L525-36 assume !(1 == ~m_pc~0); 42249#L525-38 is_master_triggered_~__retres1~0#1 := 0; 41800#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41801#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42082#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42083#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41990#L544-36 assume 1 == ~t1_pc~0; 41991#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42514#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41885#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41886#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42824#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42726#L563-36 assume 1 == ~t2_pc~0; 41782#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41538#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41539#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42601#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42261#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42262#L582-36 assume 1 == ~t3_pc~0; 42113#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42114#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42337#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42505#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42298#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42242#L601-36 assume !(1 == ~t4_pc~0); 42144#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 42143#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42890#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42808#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42809#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42714#L620-36 assume 1 == ~t5_pc~0; 42185#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 42186#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42578#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42170#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41804#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41579#L639-36 assume 1 == ~t6_pc~0; 41580#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41617#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41618#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41858#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41859#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42438#L658-36 assume !(1 == ~t7_pc~0); 41590#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 41591#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42793#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41569#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 41570#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42560#L677-36 assume 1 == ~t8_pc~0; 42737#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42363#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42481#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42865#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 42386#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 42387#L696-36 assume 1 == ~t9_pc~0; 42280#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42282#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41639#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41640#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42399#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42400#L715-36 assume !(1 == ~t10_pc~0); 42370#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 41467#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41468#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41443#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41444#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41848#L734-36 assume 1 == ~t11_pc~0; 41849#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41548#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41870#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41461#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41462#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42461#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42128#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42129#L1218-3 assume !(1 == ~T2_E~0); 41899#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41900#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42089#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 42090#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42333#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42334#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42806#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42811#L1258-3 assume !(1 == ~T10_E~0); 41879#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41880#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42777#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42795#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42797#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 42213#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42214#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42078#L1298-3 assume !(1 == ~E_7~0); 42079#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 42535#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 42076#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 42077#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41881#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41882#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 41823#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 42234#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 42673#L1663 assume !(0 == start_simulation_~tmp~3#1); 41709#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 42436#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 41660#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 42355#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 41601#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41602#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41943#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 42862#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 41969#L1644-2 [2021-11-13 18:15:49,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:49,078 INFO L85 PathProgramCache]: Analyzing trace with hash -2032217409, now seen corresponding path program 1 times [2021-11-13 18:15:49,078 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:49,078 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [488315440] [2021-11-13 18:15:49,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:49,079 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:49,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:49,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:49,131 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:49,131 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [488315440] [2021-11-13 18:15:49,131 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [488315440] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:49,131 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:49,131 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 18:15:49,132 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1258303571] [2021-11-13 18:15:49,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:49,132 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:49,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:49,133 INFO L85 PathProgramCache]: Analyzing trace with hash 85545799, now seen corresponding path program 1 times [2021-11-13 18:15:49,133 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:49,133 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [157205350] [2021-11-13 18:15:49,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:49,133 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:49,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:49,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:49,174 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:49,175 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [157205350] [2021-11-13 18:15:49,175 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [157205350] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:49,176 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:49,176 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 18:15:49,176 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1249858626] [2021-11-13 18:15:49,176 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:49,177 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:49,177 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:49,177 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-13 18:15:49,178 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-13 18:15:49,178 INFO L87 Difference]: Start difference. First operand 1476 states and 2155 transitions. cyclomatic complexity: 680 Second operand has 5 states, 5 states have (on average 27.4) internal successors, (137), 5 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:49,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:49,585 INFO L93 Difference]: Finished difference Result 4220 states and 6129 transitions. [2021-11-13 18:15:49,585 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-13 18:15:49,586 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4220 states and 6129 transitions. [2021-11-13 18:15:49,610 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3864 [2021-11-13 18:15:49,644 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4220 states to 4220 states and 6129 transitions. [2021-11-13 18:15:49,645 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4220 [2021-11-13 18:15:49,649 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4220 [2021-11-13 18:15:49,649 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4220 states and 6129 transitions. [2021-11-13 18:15:49,655 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:49,656 INFO L681 BuchiCegarLoop]: Abstraction has 4220 states and 6129 transitions. [2021-11-13 18:15:49,661 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4220 states and 6129 transitions. [2021-11-13 18:15:49,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4220 to 1518. [2021-11-13 18:15:49,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1518 states, 1518 states have (on average 1.4472990777338604) internal successors, (2197), 1517 states have internal predecessors, (2197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:49,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1518 states to 1518 states and 2197 transitions. [2021-11-13 18:15:49,703 INFO L704 BuchiCegarLoop]: Abstraction has 1518 states and 2197 transitions. [2021-11-13 18:15:49,703 INFO L587 BuchiCegarLoop]: Abstraction has 1518 states and 2197 transitions. [2021-11-13 18:15:49,703 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-13 18:15:49,704 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1518 states and 2197 transitions. [2021-11-13 18:15:49,710 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1366 [2021-11-13 18:15:49,710 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:49,710 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:49,713 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:49,713 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:49,713 INFO L791 eck$LassoCheckResult]: Stem: 48289#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 48290#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 48297#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48298#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48056#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 48057#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47925#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47835#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47555#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47190#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47191#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47239#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 47240#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48177#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48178#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 48216#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47656#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47657#L1090 assume !(0 == ~M_E~0); 47699#L1090-2 assume !(0 == ~T1_E~0); 47700#L1095-1 assume !(0 == ~T2_E~0); 48360#L1100-1 assume !(0 == ~T3_E~0); 48361#L1105-1 assume !(0 == ~T4_E~0); 47473#L1110-1 assume !(0 == ~T5_E~0); 47474#L1115-1 assume !(0 == ~T6_E~0); 47873#L1120-1 assume !(0 == ~T7_E~0); 48155#L1125-1 assume !(0 == ~T8_E~0); 48649#L1130-1 assume !(0 == ~T9_E~0); 48381#L1135-1 assume !(0 == ~T10_E~0); 47661#L1140-1 assume !(0 == ~T11_E~0); 47662#L1145-1 assume !(0 == ~E_1~0); 48314#L1150-1 assume !(0 == ~E_2~0); 47848#L1155-1 assume !(0 == ~E_3~0); 47849#L1160-1 assume !(0 == ~E_4~0); 47933#L1165-1 assume !(0 == ~E_5~0); 47934#L1170-1 assume !(0 == ~E_6~0); 48561#L1175-1 assume !(0 == ~E_7~0); 48011#L1180-1 assume !(0 == ~E_8~0); 48012#L1185-1 assume !(0 == ~E_9~0); 47658#L1190-1 assume !(0 == ~E_10~0); 47659#L1195-1 assume !(0 == ~E_11~0); 48025#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47863#L525 assume !(1 == ~m_pc~0); 47278#L525-2 is_master_triggered_~__retres1~0#1 := 0; 47279#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48526#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48427#L1350 assume !(0 != activate_threads_~tmp~1#1); 47645#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47646#L544 assume 1 == ~t1_pc~0; 47908#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47872#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48312#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47495#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 47496#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48125#L563 assume !(1 == ~t2_pc~0); 48299#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 47299#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47300#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47729#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 47730#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48200#L582 assume 1 == ~t3_pc~0; 47437#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47438#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48616#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48570#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 47373#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47374#L601 assume !(1 == ~t4_pc~0); 48329#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47874#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47875#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48323#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 48324#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48607#L620 assume 1 == ~t5_pc~0; 47328#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47329#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48151#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48152#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 48625#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48626#L639 assume !(1 == ~t6_pc~0); 48153#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 47770#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47771#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48573#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 47882#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47883#L658 assume !(1 == ~t7_pc~0); 48076#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 48077#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48187#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48188#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 47652#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47653#L677 assume 1 == ~t8_pc~0; 47885#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47454#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47455#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47726#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 47727#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48421#L696 assume !(1 == ~t9_pc~0); 48136#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 48137#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48228#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48159#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 48160#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48365#L715 assume 1 == ~t10_pc~0; 48369#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 48245#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48128#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48129#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 48003#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47446#L734 assume !(1 == ~t11_pc~0); 47447#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 47937#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48016#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47178#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 47179#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48215#L1213 assume !(1 == ~M_E~0); 48000#L1213-2 assume !(1 == ~T1_E~0); 48001#L1218-1 assume !(1 == ~T2_E~0); 47215#L1223-1 assume !(1 == ~T3_E~0); 47216#L1228-1 assume !(1 == ~T4_E~0); 47980#L1233-1 assume !(1 == ~T5_E~0); 48627#L1238-1 assume !(1 == ~T6_E~0); 48321#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48322#L1248-1 assume !(1 == ~T8_E~0); 48367#L1253-1 assume !(1 == ~T9_E~0); 48368#L1258-1 assume !(1 == ~T10_E~0); 48345#L1263-1 assume !(1 == ~T11_E~0); 48346#L1268-1 assume !(1 == ~E_1~0); 48175#L1273-1 assume !(1 == ~E_2~0); 48176#L1278-1 assume !(1 == ~E_3~0); 47768#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 47769#L1288-1 assume !(1 == ~E_5~0); 48463#L1293-1 assume !(1 == ~E_6~0); 48425#L1298-1 assume !(1 == ~E_7~0); 48203#L1303-1 assume !(1 == ~E_8~0); 47780#L1308-1 assume !(1 == ~E_9~0); 47667#L1313-1 assume !(1 == ~E_10~0); 47668#L1318-1 assume !(1 == ~E_11~0); 47677#L1323-1 assume { :end_inline_reset_delta_events } true; 47678#L1644-2 [2021-11-13 18:15:49,714 INFO L793 eck$LassoCheckResult]: Loop: 47678#L1644-2 assume !false; 48259#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48260#L1065 assume !false; 48338#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 48623#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 47297#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 48531#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 47785#L906 assume !(0 != eval_~tmp~0#1); 47787#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 48335#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48336#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48481#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 48535#L1095-3 assume !(0 == ~T2_E~0); 48496#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48497#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47550#L1110-3 assume !(0 == ~T5_E~0); 47551#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47836#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47837#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48319#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48583#L1135-3 assume !(0 == ~T10_E~0); 47757#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47251#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47252#L1150-3 assume !(0 == ~E_2~0); 47375#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47376#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47738#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47739#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 48117#L1175-3 assume !(0 == ~E_7~0); 47648#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47405#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47406#L1190-3 assume !(0 == ~E_10~0); 48576#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 48577#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47964#L525-36 assume !(1 == ~m_pc~0); 47965#L525-38 is_master_triggered_~__retres1~0#1 := 0; 47506#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47507#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47795#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 47796#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47702#L544-36 assume 1 == ~t1_pc~0; 47703#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 48234#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47590#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47591#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48558#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48456#L563-36 assume 1 == ~t2_pc~0; 47493#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47249#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47250#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48327#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47978#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47979#L582-36 assume 1 == ~t3_pc~0; 47827#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47828#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48055#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48225#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 48015#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47958#L601-36 assume 1 == ~t4_pc~0; 47856#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47857#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48631#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48541#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48542#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48444#L620-36 assume 1 == ~t5_pc~0; 47898#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47899#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48302#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47884#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47515#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47293#L639-36 assume 1 == ~t6_pc~0; 47294#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47333#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47334#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47573#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47574#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48158#L658-36 assume !(1 == ~t7_pc~0); 47304#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 47305#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48525#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47280#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 47281#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48286#L677-36 assume !(1 == ~t8_pc~0); 48081#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 48082#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48201#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48603#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 48104#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48105#L696-36 assume 1 == ~t9_pc~0; 47997#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47999#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47353#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47354#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 48118#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48119#L715-36 assume !(1 == ~t10_pc~0); 48088#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 47180#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47181#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47154#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47155#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47559#L734-36 assume 1 == ~t11_pc~0; 47560#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 47259#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47581#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47172#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 47173#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48181#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47844#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47845#L1218-3 assume !(1 == ~T2_E~0); 47610#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47611#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47803#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47804#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48051#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48052#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 48540#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 48545#L1258-3 assume !(1 == ~T10_E~0); 47592#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47593#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48508#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48528#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48530#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47929#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47930#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47793#L1298-3 assume !(1 == ~E_7~0); 47794#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 48256#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47790#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47791#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 47594#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 47595#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 47534#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 47950#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 48401#L1663 assume !(0 == start_simulation_~tmp~3#1); 47427#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 48156#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 47371#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 48075#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 47315#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 47316#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47655#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 48599#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 47678#L1644-2 [2021-11-13 18:15:49,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:49,715 INFO L85 PathProgramCache]: Analyzing trace with hash -2060717699, now seen corresponding path program 1 times [2021-11-13 18:15:49,715 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:49,715 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [153605567] [2021-11-13 18:15:49,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:49,715 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:49,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:49,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:49,756 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:49,756 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [153605567] [2021-11-13 18:15:49,756 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [153605567] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:49,756 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:49,756 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:49,757 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1854660892] [2021-11-13 18:15:49,757 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:49,757 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:49,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:49,758 INFO L85 PathProgramCache]: Analyzing trace with hash 23261701, now seen corresponding path program 1 times [2021-11-13 18:15:49,758 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:49,758 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1191987818] [2021-11-13 18:15:49,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:49,758 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:49,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:49,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:49,802 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:49,802 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1191987818] [2021-11-13 18:15:49,802 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1191987818] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:49,802 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:49,802 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 18:15:49,802 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [924692270] [2021-11-13 18:15:49,803 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:49,803 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:49,803 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:49,804 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:15:49,804 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:15:49,804 INFO L87 Difference]: Start difference. First operand 1518 states and 2197 transitions. cyclomatic complexity: 680 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:50,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:50,085 INFO L93 Difference]: Finished difference Result 4068 states and 5819 transitions. [2021-11-13 18:15:50,085 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:15:50,086 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4068 states and 5819 transitions. [2021-11-13 18:15:50,110 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3828 [2021-11-13 18:15:50,126 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4068 states to 4068 states and 5819 transitions. [2021-11-13 18:15:50,126 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4068 [2021-11-13 18:15:50,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4068 [2021-11-13 18:15:50,131 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4068 states and 5819 transitions. [2021-11-13 18:15:50,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:50,137 INFO L681 BuchiCegarLoop]: Abstraction has 4068 states and 5819 transitions. [2021-11-13 18:15:50,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4068 states and 5819 transitions. [2021-11-13 18:15:50,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4068 to 3902. [2021-11-13 18:15:50,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3902 states, 3902 states have (on average 1.433111225012814) internal successors, (5592), 3901 states have internal predecessors, (5592), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:50,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3902 states to 3902 states and 5592 transitions. [2021-11-13 18:15:50,219 INFO L704 BuchiCegarLoop]: Abstraction has 3902 states and 5592 transitions. [2021-11-13 18:15:50,253 INFO L587 BuchiCegarLoop]: Abstraction has 3902 states and 5592 transitions. [2021-11-13 18:15:50,253 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-13 18:15:50,254 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3902 states and 5592 transitions. [2021-11-13 18:15:50,273 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3750 [2021-11-13 18:15:50,273 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:50,274 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:50,276 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:50,277 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:50,277 INFO L791 eck$LassoCheckResult]: Stem: 53889#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 53890#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 53899#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53900#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53653#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 53654#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53521#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53431#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53153#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52788#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 52789#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 52837#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 52838#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53779#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 53780#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53825#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53254#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53255#L1090 assume !(0 == ~M_E~0); 53302#L1090-2 assume !(0 == ~T1_E~0); 53303#L1095-1 assume !(0 == ~T2_E~0); 53961#L1100-1 assume !(0 == ~T3_E~0); 53962#L1105-1 assume !(0 == ~T4_E~0); 53072#L1110-1 assume !(0 == ~T5_E~0); 53073#L1115-1 assume !(0 == ~T6_E~0); 53472#L1120-1 assume !(0 == ~T7_E~0); 53755#L1125-1 assume !(0 == ~T8_E~0); 54284#L1130-1 assume !(0 == ~T9_E~0); 53984#L1135-1 assume !(0 == ~T10_E~0); 53261#L1140-1 assume !(0 == ~T11_E~0); 53262#L1145-1 assume !(0 == ~E_1~0); 53914#L1150-1 assume !(0 == ~E_2~0); 53445#L1155-1 assume !(0 == ~E_3~0); 53446#L1160-1 assume !(0 == ~E_4~0); 53529#L1165-1 assume !(0 == ~E_5~0); 53530#L1170-1 assume !(0 == ~E_6~0); 54174#L1175-1 assume !(0 == ~E_7~0); 53608#L1180-1 assume !(0 == ~E_8~0); 53609#L1185-1 assume !(0 == ~E_9~0); 53256#L1190-1 assume !(0 == ~E_10~0); 53257#L1195-1 assume !(0 == ~E_11~0); 53622#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53467#L525 assume !(1 == ~m_pc~0); 52876#L525-2 is_master_triggered_~__retres1~0#1 := 0; 52877#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53626#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53627#L1350 assume !(0 != activate_threads_~tmp~1#1); 53244#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53245#L544 assume !(1 == ~t1_pc~0); 53468#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53469#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53912#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53092#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 53093#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53725#L563 assume !(1 == ~t2_pc~0); 53901#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 52897#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52898#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53331#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 53332#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53801#L582 assume 1 == ~t3_pc~0; 53037#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53038#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54243#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54185#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 52971#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52972#L601 assume !(1 == ~t4_pc~0); 53930#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 53473#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53474#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53924#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 53925#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54235#L620 assume 1 == ~t5_pc~0; 52930#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 52931#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53751#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53752#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 54256#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54257#L639 assume !(1 == ~t6_pc~0); 53753#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 53367#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53368#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54187#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 53478#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53479#L658 assume !(1 == ~t7_pc~0); 53675#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53676#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53787#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53788#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 53250#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53251#L677 assume 1 == ~t8_pc~0; 53484#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53058#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53059#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53325#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 53326#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54025#L696 assume !(1 == ~t9_pc~0); 53739#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 53740#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53833#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53761#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53762#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53965#L715 assume 1 == ~t10_pc~0; 53972#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53847#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53728#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53729#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 53599#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53046#L734 assume !(1 == ~t11_pc~0); 53047#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 53536#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53613#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52778#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 52779#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53816#L1213 assume !(1 == ~M_E~0); 53597#L1213-2 assume !(1 == ~T1_E~0); 53598#L1218-1 assume !(1 == ~T2_E~0); 52813#L1223-1 assume !(1 == ~T3_E~0); 52814#L1228-1 assume !(1 == ~T4_E~0); 53576#L1233-1 assume !(1 == ~T5_E~0); 54258#L1238-1 assume !(1 == ~T6_E~0); 53922#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53923#L1248-1 assume !(1 == ~T8_E~0); 53970#L1253-1 assume !(1 == ~T9_E~0); 53971#L1258-1 assume !(1 == ~T10_E~0); 53946#L1263-1 assume !(1 == ~T11_E~0); 53947#L1268-1 assume !(1 == ~E_1~0); 53775#L1273-1 assume !(1 == ~E_2~0); 53776#L1278-1 assume !(1 == ~E_3~0); 53365#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 53366#L1288-1 assume !(1 == ~E_5~0); 54070#L1293-1 assume !(1 == ~E_6~0); 54030#L1298-1 assume !(1 == ~E_7~0); 53804#L1303-1 assume !(1 == ~E_8~0); 53376#L1308-1 assume !(1 == ~E_9~0); 53267#L1313-1 assume !(1 == ~E_10~0); 53268#L1318-1 assume !(1 == ~E_11~0); 53278#L1323-1 assume { :end_inline_reset_delta_events } true; 53279#L1644-2 [2021-11-13 18:15:50,278 INFO L793 eck$LassoCheckResult]: Loop: 53279#L1644-2 assume !false; 56067#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 56063#L1065 assume !false; 54253#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 54254#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 52895#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 54141#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 53381#L906 assume !(0 != eval_~tmp~0#1); 53383#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53936#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53937#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54090#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54146#L1095-3 assume !(0 == ~T2_E~0); 54106#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54107#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53148#L1110-3 assume !(0 == ~T5_E~0); 53149#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53432#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53433#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53919#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54202#L1135-3 assume !(0 == ~T10_E~0); 53356#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 52849#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52850#L1150-3 assume !(0 == ~E_2~0); 52973#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52974#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53337#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53338#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53717#L1175-3 assume !(0 == ~E_7~0); 53246#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53003#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53004#L1190-3 assume !(0 == ~E_10~0); 54190#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 54191#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53559#L525-36 assume !(1 == ~m_pc~0); 53560#L525-38 is_master_triggered_~__retres1~0#1 := 0; 56546#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56545#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56544#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 56543#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53300#L544-36 assume !(1 == ~t1_pc~0); 53301#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 53836#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53188#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53189#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54171#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54061#L563-36 assume 1 == ~t2_pc~0; 53090#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52847#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52848#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53928#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53574#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53575#L582-36 assume !(1 == ~t3_pc~0); 53425#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 53424#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53652#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53827#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53612#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53554#L601-36 assume !(1 == ~t4_pc~0); 53555#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 56425#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56424#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 56423#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54228#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54048#L620-36 assume 1 == ~t5_pc~0; 53496#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53497#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53902#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53481#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 53112#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52891#L639-36 assume 1 == ~t6_pc~0; 52892#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52928#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52929#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53167#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53168#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53758#L658-36 assume !(1 == ~t7_pc~0); 52902#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 52903#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54136#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52878#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 52879#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53886#L677-36 assume 1 == ~t8_pc~0; 54183#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53679#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53802#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54227#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53701#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53702#L696-36 assume 1 == ~t9_pc~0; 53593#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53595#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52951#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52952#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53718#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53719#L715-36 assume 1 == ~t10_pc~0; 53856#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 52776#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52777#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52752#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 52753#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53157#L734-36 assume 1 == ~t11_pc~0; 53158#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 52857#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53179#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52770#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 52771#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53781#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 53441#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53442#L1218-3 assume !(1 == ~T2_E~0); 53208#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53209#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53399#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53400#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53648#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53649#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54152#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54158#L1258-3 assume !(1 == ~T10_E~0); 53190#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53191#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54117#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54138#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54140#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53525#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53526#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53389#L1298-3 assume !(1 == ~E_7~0); 53390#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53857#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 53386#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 53387#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53192#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 53193#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 56262#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 54004#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 54005#L1663 assume !(0 == start_simulation_~tmp~3#1); 53025#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 54283#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 56080#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 56078#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 56076#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 56075#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 56073#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 56071#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 53279#L1644-2 [2021-11-13 18:15:50,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:50,279 INFO L85 PathProgramCache]: Analyzing trace with hash -2098164388, now seen corresponding path program 1 times [2021-11-13 18:15:50,279 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:50,279 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [587958521] [2021-11-13 18:15:50,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:50,279 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:50,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:50,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:50,319 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:50,319 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [587958521] [2021-11-13 18:15:50,319 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [587958521] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:50,319 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:50,320 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:50,320 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1053459939] [2021-11-13 18:15:50,320 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:50,320 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:50,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:50,321 INFO L85 PathProgramCache]: Analyzing trace with hash -1860414556, now seen corresponding path program 1 times [2021-11-13 18:15:50,321 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:50,321 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [127710770] [2021-11-13 18:15:50,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:50,322 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:50,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:50,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:50,364 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:50,364 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [127710770] [2021-11-13 18:15:50,364 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [127710770] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:50,364 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:50,364 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 18:15:50,365 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [726922783] [2021-11-13 18:15:50,365 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:50,365 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:50,365 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:50,366 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:15:50,366 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:15:50,367 INFO L87 Difference]: Start difference. First operand 3902 states and 5592 transitions. cyclomatic complexity: 1692 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:50,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:50,696 INFO L93 Difference]: Finished difference Result 10909 states and 15500 transitions. [2021-11-13 18:15:50,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:15:50,697 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10909 states and 15500 transitions. [2021-11-13 18:15:50,767 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10559 [2021-11-13 18:15:50,815 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10909 states to 10909 states and 15500 transitions. [2021-11-13 18:15:50,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10909 [2021-11-13 18:15:50,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10909 [2021-11-13 18:15:50,828 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10909 states and 15500 transitions. [2021-11-13 18:15:50,842 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:50,842 INFO L681 BuchiCegarLoop]: Abstraction has 10909 states and 15500 transitions. [2021-11-13 18:15:50,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10909 states and 15500 transitions. [2021-11-13 18:15:51,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10909 to 10528. [2021-11-13 18:15:51,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10528 states, 10528 states have (on average 1.4232522796352585) internal successors, (14984), 10527 states have internal predecessors, (14984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:51,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10528 states to 10528 states and 14984 transitions. [2021-11-13 18:15:51,058 INFO L704 BuchiCegarLoop]: Abstraction has 10528 states and 14984 transitions. [2021-11-13 18:15:51,058 INFO L587 BuchiCegarLoop]: Abstraction has 10528 states and 14984 transitions. [2021-11-13 18:15:51,058 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-13 18:15:51,059 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10528 states and 14984 transitions. [2021-11-13 18:15:51,106 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10367 [2021-11-13 18:15:51,107 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:51,107 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:51,171 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:51,171 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:51,171 INFO L791 eck$LassoCheckResult]: Stem: 68712#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 68713#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 68720#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68721#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68478#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 68479#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68345#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68254#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67972#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 67611#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 67612#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 67660#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 67661#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68602#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 68603#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 68647#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 68078#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68079#L1090 assume !(0 == ~M_E~0); 68123#L1090-2 assume !(0 == ~T1_E~0); 68124#L1095-1 assume !(0 == ~T2_E~0); 68785#L1100-1 assume !(0 == ~T3_E~0); 68786#L1105-1 assume !(0 == ~T4_E~0); 67890#L1110-1 assume !(0 == ~T5_E~0); 67891#L1115-1 assume !(0 == ~T6_E~0); 68294#L1120-1 assume !(0 == ~T7_E~0); 68578#L1125-1 assume !(0 == ~T8_E~0); 69112#L1130-1 assume !(0 == ~T9_E~0); 68809#L1135-1 assume !(0 == ~T10_E~0); 68085#L1140-1 assume !(0 == ~T11_E~0); 68086#L1145-1 assume !(0 == ~E_1~0); 68738#L1150-1 assume !(0 == ~E_2~0); 68268#L1155-1 assume !(0 == ~E_3~0); 68269#L1160-1 assume !(0 == ~E_4~0); 68353#L1165-1 assume !(0 == ~E_5~0); 68354#L1170-1 assume !(0 == ~E_6~0); 69003#L1175-1 assume !(0 == ~E_7~0); 68431#L1180-1 assume !(0 == ~E_8~0); 68432#L1185-1 assume !(0 == ~E_9~0); 68080#L1190-1 assume !(0 == ~E_10~0); 68081#L1195-1 assume !(0 == ~E_11~0); 68445#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68284#L525 assume !(1 == ~m_pc~0); 67698#L525-2 is_master_triggered_~__retres1~0#1 := 0; 67699#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68449#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68450#L1350 assume !(0 != activate_threads_~tmp~1#1); 68068#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68069#L544 assume !(1 == ~t1_pc~0); 68292#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68293#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68735#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 67911#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 67912#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68548#L563 assume !(1 == ~t2_pc~0); 68722#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 67719#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67720#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68150#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 68151#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68625#L582 assume !(1 == ~t3_pc~0); 68736#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69070#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69071#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69012#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 67793#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67794#L601 assume !(1 == ~t4_pc~0); 68754#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68295#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68296#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68748#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 68749#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69062#L620 assume 1 == ~t5_pc~0; 67748#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 67749#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68574#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68575#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 69085#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69086#L639 assume !(1 == ~t6_pc~0); 68576#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 68188#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68189#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69015#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 68302#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68303#L658 assume !(1 == ~t7_pc~0); 68498#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68499#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68612#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68613#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 68074#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68075#L677 assume 1 == ~t8_pc~0; 68306#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 67874#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 67875#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 68147#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 68148#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68851#L696 assume !(1 == ~t9_pc~0); 68560#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 68561#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 68652#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 68583#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 68584#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 68790#L715 assume 1 == ~t10_pc~0; 68797#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 68669#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 68551#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 68552#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 68422#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67863#L734 assume !(1 == ~t11_pc~0); 67864#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 68357#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68436#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 67601#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 67602#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68640#L1213 assume !(1 == ~M_E~0); 68419#L1213-2 assume !(1 == ~T1_E~0); 68420#L1218-1 assume !(1 == ~T2_E~0); 67636#L1223-1 assume !(1 == ~T3_E~0); 67637#L1228-1 assume !(1 == ~T4_E~0); 68400#L1233-1 assume !(1 == ~T5_E~0); 69087#L1238-1 assume !(1 == ~T6_E~0); 68746#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 68747#L1248-1 assume !(1 == ~T8_E~0); 68795#L1253-1 assume !(1 == ~T9_E~0); 68796#L1258-1 assume !(1 == ~T10_E~0); 68771#L1263-1 assume !(1 == ~T11_E~0); 68772#L1268-1 assume !(1 == ~E_1~0); 68600#L1273-1 assume !(1 == ~E_2~0); 68601#L1278-1 assume !(1 == ~E_3~0); 68186#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 68187#L1288-1 assume !(1 == ~E_5~0); 68898#L1293-1 assume !(1 == ~E_6~0); 68855#L1298-1 assume !(1 == ~E_7~0); 68628#L1303-1 assume !(1 == ~E_8~0); 68198#L1308-1 assume !(1 == ~E_9~0); 68091#L1313-1 assume !(1 == ~E_10~0); 68092#L1318-1 assume !(1 == ~E_11~0); 68099#L1323-1 assume { :end_inline_reset_delta_events } true; 68100#L1644-2 [2021-11-13 18:15:51,172 INFO L793 eck$LassoCheckResult]: Loop: 68100#L1644-2 assume !false; 75769#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77203#L1065 assume !false; 77202#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 76755#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 76745#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 76744#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 76742#L906 assume !(0 != eval_~tmp~0#1); 76743#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77120#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77119#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 77118#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 77117#L1095-3 assume !(0 == ~T2_E~0); 77116#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69082#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67967#L1110-3 assume !(0 == ~T5_E~0); 67968#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 68255#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 68256#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 68743#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69031#L1135-3 assume !(0 == ~T10_E~0); 69096#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 77109#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 77108#L1150-3 assume !(0 == ~E_2~0); 77107#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69133#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 68159#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 68160#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 68541#L1175-3 assume !(0 == ~E_7~0); 68070#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 67825#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 67826#L1190-3 assume !(0 == ~E_10~0); 69018#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 69019#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68379#L525-36 assume !(1 == ~m_pc~0); 68380#L525-38 is_master_triggered_~__retres1~0#1 := 0; 67922#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67923#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68213#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 68214#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68121#L544-36 assume !(1 == ~t1_pc~0); 68122#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 68658#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68011#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68012#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 69000#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68889#L563-36 assume 1 == ~t2_pc~0; 67909#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 67667#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67668#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68752#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 68398#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68399#L582-36 assume !(1 == ~t3_pc~0); 68912#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 68476#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68477#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 68649#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 68435#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68378#L601-36 assume 1 == ~t4_pc~0; 68277#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68278#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69091#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68983#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 68984#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68876#L620-36 assume 1 == ~t5_pc~0; 68320#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 68321#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68727#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68305#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 67931#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 67713#L639-36 assume !(1 == ~t6_pc~0); 67715#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 67753#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 67754#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 67988#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 67989#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68581#L658-36 assume !(1 == ~t7_pc~0); 67724#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 67725#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68967#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 67700#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 67701#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68709#L677-36 assume !(1 == ~t8_pc~0); 68503#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 68504#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68626#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69055#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 68527#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68528#L696-36 assume !(1 == ~t9_pc~0); 68417#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 68418#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 67770#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 67771#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 68542#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 68543#L715-36 assume 1 == ~t10_pc~0; 68679#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 67599#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 67600#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 67575#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 67576#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67973#L734-36 assume 1 == ~t11_pc~0; 67974#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 67677#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 67998#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 67593#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 67594#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68606#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 68262#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68263#L1218-3 assume !(1 == ~T2_E~0); 68028#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68029#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68221#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 68222#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 68472#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 68473#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 68982#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 68986#L1258-3 assume !(1 == ~T10_E~0); 68009#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 68010#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 76450#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 76448#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 76447#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 76446#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 76429#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 76428#L1298-3 assume !(1 == ~E_7~0); 76427#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 76426#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 76425#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 76424#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 76423#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 76153#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 76133#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 76121#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 76120#L1663 assume !(0 == start_simulation_~tmp~3#1); 76118#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 75928#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 75923#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 75812#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 75807#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 75796#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 75786#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 75777#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 68100#L1644-2 [2021-11-13 18:15:51,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:51,172 INFO L85 PathProgramCache]: Analyzing trace with hash 919650235, now seen corresponding path program 1 times [2021-11-13 18:15:51,172 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:51,172 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1853941767] [2021-11-13 18:15:51,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:51,173 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:51,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:51,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:51,214 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:51,215 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1853941767] [2021-11-13 18:15:51,215 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1853941767] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:51,215 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:51,215 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:51,215 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1753055508] [2021-11-13 18:15:51,216 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:51,216 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:51,216 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:51,216 INFO L85 PathProgramCache]: Analyzing trace with hash 600360354, now seen corresponding path program 1 times [2021-11-13 18:15:51,217 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:51,217 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [502575835] [2021-11-13 18:15:51,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:51,217 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:51,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:51,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:51,253 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:51,254 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [502575835] [2021-11-13 18:15:51,254 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [502575835] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:51,254 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:51,254 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 18:15:51,254 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [739571320] [2021-11-13 18:15:51,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:51,255 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:51,255 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:51,256 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:15:51,256 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:15:51,256 INFO L87 Difference]: Start difference. First operand 10528 states and 14984 transitions. cyclomatic complexity: 4460 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:51,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:51,621 INFO L93 Difference]: Finished difference Result 29805 states and 42123 transitions. [2021-11-13 18:15:51,622 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:15:51,622 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29805 states and 42123 transitions. [2021-11-13 18:15:51,827 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 29227 [2021-11-13 18:15:51,947 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29805 states to 29805 states and 42123 transitions. [2021-11-13 18:15:51,947 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29805 [2021-11-13 18:15:51,985 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29805 [2021-11-13 18:15:51,985 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29805 states and 42123 transitions. [2021-11-13 18:15:52,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:52,013 INFO L681 BuchiCegarLoop]: Abstraction has 29805 states and 42123 transitions. [2021-11-13 18:15:52,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29805 states and 42123 transitions. [2021-11-13 18:15:52,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29805 to 28957. [2021-11-13 18:15:52,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28957 states, 28957 states have (on average 1.415409054805401) internal successors, (40986), 28956 states have internal predecessors, (40986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:52,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28957 states to 28957 states and 40986 transitions. [2021-11-13 18:15:52,762 INFO L704 BuchiCegarLoop]: Abstraction has 28957 states and 40986 transitions. [2021-11-13 18:15:52,762 INFO L587 BuchiCegarLoop]: Abstraction has 28957 states and 40986 transitions. [2021-11-13 18:15:52,762 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-13 18:15:52,762 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28957 states and 40986 transitions. [2021-11-13 18:15:52,970 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 28777 [2021-11-13 18:15:52,970 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:52,971 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:52,973 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:52,973 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:52,974 INFO L791 eck$LassoCheckResult]: Stem: 109083#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 109084#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 109091#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 109092#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 108832#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 108833#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 108695#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 108603#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 108318#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 107956#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 107957#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 108005#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 108006#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 108965#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 108966#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 109007#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 108424#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 108425#L1090 assume !(0 == ~M_E~0); 108470#L1090-2 assume !(0 == ~T1_E~0); 108471#L1095-1 assume !(0 == ~T2_E~0); 109163#L1100-1 assume !(0 == ~T3_E~0); 109164#L1105-1 assume !(0 == ~T4_E~0); 108233#L1110-1 assume !(0 == ~T5_E~0); 108234#L1115-1 assume !(0 == ~T6_E~0); 108642#L1120-1 assume !(0 == ~T7_E~0); 108938#L1125-1 assume !(0 == ~T8_E~0); 109562#L1130-1 assume !(0 == ~T9_E~0); 109187#L1135-1 assume !(0 == ~T10_E~0); 108429#L1140-1 assume !(0 == ~T11_E~0); 108430#L1145-1 assume !(0 == ~E_1~0); 109110#L1150-1 assume !(0 == ~E_2~0); 108616#L1155-1 assume !(0 == ~E_3~0); 108617#L1160-1 assume !(0 == ~E_4~0); 108704#L1165-1 assume !(0 == ~E_5~0); 108705#L1170-1 assume !(0 == ~E_6~0); 109408#L1175-1 assume !(0 == ~E_7~0); 108784#L1180-1 assume !(0 == ~E_8~0); 108785#L1185-1 assume !(0 == ~E_9~0); 108426#L1190-1 assume !(0 == ~E_10~0); 108427#L1195-1 assume !(0 == ~E_11~0); 108798#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 108632#L525 assume !(1 == ~m_pc~0); 108042#L525-2 is_master_triggered_~__retres1~0#1 := 0; 108043#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 108802#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 108803#L1350 assume !(0 != activate_threads_~tmp~1#1); 108412#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 108413#L544 assume !(1 == ~t1_pc~0); 108640#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 108641#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 109107#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 108255#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 108256#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108907#L563 assume !(1 == ~t2_pc~0); 109093#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 108066#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 108067#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 108499#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 108500#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 108990#L582 assume !(1 == ~t3_pc~0); 109108#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 109497#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 109498#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 109421#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 108136#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 108137#L601 assume !(1 == ~t4_pc~0); 109129#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 108643#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108644#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 109123#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 109124#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 109486#L620 assume !(1 == ~t5_pc~0); 108955#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 108956#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 108934#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 108935#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 109518#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 109519#L639 assume !(1 == ~t6_pc~0); 108936#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 108537#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 108538#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 109424#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 108650#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 108651#L658 assume !(1 == ~t7_pc~0); 108854#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 108855#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 108975#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 108976#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 108420#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 108421#L677 assume 1 == ~t8_pc~0; 108654#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 108214#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 108215#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 108496#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 108497#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 109233#L696 assume !(1 == ~t9_pc~0); 108918#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 108919#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 109018#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 108942#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 108943#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 109168#L715 assume 1 == ~t10_pc~0; 109175#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 109035#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 108910#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 108911#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 108775#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 108206#L734 assume !(1 == ~t11_pc~0); 108207#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 108708#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 108789#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 107944#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 107945#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 109005#L1213 assume !(1 == ~M_E~0); 108772#L1213-2 assume !(1 == ~T1_E~0); 108773#L1218-1 assume !(1 == ~T2_E~0); 107981#L1223-1 assume !(1 == ~T3_E~0); 107982#L1228-1 assume !(1 == ~T4_E~0); 108752#L1233-1 assume !(1 == ~T5_E~0); 109520#L1238-1 assume !(1 == ~T6_E~0); 109121#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 109122#L1248-1 assume !(1 == ~T8_E~0); 109173#L1253-1 assume !(1 == ~T9_E~0); 109174#L1258-1 assume !(1 == ~T10_E~0); 109149#L1263-1 assume !(1 == ~T11_E~0); 109150#L1268-1 assume !(1 == ~E_1~0); 108963#L1273-1 assume !(1 == ~E_2~0); 108964#L1278-1 assume !(1 == ~E_3~0); 108535#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 108536#L1288-1 assume !(1 == ~E_5~0); 109287#L1293-1 assume !(1 == ~E_6~0); 109238#L1298-1 assume !(1 == ~E_7~0); 108993#L1303-1 assume !(1 == ~E_8~0); 108546#L1308-1 assume !(1 == ~E_9~0); 108435#L1313-1 assume !(1 == ~E_10~0); 108436#L1318-1 assume !(1 == ~E_11~0); 108445#L1323-1 assume { :end_inline_reset_delta_events } true; 108446#L1644-2 [2021-11-13 18:15:52,974 INFO L793 eck$LassoCheckResult]: Loop: 108446#L1644-2 assume !false; 109048#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 109049#L1065 assume !false; 109515#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 109516#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 133981#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 133980#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 133978#L906 assume !(0 != eval_~tmp~0#1); 133979#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 136237#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 136236#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 136235#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 136234#L1095-3 assume !(0 == ~T2_E~0); 136233#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 136232#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 136231#L1110-3 assume !(0 == ~T5_E~0); 136230#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 136229#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 136228#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 136227#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 136226#L1135-3 assume !(0 == ~T10_E~0); 136225#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 136224#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 136223#L1150-3 assume !(0 == ~E_2~0); 136222#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 136221#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 136220#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 136219#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 136218#L1175-3 assume !(0 == ~E_7~0); 136217#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 136216#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 136215#L1190-3 assume !(0 == ~E_10~0); 136214#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 136213#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 136212#L525-36 assume !(1 == ~m_pc~0); 136211#L525-38 is_master_triggered_~__retres1~0#1 := 0; 136210#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 136209#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 136208#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 136207#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 136206#L544-36 assume !(1 == ~t1_pc~0); 136205#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 136204#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 136203#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 136202#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 136201#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 136200#L563-36 assume !(1 == ~t2_pc~0); 136198#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 136197#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 136196#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 136195#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 136194#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 136193#L582-36 assume !(1 == ~t3_pc~0); 136192#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 136191#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 136190#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 136189#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 136188#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 136187#L601-36 assume 1 == ~t4_pc~0; 136186#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 136184#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 136183#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 136182#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 136181#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 136180#L620-36 assume !(1 == ~t5_pc~0); 136179#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 136178#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 136177#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 136176#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 136175#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 136174#L639-36 assume !(1 == ~t6_pc~0); 136172#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 136171#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 136170#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 136169#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 136168#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 136167#L658-36 assume !(1 == ~t7_pc~0); 136165#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 136164#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 136163#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 136162#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 136161#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 136160#L677-36 assume 1 == ~t8_pc~0; 136158#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 136157#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 136156#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 136155#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 136154#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 136153#L696-36 assume !(1 == ~t9_pc~0); 136151#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 136150#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 136149#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 136148#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 136147#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 136146#L715-36 assume 1 == ~t10_pc~0; 136144#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 136143#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 136142#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 136141#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 136140#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 136139#L734-36 assume 1 == ~t11_pc~0; 136138#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 136136#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 108755#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 107938#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 107939#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 108969#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 108612#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 108613#L1218-3 assume !(1 == ~T2_E~0); 108375#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 108376#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 108569#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 108570#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 108826#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 108827#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 136072#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 136070#L1258-3 assume !(1 == ~T10_E~0); 136068#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 136066#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 136064#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 136061#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 136059#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 136057#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 136055#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 136053#L1298-3 assume !(1 == ~E_7~0); 136051#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 136048#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 136046#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 136044#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 136042#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 136040#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 108721#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 108722#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 109602#L1663 assume !(0 == start_simulation_~tmp~3#1); 108190#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 109561#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 135751#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 135750#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 108081#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 108082#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 108423#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 109550#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 108446#L1644-2 [2021-11-13 18:15:52,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:52,975 INFO L85 PathProgramCache]: Analyzing trace with hash -258324326, now seen corresponding path program 1 times [2021-11-13 18:15:52,975 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:52,975 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1298710628] [2021-11-13 18:15:52,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:52,976 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:53,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:53,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:53,036 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:53,036 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1298710628] [2021-11-13 18:15:53,037 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1298710628] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:53,037 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:53,037 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:15:53,037 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425886399] [2021-11-13 18:15:53,037 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:53,038 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:53,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:53,041 INFO L85 PathProgramCache]: Analyzing trace with hash 1585288321, now seen corresponding path program 1 times [2021-11-13 18:15:53,041 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:53,041 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [28738550] [2021-11-13 18:15:53,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:53,041 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:53,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:53,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:53,094 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:53,094 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [28738550] [2021-11-13 18:15:53,094 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [28738550] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:53,094 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:53,094 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 18:15:53,095 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1518164954] [2021-11-13 18:15:53,095 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:53,096 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:53,096 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:53,096 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:15:53,097 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:15:53,097 INFO L87 Difference]: Start difference. First operand 28957 states and 40986 transitions. cyclomatic complexity: 12037 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:53,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:53,744 INFO L93 Difference]: Finished difference Result 81863 states and 115204 transitions. [2021-11-13 18:15:53,745 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:15:53,745 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81863 states and 115204 transitions. [2021-11-13 18:15:54,525 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 80806 [2021-11-13 18:15:54,848 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81863 states to 81863 states and 115204 transitions. [2021-11-13 18:15:54,848 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 81863 [2021-11-13 18:15:55,051 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 81863 [2021-11-13 18:15:55,051 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81863 states and 115204 transitions. [2021-11-13 18:15:55,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:15:55,125 INFO L681 BuchiCegarLoop]: Abstraction has 81863 states and 115204 transitions. [2021-11-13 18:15:55,203 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81863 states and 115204 transitions. [2021-11-13 18:15:56,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81863 to 80242. [2021-11-13 18:15:56,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80242 states, 80242 states have (on average 1.4089379626629446) internal successors, (113056), 80241 states have internal predecessors, (113056), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:56,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80242 states to 80242 states and 113056 transitions. [2021-11-13 18:15:56,823 INFO L704 BuchiCegarLoop]: Abstraction has 80242 states and 113056 transitions. [2021-11-13 18:15:56,823 INFO L587 BuchiCegarLoop]: Abstraction has 80242 states and 113056 transitions. [2021-11-13 18:15:56,823 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-13 18:15:56,823 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80242 states and 113056 transitions. [2021-11-13 18:15:57,286 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 80023 [2021-11-13 18:15:57,286 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:15:57,286 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:15:57,290 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:57,290 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:15:57,291 INFO L791 eck$LassoCheckResult]: Stem: 219933#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 219934#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 219944#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 219945#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 219668#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 219669#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 219534#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 219443#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 219151#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 218788#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 218789#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 218837#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 218838#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 219814#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 219815#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 219857#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 219259#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 219260#L1090 assume !(0 == ~M_E~0); 219304#L1090-2 assume !(0 == ~T1_E~0); 219305#L1095-1 assume !(0 == ~T2_E~0); 220016#L1100-1 assume !(0 == ~T3_E~0); 220017#L1105-1 assume !(0 == ~T4_E~0); 219066#L1110-1 assume !(0 == ~T5_E~0); 219067#L1115-1 assume !(0 == ~T6_E~0); 219483#L1120-1 assume !(0 == ~T7_E~0); 219785#L1125-1 assume !(0 == ~T8_E~0); 220450#L1130-1 assume !(0 == ~T9_E~0); 220043#L1135-1 assume !(0 == ~T10_E~0); 219265#L1140-1 assume !(0 == ~T11_E~0); 219266#L1145-1 assume !(0 == ~E_1~0); 219963#L1150-1 assume !(0 == ~E_2~0); 219457#L1155-1 assume !(0 == ~E_3~0); 219458#L1160-1 assume !(0 == ~E_4~0); 219544#L1165-1 assume !(0 == ~E_5~0); 219545#L1170-1 assume !(0 == ~E_6~0); 220270#L1175-1 assume !(0 == ~E_7~0); 219624#L1180-1 assume !(0 == ~E_8~0); 219625#L1185-1 assume !(0 == ~E_9~0); 219261#L1190-1 assume !(0 == ~E_10~0); 219262#L1195-1 assume !(0 == ~E_11~0); 219638#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 219473#L525 assume !(1 == ~m_pc~0); 218874#L525-2 is_master_triggered_~__retres1~0#1 := 0; 218875#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 219641#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 219642#L1350 assume !(0 != activate_threads_~tmp~1#1); 219246#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 219247#L544 assume !(1 == ~t1_pc~0); 219481#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 219482#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 219960#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 219088#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 219089#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 219751#L563 assume !(1 == ~t2_pc~0); 219946#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 218898#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 218899#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 219337#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 219338#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 219839#L582 assume !(1 == ~t3_pc~0); 219961#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 220375#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 220376#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 220281#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 218969#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 218970#L601 assume !(1 == ~t4_pc~0); 219982#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 219484#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 219485#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 219975#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 219976#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 220357#L620 assume !(1 == ~t5_pc~0); 219804#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 219805#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 219781#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 219782#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 220399#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 220400#L639 assume !(1 == ~t6_pc~0); 219783#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 219375#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 219376#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 220287#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 219491#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 219492#L658 assume !(1 == ~t7_pc~0); 219691#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 219692#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 219824#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 219825#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 219254#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 219255#L677 assume !(1 == ~t8_pc~0); 219280#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 219047#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 219048#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 219333#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 219334#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 220088#L696 assume !(1 == ~t9_pc~0); 219763#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 219764#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 219869#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 219789#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 219790#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 220021#L715 assume 1 == ~t10_pc~0; 220029#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 219888#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 219754#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 219755#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 219615#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 219039#L734 assume !(1 == ~t11_pc~0); 219040#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 219548#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 219629#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 218776#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 218777#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 219856#L1213 assume !(1 == ~M_E~0); 219612#L1213-2 assume !(1 == ~T1_E~0); 219613#L1218-1 assume !(1 == ~T2_E~0); 218813#L1223-1 assume !(1 == ~T3_E~0); 218814#L1228-1 assume !(1 == ~T4_E~0); 219591#L1233-1 assume !(1 == ~T5_E~0); 220401#L1238-1 assume !(1 == ~T6_E~0); 219973#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 219974#L1248-1 assume !(1 == ~T8_E~0); 220027#L1253-1 assume !(1 == ~T9_E~0); 220028#L1258-1 assume !(1 == ~T10_E~0); 219999#L1263-1 assume !(1 == ~T11_E~0); 220000#L1268-1 assume !(1 == ~E_1~0); 219812#L1273-1 assume !(1 == ~E_2~0); 219813#L1278-1 assume !(1 == ~E_3~0); 219373#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 219374#L1288-1 assume !(1 == ~E_5~0); 220142#L1293-1 assume !(1 == ~E_6~0); 220094#L1298-1 assume !(1 == ~E_7~0); 219842#L1303-1 assume !(1 == ~E_8~0); 219384#L1308-1 assume !(1 == ~E_9~0); 219271#L1313-1 assume !(1 == ~E_10~0); 219272#L1318-1 assume !(1 == ~E_11~0); 219281#L1323-1 assume { :end_inline_reset_delta_events } true; 219282#L1644-2 [2021-11-13 18:15:57,291 INFO L793 eck$LassoCheckResult]: Loop: 219282#L1644-2 assume !false; 288298#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 288257#L1065 assume !false; 288258#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 288171#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 288162#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 288148#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 288149#L906 assume !(0 != eval_~tmp~0#1); 288878#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 291118#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 291117#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 291116#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 291115#L1095-3 assume !(0 == ~T2_E~0); 291114#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 291113#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 291112#L1110-3 assume !(0 == ~T5_E~0); 291111#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 291110#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 291109#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 291108#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 291107#L1135-3 assume !(0 == ~T10_E~0); 291106#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 291105#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 291104#L1150-3 assume !(0 == ~E_2~0); 291103#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 291102#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 291101#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 291100#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 291099#L1175-3 assume !(0 == ~E_7~0); 291098#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 291097#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 291096#L1190-3 assume !(0 == ~E_10~0); 291095#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 291094#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 291093#L525-36 assume !(1 == ~m_pc~0); 291092#L525-38 is_master_triggered_~__retres1~0#1 := 0; 291091#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 291090#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 291089#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 291088#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 291087#L544-36 assume !(1 == ~t1_pc~0); 291086#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 291085#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 291084#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 291083#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 291082#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 291081#L563-36 assume !(1 == ~t2_pc~0); 291079#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 291078#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 291077#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 291076#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 291075#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 291074#L582-36 assume !(1 == ~t3_pc~0); 291073#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 291072#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 291071#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 291070#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 291069#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 291068#L601-36 assume !(1 == ~t4_pc~0); 291066#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 291065#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 291064#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 291063#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 291062#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 291061#L620-36 assume !(1 == ~t5_pc~0); 291060#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 291059#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 291058#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 291057#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 291056#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 291055#L639-36 assume !(1 == ~t6_pc~0); 291053#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 291052#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 291051#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 291050#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 291049#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 291048#L658-36 assume !(1 == ~t7_pc~0); 291046#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 291045#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 291044#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 291043#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 291042#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 291041#L677-36 assume !(1 == ~t8_pc~0); 291040#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 291039#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 291038#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 291037#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 291036#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 291035#L696-36 assume !(1 == ~t9_pc~0); 291033#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 291032#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 291031#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 291030#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 291029#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 291028#L715-36 assume 1 == ~t10_pc~0; 291026#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 291025#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 291024#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 291023#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 291022#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 291021#L734-36 assume 1 == ~t11_pc~0; 291020#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 291018#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 291017#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 291016#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 291015#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 291014#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 291013#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 291011#L1218-3 assume !(1 == ~T2_E~0); 291009#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 291007#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 291005#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 291003#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 291001#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 290999#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 290998#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 290996#L1258-3 assume !(1 == ~T10_E~0); 290994#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 290992#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 290990#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 290988#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 290985#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 290983#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 290981#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 290979#L1298-3 assume !(1 == ~E_7~0); 290977#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 290975#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 290973#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 290971#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 290969#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 289069#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 288336#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 288334#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 288332#L1663 assume !(0 == start_simulation_~tmp~3#1); 288331#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 288317#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 288311#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 288310#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 288309#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 288304#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 288302#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 288299#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 219282#L1644-2 [2021-11-13 18:15:57,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:57,292 INFO L85 PathProgramCache]: Analyzing trace with hash 1174510393, now seen corresponding path program 1 times [2021-11-13 18:15:57,293 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:57,293 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1257723596] [2021-11-13 18:15:57,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:57,293 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:57,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:57,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:57,344 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:57,344 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1257723596] [2021-11-13 18:15:57,344 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1257723596] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:57,344 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:57,344 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 18:15:57,345 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [381516947] [2021-11-13 18:15:57,346 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:57,346 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:15:57,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:15:57,347 INFO L85 PathProgramCache]: Analyzing trace with hash -776101953, now seen corresponding path program 1 times [2021-11-13 18:15:57,347 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:15:57,347 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2045993649] [2021-11-13 18:15:57,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:15:57,347 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:15:57,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:15:57,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:15:57,387 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:15:57,387 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2045993649] [2021-11-13 18:15:57,387 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2045993649] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:15:57,388 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:15:57,388 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 18:15:57,388 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1463498998] [2021-11-13 18:15:57,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:15:57,389 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:15:57,389 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:15:57,389 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-13 18:15:57,389 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-13 18:15:57,390 INFO L87 Difference]: Start difference. First operand 80242 states and 113056 transitions. cyclomatic complexity: 32830 Second operand has 5 states, 5 states have (on average 27.4) internal successors, (137), 5 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:15:58,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:15:58,707 INFO L93 Difference]: Finished difference Result 186964 states and 266281 transitions. [2021-11-13 18:15:58,708 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-13 18:15:58,708 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 186964 states and 266281 transitions. [2021-11-13 18:15:59,880 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 186529 [2021-11-13 18:16:01,018 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 186964 states to 186964 states and 266281 transitions. [2021-11-13 18:16:01,018 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 186964 [2021-11-13 18:16:01,120 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 186964 [2021-11-13 18:16:01,120 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186964 states and 266281 transitions. [2021-11-13 18:16:01,368 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:16:01,369 INFO L681 BuchiCegarLoop]: Abstraction has 186964 states and 266281 transitions. [2021-11-13 18:16:01,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186964 states and 266281 transitions. [2021-11-13 18:16:02,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186964 to 82561. [2021-11-13 18:16:02,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82561 states, 82561 states have (on average 1.397451581255072) internal successors, (115375), 82560 states have internal predecessors, (115375), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:16:02,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82561 states to 82561 states and 115375 transitions. [2021-11-13 18:16:02,965 INFO L704 BuchiCegarLoop]: Abstraction has 82561 states and 115375 transitions. [2021-11-13 18:16:02,965 INFO L587 BuchiCegarLoop]: Abstraction has 82561 states and 115375 transitions. [2021-11-13 18:16:02,965 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-13 18:16:02,965 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82561 states and 115375 transitions. [2021-11-13 18:16:03,173 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 82339 [2021-11-13 18:16:03,174 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:16:03,174 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:16:03,177 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:16:03,177 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:16:03,177 INFO L791 eck$LassoCheckResult]: Stem: 487170#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 487171#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 487181#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 487182#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 486901#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 486902#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 486764#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 486671#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 486377#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 486009#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 486010#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 486058#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 486059#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 487043#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 487044#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 487088#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 486485#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 486486#L1090 assume !(0 == ~M_E~0); 486531#L1090-2 assume !(0 == ~T1_E~0); 486532#L1095-1 assume !(0 == ~T2_E~0); 487263#L1100-1 assume !(0 == ~T3_E~0); 487264#L1105-1 assume !(0 == ~T4_E~0); 486288#L1110-1 assume !(0 == ~T5_E~0); 486289#L1115-1 assume !(0 == ~T6_E~0); 486711#L1120-1 assume !(0 == ~T7_E~0); 487016#L1125-1 assume !(0 == ~T8_E~0); 487726#L1130-1 assume !(0 == ~T9_E~0); 487288#L1135-1 assume !(0 == ~T10_E~0); 486491#L1140-1 assume !(0 == ~T11_E~0); 486492#L1145-1 assume !(0 == ~E_1~0); 487201#L1150-1 assume !(0 == ~E_2~0); 486685#L1155-1 assume !(0 == ~E_3~0); 486686#L1160-1 assume !(0 == ~E_4~0); 486773#L1165-1 assume !(0 == ~E_5~0); 486774#L1170-1 assume !(0 == ~E_6~0); 487536#L1175-1 assume !(0 == ~E_7~0); 486856#L1180-1 assume !(0 == ~E_8~0); 486857#L1185-1 assume !(0 == ~E_9~0); 486487#L1190-1 assume !(0 == ~E_10~0); 486488#L1195-1 assume !(0 == ~E_11~0); 486871#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 486701#L525 assume !(1 == ~m_pc~0); 486095#L525-2 is_master_triggered_~__retres1~0#1 := 0; 486096#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 486874#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 486875#L1350 assume !(0 != activate_threads_~tmp~1#1); 486474#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 486475#L544 assume !(1 == ~t1_pc~0); 486709#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 486710#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 487198#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 486311#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 486312#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 486985#L563 assume !(1 == ~t2_pc~0); 487183#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 486119#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 486120#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 486560#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 486561#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 487069#L582 assume !(1 == ~t3_pc~0); 487199#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 487645#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 487646#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 487546#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 486189#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 486190#L601 assume !(1 == ~t4_pc~0); 487225#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 486712#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 486713#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 487217#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 487218#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 487628#L620 assume !(1 == ~t5_pc~0); 487033#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 487034#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 487012#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 487013#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 487666#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 487667#L639 assume !(1 == ~t6_pc~0); 487014#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 486599#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 486600#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 487553#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 486719#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 486720#L658 assume !(1 == ~t7_pc~0); 486924#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 486925#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 487053#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 487054#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 486481#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 486482#L677 assume !(1 == ~t8_pc~0); 486507#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 486269#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 486270#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 486557#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 486558#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 487345#L696 assume !(1 == ~t9_pc~0); 486997#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 486998#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 487101#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 487021#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 487022#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 487268#L715 assume 1 == ~t10_pc~0; 487274#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 487120#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 486988#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 486989#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 486847#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 486261#L734 assume !(1 == ~t11_pc~0); 486262#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 486777#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 486861#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 485997#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 485998#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 487087#L1213 assume !(1 == ~M_E~0); 486844#L1213-2 assume !(1 == ~T1_E~0); 486845#L1218-1 assume !(1 == ~T2_E~0); 486034#L1223-1 assume !(1 == ~T3_E~0); 486035#L1228-1 assume !(1 == ~T4_E~0); 486823#L1233-1 assume !(1 == ~T5_E~0); 487668#L1238-1 assume !(1 == ~T6_E~0); 487215#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 487216#L1248-1 assume !(1 == ~T8_E~0); 487272#L1253-1 assume !(1 == ~T9_E~0); 487273#L1258-1 assume !(1 == ~T10_E~0); 487246#L1263-1 assume !(1 == ~T11_E~0); 487247#L1268-1 assume !(1 == ~E_1~0); 487041#L1273-1 assume !(1 == ~E_2~0); 487042#L1278-1 assume !(1 == ~E_3~0); 486597#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 486598#L1288-1 assume !(1 == ~E_5~0); 487396#L1293-1 assume !(1 == ~E_6~0); 487350#L1298-1 assume !(1 == ~E_7~0); 487072#L1303-1 assume !(1 == ~E_8~0); 486610#L1308-1 assume !(1 == ~E_9~0); 486497#L1313-1 assume !(1 == ~E_10~0); 486498#L1318-1 assume !(1 == ~E_11~0); 486508#L1323-1 assume { :end_inline_reset_delta_events } true; 486509#L1644-2 [2021-11-13 18:16:03,178 INFO L793 eck$LassoCheckResult]: Loop: 486509#L1644-2 assume !false; 536475#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 536471#L1065 assume !false; 536450#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 536451#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 536426#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 536427#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 536418#L906 assume !(0 != eval_~tmp~0#1); 536419#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 548964#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 548890#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 548883#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 548875#L1095-3 assume !(0 == ~T2_E~0); 548866#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 548858#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 548851#L1110-3 assume !(0 == ~T5_E~0); 548843#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 548836#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 548828#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 548818#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 548811#L1135-3 assume !(0 == ~T10_E~0); 548802#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 548793#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 548785#L1150-3 assume !(0 == ~E_2~0); 548774#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 548700#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 548692#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 548685#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 548681#L1175-3 assume !(0 == ~E_7~0); 548599#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 548580#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 548508#L1190-3 assume !(0 == ~E_10~0); 548503#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 548497#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 548496#L525-36 assume !(1 == ~m_pc~0); 548495#L525-38 is_master_triggered_~__retres1~0#1 := 0; 548494#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 548493#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 548492#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 548491#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 548490#L544-36 assume !(1 == ~t1_pc~0); 548489#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 548488#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 548487#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 548486#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 548485#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 548484#L563-36 assume !(1 == ~t2_pc~0); 548482#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 548481#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 548480#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 548479#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 548478#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 548477#L582-36 assume !(1 == ~t3_pc~0); 548476#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 548475#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 548474#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 548473#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 548472#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 548471#L601-36 assume !(1 == ~t4_pc~0); 548469#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 548468#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 548467#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 548466#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 548465#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 548464#L620-36 assume !(1 == ~t5_pc~0); 548463#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 548462#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 548461#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 548460#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 548459#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 548458#L639-36 assume !(1 == ~t6_pc~0); 548456#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 548455#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 548454#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 548453#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 548452#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 548451#L658-36 assume !(1 == ~t7_pc~0); 548449#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 548448#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 548447#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 548446#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 548445#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 548444#L677-36 assume !(1 == ~t8_pc~0); 548443#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 548442#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 548441#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 548440#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 548439#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 548438#L696-36 assume 1 == ~t9_pc~0; 548436#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 548434#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 548432#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 548430#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 548423#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 548418#L715-36 assume 1 == ~t10_pc~0; 548412#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 548406#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 548386#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 548377#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 548372#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 548366#L734-36 assume !(1 == ~t11_pc~0); 548293#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 548285#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 548211#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 547602#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 547599#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 547597#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 547595#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 547593#L1218-3 assume !(1 == ~T2_E~0); 547591#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 547589#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 547587#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 547585#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 547583#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 547581#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 547579#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 547577#L1258-3 assume !(1 == ~T10_E~0); 547575#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 547573#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 547571#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 547569#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 547567#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 547565#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 547563#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 547561#L1298-3 assume !(1 == ~E_7~0); 547559#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 547557#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 547555#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 547553#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 547551#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 547549#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 547536#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 547534#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 547532#L1663 assume !(0 == start_simulation_~tmp~3#1); 547530#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 547461#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 547456#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 547455#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 547451#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 547449#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 547447#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 547446#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 486509#L1644-2 [2021-11-13 18:16:03,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:16:03,179 INFO L85 PathProgramCache]: Analyzing trace with hash 145151095, now seen corresponding path program 1 times [2021-11-13 18:16:03,179 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:16:03,179 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1339135295] [2021-11-13 18:16:03,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:16:03,180 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:16:03,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:16:03,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:16:03,617 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:16:03,617 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1339135295] [2021-11-13 18:16:03,617 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1339135295] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:16:03,617 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:16:03,617 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:16:03,618 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1095840859] [2021-11-13 18:16:03,618 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:16:03,618 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:16:03,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:16:03,619 INFO L85 PathProgramCache]: Analyzing trace with hash 1260549695, now seen corresponding path program 1 times [2021-11-13 18:16:03,619 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:16:03,619 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816910692] [2021-11-13 18:16:03,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:16:03,619 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:16:03,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:16:03,686 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:16:03,686 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:16:03,686 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [816910692] [2021-11-13 18:16:03,686 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [816910692] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:16:03,687 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:16:03,687 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 18:16:03,687 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005362489] [2021-11-13 18:16:03,687 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:16:03,687 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:16:03,688 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:16:03,688 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:16:03,688 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:16:03,688 INFO L87 Difference]: Start difference. First operand 82561 states and 115375 transitions. cyclomatic complexity: 32830 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:16:04,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:16:04,678 INFO L93 Difference]: Finished difference Result 232289 states and 323083 transitions. [2021-11-13 18:16:04,679 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:16:04,679 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 232289 states and 323083 transitions. [2021-11-13 18:16:06,004 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 230154 [2021-11-13 18:16:06,952 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 232289 states to 232289 states and 323083 transitions. [2021-11-13 18:16:06,952 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 232289 [2021-11-13 18:16:07,084 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 232289 [2021-11-13 18:16:07,084 INFO L73 IsDeterministic]: Start isDeterministic. Operand 232289 states and 323083 transitions. [2021-11-13 18:16:07,221 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:16:07,221 INFO L681 BuchiCegarLoop]: Abstraction has 232289 states and 323083 transitions. [2021-11-13 18:16:07,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 232289 states and 323083 transitions. [2021-11-13 18:16:09,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 232289 to 229240. [2021-11-13 18:16:09,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 229240 states, 229240 states have (on average 1.3923529924969464) internal successors, (319183), 229239 states have internal predecessors, (319183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:16:10,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 229240 states to 229240 states and 319183 transitions. [2021-11-13 18:16:10,510 INFO L704 BuchiCegarLoop]: Abstraction has 229240 states and 319183 transitions. [2021-11-13 18:16:10,510 INFO L587 BuchiCegarLoop]: Abstraction has 229240 states and 319183 transitions. [2021-11-13 18:16:10,510 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-13 18:16:10,510 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 229240 states and 319183 transitions. [2021-11-13 18:16:11,837 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 228939 [2021-11-13 18:16:11,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:16:11,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:16:11,841 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:16:11,842 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:16:11,842 INFO L791 eck$LassoCheckResult]: Stem: 802050#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 802051#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 802062#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 802063#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 801762#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 801763#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 801625#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 801532#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 801243#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 800871#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 800872#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 800921#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 800922#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 801908#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 801909#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 801957#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 801348#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 801349#L1090 assume !(0 == ~M_E~0); 801394#L1090-2 assume !(0 == ~T1_E~0); 801395#L1095-1 assume !(0 == ~T2_E~0); 802139#L1100-1 assume !(0 == ~T3_E~0); 802140#L1105-1 assume !(0 == ~T4_E~0); 801151#L1110-1 assume !(0 == ~T5_E~0); 801152#L1115-1 assume !(0 == ~T6_E~0); 801573#L1120-1 assume !(0 == ~T7_E~0); 801881#L1125-1 assume !(0 == ~T8_E~0); 802631#L1130-1 assume !(0 == ~T9_E~0); 802164#L1135-1 assume !(0 == ~T10_E~0); 801354#L1140-1 assume !(0 == ~T11_E~0); 801355#L1145-1 assume !(0 == ~E_1~0); 802080#L1150-1 assume !(0 == ~E_2~0); 801547#L1155-1 assume !(0 == ~E_3~0); 801548#L1160-1 assume !(0 == ~E_4~0); 801634#L1165-1 assume !(0 == ~E_5~0); 801635#L1170-1 assume !(0 == ~E_6~0); 802424#L1175-1 assume !(0 == ~E_7~0); 801718#L1180-1 assume !(0 == ~E_8~0); 801719#L1185-1 assume !(0 == ~E_9~0); 801350#L1190-1 assume !(0 == ~E_10~0); 801351#L1195-1 assume !(0 == ~E_11~0); 801733#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 801563#L525 assume !(1 == ~m_pc~0); 800958#L525-2 is_master_triggered_~__retres1~0#1 := 0; 800959#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 801736#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 801737#L1350 assume !(0 != activate_threads_~tmp~1#1); 801337#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 801338#L544 assume !(1 == ~t1_pc~0); 801571#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 801572#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 802077#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 801176#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 801177#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 801847#L563 assume !(1 == ~t2_pc~0); 802064#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 800982#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 800983#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 801424#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 801425#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 801936#L582 assume !(1 == ~t3_pc~0); 802078#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 802543#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 802544#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 802437#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 801054#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 801055#L601 assume !(1 == ~t4_pc~0); 802100#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 801574#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 801575#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 802093#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 802094#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 802526#L620 assume !(1 == ~t5_pc~0); 801898#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 801899#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 801877#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 801878#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 802566#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 802567#L639 assume !(1 == ~t6_pc~0); 801879#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 801465#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 801466#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 802443#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 801581#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 801582#L658 assume !(1 == ~t7_pc~0); 801788#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 801789#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 801920#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 801921#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 801344#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 801345#L677 assume !(1 == ~t8_pc~0); 801369#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 801132#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 801133#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 801420#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 801421#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 802216#L696 assume !(1 == ~t9_pc~0); 801859#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 801860#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 801971#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 801885#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 801886#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 802144#L715 assume !(1 == ~t10_pc~0); 802473#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 801992#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 801850#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 801851#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 801709#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 801124#L734 assume !(1 == ~t11_pc~0); 801125#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 801638#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 801724#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 800859#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 800860#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 801956#L1213 assume !(1 == ~M_E~0); 801706#L1213-2 assume !(1 == ~T1_E~0); 801707#L1218-1 assume !(1 == ~T2_E~0); 800896#L1223-1 assume !(1 == ~T3_E~0); 800897#L1228-1 assume !(1 == ~T4_E~0); 801682#L1233-1 assume !(1 == ~T5_E~0); 802568#L1238-1 assume !(1 == ~T6_E~0); 802091#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 802092#L1248-1 assume !(1 == ~T8_E~0); 802149#L1253-1 assume !(1 == ~T9_E~0); 802150#L1258-1 assume !(1 == ~T10_E~0); 802124#L1263-1 assume !(1 == ~T11_E~0); 802125#L1268-1 assume !(1 == ~E_1~0); 801906#L1273-1 assume !(1 == ~E_2~0); 801907#L1278-1 assume !(1 == ~E_3~0); 801463#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 801464#L1288-1 assume !(1 == ~E_5~0); 802274#L1293-1 assume !(1 == ~E_6~0); 802221#L1298-1 assume !(1 == ~E_7~0); 801939#L1303-1 assume !(1 == ~E_8~0); 801475#L1308-1 assume !(1 == ~E_9~0); 801360#L1313-1 assume !(1 == ~E_10~0); 801361#L1318-1 assume !(1 == ~E_11~0); 801370#L1323-1 assume { :end_inline_reset_delta_events } true; 801371#L1644-2 [2021-11-13 18:16:11,843 INFO L793 eck$LassoCheckResult]: Loop: 801371#L1644-2 assume !false; 967365#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 967356#L1065 assume !false; 967352#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 967344#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 967331#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 967329#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 967005#L906 assume !(0 != eval_~tmp~0#1); 967006#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 968232#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 968230#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 968228#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 968226#L1095-3 assume !(0 == ~T2_E~0); 968224#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 968222#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 968220#L1110-3 assume !(0 == ~T5_E~0); 968218#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 968216#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 968214#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 968211#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 968209#L1135-3 assume !(0 == ~T10_E~0); 968207#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 968205#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 968203#L1150-3 assume !(0 == ~E_2~0); 968200#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 968198#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 968196#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 968194#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 968192#L1175-3 assume !(0 == ~E_7~0); 968190#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 968188#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 968187#L1190-3 assume !(0 == ~E_10~0); 968186#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 968185#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 968184#L525-36 assume !(1 == ~m_pc~0); 968181#L525-38 is_master_triggered_~__retres1~0#1 := 0; 968177#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 968173#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 968171#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 968169#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 968167#L544-36 assume !(1 == ~t1_pc~0); 968164#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 968161#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 968158#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 968155#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 968153#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 968151#L563-36 assume !(1 == ~t2_pc~0); 968148#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 968145#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 968142#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 968141#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 968139#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 968137#L582-36 assume !(1 == ~t3_pc~0); 968136#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 968135#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 968133#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 968131#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 968128#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 968124#L601-36 assume !(1 == ~t4_pc~0); 968120#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 968117#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 968113#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 968112#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 968111#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 968110#L620-36 assume !(1 == ~t5_pc~0); 968108#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 968106#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 968104#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 968102#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 968100#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 968098#L639-36 assume !(1 == ~t6_pc~0); 968095#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 968093#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 968091#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 968089#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 968087#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 968085#L658-36 assume !(1 == ~t7_pc~0); 968071#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 968067#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 968063#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 968058#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 968053#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 968046#L677-36 assume !(1 == ~t8_pc~0); 968040#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 968034#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 968027#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 968021#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 968014#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 968007#L696-36 assume 1 == ~t9_pc~0; 967998#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 967990#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 967982#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 967974#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 967966#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 967959#L715-36 assume !(1 == ~t10_pc~0); 967951#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 967943#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 967934#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 967927#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 967920#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 967912#L734-36 assume !(1 == ~t11_pc~0); 967903#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 967896#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 967888#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 967881#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 967873#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 967866#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 967858#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 967851#L1218-3 assume !(1 == ~T2_E~0); 967844#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 967837#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 967830#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 967822#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 967814#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 967806#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 967798#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 967791#L1258-3 assume !(1 == ~T10_E~0); 967783#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 967775#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 967767#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 967760#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 967753#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 967745#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 967738#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 967730#L1298-3 assume !(1 == ~E_7~0); 967723#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 967716#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 967708#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 967701#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 967696#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 967585#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 967567#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 967559#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 967552#L1663 assume !(0 == start_simulation_~tmp~3#1); 967549#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 967450#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 967437#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 967426#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 967417#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 967405#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 967397#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 967390#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 801371#L1644-2 [2021-11-13 18:16:11,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:16:11,843 INFO L85 PathProgramCache]: Analyzing trace with hash -1619665514, now seen corresponding path program 1 times [2021-11-13 18:16:11,844 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:16:11,844 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [961727444] [2021-11-13 18:16:11,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:16:11,844 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:16:11,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:16:11,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:16:11,891 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:16:11,891 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [961727444] [2021-11-13 18:16:11,891 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [961727444] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:16:11,891 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:16:11,891 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:16:11,892 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1319082819] [2021-11-13 18:16:11,892 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:16:11,892 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:16:11,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:16:11,893 INFO L85 PathProgramCache]: Analyzing trace with hash -1601582882, now seen corresponding path program 1 times [2021-11-13 18:16:11,893 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:16:11,893 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1754323864] [2021-11-13 18:16:11,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:16:11,893 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:16:11,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:16:11,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:16:11,929 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:16:11,929 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1754323864] [2021-11-13 18:16:11,929 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1754323864] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:16:11,929 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:16:11,929 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 18:16:11,929 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1431971170] [2021-11-13 18:16:11,930 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:16:11,930 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:16:11,930 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:16:11,931 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:16:11,931 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:16:11,931 INFO L87 Difference]: Start difference. First operand 229240 states and 319183 transitions. cyclomatic complexity: 89975 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:16:12,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:16:12,659 INFO L93 Difference]: Finished difference Result 229240 states and 318452 transitions. [2021-11-13 18:16:12,659 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:16:12,660 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 229240 states and 318452 transitions. [2021-11-13 18:16:14,447 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 228939 [2021-11-13 18:16:14,976 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 229240 states to 229240 states and 318452 transitions. [2021-11-13 18:16:14,976 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 229240 [2021-11-13 18:16:15,064 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 229240 [2021-11-13 18:16:15,064 INFO L73 IsDeterministic]: Start isDeterministic. Operand 229240 states and 318452 transitions. [2021-11-13 18:16:15,153 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:16:15,154 INFO L681 BuchiCegarLoop]: Abstraction has 229240 states and 318452 transitions. [2021-11-13 18:16:15,236 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 229240 states and 318452 transitions. [2021-11-13 18:16:17,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 229240 to 229240. [2021-11-13 18:16:17,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 229240 states, 229240 states have (on average 1.3891641947304136) internal successors, (318452), 229239 states have internal predecessors, (318452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:16:18,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 229240 states to 229240 states and 318452 transitions. [2021-11-13 18:16:18,285 INFO L704 BuchiCegarLoop]: Abstraction has 229240 states and 318452 transitions. [2021-11-13 18:16:18,285 INFO L587 BuchiCegarLoop]: Abstraction has 229240 states and 318452 transitions. [2021-11-13 18:16:18,285 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-13 18:16:18,285 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 229240 states and 318452 transitions. [2021-11-13 18:16:19,753 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 228939 [2021-11-13 18:16:19,753 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:16:19,753 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:16:19,779 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:16:19,779 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:16:19,781 INFO L791 eck$LassoCheckResult]: Stem: 1260507#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1260508#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1260518#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1260519#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1260244#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1260245#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1260108#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1260019#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1259723#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1259360#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1259361#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1259410#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1259411#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1260385#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1260386#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1260435#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1259832#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1259833#L1090 assume !(0 == ~M_E~0); 1259884#L1090-2 assume !(0 == ~T1_E~0); 1259885#L1095-1 assume !(0 == ~T2_E~0); 1260593#L1100-1 assume !(0 == ~T3_E~0); 1260594#L1105-1 assume !(0 == ~T4_E~0); 1259640#L1110-1 assume !(0 == ~T5_E~0); 1259641#L1115-1 assume !(0 == ~T6_E~0); 1260061#L1120-1 assume !(0 == ~T7_E~0); 1260356#L1125-1 assume !(0 == ~T8_E~0); 1261038#L1130-1 assume !(0 == ~T9_E~0); 1260617#L1135-1 assume !(0 == ~T10_E~0); 1259838#L1140-1 assume !(0 == ~T11_E~0); 1259839#L1145-1 assume !(0 == ~E_1~0); 1260534#L1150-1 assume !(0 == ~E_2~0); 1260035#L1155-1 assume !(0 == ~E_3~0); 1260036#L1160-1 assume !(0 == ~E_4~0); 1260116#L1165-1 assume !(0 == ~E_5~0); 1260117#L1170-1 assume !(0 == ~E_6~0); 1260850#L1175-1 assume !(0 == ~E_7~0); 1260199#L1180-1 assume !(0 == ~E_8~0); 1260200#L1185-1 assume !(0 == ~E_9~0); 1259834#L1190-1 assume !(0 == ~E_10~0); 1259835#L1195-1 assume !(0 == ~E_11~0); 1260213#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1260056#L525 assume !(1 == ~m_pc~0); 1259447#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1259448#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1260216#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1260217#L1350 assume !(0 != activate_threads_~tmp~1#1); 1259821#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1259822#L544 assume !(1 == ~t1_pc~0); 1260057#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1260058#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1260531#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1259662#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1259663#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1260324#L563 assume !(1 == ~t2_pc~0); 1260520#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1259471#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1259472#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1259912#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1259913#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1260407#L582 assume !(1 == ~t3_pc~0); 1260532#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1260953#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1260954#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1260866#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1259541#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1259542#L601 assume !(1 == ~t4_pc~0); 1260554#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1260062#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1260063#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1260547#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1260548#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1260941#L620 assume !(1 == ~t5_pc~0); 1260376#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1260377#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1260352#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1260353#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1260974#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1260975#L639 assume !(1 == ~t6_pc~0); 1260355#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1259949#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1259950#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1260868#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1260067#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1260068#L658 assume !(1 == ~t7_pc~0); 1260268#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1260269#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1260393#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1260394#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1259828#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1259829#L677 assume !(1 == ~t8_pc~0); 1259855#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1259625#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1259626#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1259906#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1259907#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1260672#L696 assume !(1 == ~t9_pc~0); 1260340#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1260341#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1260444#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1260364#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1260365#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1260597#L715 assume !(1 == ~t10_pc~0); 1260897#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1260458#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1260327#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1260328#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1260190#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1259613#L734 assume !(1 == ~t11_pc~0); 1259614#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1260123#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1260204#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1259350#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1259351#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1260427#L1213 assume !(1 == ~M_E~0); 1260188#L1213-2 assume !(1 == ~T1_E~0); 1260189#L1218-1 assume !(1 == ~T2_E~0); 1259385#L1223-1 assume !(1 == ~T3_E~0); 1259386#L1228-1 assume !(1 == ~T4_E~0); 1260163#L1233-1 assume !(1 == ~T5_E~0); 1260976#L1238-1 assume !(1 == ~T6_E~0); 1260545#L1243-1 assume !(1 == ~T7_E~0); 1260546#L1248-1 assume !(1 == ~T8_E~0); 1260602#L1253-1 assume !(1 == ~T9_E~0); 1260603#L1258-1 assume !(1 == ~T10_E~0); 1260578#L1263-1 assume !(1 == ~T11_E~0); 1260579#L1268-1 assume !(1 == ~E_1~0); 1260381#L1273-1 assume !(1 == ~E_2~0); 1260382#L1278-1 assume !(1 == ~E_3~0); 1259947#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1259948#L1288-1 assume !(1 == ~E_5~0); 1260726#L1293-1 assume !(1 == ~E_6~0); 1260681#L1298-1 assume !(1 == ~E_7~0); 1260410#L1303-1 assume !(1 == ~E_8~0); 1259959#L1308-1 assume !(1 == ~E_9~0); 1259846#L1313-1 assume !(1 == ~E_10~0); 1259847#L1318-1 assume !(1 == ~E_11~0); 1259856#L1323-1 assume { :end_inline_reset_delta_events } true; 1259857#L1644-2 [2021-11-13 18:16:19,784 INFO L793 eck$LassoCheckResult]: Loop: 1259857#L1644-2 assume !false; 1363585#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1363574#L1065 assume !false; 1363571#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1363407#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1363390#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1363383#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 1363373#L906 assume !(0 != eval_~tmp~0#1); 1363374#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1364377#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1364376#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1364375#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1364374#L1095-3 assume !(0 == ~T2_E~0); 1364373#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1364372#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1364371#L1110-3 assume !(0 == ~T5_E~0); 1364370#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1364369#L1120-3 assume !(0 == ~T7_E~0); 1364368#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1364367#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1364366#L1135-3 assume !(0 == ~T10_E~0); 1364365#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1364364#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1364363#L1150-3 assume !(0 == ~E_2~0); 1364362#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1364361#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1364360#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1364358#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1364355#L1175-3 assume !(0 == ~E_7~0); 1364352#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1364349#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1364346#L1190-3 assume !(0 == ~E_10~0); 1364343#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1364340#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1364336#L525-36 assume !(1 == ~m_pc~0); 1364333#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1364330#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1364327#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1364324#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1364320#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1364317#L544-36 assume !(1 == ~t1_pc~0); 1364313#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1364310#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1364307#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1364304#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1364301#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1364298#L563-36 assume !(1 == ~t2_pc~0); 1364294#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1364291#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1364288#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1364285#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1364282#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1364278#L582-36 assume !(1 == ~t3_pc~0); 1364273#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1364269#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1364265#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1364259#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1364257#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1364256#L601-36 assume !(1 == ~t4_pc~0); 1364253#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1364251#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1364249#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1364247#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1364245#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1364243#L620-36 assume !(1 == ~t5_pc~0); 1364241#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1364238#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1364236#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1364234#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1364232#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1364230#L639-36 assume !(1 == ~t6_pc~0); 1364226#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1364223#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1364220#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1364216#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1364212#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1364206#L658-36 assume !(1 == ~t7_pc~0); 1364201#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1364197#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1364192#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1364187#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 1364182#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1364177#L677-36 assume !(1 == ~t8_pc~0); 1364171#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1364165#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1364159#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1364153#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1364146#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1364141#L696-36 assume 1 == ~t9_pc~0; 1364135#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1364129#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1364123#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1364116#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1364111#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1364106#L715-36 assume !(1 == ~t10_pc~0); 1364100#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1364094#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1364089#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1364084#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1364078#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1364073#L734-36 assume 1 == ~t11_pc~0; 1364068#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1364062#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1364057#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1364051#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1364046#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1364041#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1364035#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1364030#L1218-3 assume !(1 == ~T2_E~0); 1364025#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1364020#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1364014#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1364008#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1364003#L1243-3 assume !(1 == ~T7_E~0); 1363998#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1363993#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1363990#L1258-3 assume !(1 == ~T10_E~0); 1363988#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1363986#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1363984#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1363982#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1363979#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1363977#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1363975#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1363973#L1298-3 assume !(1 == ~E_7~0); 1363971#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1363969#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1363967#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1363965#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1363964#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1363938#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1363921#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1363915#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1363908#L1663 assume !(0 == start_simulation_~tmp~3#1); 1363905#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1363666#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1363651#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1363639#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 1363638#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1363624#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1363613#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1363604#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1259857#L1644-2 [2021-11-13 18:16:19,784 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:16:19,784 INFO L85 PathProgramCache]: Analyzing trace with hash 1086953880, now seen corresponding path program 1 times [2021-11-13 18:16:19,785 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:16:19,785 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1724115612] [2021-11-13 18:16:19,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:16:19,785 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:16:19,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:16:19,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:16:19,864 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:16:19,865 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1724115612] [2021-11-13 18:16:19,865 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1724115612] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:16:19,865 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:16:19,865 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:16:19,865 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [591578076] [2021-11-13 18:16:19,865 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:16:19,866 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:16:19,866 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:16:19,866 INFO L85 PathProgramCache]: Analyzing trace with hash 1233538307, now seen corresponding path program 1 times [2021-11-13 18:16:19,866 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:16:19,867 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636703646] [2021-11-13 18:16:19,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:16:19,867 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:16:19,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:16:19,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:16:19,936 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:16:19,936 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1636703646] [2021-11-13 18:16:19,936 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1636703646] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:16:19,936 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:16:19,936 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 18:16:19,936 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1253535919] [2021-11-13 18:16:19,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:16:19,937 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:16:19,937 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:16:19,937 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:16:19,938 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:16:19,938 INFO L87 Difference]: Start difference. First operand 229240 states and 318452 transitions. cyclomatic complexity: 89244 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:16:20,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:16:20,699 INFO L93 Difference]: Finished difference Result 229240 states and 315663 transitions. [2021-11-13 18:16:20,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:16:20,700 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 229240 states and 315663 transitions. [2021-11-13 18:16:22,571 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 228939 [2021-11-13 18:16:23,149 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 229240 states to 229240 states and 315663 transitions. [2021-11-13 18:16:23,149 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 229240 [2021-11-13 18:16:23,255 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 229240 [2021-11-13 18:16:23,255 INFO L73 IsDeterministic]: Start isDeterministic. Operand 229240 states and 315663 transitions. [2021-11-13 18:16:23,355 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:16:23,355 INFO L681 BuchiCegarLoop]: Abstraction has 229240 states and 315663 transitions. [2021-11-13 18:16:23,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 229240 states and 315663 transitions. [2021-11-13 18:16:26,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 229240 to 229240. [2021-11-13 18:16:26,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 229240 states, 229240 states have (on average 1.3769979061245856) internal successors, (315663), 229239 states have internal predecessors, (315663), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:16:26,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 229240 states to 229240 states and 315663 transitions. [2021-11-13 18:16:26,965 INFO L704 BuchiCegarLoop]: Abstraction has 229240 states and 315663 transitions. [2021-11-13 18:16:26,965 INFO L587 BuchiCegarLoop]: Abstraction has 229240 states and 315663 transitions. [2021-11-13 18:16:26,965 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-13 18:16:26,965 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 229240 states and 315663 transitions. [2021-11-13 18:16:27,608 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 228939 [2021-11-13 18:16:27,608 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:16:27,608 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:16:27,611 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:16:27,612 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:16:27,612 INFO L791 eck$LassoCheckResult]: Stem: 1718994#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1718995#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1719004#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1719005#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1718726#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1718727#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1718588#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1718500#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1718211#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1717849#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1717850#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1717897#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1717898#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1718874#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1718875#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1718924#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1718319#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1718320#L1090 assume !(0 == ~M_E~0); 1718370#L1090-2 assume !(0 == ~T1_E~0); 1718371#L1095-1 assume !(0 == ~T2_E~0); 1719077#L1100-1 assume !(0 == ~T3_E~0); 1719078#L1105-1 assume !(0 == ~T4_E~0); 1718129#L1110-1 assume !(0 == ~T5_E~0); 1718130#L1115-1 assume !(0 == ~T6_E~0); 1718539#L1120-1 assume !(0 == ~T7_E~0); 1718845#L1125-1 assume !(0 == ~T8_E~0); 1719531#L1130-1 assume !(0 == ~T9_E~0); 1719100#L1135-1 assume !(0 == ~T10_E~0); 1718325#L1140-1 assume !(0 == ~T11_E~0); 1718326#L1145-1 assume !(0 == ~E_1~0); 1719022#L1150-1 assume !(0 == ~E_2~0); 1718514#L1155-1 assume !(0 == ~E_3~0); 1718515#L1160-1 assume !(0 == ~E_4~0); 1718597#L1165-1 assume !(0 == ~E_5~0); 1718598#L1170-1 assume !(0 == ~E_6~0); 1719344#L1175-1 assume !(0 == ~E_7~0); 1718682#L1180-1 assume !(0 == ~E_8~0); 1718683#L1185-1 assume !(0 == ~E_9~0); 1718321#L1190-1 assume !(0 == ~E_10~0); 1718322#L1195-1 assume !(0 == ~E_11~0); 1718696#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1718531#L525 assume !(1 == ~m_pc~0); 1717934#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1717935#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1718699#L537 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1718700#L1350 assume !(0 != activate_threads_~tmp~1#1); 1718308#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1718309#L544 assume !(1 == ~t1_pc~0); 1718535#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1718536#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1719019#L556 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1718150#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1718151#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1718812#L563 assume !(1 == ~t2_pc~0); 1719006#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1717958#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1717959#L575 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1718397#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1718398#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1718899#L582 assume !(1 == ~t3_pc~0); 1719020#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1719449#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1719450#L594 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1719358#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1718028#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1718029#L601 assume !(1 == ~t4_pc~0); 1719040#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1718540#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1718541#L613 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1719034#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1719035#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1719434#L620 assume !(1 == ~t5_pc~0); 1718864#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1718865#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1718842#L632 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1718843#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1719473#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1719474#L639 assume !(1 == ~t6_pc~0); 1718844#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1718434#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1718435#L651 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1719360#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1718545#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1718546#L658 assume !(1 == ~t7_pc~0); 1718753#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1718754#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1718882#L670 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1718883#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1718314#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1718315#L677 assume !(1 == ~t8_pc~0); 1718342#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1718115#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1718116#L689 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1718391#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1718392#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1719157#L696 assume !(1 == ~t9_pc~0); 1718826#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1718827#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1718932#L708 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1718852#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1718853#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1719081#L715 assume !(1 == ~t10_pc~0); 1719387#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1718946#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1718815#L727 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1718816#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1718673#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1718101#L734 assume !(1 == ~t11_pc~0); 1718102#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1718604#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1718687#L746 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1717839#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1717840#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1718915#L1213 assume !(1 == ~M_E~0); 1718671#L1213-2 assume !(1 == ~T1_E~0); 1718672#L1218-1 assume !(1 == ~T2_E~0); 1717874#L1223-1 assume !(1 == ~T3_E~0); 1717875#L1228-1 assume !(1 == ~T4_E~0); 1718645#L1233-1 assume !(1 == ~T5_E~0); 1719475#L1238-1 assume !(1 == ~T6_E~0); 1719032#L1243-1 assume !(1 == ~T7_E~0); 1719033#L1248-1 assume !(1 == ~T8_E~0); 1719086#L1253-1 assume !(1 == ~T9_E~0); 1719087#L1258-1 assume !(1 == ~T10_E~0); 1719061#L1263-1 assume !(1 == ~T11_E~0); 1719062#L1268-1 assume !(1 == ~E_1~0); 1718869#L1273-1 assume !(1 == ~E_2~0); 1718870#L1278-1 assume !(1 == ~E_3~0); 1718432#L1283-1 assume !(1 == ~E_4~0); 1718433#L1288-1 assume !(1 == ~E_5~0); 1719213#L1293-1 assume !(1 == ~E_6~0); 1719163#L1298-1 assume !(1 == ~E_7~0); 1718902#L1303-1 assume !(1 == ~E_8~0); 1718443#L1308-1 assume !(1 == ~E_9~0); 1718333#L1313-1 assume !(1 == ~E_10~0); 1718334#L1318-1 assume !(1 == ~E_11~0); 1718343#L1323-1 assume { :end_inline_reset_delta_events } true; 1718344#L1644-2 [2021-11-13 18:16:27,613 INFO L793 eck$LassoCheckResult]: Loop: 1718344#L1644-2 assume !false; 1806474#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1806469#L1065 assume !false; 1806468#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1803107#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1803095#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1803096#L892 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 1806431#L906 assume !(0 != eval_~tmp~0#1); 1806432#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1815313#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1815311#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1815309#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1815306#L1095-3 assume !(0 == ~T2_E~0); 1815304#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1815302#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1815300#L1110-3 assume !(0 == ~T5_E~0); 1815298#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1815296#L1120-3 assume !(0 == ~T7_E~0); 1815294#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1815292#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1815290#L1135-3 assume !(0 == ~T10_E~0); 1815288#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1815286#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1815284#L1150-3 assume !(0 == ~E_2~0); 1815280#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1815278#L1160-3 assume !(0 == ~E_4~0); 1815276#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1815274#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1815271#L1175-3 assume !(0 == ~E_7~0); 1815269#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1815267#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1815266#L1190-3 assume !(0 == ~E_10~0); 1815264#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1815262#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1815260#L525-36 assume !(1 == ~m_pc~0); 1815258#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1815256#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1815253#L537-12 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1815251#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1815249#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1815247#L544-36 assume !(1 == ~t1_pc~0); 1815245#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1815244#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1815240#L556-12 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1815238#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1815236#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1815235#L563-36 assume 1 == ~t2_pc~0; 1815234#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1815228#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1815227#L575-12 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1815226#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1815225#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1815224#L582-36 assume !(1 == ~t3_pc~0); 1815223#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1815222#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1815221#L594-12 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1815219#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1815218#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1815216#L601-36 assume !(1 == ~t4_pc~0); 1815215#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1815214#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1815213#L613-12 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1815212#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1815211#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1815210#L620-36 assume !(1 == ~t5_pc~0); 1815209#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1815208#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1815206#L632-12 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1815205#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1815204#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1815203#L639-36 assume 1 == ~t6_pc~0; 1815202#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1815199#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1815197#L651-12 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1815195#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1815193#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1815191#L658-36 assume !(1 == ~t7_pc~0); 1815188#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1815186#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1815184#L670-12 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1815182#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 1815180#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1815178#L677-36 assume !(1 == ~t8_pc~0); 1815176#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1815174#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1815172#L689-12 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1815170#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1815169#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1815168#L696-36 assume !(1 == ~t9_pc~0); 1815163#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1815161#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1815159#L708-12 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1815157#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1815154#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1815152#L715-36 assume !(1 == ~t10_pc~0); 1815149#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1815147#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1815145#L727-12 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1815143#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1815141#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1815139#L734-36 assume !(1 == ~t11_pc~0); 1815135#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1815133#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1815131#L746-12 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1815129#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1815127#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1815125#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1815123#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1814361#L1218-3 assume !(1 == ~T2_E~0); 1814358#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1814356#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1814354#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1814352#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1814350#L1243-3 assume !(1 == ~T7_E~0); 1814348#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1814346#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1814344#L1258-3 assume !(1 == ~T10_E~0); 1814342#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1814340#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1814338#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1814336#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1814334#L1283-3 assume !(1 == ~E_4~0); 1814331#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1814329#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1814327#L1298-3 assume !(1 == ~E_7~0); 1806619#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1806616#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1806614#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1806612#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1806610#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1806608#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1806595#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1806593#L892-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1806590#L1663 assume !(0 == start_simulation_~tmp~3#1); 1806587#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1806485#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1806480#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1806479#L892-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 1806478#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1806477#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1806476#L1626 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1806475#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1718344#L1644-2 [2021-11-13 18:16:27,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:16:27,614 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 1 times [2021-11-13 18:16:27,614 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:16:27,614 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1136327889] [2021-11-13 18:16:27,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:16:27,615 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:16:27,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-13 18:16:27,638 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-13 18:16:27,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-13 18:16:27,776 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-13 18:16:27,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:16:27,777 INFO L85 PathProgramCache]: Analyzing trace with hash 1825230405, now seen corresponding path program 1 times [2021-11-13 18:16:27,778 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:16:27,778 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1201002515] [2021-11-13 18:16:27,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:16:27,778 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:16:27,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:16:27,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:16:27,825 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:16:27,825 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1201002515] [2021-11-13 18:16:27,825 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1201002515] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:16:27,825 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:16:27,825 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 18:16:27,826 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [899412123] [2021-11-13 18:16:27,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:16:27,826 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:16:27,826 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:16:27,827 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-13 18:16:27,827 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-13 18:16:27,827 INFO L87 Difference]: Start difference. First operand 229240 states and 315663 transitions. cyclomatic complexity: 86455 Second operand has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:16:30,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:16:30,181 INFO L93 Difference]: Finished difference Result 421594 states and 573549 transitions. [2021-11-13 18:16:30,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-11-13 18:16:30,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 421594 states and 573549 transitions.