./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.12.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 63182f13 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/bin/uautomizer-YU5uOKAj3y/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/bin/uautomizer-YU5uOKAj3y/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/bin/uautomizer-YU5uOKAj3y/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/bin/uautomizer-YU5uOKAj3y/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.12.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/bin/uautomizer-YU5uOKAj3y/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/bin/uautomizer-YU5uOKAj3y --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-63182f1 [2021-11-13 18:36:17,004 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-13 18:36:17,008 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-13 18:36:17,075 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-13 18:36:17,076 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-13 18:36:17,083 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-13 18:36:17,085 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-13 18:36:17,091 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-13 18:36:17,095 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-13 18:36:17,104 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-13 18:36:17,106 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-13 18:36:17,108 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-13 18:36:17,109 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-13 18:36:17,113 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-13 18:36:17,117 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-13 18:36:17,128 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-13 18:36:17,131 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-13 18:36:17,133 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-13 18:36:17,136 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-13 18:36:17,144 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-13 18:36:17,148 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-13 18:36:17,150 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-13 18:36:17,154 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-13 18:36:17,156 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-13 18:36:17,164 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-13 18:36:17,164 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-13 18:36:17,165 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-13 18:36:17,168 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-13 18:36:17,169 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-13 18:36:17,171 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-13 18:36:17,172 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-13 18:36:17,173 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-13 18:36:17,176 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-13 18:36:17,177 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-13 18:36:17,179 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-13 18:36:17,180 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-13 18:36:17,181 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-13 18:36:17,181 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-13 18:36:17,182 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-13 18:36:17,183 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-13 18:36:17,184 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-13 18:36:17,185 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/bin/uautomizer-YU5uOKAj3y/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-13 18:36:17,249 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-13 18:36:17,250 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-13 18:36:17,250 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-13 18:36:17,251 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-13 18:36:17,252 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-13 18:36:17,252 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-13 18:36:17,253 INFO L138 SettingsManager]: * Use SBE=true [2021-11-13 18:36:17,253 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-13 18:36:17,253 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-13 18:36:17,254 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-13 18:36:17,254 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-13 18:36:17,254 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-13 18:36:17,255 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-13 18:36:17,255 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-13 18:36:17,255 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-13 18:36:17,256 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-13 18:36:17,256 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-13 18:36:17,256 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-13 18:36:17,256 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-13 18:36:17,257 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-13 18:36:17,257 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-13 18:36:17,257 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-13 18:36:17,258 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-13 18:36:17,258 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-13 18:36:17,258 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-13 18:36:17,259 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-13 18:36:17,259 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-13 18:36:17,259 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-13 18:36:17,259 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-13 18:36:17,260 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-13 18:36:17,260 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-13 18:36:17,260 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-13 18:36:17,262 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-13 18:36:17,262 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/bin/uautomizer-YU5uOKAj3y/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/bin/uautomizer-YU5uOKAj3y Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 [2021-11-13 18:36:17,625 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-13 18:36:17,661 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-13 18:36:17,665 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-13 18:36:17,666 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-13 18:36:17,668 INFO L275 PluginConnector]: CDTParser initialized [2021-11-13 18:36:17,670 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/bin/uautomizer-YU5uOKAj3y/../../sv-benchmarks/c/systemc/transmitter.12.cil.c [2021-11-13 18:36:17,791 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/bin/uautomizer-YU5uOKAj3y/data/73b01a8b6/89045e8cfded40bb8208bcf5c26b2fb4/FLAGed20ada95 [2021-11-13 18:36:18,428 INFO L306 CDTParser]: Found 1 translation units. [2021-11-13 18:36:18,429 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/sv-benchmarks/c/systemc/transmitter.12.cil.c [2021-11-13 18:36:18,454 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/bin/uautomizer-YU5uOKAj3y/data/73b01a8b6/89045e8cfded40bb8208bcf5c26b2fb4/FLAGed20ada95 [2021-11-13 18:36:18,736 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/bin/uautomizer-YU5uOKAj3y/data/73b01a8b6/89045e8cfded40bb8208bcf5c26b2fb4 [2021-11-13 18:36:18,740 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-13 18:36:18,742 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-13 18:36:18,746 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-13 18:36:18,747 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-13 18:36:18,752 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-13 18:36:18,753 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 06:36:18" (1/1) ... [2021-11-13 18:36:18,756 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@35c04c56 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:36:18, skipping insertion in model container [2021-11-13 18:36:18,757 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 06:36:18" (1/1) ... [2021-11-13 18:36:18,766 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-13 18:36:18,827 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-13 18:36:19,030 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/sv-benchmarks/c/systemc/transmitter.12.cil.c[706,719] [2021-11-13 18:36:19,189 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-13 18:36:19,209 INFO L203 MainTranslator]: Completed pre-run [2021-11-13 18:36:19,222 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/sv-benchmarks/c/systemc/transmitter.12.cil.c[706,719] [2021-11-13 18:36:19,349 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-13 18:36:19,395 INFO L208 MainTranslator]: Completed translation [2021-11-13 18:36:19,396 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:36:19 WrapperNode [2021-11-13 18:36:19,396 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-13 18:36:19,397 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-13 18:36:19,398 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-13 18:36:19,398 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-13 18:36:19,407 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:36:19" (1/1) ... [2021-11-13 18:36:19,423 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:36:19" (1/1) ... [2021-11-13 18:36:19,614 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-13 18:36:19,631 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-13 18:36:19,631 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-13 18:36:19,631 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-13 18:36:19,642 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:36:19" (1/1) ... [2021-11-13 18:36:19,642 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:36:19" (1/1) ... [2021-11-13 18:36:19,657 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:36:19" (1/1) ... [2021-11-13 18:36:19,657 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:36:19" (1/1) ... [2021-11-13 18:36:19,715 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:36:19" (1/1) ... [2021-11-13 18:36:19,803 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:36:19" (1/1) ... [2021-11-13 18:36:19,811 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:36:19" (1/1) ... [2021-11-13 18:36:19,827 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-13 18:36:19,828 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-13 18:36:19,828 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-13 18:36:19,828 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-13 18:36:19,830 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:36:19" (1/1) ... [2021-11-13 18:36:19,839 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-13 18:36:19,852 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/bin/uautomizer-YU5uOKAj3y/z3 [2021-11-13 18:36:19,871 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/bin/uautomizer-YU5uOKAj3y/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-13 18:36:19,875 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e6bda366-a3f9-499b-9096-ac1e961c6104/bin/uautomizer-YU5uOKAj3y/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-13 18:36:19,930 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-13 18:36:19,930 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-13 18:36:19,930 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-13 18:36:19,930 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-13 18:36:22,700 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-13 18:36:22,701 INFO L299 CfgBuilder]: Removed 16 assume(true) statements. [2021-11-13 18:36:22,706 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 06:36:22 BoogieIcfgContainer [2021-11-13 18:36:22,707 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-13 18:36:22,708 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-13 18:36:22,708 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-13 18:36:22,712 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-13 18:36:22,713 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-13 18:36:22,714 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 06:36:18" (1/3) ... [2021-11-13 18:36:22,716 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@13afdc53 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 06:36:22, skipping insertion in model container [2021-11-13 18:36:22,716 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-13 18:36:22,717 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:36:19" (2/3) ... [2021-11-13 18:36:22,718 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@13afdc53 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 06:36:22, skipping insertion in model container [2021-11-13 18:36:22,718 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-13 18:36:22,719 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 06:36:22" (3/3) ... [2021-11-13 18:36:22,720 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.12.cil.c [2021-11-13 18:36:22,792 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-13 18:36:22,792 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-13 18:36:22,792 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-13 18:36:22,792 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-13 18:36:22,792 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-13 18:36:22,793 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-13 18:36:22,793 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-13 18:36:22,793 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-13 18:36:22,856 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1695 states, 1694 states have (on average 1.5017709563164108) internal successors, (2544), 1694 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:22,977 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1530 [2021-11-13 18:36:22,978 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:22,978 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:23,014 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:23,015 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:23,015 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-13 18:36:23,021 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1695 states, 1694 states have (on average 1.5017709563164108) internal successors, (2544), 1694 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:23,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1530 [2021-11-13 18:36:23,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:23,087 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:23,091 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:23,091 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:23,102 INFO L791 eck$LassoCheckResult]: Stem: 424#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1609#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1450#L1731true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 696#L814true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 529#L821true assume !(1 == ~m_i~0);~m_st~0 := 2; 598#L821-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 877#L826-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1186#L831-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1031#L836-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1332#L841-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 120#L846-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1624#L851-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 945#L856-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 451#L861-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 481#L866-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 392#L871-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 700#L876-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 693#L881-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 244#L1174true assume !(0 == ~M_E~0); 1354#L1174-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 167#L1179-1true assume !(0 == ~T2_E~0); 119#L1184-1true assume !(0 == ~T3_E~0); 138#L1189-1true assume !(0 == ~T4_E~0); 188#L1194-1true assume !(0 == ~T5_E~0); 819#L1199-1true assume !(0 == ~T6_E~0); 979#L1204-1true assume !(0 == ~T7_E~0); 742#L1209-1true assume !(0 == ~T8_E~0); 1244#L1214-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1637#L1219-1true assume !(0 == ~T10_E~0); 1555#L1224-1true assume !(0 == ~T11_E~0); 307#L1229-1true assume !(0 == ~T12_E~0); 83#L1234-1true assume !(0 == ~E_1~0); 491#L1239-1true assume !(0 == ~E_2~0); 98#L1244-1true assume !(0 == ~E_3~0); 1336#L1249-1true assume !(0 == ~E_4~0); 468#L1254-1true assume 0 == ~E_5~0;~E_5~0 := 1; 51#L1259-1true assume !(0 == ~E_6~0); 31#L1264-1true assume !(0 == ~E_7~0); 1688#L1269-1true assume !(0 == ~E_8~0); 1612#L1274-1true assume !(0 == ~E_9~0); 1325#L1279-1true assume !(0 == ~E_10~0); 140#L1284-1true assume !(0 == ~E_11~0); 1466#L1289-1true assume !(0 == ~E_12~0); 508#L1294-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1341#L566true assume 1 == ~m_pc~0; 39#L567true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 972#L577true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 767#L578true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1189#L1455true assume !(0 != activate_threads_~tmp~1#1); 256#L1455-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 791#L585true assume 1 == ~t1_pc~0; 82#L586true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1616#L596true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 714#L597true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1535#L1463true assume !(0 != activate_threads_~tmp___0~0#1); 1404#L1463-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1397#L604true assume !(1 == ~t2_pc~0); 783#L604-2true is_transmit2_triggered_~__retres1~2#1 := 0; 1363#L615true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 413#L616true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1198#L1471true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 986#L1471-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1465#L623true assume 1 == ~t3_pc~0; 359#L624true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1662#L634true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 454#L635true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1025#L1479true assume !(0 != activate_threads_~tmp___2~0#1); 1242#L1479-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38#L642true assume !(1 == ~t4_pc~0); 663#L642-2true is_transmit4_triggered_~__retres1~4#1 := 0; 265#L653true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 521#L654true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 71#L1487true assume !(0 != activate_threads_~tmp___3~0#1); 796#L1487-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1123#L661true assume 1 == ~t5_pc~0; 149#L662true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 708#L672true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130#L673true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1100#L1495true assume !(0 != activate_threads_~tmp___4~0#1); 827#L1495-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1689#L680true assume !(1 == ~t6_pc~0); 1691#L680-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1490#L691true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 562#L692true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1115#L1503true assume !(0 != activate_threads_~tmp___5~0#1); 1401#L1503-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1393#L699true assume 1 == ~t7_pc~0; 674#L700true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 894#L710true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 144#L711true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 589#L1511true assume !(0 != activate_threads_~tmp___6~0#1); 804#L1511-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 509#L718true assume !(1 == ~t8_pc~0); 1250#L718-2true is_transmit8_triggered_~__retres1~8#1 := 0; 137#L729true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1499#L730true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 158#L1519true assume !(0 != activate_threads_~tmp___7~0#1); 226#L1519-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 857#L737true assume 1 == ~t9_pc~0; 1502#L738true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1284#L748true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 735#L749true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1638#L1527true assume !(0 != activate_threads_~tmp___8~0#1); 404#L1527-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1094#L756true assume 1 == ~t10_pc~0; 887#L757true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 814#L767true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5#L768true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 536#L1535true assume !(0 != activate_threads_~tmp___9~0#1); 290#L1535-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 754#L775true assume !(1 == ~t11_pc~0); 445#L775-2true is_transmit11_triggered_~__retres1~11#1 := 0; 1262#L786true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 223#L787true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 104#L1543true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 849#L1543-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 198#L794true assume 1 == ~t12_pc~0; 117#L795true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1101#L805true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 975#L806true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 181#L1551true assume !(0 != activate_threads_~tmp___11~0#1); 690#L1551-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 456#L1307true assume !(1 == ~M_E~0); 541#L1307-2true assume !(1 == ~T1_E~0); 1445#L1312-1true assume !(1 == ~T2_E~0); 479#L1317-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 640#L1322-1true assume !(1 == ~T4_E~0); 295#L1327-1true assume !(1 == ~T5_E~0); 677#L1332-1true assume !(1 == ~T6_E~0); 1414#L1337-1true assume !(1 == ~T7_E~0); 636#L1342-1true assume !(1 == ~T8_E~0); 1322#L1347-1true assume !(1 == ~T9_E~0); 1065#L1352-1true assume !(1 == ~T10_E~0); 895#L1357-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 391#L1362-1true assume !(1 == ~T12_E~0); 1136#L1367-1true assume !(1 == ~E_1~0); 189#L1372-1true assume !(1 == ~E_2~0); 488#L1377-1true assume !(1 == ~E_3~0); 351#L1382-1true assume !(1 == ~E_4~0); 784#L1387-1true assume !(1 == ~E_5~0); 1258#L1392-1true assume !(1 == ~E_6~0); 363#L1397-1true assume 1 == ~E_7~0;~E_7~0 := 2; 1389#L1402-1true assume !(1 == ~E_8~0); 195#L1407-1true assume !(1 == ~E_9~0); 1520#L1412-1true assume !(1 == ~E_10~0); 974#L1417-1true assume !(1 == ~E_11~0); 1696#L1422-1true assume !(1 == ~E_12~0); 1385#L1427-1true assume { :end_inline_reset_delta_events } true; 96#L1768-2true [2021-11-13 18:36:23,106 INFO L793 eck$LassoCheckResult]: Loop: 96#L1768-2true assume !false; 522#L1769true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 844#L1149true assume false; 1434#L1164true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1419#L814-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 999#L1174-3true assume !(0 == ~M_E~0); 992#L1174-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 717#L1179-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1398#L1184-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 896#L1189-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 577#L1194-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 176#L1199-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 824#L1204-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 302#L1209-3true assume !(0 == ~T8_E~0); 14#L1214-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 629#L1219-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 412#L1224-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1693#L1229-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 425#L1234-3true assume 0 == ~E_1~0;~E_1~0 := 1; 100#L1239-3true assume 0 == ~E_2~0;~E_2~0 := 1; 336#L1244-3true assume 0 == ~E_3~0;~E_3~0 := 1; 662#L1249-3true assume !(0 == ~E_4~0); 1446#L1254-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1237#L1259-3true assume 0 == ~E_6~0;~E_6~0 := 1; 765#L1264-3true assume 0 == ~E_7~0;~E_7~0 := 1; 103#L1269-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1504#L1274-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1321#L1279-3true assume 0 == ~E_10~0;~E_10~0 := 1; 411#L1284-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1379#L1289-3true assume !(0 == ~E_12~0); 403#L1294-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 218#L566-39true assume !(1 == ~m_pc~0); 654#L566-41true is_master_triggered_~__retres1~0#1 := 0; 606#L577-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 396#L578-13true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1251#L1455-39true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 836#L1455-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1298#L585-39true assume 1 == ~t1_pc~0; 968#L586-13true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 333#L596-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 260#L597-13true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1225#L1463-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 871#L1463-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 593#L604-39true assume !(1 == ~t2_pc~0); 1222#L604-41true is_transmit2_triggered_~__retres1~2#1 := 0; 339#L615-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1134#L616-13true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 631#L1471-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1007#L1471-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 326#L623-39true assume !(1 == ~t3_pc~0); 650#L623-41true is_transmit3_triggered_~__retres1~3#1 := 0; 853#L634-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1486#L635-13true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 245#L1479-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 803#L1479-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1304#L642-39true assume 1 == ~t4_pc~0; 448#L643-13true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 753#L653-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 179#L654-13true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1040#L1487-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1184#L1487-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 204#L661-39true assume !(1 == ~t5_pc~0); 25#L661-41true is_transmit5_triggered_~__retres1~5#1 := 0; 1627#L672-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 961#L673-13true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1151#L1495-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 855#L1495-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1176#L680-39true assume !(1 == ~t6_pc~0); 977#L680-41true is_transmit6_triggered_~__retres1~6#1 := 0; 1145#L691-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 785#L692-13true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 289#L1503-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1491#L1503-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1248#L699-39true assume 1 == ~t7_pc~0; 579#L700-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 381#L710-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 982#L711-13true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1269#L1511-39true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1143#L1511-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1141#L718-39true assume 1 == ~t8_pc~0; 511#L719-13true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1388#L729-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 461#L730-13true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1153#L1519-39true assume !(0 != activate_threads_~tmp___7~0#1); 707#L1519-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 683#L737-39true assume 1 == ~t9_pc~0; 276#L738-13true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 452#L748-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1323#L749-13true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1449#L1527-39true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1099#L1527-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1027#L756-39true assume 1 == ~t10_pc~0; 1376#L757-13true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1515#L767-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 352#L768-13true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 434#L1535-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 565#L1535-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77#L775-39true assume !(1 == ~t11_pc~0); 460#L775-41true is_transmit11_triggered_~__retres1~11#1 := 0; 431#L786-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1694#L787-13true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1546#L1543-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 759#L1543-41true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 467#L794-39true assume 1 == ~t12_pc~0; 277#L795-13true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 914#L805-13true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1347#L806-13true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 810#L1551-39true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49#L1551-41true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1307#L1307-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1199#L1307-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1610#L1312-3true assume !(1 == ~T2_E~0); 1604#L1317-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 828#L1322-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1672#L1327-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 112#L1332-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 99#L1337-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 533#L1342-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 957#L1347-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 632#L1352-3true assume !(1 == ~T10_E~0); 1112#L1357-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1683#L1362-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1541#L1367-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1508#L1372-3true assume 1 == ~E_2~0;~E_2~0 := 2; 20#L1377-3true assume 1 == ~E_3~0;~E_3~0 := 2; 428#L1382-3true assume 1 == ~E_4~0;~E_4~0 := 2; 343#L1387-3true assume 1 == ~E_5~0;~E_5~0 := 2; 927#L1392-3true assume !(1 == ~E_6~0); 1595#L1397-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1373#L1402-3true assume 1 == ~E_8~0;~E_8~0 := 2; 605#L1407-3true assume 1 == ~E_9~0;~E_9~0 := 2; 156#L1412-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1149#L1417-3true assume 1 == ~E_11~0;~E_11~0 := 2; 547#L1422-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1105#L1427-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 161#L894-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1651#L961-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 739#L962-1true start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 609#L1787true assume !(0 == start_simulation_~tmp~3#1); 1433#L1787-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1215#L894-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1010#L961-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 647#L962-2true stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 1318#L1742true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 330#L1749true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 331#L1750true start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1590#L1800true assume !(0 != start_simulation_~tmp___0~1#1); 96#L1768-2true [2021-11-13 18:36:23,114 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:23,115 INFO L85 PathProgramCache]: Analyzing trace with hash -1422298547, now seen corresponding path program 1 times [2021-11-13 18:36:23,125 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:23,125 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [938519245] [2021-11-13 18:36:23,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:23,127 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:23,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:23,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:23,409 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:23,410 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [938519245] [2021-11-13 18:36:23,411 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [938519245] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:23,411 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:23,412 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:23,414 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2053825712] [2021-11-13 18:36:23,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:23,421 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:23,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:23,432 INFO L85 PathProgramCache]: Analyzing trace with hash -1819192778, now seen corresponding path program 1 times [2021-11-13 18:36:23,432 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:23,433 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1127369852] [2021-11-13 18:36:23,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:23,433 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:23,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:23,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:23,505 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:23,506 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1127369852] [2021-11-13 18:36:23,506 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1127369852] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:23,507 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:23,507 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:36:23,507 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [484392270] [2021-11-13 18:36:23,508 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:23,510 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:23,511 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:23,564 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-11-13 18:36:23,565 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-11-13 18:36:23,571 INFO L87 Difference]: Start difference. First operand has 1695 states, 1694 states have (on average 1.5017709563164108) internal successors, (2544), 1694 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 73.5) internal successors, (147), 2 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:23,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:23,683 INFO L93 Difference]: Finished difference Result 1694 states and 2510 transitions. [2021-11-13 18:36:23,684 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-11-13 18:36:23,690 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1694 states and 2510 transitions. [2021-11-13 18:36:23,712 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:23,735 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1694 states to 1688 states and 2504 transitions. [2021-11-13 18:36:23,737 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-13 18:36:23,740 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-13 18:36:23,741 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2504 transitions. [2021-11-13 18:36:23,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:23,750 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2504 transitions. [2021-11-13 18:36:23,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2504 transitions. [2021-11-13 18:36:23,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-13 18:36:23,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4834123222748816) internal successors, (2504), 1687 states have internal predecessors, (2504), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:23,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2504 transitions. [2021-11-13 18:36:23,862 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2504 transitions. [2021-11-13 18:36:23,862 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2504 transitions. [2021-11-13 18:36:23,862 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-13 18:36:23,862 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2504 transitions. [2021-11-13 18:36:23,878 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:23,879 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:23,879 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:23,883 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:23,884 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:23,885 INFO L791 eck$LassoCheckResult]: Stem: 4201#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 4202#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 5055#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4547#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4354#L821 assume !(1 == ~m_i~0);~m_st~0 := 2; 4355#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4440#L826-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4741#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4863#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4864#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3652#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3653#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4801#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4247#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4248#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4154#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4155#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4543#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3896#L1174 assume !(0 == ~M_E~0); 3897#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3748#L1179-1 assume !(0 == ~T2_E~0); 3650#L1184-1 assume !(0 == ~T3_E~0); 3651#L1189-1 assume !(0 == ~T4_E~0); 3689#L1194-1 assume !(0 == ~T5_E~0); 3789#L1199-1 assume !(0 == ~T6_E~0); 4684#L1204-1 assume !(0 == ~T7_E~0); 4603#L1209-1 assume !(0 == ~T8_E~0); 4604#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4992#L1219-1 assume !(0 == ~T10_E~0); 5077#L1224-1 assume !(0 == ~T11_E~0); 4014#L1229-1 assume !(0 == ~T12_E~0); 3575#L1234-1 assume !(0 == ~E_1~0); 3576#L1239-1 assume !(0 == ~E_2~0); 3609#L1244-1 assume !(0 == ~E_3~0); 3610#L1249-1 assume !(0 == ~E_4~0); 4271#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3505#L1259-1 assume !(0 == ~E_6~0); 3460#L1264-1 assume !(0 == ~E_7~0); 3461#L1269-1 assume !(0 == ~E_8~0); 5082#L1274-1 assume !(0 == ~E_9~0); 5017#L1279-1 assume !(0 == ~E_10~0); 3693#L1284-1 assume !(0 == ~E_11~0); 3694#L1289-1 assume !(0 == ~E_12~0); 4323#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4324#L566 assume 1 == ~m_pc~0; 3477#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3478#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4632#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4633#L1455 assume !(0 != activate_threads_~tmp~1#1); 3923#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3924#L585 assume 1 == ~t1_pc~0; 3572#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3573#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4573#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4574#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 5042#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5040#L604 assume !(1 == ~t2_pc~0); 4652#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4653#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4186#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4187#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4824#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4825#L623 assume 1 == ~t3_pc~0; 4101#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3441#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4251#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4252#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 4859#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3474#L642 assume !(1 == ~t4_pc~0); 3475#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3940#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3941#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3546#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 3547#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4664#L661 assume 1 == ~t5_pc~0; 3711#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3712#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3673#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3674#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 4693#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4694#L680 assume !(1 == ~t6_pc~0); 4134#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4135#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4396#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4397#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 4925#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5038#L699 assume 1 == ~t7_pc~0; 4524#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4525#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3701#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3702#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 4426#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4325#L718 assume !(1 == ~t8_pc~0); 4326#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3687#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3688#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3729#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 3730#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3863#L737 assume 1 == ~t9_pc~0; 4728#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3998#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4599#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4600#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 4172#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4173#L756 assume 1 == ~t10_pc~0; 4752#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4418#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3404#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3405#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 3980#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3981#L775 assume !(1 == ~t11_pc~0); 4235#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 4236#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3857#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3621#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3622#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3808#L794 assume 1 == ~t12_pc~0; 3648#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 3626#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4819#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 3774#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 3775#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4254#L1307 assume !(1 == ~M_E~0); 4255#L1307-2 assume !(1 == ~T1_E~0); 4366#L1312-1 assume !(1 == ~T2_E~0); 4285#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4286#L1322-1 assume !(1 == ~T4_E~0); 3989#L1327-1 assume !(1 == ~T5_E~0); 3990#L1332-1 assume !(1 == ~T6_E~0); 4528#L1337-1 assume !(1 == ~T7_E~0); 4490#L1342-1 assume !(1 == ~T8_E~0); 4491#L1347-1 assume !(1 == ~T9_E~0); 4888#L1352-1 assume !(1 == ~T10_E~0); 4761#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4152#L1362-1 assume !(1 == ~T12_E~0); 4153#L1367-1 assume !(1 == ~E_1~0); 3790#L1372-1 assume !(1 == ~E_2~0); 3791#L1377-1 assume !(1 == ~E_3~0); 4084#L1382-1 assume !(1 == ~E_4~0); 4085#L1387-1 assume !(1 == ~E_5~0); 4654#L1392-1 assume !(1 == ~E_6~0); 4104#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4105#L1402-1 assume !(1 == ~E_8~0); 3801#L1407-1 assume !(1 == ~E_9~0); 3802#L1412-1 assume !(1 == ~E_10~0); 4817#L1417-1 assume !(1 == ~E_11~0); 4818#L1422-1 assume !(1 == ~E_12~0); 5036#L1427-1 assume { :end_inline_reset_delta_events } true; 3605#L1768-2 [2021-11-13 18:36:23,886 INFO L793 eck$LassoCheckResult]: Loop: 3605#L1768-2 assume !false; 3606#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4344#L1149 assume !false; 4716#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4869#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3995#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3901#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 3902#L976 assume !(0 != eval_~tmp~0#1); 5035#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5045#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4836#L1174-3 assume !(0 == ~M_E~0); 4829#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4578#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4579#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4762#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4413#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3763#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3764#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4005#L1209-3 assume !(0 == ~T8_E~0); 3425#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3426#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4184#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4185#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4203#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3613#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3614#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4057#L1249-3 assume !(0 == ~E_4~0); 4516#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4988#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4630#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3619#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3620#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5015#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4182#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4183#L1289-3 assume !(0 == ~E_12~0); 4171#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3847#L566-39 assume 1 == ~m_pc~0; 3848#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4450#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4162#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4163#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4705#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4706#L585-39 assume 1 == ~t1_pc~0; 4816#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3856#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3931#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3932#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4738#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4431#L604-39 assume 1 == ~t2_pc~0; 4432#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4063#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4064#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4481#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4482#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4046#L623-39 assume 1 == ~t3_pc~0; 3442#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3444#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4722#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3898#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3899#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4670#L642-39 assume 1 == ~t4_pc~0; 4241#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4242#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3770#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3771#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4868#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3819#L661-39 assume !(1 == ~t5_pc~0); 3450#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 3451#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4811#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4812#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4725#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4726#L680-39 assume 1 == ~t6_pc~0; 3512#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3513#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4655#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3978#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3979#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4993#L699-39 assume !(1 == ~t7_pc~0); 4416#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 4137#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4138#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4821#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4942#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4940#L718-39 assume 1 == ~t8_pc~0; 4329#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4330#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4262#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4263#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 4565#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4534#L737-39 assume 1 == ~t9_pc~0; 3959#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3960#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4249#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5016#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4917#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4860#L756-39 assume !(1 == ~t10_pc~0); 4341#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 4342#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4086#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4087#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4219#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3559#L775-39 assume 1 == ~t11_pc~0; 3560#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4212#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4213#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5075#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4623#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4270#L794-39 assume !(1 == ~t12_pc~0); 3955#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 3956#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4776#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4677#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3501#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3502#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4969#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4970#L1312-3 assume !(1 == ~T2_E~0); 5081#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4695#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4696#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3640#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3611#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3612#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4358#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4483#L1352-3 assume !(1 == ~T10_E~0); 4484#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4923#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5074#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5065#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3438#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3439#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4070#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4071#L1392-3 assume !(1 == ~E_6~0); 4786#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5032#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4449#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3725#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3726#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4374#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4375#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3735#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3736#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4602#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4454#L1787 assume !(0 == start_simulation_~tmp~3#1); 4455#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4978#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3706#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4501#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 4502#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4053#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4054#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 4055#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 3605#L1768-2 [2021-11-13 18:36:23,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:23,888 INFO L85 PathProgramCache]: Analyzing trace with hash -1422298547, now seen corresponding path program 2 times [2021-11-13 18:36:23,889 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:23,889 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2037839948] [2021-11-13 18:36:23,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:23,890 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:23,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:24,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:24,036 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:24,036 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2037839948] [2021-11-13 18:36:24,037 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2037839948] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:24,044 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:24,044 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:24,044 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [16448900] [2021-11-13 18:36:24,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:24,079 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:24,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:24,081 INFO L85 PathProgramCache]: Analyzing trace with hash -1764555615, now seen corresponding path program 1 times [2021-11-13 18:36:24,081 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:24,081 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [279244362] [2021-11-13 18:36:24,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:24,082 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:24,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:24,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:24,306 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:24,306 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [279244362] [2021-11-13 18:36:24,307 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [279244362] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:24,307 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:24,307 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:24,308 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [682380814] [2021-11-13 18:36:24,308 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:24,309 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:24,309 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:24,309 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:36:24,310 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:36:24,310 INFO L87 Difference]: Start difference. First operand 1688 states and 2504 transitions. cyclomatic complexity: 817 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:24,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:24,395 INFO L93 Difference]: Finished difference Result 1688 states and 2503 transitions. [2021-11-13 18:36:24,396 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:36:24,399 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2503 transitions. [2021-11-13 18:36:24,422 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:24,443 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2503 transitions. [2021-11-13 18:36:24,443 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-13 18:36:24,446 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-13 18:36:24,446 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2503 transitions. [2021-11-13 18:36:24,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:24,450 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2503 transitions. [2021-11-13 18:36:24,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2503 transitions. [2021-11-13 18:36:24,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-13 18:36:24,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4828199052132702) internal successors, (2503), 1687 states have internal predecessors, (2503), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:24,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2503 transitions. [2021-11-13 18:36:24,497 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2503 transitions. [2021-11-13 18:36:24,497 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2503 transitions. [2021-11-13 18:36:24,497 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-13 18:36:24,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2503 transitions. [2021-11-13 18:36:24,514 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:24,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:24,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:24,517 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:24,518 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:24,520 INFO L791 eck$LassoCheckResult]: Stem: 7584#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 7585#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 8438#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7930#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7737#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 7738#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7823#L826-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8124#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8246#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8247#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7035#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7036#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8184#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7630#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7631#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7537#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7538#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 7926#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7279#L1174 assume !(0 == ~M_E~0); 7280#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7131#L1179-1 assume !(0 == ~T2_E~0); 7033#L1184-1 assume !(0 == ~T3_E~0); 7034#L1189-1 assume !(0 == ~T4_E~0); 7072#L1194-1 assume !(0 == ~T5_E~0); 7172#L1199-1 assume !(0 == ~T6_E~0); 8067#L1204-1 assume !(0 == ~T7_E~0); 7986#L1209-1 assume !(0 == ~T8_E~0); 7987#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8375#L1219-1 assume !(0 == ~T10_E~0); 8460#L1224-1 assume !(0 == ~T11_E~0); 7397#L1229-1 assume !(0 == ~T12_E~0); 6958#L1234-1 assume !(0 == ~E_1~0); 6959#L1239-1 assume !(0 == ~E_2~0); 6992#L1244-1 assume !(0 == ~E_3~0); 6993#L1249-1 assume !(0 == ~E_4~0); 7654#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6888#L1259-1 assume !(0 == ~E_6~0); 6843#L1264-1 assume !(0 == ~E_7~0); 6844#L1269-1 assume !(0 == ~E_8~0); 8465#L1274-1 assume !(0 == ~E_9~0); 8400#L1279-1 assume !(0 == ~E_10~0); 7076#L1284-1 assume !(0 == ~E_11~0); 7077#L1289-1 assume !(0 == ~E_12~0); 7706#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7707#L566 assume 1 == ~m_pc~0; 6860#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6861#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8015#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8016#L1455 assume !(0 != activate_threads_~tmp~1#1); 7306#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7307#L585 assume 1 == ~t1_pc~0; 6955#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6956#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7956#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7957#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 8425#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8423#L604 assume !(1 == ~t2_pc~0); 8035#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8036#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7569#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7570#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8207#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8208#L623 assume 1 == ~t3_pc~0; 7484#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6824#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7634#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7635#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 8242#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6857#L642 assume !(1 == ~t4_pc~0); 6858#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7323#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7324#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6929#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 6930#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8047#L661 assume 1 == ~t5_pc~0; 7094#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7095#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7056#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7057#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 8076#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8077#L680 assume !(1 == ~t6_pc~0); 7517#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7518#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7779#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7780#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 8308#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8421#L699 assume 1 == ~t7_pc~0; 7907#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7908#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7084#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7085#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 7809#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7708#L718 assume !(1 == ~t8_pc~0); 7709#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7070#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7071#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7112#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 7113#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7246#L737 assume 1 == ~t9_pc~0; 8111#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7381#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7982#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7983#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 7555#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7556#L756 assume 1 == ~t10_pc~0; 8135#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7801#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6787#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 6788#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 7363#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7364#L775 assume !(1 == ~t11_pc~0); 7618#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 7619#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7240#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7004#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7005#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7191#L794 assume 1 == ~t12_pc~0; 7031#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7009#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8202#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 7157#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 7158#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7637#L1307 assume !(1 == ~M_E~0); 7638#L1307-2 assume !(1 == ~T1_E~0); 7749#L1312-1 assume !(1 == ~T2_E~0); 7668#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7669#L1322-1 assume !(1 == ~T4_E~0); 7372#L1327-1 assume !(1 == ~T5_E~0); 7373#L1332-1 assume !(1 == ~T6_E~0); 7911#L1337-1 assume !(1 == ~T7_E~0); 7873#L1342-1 assume !(1 == ~T8_E~0); 7874#L1347-1 assume !(1 == ~T9_E~0); 8271#L1352-1 assume !(1 == ~T10_E~0); 8144#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7535#L1362-1 assume !(1 == ~T12_E~0); 7536#L1367-1 assume !(1 == ~E_1~0); 7173#L1372-1 assume !(1 == ~E_2~0); 7174#L1377-1 assume !(1 == ~E_3~0); 7467#L1382-1 assume !(1 == ~E_4~0); 7468#L1387-1 assume !(1 == ~E_5~0); 8037#L1392-1 assume !(1 == ~E_6~0); 7487#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7488#L1402-1 assume !(1 == ~E_8~0); 7184#L1407-1 assume !(1 == ~E_9~0); 7185#L1412-1 assume !(1 == ~E_10~0); 8200#L1417-1 assume !(1 == ~E_11~0); 8201#L1422-1 assume !(1 == ~E_12~0); 8419#L1427-1 assume { :end_inline_reset_delta_events } true; 6988#L1768-2 [2021-11-13 18:36:24,521 INFO L793 eck$LassoCheckResult]: Loop: 6988#L1768-2 assume !false; 6989#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7727#L1149 assume !false; 8099#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8252#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7378#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7284#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 7285#L976 assume !(0 != eval_~tmp~0#1); 8418#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8428#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8219#L1174-3 assume !(0 == ~M_E~0); 8212#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7961#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7962#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8145#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7796#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7146#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7147#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7388#L1209-3 assume !(0 == ~T8_E~0); 6808#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6809#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7567#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7568#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 7586#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6996#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6997#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7440#L1249-3 assume !(0 == ~E_4~0); 7899#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8371#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8013#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7002#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7003#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8398#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7565#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7566#L1289-3 assume !(0 == ~E_12~0); 7554#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7230#L566-39 assume !(1 == ~m_pc~0); 7232#L566-41 is_master_triggered_~__retres1~0#1 := 0; 7833#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7545#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7546#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8088#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8089#L585-39 assume !(1 == ~t1_pc~0); 7238#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 7239#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7314#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7315#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8121#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7814#L604-39 assume 1 == ~t2_pc~0; 7815#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7446#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7447#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7864#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7865#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7429#L623-39 assume 1 == ~t3_pc~0; 6825#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6827#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8105#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7281#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7282#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8053#L642-39 assume 1 == ~t4_pc~0; 7624#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7625#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7153#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7154#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8251#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7202#L661-39 assume !(1 == ~t5_pc~0); 6833#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 6834#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8194#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8195#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8108#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8109#L680-39 assume !(1 == ~t6_pc~0); 6897#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 6896#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8038#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7361#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7362#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8376#L699-39 assume 1 == ~t7_pc~0; 7798#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7520#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7521#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8204#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8325#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8323#L718-39 assume 1 == ~t8_pc~0; 7712#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7713#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7645#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7646#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 7948#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7917#L737-39 assume !(1 == ~t9_pc~0); 7344#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 7343#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7632#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8399#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8300#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8243#L756-39 assume 1 == ~t10_pc~0; 8244#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7725#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7469#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7470#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 7602#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6942#L775-39 assume !(1 == ~t11_pc~0); 6944#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 7595#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7596#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8458#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8006#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7653#L794-39 assume 1 == ~t12_pc~0; 7345#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7339#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8159#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8060#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 6884#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6885#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8352#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8353#L1312-3 assume !(1 == ~T2_E~0); 8464#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8078#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8079#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7023#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6994#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6995#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7741#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7866#L1352-3 assume !(1 == ~T10_E~0); 7867#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8306#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8457#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8448#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6821#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6822#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7453#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7454#L1392-3 assume !(1 == ~E_6~0); 8169#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8415#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7832#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7108#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7109#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7757#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 7758#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7118#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7119#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7985#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 7837#L1787 assume !(0 == start_simulation_~tmp~3#1); 7838#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8361#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7089#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7884#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 7885#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7436#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7437#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 7438#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 6988#L1768-2 [2021-11-13 18:36:24,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:24,526 INFO L85 PathProgramCache]: Analyzing trace with hash -1760586097, now seen corresponding path program 1 times [2021-11-13 18:36:24,526 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:24,526 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542205956] [2021-11-13 18:36:24,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:24,527 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:24,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:24,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:24,655 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:24,655 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1542205956] [2021-11-13 18:36:24,656 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1542205956] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:24,656 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:24,657 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:24,657 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1224056742] [2021-11-13 18:36:24,658 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:24,659 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:24,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:24,661 INFO L85 PathProgramCache]: Analyzing trace with hash 1578992735, now seen corresponding path program 1 times [2021-11-13 18:36:24,661 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:24,661 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1301820165] [2021-11-13 18:36:24,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:24,664 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:24,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:24,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:24,746 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:24,746 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1301820165] [2021-11-13 18:36:24,747 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1301820165] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:24,747 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:24,747 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:24,748 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1832217577] [2021-11-13 18:36:24,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:24,749 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:24,749 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:24,749 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:36:24,750 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:36:24,750 INFO L87 Difference]: Start difference. First operand 1688 states and 2503 transitions. cyclomatic complexity: 816 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:24,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:24,807 INFO L93 Difference]: Finished difference Result 1688 states and 2502 transitions. [2021-11-13 18:36:24,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:36:24,809 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2502 transitions. [2021-11-13 18:36:24,877 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:24,896 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2502 transitions. [2021-11-13 18:36:24,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-13 18:36:24,898 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-13 18:36:24,899 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2502 transitions. [2021-11-13 18:36:24,902 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:24,902 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2502 transitions. [2021-11-13 18:36:24,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2502 transitions. [2021-11-13 18:36:24,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-13 18:36:24,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4822274881516588) internal successors, (2502), 1687 states have internal predecessors, (2502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:24,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2502 transitions. [2021-11-13 18:36:24,947 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2502 transitions. [2021-11-13 18:36:24,948 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2502 transitions. [2021-11-13 18:36:24,948 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-13 18:36:24,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2502 transitions. [2021-11-13 18:36:24,964 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:24,964 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:24,964 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:24,968 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:24,968 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:24,969 INFO L791 eck$LassoCheckResult]: Stem: 10967#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 10968#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11821#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11313#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11120#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 11121#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11206#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11507#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 11629#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11630#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10418#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10419#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11567#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11013#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11014#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10920#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 10921#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11309#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10662#L1174 assume !(0 == ~M_E~0); 10663#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10514#L1179-1 assume !(0 == ~T2_E~0); 10416#L1184-1 assume !(0 == ~T3_E~0); 10417#L1189-1 assume !(0 == ~T4_E~0); 10455#L1194-1 assume !(0 == ~T5_E~0); 10555#L1199-1 assume !(0 == ~T6_E~0); 11450#L1204-1 assume !(0 == ~T7_E~0); 11369#L1209-1 assume !(0 == ~T8_E~0); 11370#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11758#L1219-1 assume !(0 == ~T10_E~0); 11843#L1224-1 assume !(0 == ~T11_E~0); 10780#L1229-1 assume !(0 == ~T12_E~0); 10341#L1234-1 assume !(0 == ~E_1~0); 10342#L1239-1 assume !(0 == ~E_2~0); 10375#L1244-1 assume !(0 == ~E_3~0); 10376#L1249-1 assume !(0 == ~E_4~0); 11037#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10271#L1259-1 assume !(0 == ~E_6~0); 10226#L1264-1 assume !(0 == ~E_7~0); 10227#L1269-1 assume !(0 == ~E_8~0); 11848#L1274-1 assume !(0 == ~E_9~0); 11783#L1279-1 assume !(0 == ~E_10~0); 10459#L1284-1 assume !(0 == ~E_11~0); 10460#L1289-1 assume !(0 == ~E_12~0); 11089#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11090#L566 assume 1 == ~m_pc~0; 10243#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10244#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11398#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11399#L1455 assume !(0 != activate_threads_~tmp~1#1); 10689#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10690#L585 assume 1 == ~t1_pc~0; 10338#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10339#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11339#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11340#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 11808#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11806#L604 assume !(1 == ~t2_pc~0); 11418#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11419#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10952#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10953#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11590#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11591#L623 assume 1 == ~t3_pc~0; 10867#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10207#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11017#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11018#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 11625#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10240#L642 assume !(1 == ~t4_pc~0); 10241#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10706#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10707#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10312#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 10313#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11430#L661 assume 1 == ~t5_pc~0; 10477#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10478#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10439#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10440#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 11459#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11460#L680 assume !(1 == ~t6_pc~0); 10900#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10901#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11162#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11163#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 11691#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11804#L699 assume 1 == ~t7_pc~0; 11290#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11291#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10467#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10468#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 11192#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11091#L718 assume !(1 == ~t8_pc~0); 11092#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10453#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10454#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10495#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 10496#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10629#L737 assume 1 == ~t9_pc~0; 11494#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10764#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11365#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11366#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 10938#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10939#L756 assume 1 == ~t10_pc~0; 11518#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11184#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10170#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10171#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 10746#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10747#L775 assume !(1 == ~t11_pc~0); 11001#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 11002#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10623#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10387#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10388#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 10574#L794 assume 1 == ~t12_pc~0; 10414#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 10392#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11585#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 10540#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 10541#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11020#L1307 assume !(1 == ~M_E~0); 11021#L1307-2 assume !(1 == ~T1_E~0); 11132#L1312-1 assume !(1 == ~T2_E~0); 11051#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11052#L1322-1 assume !(1 == ~T4_E~0); 10755#L1327-1 assume !(1 == ~T5_E~0); 10756#L1332-1 assume !(1 == ~T6_E~0); 11294#L1337-1 assume !(1 == ~T7_E~0); 11256#L1342-1 assume !(1 == ~T8_E~0); 11257#L1347-1 assume !(1 == ~T9_E~0); 11654#L1352-1 assume !(1 == ~T10_E~0); 11527#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10918#L1362-1 assume !(1 == ~T12_E~0); 10919#L1367-1 assume !(1 == ~E_1~0); 10556#L1372-1 assume !(1 == ~E_2~0); 10557#L1377-1 assume !(1 == ~E_3~0); 10850#L1382-1 assume !(1 == ~E_4~0); 10851#L1387-1 assume !(1 == ~E_5~0); 11420#L1392-1 assume !(1 == ~E_6~0); 10870#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10871#L1402-1 assume !(1 == ~E_8~0); 10567#L1407-1 assume !(1 == ~E_9~0); 10568#L1412-1 assume !(1 == ~E_10~0); 11583#L1417-1 assume !(1 == ~E_11~0); 11584#L1422-1 assume !(1 == ~E_12~0); 11802#L1427-1 assume { :end_inline_reset_delta_events } true; 10371#L1768-2 [2021-11-13 18:36:24,969 INFO L793 eck$LassoCheckResult]: Loop: 10371#L1768-2 assume !false; 10372#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11110#L1149 assume !false; 11482#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11635#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10761#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10667#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 10668#L976 assume !(0 != eval_~tmp~0#1); 11801#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11811#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11602#L1174-3 assume !(0 == ~M_E~0); 11595#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11344#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11345#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11528#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11179#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10529#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10530#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10771#L1209-3 assume !(0 == ~T8_E~0); 10191#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10192#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10950#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 10951#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 10969#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10379#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10380#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10823#L1249-3 assume !(0 == ~E_4~0); 11282#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11754#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11396#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10385#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10386#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11781#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 10948#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10949#L1289-3 assume !(0 == ~E_12~0); 10937#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10613#L566-39 assume 1 == ~m_pc~0; 10614#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11216#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10928#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10929#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11471#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11472#L585-39 assume !(1 == ~t1_pc~0); 10621#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 10622#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10697#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10698#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11504#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11197#L604-39 assume 1 == ~t2_pc~0; 11198#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10829#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10830#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11247#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11248#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10812#L623-39 assume 1 == ~t3_pc~0; 10208#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10210#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11488#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10664#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10665#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11436#L642-39 assume !(1 == ~t4_pc~0); 11009#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 11008#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10536#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10537#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11634#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10585#L661-39 assume !(1 == ~t5_pc~0); 10216#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 10217#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11577#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11578#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11491#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11492#L680-39 assume 1 == ~t6_pc~0; 10278#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10279#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11421#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10744#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10745#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11759#L699-39 assume 1 == ~t7_pc~0; 11181#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10903#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10904#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11587#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11708#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11706#L718-39 assume 1 == ~t8_pc~0; 11095#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11096#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11028#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11029#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 11331#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11300#L737-39 assume 1 == ~t9_pc~0; 10725#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10726#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11015#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11782#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11683#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11626#L756-39 assume !(1 == ~t10_pc~0); 11107#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 11108#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10852#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10853#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 10985#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10325#L775-39 assume 1 == ~t11_pc~0; 10326#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10978#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10979#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11841#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11389#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11036#L794-39 assume !(1 == ~t12_pc~0); 10721#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 10722#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11542#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 11443#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 10267#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10268#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11735#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11736#L1312-3 assume !(1 == ~T2_E~0); 11847#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11461#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11462#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10406#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10377#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10378#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11124#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11249#L1352-3 assume !(1 == ~T10_E~0); 11250#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11689#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11840#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11831#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10204#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10205#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10836#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10837#L1392-3 assume !(1 == ~E_6~0); 11552#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11798#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11215#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10491#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10492#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 11140#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 11141#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 10501#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10502#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11368#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11220#L1787 assume !(0 == start_simulation_~tmp~3#1); 11221#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11744#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10472#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11267#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 11268#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10819#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10820#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 10821#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 10371#L1768-2 [2021-11-13 18:36:24,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:24,971 INFO L85 PathProgramCache]: Analyzing trace with hash -1220156591, now seen corresponding path program 1 times [2021-11-13 18:36:24,971 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:24,972 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [621372137] [2021-11-13 18:36:24,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:24,972 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:24,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:25,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:25,021 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:25,021 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [621372137] [2021-11-13 18:36:25,021 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [621372137] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:25,022 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:25,022 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:25,022 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [155387894] [2021-11-13 18:36:25,022 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:25,023 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:25,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:25,024 INFO L85 PathProgramCache]: Analyzing trace with hash -601300672, now seen corresponding path program 1 times [2021-11-13 18:36:25,024 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:25,025 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295914111] [2021-11-13 18:36:25,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:25,025 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:25,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:25,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:25,117 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:25,118 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [295914111] [2021-11-13 18:36:25,119 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [295914111] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:25,119 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:25,119 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:25,119 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1863127108] [2021-11-13 18:36:25,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:25,120 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:25,121 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:25,121 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:36:25,121 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:36:25,122 INFO L87 Difference]: Start difference. First operand 1688 states and 2502 transitions. cyclomatic complexity: 815 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:25,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:25,188 INFO L93 Difference]: Finished difference Result 1688 states and 2501 transitions. [2021-11-13 18:36:25,188 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:36:25,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2501 transitions. [2021-11-13 18:36:25,211 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:25,230 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2501 transitions. [2021-11-13 18:36:25,230 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-13 18:36:25,233 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-13 18:36:25,233 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2501 transitions. [2021-11-13 18:36:25,238 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:25,238 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2501 transitions. [2021-11-13 18:36:25,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2501 transitions. [2021-11-13 18:36:25,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-13 18:36:25,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4816350710900474) internal successors, (2501), 1687 states have internal predecessors, (2501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:25,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2501 transitions. [2021-11-13 18:36:25,288 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2501 transitions. [2021-11-13 18:36:25,288 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2501 transitions. [2021-11-13 18:36:25,288 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-13 18:36:25,289 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2501 transitions. [2021-11-13 18:36:25,303 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:25,304 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:25,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:25,307 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:25,308 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:25,308 INFO L791 eck$LassoCheckResult]: Stem: 14351#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 14352#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 15204#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14698#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14503#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 14504#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14589#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14891#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15012#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 15013#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13801#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13802#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14950#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14396#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14397#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14303#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 14304#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 14693#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14045#L1174 assume !(0 == ~M_E~0); 14046#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13897#L1179-1 assume !(0 == ~T2_E~0); 13799#L1184-1 assume !(0 == ~T3_E~0); 13800#L1189-1 assume !(0 == ~T4_E~0); 13838#L1194-1 assume !(0 == ~T5_E~0); 13938#L1199-1 assume !(0 == ~T6_E~0); 14833#L1204-1 assume !(0 == ~T7_E~0); 14752#L1209-1 assume !(0 == ~T8_E~0); 14753#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15141#L1219-1 assume !(0 == ~T10_E~0); 15226#L1224-1 assume !(0 == ~T11_E~0); 14164#L1229-1 assume !(0 == ~T12_E~0); 13726#L1234-1 assume !(0 == ~E_1~0); 13727#L1239-1 assume !(0 == ~E_2~0); 13760#L1244-1 assume !(0 == ~E_3~0); 13761#L1249-1 assume !(0 == ~E_4~0); 14420#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 13654#L1259-1 assume !(0 == ~E_6~0); 13609#L1264-1 assume !(0 == ~E_7~0); 13610#L1269-1 assume !(0 == ~E_8~0); 15231#L1274-1 assume !(0 == ~E_9~0); 15166#L1279-1 assume !(0 == ~E_10~0); 13842#L1284-1 assume !(0 == ~E_11~0); 13843#L1289-1 assume !(0 == ~E_12~0); 14472#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14473#L566 assume 1 == ~m_pc~0; 13626#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13627#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14781#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14782#L1455 assume !(0 != activate_threads_~tmp~1#1); 14072#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14073#L585 assume 1 == ~t1_pc~0; 13721#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13722#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14722#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14723#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 15191#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15189#L604 assume !(1 == ~t2_pc~0); 14801#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14802#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14335#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14336#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14975#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14976#L623 assume 1 == ~t3_pc~0; 14250#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13590#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14400#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14401#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 15008#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13623#L642 assume !(1 == ~t4_pc~0); 13624#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14089#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14090#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13697#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 13698#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14813#L661 assume 1 == ~t5_pc~0; 13860#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13861#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13822#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13823#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 14844#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14845#L680 assume !(1 == ~t6_pc~0); 14283#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14284#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14545#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14546#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 15074#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15187#L699 assume 1 == ~t7_pc~0; 14673#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14674#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13850#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13851#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 14575#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14474#L718 assume !(1 == ~t8_pc~0); 14475#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 13836#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13837#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13878#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 13879#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14012#L737 assume 1 == ~t9_pc~0; 14878#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14148#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14748#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14749#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 14321#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14322#L756 assume 1 == ~t10_pc~0; 14901#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14567#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13553#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13554#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 14129#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14130#L775 assume !(1 == ~t11_pc~0); 14384#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 14385#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14009#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13770#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13771#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13957#L794 assume 1 == ~t12_pc~0; 13798#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 13775#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14968#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13925#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 13926#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14403#L1307 assume !(1 == ~M_E~0); 14404#L1307-2 assume !(1 == ~T1_E~0); 14515#L1312-1 assume !(1 == ~T2_E~0); 14434#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14435#L1322-1 assume !(1 == ~T4_E~0); 14138#L1327-1 assume !(1 == ~T5_E~0); 14139#L1332-1 assume !(1 == ~T6_E~0); 14677#L1337-1 assume !(1 == ~T7_E~0); 14639#L1342-1 assume !(1 == ~T8_E~0); 14640#L1347-1 assume !(1 == ~T9_E~0); 15037#L1352-1 assume !(1 == ~T10_E~0); 14910#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14301#L1362-1 assume !(1 == ~T12_E~0); 14302#L1367-1 assume !(1 == ~E_1~0); 13939#L1372-1 assume !(1 == ~E_2~0); 13940#L1377-1 assume !(1 == ~E_3~0); 14233#L1382-1 assume !(1 == ~E_4~0); 14234#L1387-1 assume !(1 == ~E_5~0); 14803#L1392-1 assume !(1 == ~E_6~0); 14255#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14256#L1402-1 assume !(1 == ~E_8~0); 13955#L1407-1 assume !(1 == ~E_9~0); 13956#L1412-1 assume !(1 == ~E_10~0); 14966#L1417-1 assume !(1 == ~E_11~0); 14967#L1422-1 assume !(1 == ~E_12~0); 15185#L1427-1 assume { :end_inline_reset_delta_events } true; 13754#L1768-2 [2021-11-13 18:36:25,309 INFO L793 eck$LassoCheckResult]: Loop: 13754#L1768-2 assume !false; 13755#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14495#L1149 assume !false; 14866#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15018#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14144#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14056#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 14057#L976 assume !(0 != eval_~tmp~0#1); 15184#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15194#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14985#L1174-3 assume !(0 == ~M_E~0); 14978#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14727#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14728#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14912#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14562#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13915#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13916#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14154#L1209-3 assume !(0 == ~T8_E~0); 13574#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13575#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14333#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14334#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14353#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13762#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13763#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14209#L1249-3 assume !(0 == ~E_4~0); 14665#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15137#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14779#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13768#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13769#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15164#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14331#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14332#L1289-3 assume !(0 == ~E_12~0); 14320#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13993#L566-39 assume 1 == ~m_pc~0; 13994#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14599#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14311#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14312#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14854#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14855#L585-39 assume !(1 == ~t1_pc~0); 14004#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 14005#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14080#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14081#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14887#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14580#L604-39 assume 1 == ~t2_pc~0; 14581#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14212#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14213#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14630#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14631#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14195#L623-39 assume 1 == ~t3_pc~0; 13591#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13593#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14871#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14047#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14048#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14819#L642-39 assume 1 == ~t4_pc~0; 14390#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14391#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13919#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13920#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15017#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13968#L661-39 assume 1 == ~t5_pc~0; 13969#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13600#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14960#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14961#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14874#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14875#L680-39 assume 1 == ~t6_pc~0; 13661#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13662#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14804#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14127#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14128#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15142#L699-39 assume 1 == ~t7_pc~0; 14564#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14286#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14287#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14970#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15091#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15089#L718-39 assume !(1 == ~t8_pc~0); 14480#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 14479#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14411#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14412#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 14713#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14683#L737-39 assume 1 == ~t9_pc~0; 14108#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14109#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14398#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15165#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15066#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15009#L756-39 assume 1 == ~t10_pc~0; 15010#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14491#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14235#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14236#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14368#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13708#L775-39 assume 1 == ~t11_pc~0; 13709#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14361#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14362#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15224#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14772#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 14419#L794-39 assume !(1 == ~t12_pc~0); 14104#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 14105#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14925#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 14826#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13650#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13651#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15118#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15119#L1312-3 assume !(1 == ~T2_E~0); 15230#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14842#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14843#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13789#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13758#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13759#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14507#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14632#L1352-3 assume !(1 == ~T10_E~0); 14633#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15072#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15223#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15214#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13584#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13585#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14219#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14220#L1392-3 assume !(1 == ~E_6~0); 14935#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15181#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14598#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13874#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13875#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 14523#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 14524#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 13884#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 13885#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14751#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 14602#L1787 assume !(0 == start_simulation_~tmp~3#1); 14603#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15127#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 13855#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14650#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 14651#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14202#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14203#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 14204#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 13754#L1768-2 [2021-11-13 18:36:25,310 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:25,310 INFO L85 PathProgramCache]: Analyzing trace with hash -1064176049, now seen corresponding path program 1 times [2021-11-13 18:36:25,311 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:25,311 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1454839426] [2021-11-13 18:36:25,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:25,312 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:25,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:25,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:25,407 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:25,407 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1454839426] [2021-11-13 18:36:25,407 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1454839426] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:25,408 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:25,408 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:25,408 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [335432964] [2021-11-13 18:36:25,408 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:25,409 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:25,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:25,410 INFO L85 PathProgramCache]: Analyzing trace with hash 1933371202, now seen corresponding path program 1 times [2021-11-13 18:36:25,410 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:25,411 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1904764645] [2021-11-13 18:36:25,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:25,411 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:25,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:25,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:25,490 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:25,491 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1904764645] [2021-11-13 18:36:25,491 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1904764645] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:25,491 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:25,493 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:25,493 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [127952947] [2021-11-13 18:36:25,494 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:25,494 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:25,495 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:25,495 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:36:25,495 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:36:25,496 INFO L87 Difference]: Start difference. First operand 1688 states and 2501 transitions. cyclomatic complexity: 814 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:25,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:25,553 INFO L93 Difference]: Finished difference Result 1688 states and 2500 transitions. [2021-11-13 18:36:25,553 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:36:25,557 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2500 transitions. [2021-11-13 18:36:25,580 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:25,601 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2500 transitions. [2021-11-13 18:36:25,602 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-13 18:36:25,604 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-13 18:36:25,605 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2500 transitions. [2021-11-13 18:36:25,608 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:25,609 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2500 transitions. [2021-11-13 18:36:25,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2500 transitions. [2021-11-13 18:36:25,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-13 18:36:25,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.481042654028436) internal successors, (2500), 1687 states have internal predecessors, (2500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:25,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2500 transitions. [2021-11-13 18:36:25,660 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2500 transitions. [2021-11-13 18:36:25,661 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2500 transitions. [2021-11-13 18:36:25,661 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-13 18:36:25,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2500 transitions. [2021-11-13 18:36:25,673 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:25,673 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:25,673 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:25,677 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:25,677 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:25,678 INFO L791 eck$LassoCheckResult]: Stem: 17733#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 17734#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 18587#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18081#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17886#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 17887#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17972#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18273#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18395#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18396#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17184#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17185#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18333#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17779#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17780#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17686#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17687#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18076#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17428#L1174 assume !(0 == ~M_E~0); 17429#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17280#L1179-1 assume !(0 == ~T2_E~0); 17182#L1184-1 assume !(0 == ~T3_E~0); 17183#L1189-1 assume !(0 == ~T4_E~0); 17221#L1194-1 assume !(0 == ~T5_E~0); 17321#L1199-1 assume !(0 == ~T6_E~0); 18216#L1204-1 assume !(0 == ~T7_E~0); 18135#L1209-1 assume !(0 == ~T8_E~0); 18136#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18524#L1219-1 assume !(0 == ~T10_E~0); 18609#L1224-1 assume !(0 == ~T11_E~0); 17546#L1229-1 assume !(0 == ~T12_E~0); 17107#L1234-1 assume !(0 == ~E_1~0); 17108#L1239-1 assume !(0 == ~E_2~0); 17143#L1244-1 assume !(0 == ~E_3~0); 17144#L1249-1 assume !(0 == ~E_4~0); 17803#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17037#L1259-1 assume !(0 == ~E_6~0); 16992#L1264-1 assume !(0 == ~E_7~0); 16993#L1269-1 assume !(0 == ~E_8~0); 18614#L1274-1 assume !(0 == ~E_9~0); 18549#L1279-1 assume !(0 == ~E_10~0); 17225#L1284-1 assume !(0 == ~E_11~0); 17226#L1289-1 assume !(0 == ~E_12~0); 17855#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17856#L566 assume 1 == ~m_pc~0; 17009#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17010#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18164#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18165#L1455 assume !(0 != activate_threads_~tmp~1#1); 17455#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17456#L585 assume 1 == ~t1_pc~0; 17104#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17105#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18105#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18106#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 18574#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18572#L604 assume !(1 == ~t2_pc~0); 18184#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18185#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17718#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17719#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18358#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18359#L623 assume 1 == ~t3_pc~0; 17633#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16973#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17783#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17784#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 18391#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17006#L642 assume !(1 == ~t4_pc~0); 17007#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17472#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17473#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17078#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 17079#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18196#L661 assume 1 == ~t5_pc~0; 17243#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17244#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17205#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17206#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 18227#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18228#L680 assume !(1 == ~t6_pc~0); 17666#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17667#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17928#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17929#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 18457#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18570#L699 assume 1 == ~t7_pc~0; 18056#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18057#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17233#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17234#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 17958#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17857#L718 assume !(1 == ~t8_pc~0); 17858#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17219#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17220#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17261#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 17262#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17395#L737 assume 1 == ~t9_pc~0; 18261#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17530#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18131#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18132#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 17704#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17705#L756 assume 1 == ~t10_pc~0; 18284#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17950#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16936#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16937#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 17512#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17513#L775 assume !(1 == ~t11_pc~0); 17767#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 17768#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17389#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17153#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17154#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17340#L794 assume 1 == ~t12_pc~0; 17181#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17158#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18351#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17308#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 17309#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17786#L1307 assume !(1 == ~M_E~0); 17787#L1307-2 assume !(1 == ~T1_E~0); 17898#L1312-1 assume !(1 == ~T2_E~0); 17817#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17818#L1322-1 assume !(1 == ~T4_E~0); 17521#L1327-1 assume !(1 == ~T5_E~0); 17522#L1332-1 assume !(1 == ~T6_E~0); 18060#L1337-1 assume !(1 == ~T7_E~0); 18022#L1342-1 assume !(1 == ~T8_E~0); 18023#L1347-1 assume !(1 == ~T9_E~0); 18420#L1352-1 assume !(1 == ~T10_E~0); 18293#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17684#L1362-1 assume !(1 == ~T12_E~0); 17685#L1367-1 assume !(1 == ~E_1~0); 17322#L1372-1 assume !(1 == ~E_2~0); 17323#L1377-1 assume !(1 == ~E_3~0); 17616#L1382-1 assume !(1 == ~E_4~0); 17617#L1387-1 assume !(1 == ~E_5~0); 18186#L1392-1 assume !(1 == ~E_6~0); 17638#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 17639#L1402-1 assume !(1 == ~E_8~0); 17335#L1407-1 assume !(1 == ~E_9~0); 17336#L1412-1 assume !(1 == ~E_10~0); 18349#L1417-1 assume !(1 == ~E_11~0); 18350#L1422-1 assume !(1 == ~E_12~0); 18568#L1427-1 assume { :end_inline_reset_delta_events } true; 17137#L1768-2 [2021-11-13 18:36:25,679 INFO L793 eck$LassoCheckResult]: Loop: 17137#L1768-2 assume !false; 17138#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17876#L1149 assume !false; 18248#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18401#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17527#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 17433#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 17434#L976 assume !(0 != eval_~tmp~0#1); 18567#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18577#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18368#L1174-3 assume !(0 == ~M_E~0); 18361#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18110#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18111#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18295#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17945#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17298#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17299#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17537#L1209-3 assume !(0 == ~T8_E~0); 16957#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16958#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17716#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17717#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17735#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17145#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17146#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17589#L1249-3 assume !(0 == ~E_4~0); 18048#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18520#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18162#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17151#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17152#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18547#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17714#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 17715#L1289-3 assume !(0 == ~E_12~0); 17703#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17379#L566-39 assume 1 == ~m_pc~0; 17380#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17982#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17694#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17695#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18237#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18238#L585-39 assume !(1 == ~t1_pc~0); 17387#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 17388#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17463#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17464#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18270#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17963#L604-39 assume 1 == ~t2_pc~0; 17964#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17595#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17596#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18015#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18016#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17578#L623-39 assume 1 == ~t3_pc~0; 16976#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16978#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18254#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17430#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17431#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18202#L642-39 assume !(1 == ~t4_pc~0); 17777#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 17776#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17302#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17303#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18400#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17353#L661-39 assume !(1 == ~t5_pc~0); 16982#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 16983#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18343#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18344#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18258#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18259#L680-39 assume 1 == ~t6_pc~0; 17046#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17047#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18187#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17510#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17511#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18525#L699-39 assume 1 == ~t7_pc~0; 17947#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17669#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17670#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18353#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18473#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18471#L718-39 assume 1 == ~t8_pc~0; 17861#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17862#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17794#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17795#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 18096#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18066#L737-39 assume 1 == ~t9_pc~0; 17491#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17492#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17781#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18548#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18449#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18392#L756-39 assume !(1 == ~t10_pc~0); 17873#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 17874#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17618#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17619#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17751#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17091#L775-39 assume 1 == ~t11_pc~0; 17092#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17744#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17745#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18607#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18155#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17802#L794-39 assume 1 == ~t12_pc~0; 17494#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17488#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18308#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 18209#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17033#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17034#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18501#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18502#L1312-3 assume !(1 == ~T2_E~0); 18613#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18225#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18226#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17170#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17141#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17142#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17890#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18013#L1352-3 assume !(1 == ~T10_E~0); 18014#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18454#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18606#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18597#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16967#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16968#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17602#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17603#L1392-3 assume !(1 == ~E_6~0); 18318#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18564#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17981#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17257#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17258#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17904#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17905#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 17267#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17268#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18134#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 17985#L1787 assume !(0 == start_simulation_~tmp~3#1); 17986#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18510#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17238#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18033#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 18034#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17585#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17586#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 17587#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 17137#L1768-2 [2021-11-13 18:36:25,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:25,681 INFO L85 PathProgramCache]: Analyzing trace with hash -1474786415, now seen corresponding path program 1 times [2021-11-13 18:36:25,681 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:25,681 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [553833358] [2021-11-13 18:36:25,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:25,682 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:25,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:25,740 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:25,741 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:25,742 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [553833358] [2021-11-13 18:36:25,742 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [553833358] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:25,742 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:25,743 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:25,743 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1794366466] [2021-11-13 18:36:25,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:25,744 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:25,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:25,745 INFO L85 PathProgramCache]: Analyzing trace with hash 673802017, now seen corresponding path program 1 times [2021-11-13 18:36:25,746 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:25,752 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1098320962] [2021-11-13 18:36:25,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:25,757 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:25,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:25,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:25,820 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:25,820 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1098320962] [2021-11-13 18:36:25,820 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1098320962] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:25,820 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:25,821 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:25,821 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1008967901] [2021-11-13 18:36:25,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:25,825 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:25,825 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:25,826 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:36:25,827 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:36:25,827 INFO L87 Difference]: Start difference. First operand 1688 states and 2500 transitions. cyclomatic complexity: 813 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:25,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:25,885 INFO L93 Difference]: Finished difference Result 1688 states and 2499 transitions. [2021-11-13 18:36:25,886 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:36:25,888 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2499 transitions. [2021-11-13 18:36:25,909 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:25,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2499 transitions. [2021-11-13 18:36:25,930 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-13 18:36:25,932 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-13 18:36:25,932 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2499 transitions. [2021-11-13 18:36:25,936 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:25,936 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2499 transitions. [2021-11-13 18:36:25,941 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2499 transitions. [2021-11-13 18:36:25,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-13 18:36:25,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4804502369668247) internal successors, (2499), 1687 states have internal predecessors, (2499), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:25,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2499 transitions. [2021-11-13 18:36:25,993 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2499 transitions. [2021-11-13 18:36:25,993 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2499 transitions. [2021-11-13 18:36:25,993 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-13 18:36:25,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2499 transitions. [2021-11-13 18:36:26,005 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:26,005 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:26,005 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:26,009 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:26,009 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:26,009 INFO L791 eck$LassoCheckResult]: Stem: 21116#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 21117#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 21970#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21462#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21269#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 21270#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21355#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21656#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21778#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21779#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20567#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20568#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21716#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21162#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21163#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21069#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21070#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21458#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20811#L1174 assume !(0 == ~M_E~0); 20812#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20663#L1179-1 assume !(0 == ~T2_E~0); 20565#L1184-1 assume !(0 == ~T3_E~0); 20566#L1189-1 assume !(0 == ~T4_E~0); 20604#L1194-1 assume !(0 == ~T5_E~0); 20704#L1199-1 assume !(0 == ~T6_E~0); 21599#L1204-1 assume !(0 == ~T7_E~0); 21518#L1209-1 assume !(0 == ~T8_E~0); 21519#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21907#L1219-1 assume !(0 == ~T10_E~0); 21992#L1224-1 assume !(0 == ~T11_E~0); 20929#L1229-1 assume !(0 == ~T12_E~0); 20490#L1234-1 assume !(0 == ~E_1~0); 20491#L1239-1 assume !(0 == ~E_2~0); 20524#L1244-1 assume !(0 == ~E_3~0); 20525#L1249-1 assume !(0 == ~E_4~0); 21186#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 20420#L1259-1 assume !(0 == ~E_6~0); 20375#L1264-1 assume !(0 == ~E_7~0); 20376#L1269-1 assume !(0 == ~E_8~0); 21997#L1274-1 assume !(0 == ~E_9~0); 21932#L1279-1 assume !(0 == ~E_10~0); 20608#L1284-1 assume !(0 == ~E_11~0); 20609#L1289-1 assume !(0 == ~E_12~0); 21238#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21239#L566 assume 1 == ~m_pc~0; 20392#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20393#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21547#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21548#L1455 assume !(0 != activate_threads_~tmp~1#1); 20838#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20839#L585 assume 1 == ~t1_pc~0; 20487#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20488#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21488#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21489#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 21957#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21955#L604 assume !(1 == ~t2_pc~0); 21567#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21568#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21101#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21102#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21739#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21740#L623 assume 1 == ~t3_pc~0; 21016#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20356#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21166#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21167#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 21774#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20389#L642 assume !(1 == ~t4_pc~0); 20390#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20855#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20856#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20461#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 20462#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21579#L661 assume 1 == ~t5_pc~0; 20626#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20627#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20588#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20589#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 21608#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21609#L680 assume !(1 == ~t6_pc~0); 21049#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21050#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21311#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21312#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 21840#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21953#L699 assume 1 == ~t7_pc~0; 21439#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21440#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20616#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20617#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 21341#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21240#L718 assume !(1 == ~t8_pc~0); 21241#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 20602#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20603#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20644#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 20645#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20778#L737 assume 1 == ~t9_pc~0; 21643#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20913#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21514#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21515#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 21087#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21088#L756 assume 1 == ~t10_pc~0; 21667#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21333#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20319#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20320#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 20895#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20896#L775 assume !(1 == ~t11_pc~0); 21150#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 21151#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20772#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20536#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20537#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20723#L794 assume 1 == ~t12_pc~0; 20563#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20541#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21734#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 20689#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 20690#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21169#L1307 assume !(1 == ~M_E~0); 21170#L1307-2 assume !(1 == ~T1_E~0); 21281#L1312-1 assume !(1 == ~T2_E~0); 21200#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21201#L1322-1 assume !(1 == ~T4_E~0); 20904#L1327-1 assume !(1 == ~T5_E~0); 20905#L1332-1 assume !(1 == ~T6_E~0); 21443#L1337-1 assume !(1 == ~T7_E~0); 21405#L1342-1 assume !(1 == ~T8_E~0); 21406#L1347-1 assume !(1 == ~T9_E~0); 21803#L1352-1 assume !(1 == ~T10_E~0); 21676#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21067#L1362-1 assume !(1 == ~T12_E~0); 21068#L1367-1 assume !(1 == ~E_1~0); 20705#L1372-1 assume !(1 == ~E_2~0); 20706#L1377-1 assume !(1 == ~E_3~0); 20999#L1382-1 assume !(1 == ~E_4~0); 21000#L1387-1 assume !(1 == ~E_5~0); 21569#L1392-1 assume !(1 == ~E_6~0); 21019#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 21020#L1402-1 assume !(1 == ~E_8~0); 20716#L1407-1 assume !(1 == ~E_9~0); 20717#L1412-1 assume !(1 == ~E_10~0); 21732#L1417-1 assume !(1 == ~E_11~0); 21733#L1422-1 assume !(1 == ~E_12~0); 21951#L1427-1 assume { :end_inline_reset_delta_events } true; 20520#L1768-2 [2021-11-13 18:36:26,010 INFO L793 eck$LassoCheckResult]: Loop: 20520#L1768-2 assume !false; 20521#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21259#L1149 assume !false; 21631#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21784#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20910#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 20816#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 20817#L976 assume !(0 != eval_~tmp~0#1); 21950#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21960#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21751#L1174-3 assume !(0 == ~M_E~0); 21744#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21493#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21494#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21677#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21328#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20678#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20679#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20920#L1209-3 assume !(0 == ~T8_E~0); 20340#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 20341#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21099#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21100#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21118#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20528#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20529#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20972#L1249-3 assume !(0 == ~E_4~0); 21431#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21903#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21545#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20534#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20535#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21930#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21097#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 21098#L1289-3 assume !(0 == ~E_12~0); 21086#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20762#L566-39 assume 1 == ~m_pc~0; 20763#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21365#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21077#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21078#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21620#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21621#L585-39 assume !(1 == ~t1_pc~0); 20770#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 20771#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20846#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20847#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21653#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21346#L604-39 assume 1 == ~t2_pc~0; 21347#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20978#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20979#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21396#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21397#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20961#L623-39 assume 1 == ~t3_pc~0; 20357#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20359#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21637#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20813#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20814#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21585#L642-39 assume 1 == ~t4_pc~0; 21156#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21157#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20685#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20686#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21783#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20734#L661-39 assume !(1 == ~t5_pc~0); 20365#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 20366#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21726#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21727#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21640#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21641#L680-39 assume 1 == ~t6_pc~0; 20427#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20428#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21570#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20893#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20894#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21908#L699-39 assume 1 == ~t7_pc~0; 21330#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21052#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21053#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21736#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21857#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21855#L718-39 assume 1 == ~t8_pc~0; 21244#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21245#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21177#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21178#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 21480#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21449#L737-39 assume 1 == ~t9_pc~0; 20874#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20875#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21164#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21931#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21832#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21775#L756-39 assume 1 == ~t10_pc~0; 21776#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21257#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21001#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21002#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21134#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20474#L775-39 assume 1 == ~t11_pc~0; 20475#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21127#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21128#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21990#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21538#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21185#L794-39 assume !(1 == ~t12_pc~0); 20870#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 20871#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21691#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21592#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20416#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20417#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21884#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21885#L1312-3 assume !(1 == ~T2_E~0); 21996#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21610#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21611#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20555#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20526#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20527#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21273#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21398#L1352-3 assume !(1 == ~T10_E~0); 21399#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21838#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 21989#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21980#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20353#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20354#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20985#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20986#L1392-3 assume !(1 == ~E_6~0); 21701#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21947#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21364#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20640#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20641#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21289#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21290#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 20650#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20651#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21517#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 21369#L1787 assume !(0 == start_simulation_~tmp~3#1); 21370#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21893#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20621#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21416#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 21417#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20968#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20969#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 20970#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 20520#L1768-2 [2021-11-13 18:36:26,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:26,011 INFO L85 PathProgramCache]: Analyzing trace with hash 313083407, now seen corresponding path program 1 times [2021-11-13 18:36:26,011 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:26,012 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [338111871] [2021-11-13 18:36:26,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:26,012 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:26,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:26,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:26,062 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:26,062 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [338111871] [2021-11-13 18:36:26,062 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [338111871] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:26,063 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:26,063 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:26,063 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1006387994] [2021-11-13 18:36:26,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:26,064 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:26,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:26,064 INFO L85 PathProgramCache]: Analyzing trace with hash 1017478530, now seen corresponding path program 1 times [2021-11-13 18:36:26,065 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:26,065 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143015454] [2021-11-13 18:36:26,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:26,065 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:26,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:26,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:26,145 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:26,146 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2143015454] [2021-11-13 18:36:26,146 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2143015454] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:26,146 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:26,146 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:26,146 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1158653001] [2021-11-13 18:36:26,147 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:26,147 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:26,148 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:26,148 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:36:26,148 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:36:26,148 INFO L87 Difference]: Start difference. First operand 1688 states and 2499 transitions. cyclomatic complexity: 812 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:26,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:26,220 INFO L93 Difference]: Finished difference Result 1688 states and 2498 transitions. [2021-11-13 18:36:26,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:36:26,224 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2498 transitions. [2021-11-13 18:36:26,239 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:26,256 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2498 transitions. [2021-11-13 18:36:26,256 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-13 18:36:26,261 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-13 18:36:26,261 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2498 transitions. [2021-11-13 18:36:26,265 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:26,265 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2498 transitions. [2021-11-13 18:36:26,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2498 transitions. [2021-11-13 18:36:26,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-13 18:36:26,314 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4798578199052133) internal successors, (2498), 1687 states have internal predecessors, (2498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:26,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2498 transitions. [2021-11-13 18:36:26,322 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2498 transitions. [2021-11-13 18:36:26,322 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2498 transitions. [2021-11-13 18:36:26,322 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-13 18:36:26,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2498 transitions. [2021-11-13 18:36:26,333 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:26,333 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:26,333 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:26,336 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:26,336 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:26,337 INFO L791 eck$LassoCheckResult]: Stem: 24499#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 24500#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 25353#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24845#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24652#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 24653#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24738#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25039#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25161#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25162#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23950#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23951#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25099#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24545#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24546#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24452#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24453#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24841#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24194#L1174 assume !(0 == ~M_E~0); 24195#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24046#L1179-1 assume !(0 == ~T2_E~0); 23948#L1184-1 assume !(0 == ~T3_E~0); 23949#L1189-1 assume !(0 == ~T4_E~0); 23987#L1194-1 assume !(0 == ~T5_E~0); 24087#L1199-1 assume !(0 == ~T6_E~0); 24982#L1204-1 assume !(0 == ~T7_E~0); 24901#L1209-1 assume !(0 == ~T8_E~0); 24902#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25290#L1219-1 assume !(0 == ~T10_E~0); 25375#L1224-1 assume !(0 == ~T11_E~0); 24312#L1229-1 assume !(0 == ~T12_E~0); 23873#L1234-1 assume !(0 == ~E_1~0); 23874#L1239-1 assume !(0 == ~E_2~0); 23907#L1244-1 assume !(0 == ~E_3~0); 23908#L1249-1 assume !(0 == ~E_4~0); 24569#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 23803#L1259-1 assume !(0 == ~E_6~0); 23758#L1264-1 assume !(0 == ~E_7~0); 23759#L1269-1 assume !(0 == ~E_8~0); 25380#L1274-1 assume !(0 == ~E_9~0); 25315#L1279-1 assume !(0 == ~E_10~0); 23991#L1284-1 assume !(0 == ~E_11~0); 23992#L1289-1 assume !(0 == ~E_12~0); 24621#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24622#L566 assume 1 == ~m_pc~0; 23775#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23776#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24930#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24931#L1455 assume !(0 != activate_threads_~tmp~1#1); 24221#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24222#L585 assume 1 == ~t1_pc~0; 23870#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23871#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24871#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24872#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 25340#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25338#L604 assume !(1 == ~t2_pc~0); 24950#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24951#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24484#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24485#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25122#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25123#L623 assume 1 == ~t3_pc~0; 24399#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23739#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24549#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24550#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 25157#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23772#L642 assume !(1 == ~t4_pc~0); 23773#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24238#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24239#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23844#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 23845#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24962#L661 assume 1 == ~t5_pc~0; 24009#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24010#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23971#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23972#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 24991#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24992#L680 assume !(1 == ~t6_pc~0); 24432#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24433#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24694#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24695#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 25223#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25336#L699 assume 1 == ~t7_pc~0; 24822#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24823#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23999#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24000#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 24724#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24623#L718 assume !(1 == ~t8_pc~0); 24624#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23985#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23986#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24027#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 24028#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24161#L737 assume 1 == ~t9_pc~0; 25026#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24296#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24897#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24898#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 24470#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24471#L756 assume 1 == ~t10_pc~0; 25050#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24716#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23702#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23703#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 24278#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24279#L775 assume !(1 == ~t11_pc~0); 24533#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 24534#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24155#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23919#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23920#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24106#L794 assume 1 == ~t12_pc~0; 23946#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23924#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25117#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 24072#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 24073#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24552#L1307 assume !(1 == ~M_E~0); 24553#L1307-2 assume !(1 == ~T1_E~0); 24664#L1312-1 assume !(1 == ~T2_E~0); 24583#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24584#L1322-1 assume !(1 == ~T4_E~0); 24287#L1327-1 assume !(1 == ~T5_E~0); 24288#L1332-1 assume !(1 == ~T6_E~0); 24826#L1337-1 assume !(1 == ~T7_E~0); 24788#L1342-1 assume !(1 == ~T8_E~0); 24789#L1347-1 assume !(1 == ~T9_E~0); 25186#L1352-1 assume !(1 == ~T10_E~0); 25059#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24450#L1362-1 assume !(1 == ~T12_E~0); 24451#L1367-1 assume !(1 == ~E_1~0); 24088#L1372-1 assume !(1 == ~E_2~0); 24089#L1377-1 assume !(1 == ~E_3~0); 24382#L1382-1 assume !(1 == ~E_4~0); 24383#L1387-1 assume !(1 == ~E_5~0); 24952#L1392-1 assume !(1 == ~E_6~0); 24402#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 24403#L1402-1 assume !(1 == ~E_8~0); 24099#L1407-1 assume !(1 == ~E_9~0); 24100#L1412-1 assume !(1 == ~E_10~0); 25115#L1417-1 assume !(1 == ~E_11~0); 25116#L1422-1 assume !(1 == ~E_12~0); 25334#L1427-1 assume { :end_inline_reset_delta_events } true; 23903#L1768-2 [2021-11-13 18:36:26,338 INFO L793 eck$LassoCheckResult]: Loop: 23903#L1768-2 assume !false; 23904#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24642#L1149 assume !false; 25014#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25167#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24293#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24199#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 24200#L976 assume !(0 != eval_~tmp~0#1); 25333#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25343#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25134#L1174-3 assume !(0 == ~M_E~0); 25127#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24876#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24877#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25060#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24711#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24061#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24062#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24303#L1209-3 assume !(0 == ~T8_E~0); 23723#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23724#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24482#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24483#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24501#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23911#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23912#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24355#L1249-3 assume !(0 == ~E_4~0); 24814#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25286#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24928#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23917#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23918#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25313#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24480#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24481#L1289-3 assume !(0 == ~E_12~0); 24469#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24145#L566-39 assume 1 == ~m_pc~0; 24146#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24748#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24460#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24461#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25003#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25004#L585-39 assume !(1 == ~t1_pc~0); 24153#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 24154#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24229#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24230#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25036#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24729#L604-39 assume 1 == ~t2_pc~0; 24730#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24361#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24362#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24779#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24780#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24344#L623-39 assume 1 == ~t3_pc~0; 23740#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23742#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25020#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24196#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24197#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24968#L642-39 assume 1 == ~t4_pc~0; 24539#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24540#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24068#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24069#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25166#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24117#L661-39 assume !(1 == ~t5_pc~0); 23748#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 23749#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25109#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25110#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25023#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25024#L680-39 assume 1 == ~t6_pc~0; 23810#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23811#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24953#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24276#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24277#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25291#L699-39 assume 1 == ~t7_pc~0; 24713#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24435#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24436#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25119#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25240#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25238#L718-39 assume 1 == ~t8_pc~0; 24627#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24628#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24560#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24561#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 24863#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24832#L737-39 assume 1 == ~t9_pc~0; 24257#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24258#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24547#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25314#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25215#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25158#L756-39 assume 1 == ~t10_pc~0; 25159#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24640#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24384#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24385#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24517#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23857#L775-39 assume 1 == ~t11_pc~0; 23858#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24510#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24511#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25373#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24921#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24568#L794-39 assume 1 == ~t12_pc~0; 24260#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24254#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25074#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 24975#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 23799#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23800#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25267#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25268#L1312-3 assume !(1 == ~T2_E~0); 25379#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24993#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24994#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23938#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23909#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23910#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24656#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24781#L1352-3 assume !(1 == ~T10_E~0); 24782#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25221#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25372#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25363#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23736#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23737#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24368#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24369#L1392-3 assume !(1 == ~E_6~0); 25084#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25330#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24747#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24023#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24024#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24672#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24673#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 24033#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24034#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24900#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 24752#L1787 assume !(0 == start_simulation_~tmp~3#1); 24753#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25276#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24004#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24799#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 24800#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24351#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24352#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 24353#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 23903#L1768-2 [2021-11-13 18:36:26,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:26,339 INFO L85 PathProgramCache]: Analyzing trace with hash -1846000687, now seen corresponding path program 1 times [2021-11-13 18:36:26,339 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:26,339 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [6739424] [2021-11-13 18:36:26,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:26,340 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:26,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:26,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:26,407 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:26,408 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [6739424] [2021-11-13 18:36:26,408 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [6739424] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:26,409 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:26,410 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:26,410 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1960112820] [2021-11-13 18:36:26,410 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:26,411 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:26,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:26,411 INFO L85 PathProgramCache]: Analyzing trace with hash -2002386077, now seen corresponding path program 1 times [2021-11-13 18:36:26,411 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:26,417 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [906087835] [2021-11-13 18:36:26,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:26,418 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:26,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:26,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:26,542 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:26,542 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [906087835] [2021-11-13 18:36:26,542 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [906087835] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:26,542 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:26,543 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:26,543 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1402103360] [2021-11-13 18:36:26,543 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:26,544 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:26,544 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:26,544 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:36:26,544 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:36:26,545 INFO L87 Difference]: Start difference. First operand 1688 states and 2498 transitions. cyclomatic complexity: 811 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:26,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:26,595 INFO L93 Difference]: Finished difference Result 1688 states and 2497 transitions. [2021-11-13 18:36:26,595 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:36:26,596 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2497 transitions. [2021-11-13 18:36:26,611 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:26,628 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2497 transitions. [2021-11-13 18:36:26,628 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-13 18:36:26,630 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-13 18:36:26,630 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2497 transitions. [2021-11-13 18:36:26,634 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:26,634 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2497 transitions. [2021-11-13 18:36:26,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2497 transitions. [2021-11-13 18:36:26,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-13 18:36:26,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4792654028436019) internal successors, (2497), 1687 states have internal predecessors, (2497), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:26,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2497 transitions. [2021-11-13 18:36:26,681 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2497 transitions. [2021-11-13 18:36:26,681 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2497 transitions. [2021-11-13 18:36:26,681 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-13 18:36:26,681 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2497 transitions. [2021-11-13 18:36:26,692 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:26,692 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:26,692 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:26,695 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:26,695 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:26,696 INFO L791 eck$LassoCheckResult]: Stem: 27882#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 27883#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 28736#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28228#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28035#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 28036#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28121#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28422#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28544#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28545#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27333#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27334#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28482#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27928#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27929#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 27835#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 27836#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28224#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27577#L1174 assume !(0 == ~M_E~0); 27578#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27429#L1179-1 assume !(0 == ~T2_E~0); 27331#L1184-1 assume !(0 == ~T3_E~0); 27332#L1189-1 assume !(0 == ~T4_E~0); 27370#L1194-1 assume !(0 == ~T5_E~0); 27470#L1199-1 assume !(0 == ~T6_E~0); 28365#L1204-1 assume !(0 == ~T7_E~0); 28284#L1209-1 assume !(0 == ~T8_E~0); 28285#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28673#L1219-1 assume !(0 == ~T10_E~0); 28758#L1224-1 assume !(0 == ~T11_E~0); 27695#L1229-1 assume !(0 == ~T12_E~0); 27256#L1234-1 assume !(0 == ~E_1~0); 27257#L1239-1 assume !(0 == ~E_2~0); 27290#L1244-1 assume !(0 == ~E_3~0); 27291#L1249-1 assume !(0 == ~E_4~0); 27952#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 27186#L1259-1 assume !(0 == ~E_6~0); 27141#L1264-1 assume !(0 == ~E_7~0); 27142#L1269-1 assume !(0 == ~E_8~0); 28763#L1274-1 assume !(0 == ~E_9~0); 28698#L1279-1 assume !(0 == ~E_10~0); 27374#L1284-1 assume !(0 == ~E_11~0); 27375#L1289-1 assume !(0 == ~E_12~0); 28004#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28005#L566 assume 1 == ~m_pc~0; 27158#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27159#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28313#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28314#L1455 assume !(0 != activate_threads_~tmp~1#1); 27604#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27605#L585 assume 1 == ~t1_pc~0; 27253#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27254#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28254#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28255#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 28723#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28721#L604 assume !(1 == ~t2_pc~0); 28333#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28334#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27867#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27868#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28505#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28506#L623 assume 1 == ~t3_pc~0; 27782#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27122#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27932#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27933#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 28540#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27155#L642 assume !(1 == ~t4_pc~0); 27156#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27621#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27622#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27227#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 27228#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28345#L661 assume 1 == ~t5_pc~0; 27392#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27393#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27354#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27355#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 28374#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28375#L680 assume !(1 == ~t6_pc~0); 27815#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27816#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28077#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28078#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 28606#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28719#L699 assume 1 == ~t7_pc~0; 28205#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28206#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27382#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 27383#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 28107#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28006#L718 assume !(1 == ~t8_pc~0); 28007#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27368#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27369#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27410#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 27411#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27544#L737 assume 1 == ~t9_pc~0; 28409#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27679#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28280#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28281#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 27853#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27854#L756 assume 1 == ~t10_pc~0; 28433#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28099#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27085#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27086#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 27661#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27662#L775 assume !(1 == ~t11_pc~0); 27916#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 27917#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27538#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27302#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27303#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27489#L794 assume 1 == ~t12_pc~0; 27329#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27307#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28500#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 27455#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 27456#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27935#L1307 assume !(1 == ~M_E~0); 27936#L1307-2 assume !(1 == ~T1_E~0); 28047#L1312-1 assume !(1 == ~T2_E~0); 27966#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27967#L1322-1 assume !(1 == ~T4_E~0); 27670#L1327-1 assume !(1 == ~T5_E~0); 27671#L1332-1 assume !(1 == ~T6_E~0); 28209#L1337-1 assume !(1 == ~T7_E~0); 28171#L1342-1 assume !(1 == ~T8_E~0); 28172#L1347-1 assume !(1 == ~T9_E~0); 28569#L1352-1 assume !(1 == ~T10_E~0); 28442#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27833#L1362-1 assume !(1 == ~T12_E~0); 27834#L1367-1 assume !(1 == ~E_1~0); 27471#L1372-1 assume !(1 == ~E_2~0); 27472#L1377-1 assume !(1 == ~E_3~0); 27765#L1382-1 assume !(1 == ~E_4~0); 27766#L1387-1 assume !(1 == ~E_5~0); 28335#L1392-1 assume !(1 == ~E_6~0); 27785#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27786#L1402-1 assume !(1 == ~E_8~0); 27482#L1407-1 assume !(1 == ~E_9~0); 27483#L1412-1 assume !(1 == ~E_10~0); 28498#L1417-1 assume !(1 == ~E_11~0); 28499#L1422-1 assume !(1 == ~E_12~0); 28717#L1427-1 assume { :end_inline_reset_delta_events } true; 27286#L1768-2 [2021-11-13 18:36:26,697 INFO L793 eck$LassoCheckResult]: Loop: 27286#L1768-2 assume !false; 27287#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28025#L1149 assume !false; 28397#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28550#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27676#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 27582#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 27583#L976 assume !(0 != eval_~tmp~0#1); 28716#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28726#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28517#L1174-3 assume !(0 == ~M_E~0); 28510#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28259#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28260#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28443#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28094#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27444#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27445#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27686#L1209-3 assume !(0 == ~T8_E~0); 27106#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27107#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27865#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 27866#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 27884#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27294#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27295#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27738#L1249-3 assume !(0 == ~E_4~0); 28197#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28669#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28311#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27300#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27301#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28696#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27863#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 27864#L1289-3 assume !(0 == ~E_12~0); 27852#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27528#L566-39 assume 1 == ~m_pc~0; 27529#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 28131#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27843#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27844#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28386#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28387#L585-39 assume !(1 == ~t1_pc~0); 27536#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 27537#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27612#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27613#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28419#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28112#L604-39 assume 1 == ~t2_pc~0; 28113#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27744#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27745#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28162#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28163#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27727#L623-39 assume 1 == ~t3_pc~0; 27123#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27125#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28403#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27579#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27580#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28351#L642-39 assume 1 == ~t4_pc~0; 27922#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27923#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27451#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27452#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28549#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27500#L661-39 assume !(1 == ~t5_pc~0); 27131#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 27132#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28492#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28493#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28406#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28407#L680-39 assume 1 == ~t6_pc~0; 27193#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27194#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28336#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27659#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27660#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28674#L699-39 assume 1 == ~t7_pc~0; 28096#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27818#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27819#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28502#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28623#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28621#L718-39 assume 1 == ~t8_pc~0; 28010#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28011#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27943#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27944#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 28246#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28215#L737-39 assume 1 == ~t9_pc~0; 27640#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27641#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27930#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28697#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28598#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28541#L756-39 assume !(1 == ~t10_pc~0); 28022#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 28023#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27767#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27768#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 27900#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27240#L775-39 assume 1 == ~t11_pc~0; 27241#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 27893#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27894#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28756#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28304#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27951#L794-39 assume !(1 == ~t12_pc~0); 27636#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 27637#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28457#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 28358#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 27182#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27183#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28650#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28651#L1312-3 assume !(1 == ~T2_E~0); 28762#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28376#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28377#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27321#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27292#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27293#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28039#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28164#L1352-3 assume !(1 == ~T10_E~0); 28165#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28604#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28755#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28746#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27119#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27120#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27751#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27752#L1392-3 assume !(1 == ~E_6~0); 28467#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28713#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28130#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27406#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 27407#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28055#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28056#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 27416#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27417#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28283#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 28135#L1787 assume !(0 == start_simulation_~tmp~3#1); 28136#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28659#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27387#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28182#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 28183#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27734#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27735#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 27736#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 27286#L1768-2 [2021-11-13 18:36:26,698 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:26,698 INFO L85 PathProgramCache]: Analyzing trace with hash -1915648561, now seen corresponding path program 1 times [2021-11-13 18:36:26,698 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:26,699 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [48467398] [2021-11-13 18:36:26,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:26,699 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:26,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:26,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:26,740 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:26,740 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [48467398] [2021-11-13 18:36:26,740 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [48467398] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:26,740 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:26,740 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:26,741 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1946548213] [2021-11-13 18:36:26,741 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:26,741 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:26,742 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:26,742 INFO L85 PathProgramCache]: Analyzing trace with hash 1025229089, now seen corresponding path program 1 times [2021-11-13 18:36:26,742 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:26,743 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [987445043] [2021-11-13 18:36:26,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:26,743 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:26,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:26,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:26,796 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:26,796 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [987445043] [2021-11-13 18:36:26,797 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [987445043] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:26,797 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:26,797 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:26,797 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1550851543] [2021-11-13 18:36:26,797 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:26,798 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:26,798 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:26,799 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:36:26,799 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:36:26,799 INFO L87 Difference]: Start difference. First operand 1688 states and 2497 transitions. cyclomatic complexity: 810 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:26,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:26,850 INFO L93 Difference]: Finished difference Result 1688 states and 2496 transitions. [2021-11-13 18:36:26,851 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:36:26,852 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2496 transitions. [2021-11-13 18:36:26,867 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:26,885 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2496 transitions. [2021-11-13 18:36:26,885 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-13 18:36:26,887 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-13 18:36:26,888 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2496 transitions. [2021-11-13 18:36:26,891 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:26,892 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2496 transitions. [2021-11-13 18:36:26,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2496 transitions. [2021-11-13 18:36:26,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-13 18:36:26,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4786729857819905) internal successors, (2496), 1687 states have internal predecessors, (2496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:26,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2496 transitions. [2021-11-13 18:36:26,938 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2496 transitions. [2021-11-13 18:36:26,938 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2496 transitions. [2021-11-13 18:36:26,938 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-13 18:36:26,938 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2496 transitions. [2021-11-13 18:36:26,949 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:26,950 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:26,950 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:26,953 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:26,954 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:26,954 INFO L791 eck$LassoCheckResult]: Stem: 31265#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 31266#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 32119#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31611#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31418#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 31419#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31504#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31805#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31927#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31928#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30716#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30717#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31865#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 31311#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31312#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 31218#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 31219#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 31607#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30960#L1174 assume !(0 == ~M_E~0); 30961#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30812#L1179-1 assume !(0 == ~T2_E~0); 30714#L1184-1 assume !(0 == ~T3_E~0); 30715#L1189-1 assume !(0 == ~T4_E~0); 30753#L1194-1 assume !(0 == ~T5_E~0); 30853#L1199-1 assume !(0 == ~T6_E~0); 31748#L1204-1 assume !(0 == ~T7_E~0); 31667#L1209-1 assume !(0 == ~T8_E~0); 31668#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32056#L1219-1 assume !(0 == ~T10_E~0); 32141#L1224-1 assume !(0 == ~T11_E~0); 31078#L1229-1 assume !(0 == ~T12_E~0); 30639#L1234-1 assume !(0 == ~E_1~0); 30640#L1239-1 assume !(0 == ~E_2~0); 30673#L1244-1 assume !(0 == ~E_3~0); 30674#L1249-1 assume !(0 == ~E_4~0); 31335#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 30569#L1259-1 assume !(0 == ~E_6~0); 30524#L1264-1 assume !(0 == ~E_7~0); 30525#L1269-1 assume !(0 == ~E_8~0); 32146#L1274-1 assume !(0 == ~E_9~0); 32081#L1279-1 assume !(0 == ~E_10~0); 30757#L1284-1 assume !(0 == ~E_11~0); 30758#L1289-1 assume !(0 == ~E_12~0); 31387#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31388#L566 assume 1 == ~m_pc~0; 30541#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30542#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31696#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31697#L1455 assume !(0 != activate_threads_~tmp~1#1); 30987#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30988#L585 assume 1 == ~t1_pc~0; 30636#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30637#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31637#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31638#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 32106#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32104#L604 assume !(1 == ~t2_pc~0); 31716#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31717#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31250#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31251#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31888#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31889#L623 assume 1 == ~t3_pc~0; 31165#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30505#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31315#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31316#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 31923#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30538#L642 assume !(1 == ~t4_pc~0); 30539#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31004#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31005#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30610#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 30611#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31728#L661 assume 1 == ~t5_pc~0; 30775#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30776#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30737#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30738#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 31757#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31758#L680 assume !(1 == ~t6_pc~0); 31198#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31199#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31460#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31461#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 31989#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32102#L699 assume 1 == ~t7_pc~0; 31588#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31589#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30765#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30766#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 31490#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31389#L718 assume !(1 == ~t8_pc~0); 31390#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30751#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30752#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30793#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 30794#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30927#L737 assume 1 == ~t9_pc~0; 31792#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31062#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31663#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31664#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 31236#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31237#L756 assume 1 == ~t10_pc~0; 31816#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31482#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30468#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30469#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 31044#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31045#L775 assume !(1 == ~t11_pc~0); 31299#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 31300#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30921#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30685#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 30686#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30872#L794 assume 1 == ~t12_pc~0; 30712#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 30690#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31883#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30838#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 30839#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31318#L1307 assume !(1 == ~M_E~0); 31319#L1307-2 assume !(1 == ~T1_E~0); 31430#L1312-1 assume !(1 == ~T2_E~0); 31349#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31350#L1322-1 assume !(1 == ~T4_E~0); 31053#L1327-1 assume !(1 == ~T5_E~0); 31054#L1332-1 assume !(1 == ~T6_E~0); 31592#L1337-1 assume !(1 == ~T7_E~0); 31554#L1342-1 assume !(1 == ~T8_E~0); 31555#L1347-1 assume !(1 == ~T9_E~0); 31952#L1352-1 assume !(1 == ~T10_E~0); 31825#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31216#L1362-1 assume !(1 == ~T12_E~0); 31217#L1367-1 assume !(1 == ~E_1~0); 30854#L1372-1 assume !(1 == ~E_2~0); 30855#L1377-1 assume !(1 == ~E_3~0); 31148#L1382-1 assume !(1 == ~E_4~0); 31149#L1387-1 assume !(1 == ~E_5~0); 31718#L1392-1 assume !(1 == ~E_6~0); 31168#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 31169#L1402-1 assume !(1 == ~E_8~0); 30865#L1407-1 assume !(1 == ~E_9~0); 30866#L1412-1 assume !(1 == ~E_10~0); 31881#L1417-1 assume !(1 == ~E_11~0); 31882#L1422-1 assume !(1 == ~E_12~0); 32100#L1427-1 assume { :end_inline_reset_delta_events } true; 30669#L1768-2 [2021-11-13 18:36:26,955 INFO L793 eck$LassoCheckResult]: Loop: 30669#L1768-2 assume !false; 30670#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31408#L1149 assume !false; 31780#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 31933#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 31059#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 30965#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 30966#L976 assume !(0 != eval_~tmp~0#1); 32099#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32109#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31900#L1174-3 assume !(0 == ~M_E~0); 31893#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31642#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31643#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31826#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31477#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30827#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30828#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31069#L1209-3 assume !(0 == ~T8_E~0); 30489#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30490#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31248#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 31249#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 31267#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30677#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30678#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31121#L1249-3 assume !(0 == ~E_4~0); 31580#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32052#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31694#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30683#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30684#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32079#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31246#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31247#L1289-3 assume !(0 == ~E_12~0); 31235#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30911#L566-39 assume 1 == ~m_pc~0; 30912#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31514#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31226#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31227#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31769#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31770#L585-39 assume !(1 == ~t1_pc~0); 30919#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 30920#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30995#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30996#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31802#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31495#L604-39 assume 1 == ~t2_pc~0; 31496#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31127#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31128#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31545#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31546#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31110#L623-39 assume 1 == ~t3_pc~0; 30506#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30508#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31786#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30962#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30963#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31734#L642-39 assume 1 == ~t4_pc~0; 31305#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31306#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30834#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30835#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31932#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30883#L661-39 assume !(1 == ~t5_pc~0); 30514#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 30515#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31875#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31876#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31789#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31790#L680-39 assume 1 == ~t6_pc~0; 30576#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30577#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31719#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31042#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31043#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32057#L699-39 assume 1 == ~t7_pc~0; 31479#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31201#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31202#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31885#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32006#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32004#L718-39 assume 1 == ~t8_pc~0; 31393#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31394#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31326#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31327#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 31629#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31598#L737-39 assume !(1 == ~t9_pc~0); 31025#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 31024#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31313#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32080#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 31981#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31924#L756-39 assume 1 == ~t10_pc~0; 31925#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31406#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31150#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31151#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31283#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30623#L775-39 assume 1 == ~t11_pc~0; 30624#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 31276#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31277#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32139#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31687#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31334#L794-39 assume 1 == ~t12_pc~0; 31026#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31020#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31840#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 31741#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 30565#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30566#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32033#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32034#L1312-3 assume !(1 == ~T2_E~0); 32145#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31759#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31760#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30704#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30675#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30676#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 31422#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31547#L1352-3 assume !(1 == ~T10_E~0); 31548#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31987#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32138#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32129#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30502#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30503#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31134#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31135#L1392-3 assume !(1 == ~E_6~0); 31850#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32096#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31513#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30789#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30790#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 31438#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 31439#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 30799#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 30800#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 31666#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 31518#L1787 assume !(0 == start_simulation_~tmp~3#1); 31519#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32042#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 30770#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 31565#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 31566#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31117#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31118#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 31119#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 30669#L1768-2 [2021-11-13 18:36:26,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:26,956 INFO L85 PathProgramCache]: Analyzing trace with hash 1961430033, now seen corresponding path program 1 times [2021-11-13 18:36:26,957 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:26,957 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1705138966] [2021-11-13 18:36:26,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:26,957 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:26,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:26,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:26,997 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:26,998 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1705138966] [2021-11-13 18:36:26,998 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1705138966] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:26,998 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:26,998 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:26,999 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386960073] [2021-11-13 18:36:26,999 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:27,000 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:27,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:27,000 INFO L85 PathProgramCache]: Analyzing trace with hash -182660158, now seen corresponding path program 1 times [2021-11-13 18:36:27,001 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:27,001 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905565180] [2021-11-13 18:36:27,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:27,001 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:27,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:27,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:27,052 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:27,052 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905565180] [2021-11-13 18:36:27,053 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [905565180] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:27,053 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:27,053 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:27,053 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [943427689] [2021-11-13 18:36:27,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:27,054 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:27,054 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:27,055 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:36:27,055 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:36:27,056 INFO L87 Difference]: Start difference. First operand 1688 states and 2496 transitions. cyclomatic complexity: 809 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:27,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:27,101 INFO L93 Difference]: Finished difference Result 1688 states and 2495 transitions. [2021-11-13 18:36:27,102 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:36:27,103 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2495 transitions. [2021-11-13 18:36:27,116 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:27,131 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2495 transitions. [2021-11-13 18:36:27,132 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-13 18:36:27,134 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-13 18:36:27,134 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2495 transitions. [2021-11-13 18:36:27,138 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:27,138 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2495 transitions. [2021-11-13 18:36:27,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2495 transitions. [2021-11-13 18:36:27,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-13 18:36:27,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.478080568720379) internal successors, (2495), 1687 states have internal predecessors, (2495), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:27,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2495 transitions. [2021-11-13 18:36:27,182 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2495 transitions. [2021-11-13 18:36:27,182 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2495 transitions. [2021-11-13 18:36:27,182 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-13 18:36:27,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2495 transitions. [2021-11-13 18:36:27,193 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:27,193 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:27,193 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:27,197 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:27,197 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:27,198 INFO L791 eck$LassoCheckResult]: Stem: 34648#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 34649#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 35502#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34996#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34801#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 34802#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34887#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35189#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35310#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35311#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34099#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34100#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35248#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 34694#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 34695#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 34601#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 34602#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 34991#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34343#L1174 assume !(0 == ~M_E~0); 34344#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34195#L1179-1 assume !(0 == ~T2_E~0); 34097#L1184-1 assume !(0 == ~T3_E~0); 34098#L1189-1 assume !(0 == ~T4_E~0); 34136#L1194-1 assume !(0 == ~T5_E~0); 34236#L1199-1 assume !(0 == ~T6_E~0); 35131#L1204-1 assume !(0 == ~T7_E~0); 35050#L1209-1 assume !(0 == ~T8_E~0); 35051#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35439#L1219-1 assume !(0 == ~T10_E~0); 35524#L1224-1 assume !(0 == ~T11_E~0); 34462#L1229-1 assume !(0 == ~T12_E~0); 34024#L1234-1 assume !(0 == ~E_1~0); 34025#L1239-1 assume !(0 == ~E_2~0); 34058#L1244-1 assume !(0 == ~E_3~0); 34059#L1249-1 assume !(0 == ~E_4~0); 34718#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 33952#L1259-1 assume !(0 == ~E_6~0); 33907#L1264-1 assume !(0 == ~E_7~0); 33908#L1269-1 assume !(0 == ~E_8~0); 35529#L1274-1 assume !(0 == ~E_9~0); 35464#L1279-1 assume !(0 == ~E_10~0); 34140#L1284-1 assume !(0 == ~E_11~0); 34141#L1289-1 assume !(0 == ~E_12~0); 34770#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34771#L566 assume 1 == ~m_pc~0; 33924#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 33925#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35079#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35080#L1455 assume !(0 != activate_threads_~tmp~1#1); 34370#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34371#L585 assume 1 == ~t1_pc~0; 34019#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34020#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35020#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35021#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 35489#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35487#L604 assume !(1 == ~t2_pc~0); 35099#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35100#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34633#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34634#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35273#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35274#L623 assume 1 == ~t3_pc~0; 34548#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33888#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34698#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34699#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 35306#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33921#L642 assume !(1 == ~t4_pc~0); 33922#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 34387#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34388#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33995#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 33996#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35111#L661 assume 1 == ~t5_pc~0; 34158#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34159#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34120#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34121#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 35142#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35143#L680 assume !(1 == ~t6_pc~0); 34581#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34582#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34843#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34844#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 35372#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35485#L699 assume 1 == ~t7_pc~0; 34971#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34972#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34148#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34149#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 34873#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34772#L718 assume !(1 == ~t8_pc~0); 34773#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 34134#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34135#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34176#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 34177#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34310#L737 assume 1 == ~t9_pc~0; 35176#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34445#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35046#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35047#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 34619#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34620#L756 assume 1 == ~t10_pc~0; 35199#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34865#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33851#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33852#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 34427#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34428#L775 assume !(1 == ~t11_pc~0); 34682#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 34683#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34304#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34068#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 34069#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34255#L794 assume 1 == ~t12_pc~0; 34096#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34073#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35266#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34223#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 34224#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34701#L1307 assume !(1 == ~M_E~0); 34702#L1307-2 assume !(1 == ~T1_E~0); 34813#L1312-1 assume !(1 == ~T2_E~0); 34732#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34733#L1322-1 assume !(1 == ~T4_E~0); 34436#L1327-1 assume !(1 == ~T5_E~0); 34437#L1332-1 assume !(1 == ~T6_E~0); 34975#L1337-1 assume !(1 == ~T7_E~0); 34937#L1342-1 assume !(1 == ~T8_E~0); 34938#L1347-1 assume !(1 == ~T9_E~0); 35335#L1352-1 assume !(1 == ~T10_E~0); 35208#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34599#L1362-1 assume !(1 == ~T12_E~0); 34600#L1367-1 assume !(1 == ~E_1~0); 34237#L1372-1 assume !(1 == ~E_2~0); 34238#L1377-1 assume !(1 == ~E_3~0); 34531#L1382-1 assume !(1 == ~E_4~0); 34532#L1387-1 assume !(1 == ~E_5~0); 35101#L1392-1 assume !(1 == ~E_6~0); 34553#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34554#L1402-1 assume !(1 == ~E_8~0); 34250#L1407-1 assume !(1 == ~E_9~0); 34251#L1412-1 assume !(1 == ~E_10~0); 35264#L1417-1 assume !(1 == ~E_11~0); 35265#L1422-1 assume !(1 == ~E_12~0); 35483#L1427-1 assume { :end_inline_reset_delta_events } true; 34052#L1768-2 [2021-11-13 18:36:27,198 INFO L793 eck$LassoCheckResult]: Loop: 34052#L1768-2 assume !false; 34053#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34793#L1149 assume !false; 35164#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 35316#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34442#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 34354#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 34355#L976 assume !(0 != eval_~tmp~0#1); 35482#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35492#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35283#L1174-3 assume !(0 == ~M_E~0); 35276#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35025#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35026#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35210#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34860#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34213#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34214#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34452#L1209-3 assume !(0 == ~T8_E~0); 33872#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33873#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34631#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 34632#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 34650#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34060#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34061#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34504#L1249-3 assume !(0 == ~E_4~0); 34963#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35435#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35077#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34066#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34067#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35462#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34629#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34630#L1289-3 assume !(0 == ~E_12~0); 34618#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34294#L566-39 assume 1 == ~m_pc~0; 34295#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34897#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34609#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34610#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35152#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35153#L585-39 assume !(1 == ~t1_pc~0); 34301#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 34302#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34378#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34379#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35185#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34877#L604-39 assume 1 == ~t2_pc~0; 34878#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34510#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34511#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34928#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34929#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34493#L623-39 assume 1 == ~t3_pc~0; 33889#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33891#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35169#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34345#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34346#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35117#L642-39 assume 1 == ~t4_pc~0; 34688#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34689#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34217#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34218#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35315#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34264#L661-39 assume !(1 == ~t5_pc~0); 33897#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 33898#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35258#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35259#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35172#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35173#L680-39 assume 1 == ~t6_pc~0; 33959#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33960#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35102#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34425#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34426#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35440#L699-39 assume 1 == ~t7_pc~0; 34862#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34584#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34585#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35268#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35389#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35387#L718-39 assume 1 == ~t8_pc~0; 34776#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34777#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34709#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34710#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 35011#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34981#L737-39 assume 1 == ~t9_pc~0; 34406#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34407#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34696#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35463#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35364#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35307#L756-39 assume !(1 == ~t10_pc~0); 34788#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 34789#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34533#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34534#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34666#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34006#L775-39 assume 1 == ~t11_pc~0; 34007#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34659#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34660#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35522#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35070#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34717#L794-39 assume !(1 == ~t12_pc~0); 34402#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 34403#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35223#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 35124#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33948#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33949#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35416#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35417#L1312-3 assume !(1 == ~T2_E~0); 35528#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35140#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35141#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34087#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34056#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34057#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34805#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34930#L1352-3 assume !(1 == ~T10_E~0); 34931#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35370#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35521#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35512#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33882#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33883#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34517#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34518#L1392-3 assume !(1 == ~E_6~0); 35233#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35479#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34896#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34172#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 34173#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 34819#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 34820#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 34182#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34183#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 35049#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 34900#L1787 assume !(0 == start_simulation_~tmp~3#1); 34901#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 35425#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34153#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 34948#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 34949#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34500#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34501#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 34502#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 34052#L1768-2 [2021-11-13 18:36:27,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:27,199 INFO L85 PathProgramCache]: Analyzing trace with hash -716096813, now seen corresponding path program 1 times [2021-11-13 18:36:27,200 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:27,200 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1657540848] [2021-11-13 18:36:27,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:27,200 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:27,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:27,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:27,240 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:27,240 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1657540848] [2021-11-13 18:36:27,240 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1657540848] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:27,240 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:27,241 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:27,241 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1509711437] [2021-11-13 18:36:27,241 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:27,242 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:27,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:27,242 INFO L85 PathProgramCache]: Analyzing trace with hash 1025229089, now seen corresponding path program 2 times [2021-11-13 18:36:27,243 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:27,243 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113860065] [2021-11-13 18:36:27,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:27,243 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:27,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:27,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:27,293 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:27,294 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2113860065] [2021-11-13 18:36:27,294 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2113860065] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:27,294 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:27,294 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:27,295 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1006346733] [2021-11-13 18:36:27,295 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:27,296 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:27,296 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:27,296 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:36:27,296 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:36:27,297 INFO L87 Difference]: Start difference. First operand 1688 states and 2495 transitions. cyclomatic complexity: 808 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:27,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:27,379 INFO L93 Difference]: Finished difference Result 1688 states and 2494 transitions. [2021-11-13 18:36:27,379 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:36:27,380 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2494 transitions. [2021-11-13 18:36:27,392 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:27,419 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2494 transitions. [2021-11-13 18:36:27,419 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-13 18:36:27,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-13 18:36:27,422 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2494 transitions. [2021-11-13 18:36:27,425 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:27,426 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2494 transitions. [2021-11-13 18:36:27,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2494 transitions. [2021-11-13 18:36:27,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-13 18:36:27,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4774881516587677) internal successors, (2494), 1687 states have internal predecessors, (2494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:27,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2494 transitions. [2021-11-13 18:36:27,495 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2494 transitions. [2021-11-13 18:36:27,495 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2494 transitions. [2021-11-13 18:36:27,495 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-13 18:36:27,495 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2494 transitions. [2021-11-13 18:36:27,508 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:27,508 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:27,508 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:27,512 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:27,512 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:27,513 INFO L791 eck$LassoCheckResult]: Stem: 38031#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 38032#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 38885#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38379#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38184#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 38185#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38270#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38571#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38693#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38694#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37482#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37483#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38631#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38077#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38078#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 37984#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 37985#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 38374#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37726#L1174 assume !(0 == ~M_E~0); 37727#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37578#L1179-1 assume !(0 == ~T2_E~0); 37480#L1184-1 assume !(0 == ~T3_E~0); 37481#L1189-1 assume !(0 == ~T4_E~0); 37519#L1194-1 assume !(0 == ~T5_E~0); 37619#L1199-1 assume !(0 == ~T6_E~0); 38514#L1204-1 assume !(0 == ~T7_E~0); 38433#L1209-1 assume !(0 == ~T8_E~0); 38434#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38822#L1219-1 assume !(0 == ~T10_E~0); 38907#L1224-1 assume !(0 == ~T11_E~0); 37844#L1229-1 assume !(0 == ~T12_E~0); 37405#L1234-1 assume !(0 == ~E_1~0); 37406#L1239-1 assume !(0 == ~E_2~0); 37441#L1244-1 assume !(0 == ~E_3~0); 37442#L1249-1 assume !(0 == ~E_4~0); 38101#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 37335#L1259-1 assume !(0 == ~E_6~0); 37290#L1264-1 assume !(0 == ~E_7~0); 37291#L1269-1 assume !(0 == ~E_8~0); 38912#L1274-1 assume !(0 == ~E_9~0); 38847#L1279-1 assume !(0 == ~E_10~0); 37523#L1284-1 assume !(0 == ~E_11~0); 37524#L1289-1 assume !(0 == ~E_12~0); 38153#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38154#L566 assume 1 == ~m_pc~0; 37307#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 37308#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38462#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38463#L1455 assume !(0 != activate_threads_~tmp~1#1); 37753#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37754#L585 assume 1 == ~t1_pc~0; 37402#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37403#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38403#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38404#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 38872#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38870#L604 assume !(1 == ~t2_pc~0); 38482#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38483#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38016#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38017#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38654#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38655#L623 assume 1 == ~t3_pc~0; 37931#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37271#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38081#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38082#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 38689#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37304#L642 assume !(1 == ~t4_pc~0); 37305#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37770#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37771#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37376#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 37377#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38494#L661 assume 1 == ~t5_pc~0; 37541#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37542#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37503#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37504#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 38525#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38526#L680 assume !(1 == ~t6_pc~0); 37964#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 37965#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38226#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38227#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 38755#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38868#L699 assume 1 == ~t7_pc~0; 38354#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38355#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37531#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37532#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 38256#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38155#L718 assume !(1 == ~t8_pc~0); 38156#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 37517#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37518#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37559#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 37560#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37693#L737 assume 1 == ~t9_pc~0; 38558#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37828#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38429#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38430#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 38002#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38003#L756 assume 1 == ~t10_pc~0; 38582#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38248#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37234#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37235#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 37810#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37811#L775 assume !(1 == ~t11_pc~0); 38065#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 38066#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37687#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37451#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 37452#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37638#L794 assume 1 == ~t12_pc~0; 37479#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37456#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38649#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 37604#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 37605#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38084#L1307 assume !(1 == ~M_E~0); 38085#L1307-2 assume !(1 == ~T1_E~0); 38196#L1312-1 assume !(1 == ~T2_E~0); 38115#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38116#L1322-1 assume !(1 == ~T4_E~0); 37819#L1327-1 assume !(1 == ~T5_E~0); 37820#L1332-1 assume !(1 == ~T6_E~0); 38358#L1337-1 assume !(1 == ~T7_E~0); 38320#L1342-1 assume !(1 == ~T8_E~0); 38321#L1347-1 assume !(1 == ~T9_E~0); 38718#L1352-1 assume !(1 == ~T10_E~0); 38591#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37982#L1362-1 assume !(1 == ~T12_E~0); 37983#L1367-1 assume !(1 == ~E_1~0); 37620#L1372-1 assume !(1 == ~E_2~0); 37621#L1377-1 assume !(1 == ~E_3~0); 37914#L1382-1 assume !(1 == ~E_4~0); 37915#L1387-1 assume !(1 == ~E_5~0); 38484#L1392-1 assume !(1 == ~E_6~0); 37934#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 37935#L1402-1 assume !(1 == ~E_8~0); 37631#L1407-1 assume !(1 == ~E_9~0); 37632#L1412-1 assume !(1 == ~E_10~0); 38647#L1417-1 assume !(1 == ~E_11~0); 38648#L1422-1 assume !(1 == ~E_12~0); 38866#L1427-1 assume { :end_inline_reset_delta_events } true; 37435#L1768-2 [2021-11-13 18:36:27,513 INFO L793 eck$LassoCheckResult]: Loop: 37435#L1768-2 assume !false; 37436#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38174#L1149 assume !false; 38546#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 38699#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37825#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37731#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 37732#L976 assume !(0 != eval_~tmp~0#1); 38865#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38875#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38666#L1174-3 assume !(0 == ~M_E~0); 38659#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38408#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38409#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38593#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38243#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37596#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37597#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37835#L1209-3 assume !(0 == ~T8_E~0); 37255#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37256#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38014#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 38015#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 38033#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37443#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37444#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37887#L1249-3 assume !(0 == ~E_4~0); 38346#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38818#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38460#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37449#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37450#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38845#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38012#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38013#L1289-3 assume !(0 == ~E_12~0); 38001#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37677#L566-39 assume 1 == ~m_pc~0; 37678#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38280#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37992#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37993#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38535#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38536#L585-39 assume !(1 == ~t1_pc~0); 37685#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 37686#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37761#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37762#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38568#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38261#L604-39 assume 1 == ~t2_pc~0; 38262#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37893#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37894#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38313#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38314#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37876#L623-39 assume 1 == ~t3_pc~0; 37274#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37276#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38552#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37728#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37729#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38500#L642-39 assume 1 == ~t4_pc~0; 38073#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38074#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37600#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37601#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38698#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37651#L661-39 assume !(1 == ~t5_pc~0); 37280#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 37281#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38641#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38642#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38555#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38556#L680-39 assume 1 == ~t6_pc~0; 37344#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37345#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38485#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37808#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37809#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38823#L699-39 assume 1 == ~t7_pc~0; 38245#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37967#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37968#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38651#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38772#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38770#L718-39 assume 1 == ~t8_pc~0; 38160#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38161#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38092#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38093#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 38394#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38363#L737-39 assume 1 == ~t9_pc~0; 37789#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37790#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38079#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38846#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38747#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38690#L756-39 assume 1 == ~t10_pc~0; 38691#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38169#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37916#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37917#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38049#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37389#L775-39 assume 1 == ~t11_pc~0; 37390#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38042#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38043#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38905#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38453#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38100#L794-39 assume 1 == ~t12_pc~0; 37792#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37786#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38606#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38507#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37331#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37332#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38799#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38800#L1312-3 assume !(1 == ~T2_E~0); 38911#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38523#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38524#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37468#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37439#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37440#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38188#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38311#L1352-3 assume !(1 == ~T10_E~0); 38312#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38752#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38904#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38895#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37265#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37266#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37900#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37901#L1392-3 assume !(1 == ~E_6~0); 38616#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38862#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38279#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37555#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37556#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 38202#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 38203#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37565#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37566#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 38432#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 38283#L1787 assume !(0 == start_simulation_~tmp~3#1); 38284#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 38808#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37536#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 38331#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 38332#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37883#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37884#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 37885#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 37435#L1768-2 [2021-11-13 18:36:27,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:27,514 INFO L85 PathProgramCache]: Analyzing trace with hash -1079563311, now seen corresponding path program 1 times [2021-11-13 18:36:27,515 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:27,515 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021884474] [2021-11-13 18:36:27,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:27,516 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:27,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:27,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:27,558 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:27,558 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021884474] [2021-11-13 18:36:27,558 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1021884474] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:27,561 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:27,562 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:27,564 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1983244024] [2021-11-13 18:36:27,565 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:27,565 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:27,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:27,566 INFO L85 PathProgramCache]: Analyzing trace with hash -2002386077, now seen corresponding path program 2 times [2021-11-13 18:36:27,566 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:27,567 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1257499993] [2021-11-13 18:36:27,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:27,567 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:27,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:27,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:27,618 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:27,618 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1257499993] [2021-11-13 18:36:27,619 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1257499993] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:27,619 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:27,619 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:27,619 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1299310318] [2021-11-13 18:36:27,620 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:27,620 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:27,620 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:27,621 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:36:27,621 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:36:27,622 INFO L87 Difference]: Start difference. First operand 1688 states and 2494 transitions. cyclomatic complexity: 807 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:27,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:27,669 INFO L93 Difference]: Finished difference Result 1688 states and 2493 transitions. [2021-11-13 18:36:27,670 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:36:27,671 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2493 transitions. [2021-11-13 18:36:27,684 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:27,695 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2493 transitions. [2021-11-13 18:36:27,696 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-13 18:36:27,698 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-13 18:36:27,698 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2493 transitions. [2021-11-13 18:36:27,702 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:27,702 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2493 transitions. [2021-11-13 18:36:27,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2493 transitions. [2021-11-13 18:36:27,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-13 18:36:27,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4768957345971565) internal successors, (2493), 1687 states have internal predecessors, (2493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:27,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2493 transitions. [2021-11-13 18:36:27,746 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2493 transitions. [2021-11-13 18:36:27,746 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2493 transitions. [2021-11-13 18:36:27,746 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-13 18:36:27,746 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2493 transitions. [2021-11-13 18:36:27,757 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:27,757 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:27,757 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:27,761 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:27,761 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:27,762 INFO L791 eck$LassoCheckResult]: Stem: 41414#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 41415#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 42268#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41760#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41567#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 41568#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41653#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41954#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42076#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42077#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40865#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40866#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42014#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41460#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41461#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41367#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 41368#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 41756#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41109#L1174 assume !(0 == ~M_E~0); 41110#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40961#L1179-1 assume !(0 == ~T2_E~0); 40863#L1184-1 assume !(0 == ~T3_E~0); 40864#L1189-1 assume !(0 == ~T4_E~0); 40902#L1194-1 assume !(0 == ~T5_E~0); 41002#L1199-1 assume !(0 == ~T6_E~0); 41897#L1204-1 assume !(0 == ~T7_E~0); 41816#L1209-1 assume !(0 == ~T8_E~0); 41817#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42205#L1219-1 assume !(0 == ~T10_E~0); 42290#L1224-1 assume !(0 == ~T11_E~0); 41227#L1229-1 assume !(0 == ~T12_E~0); 40788#L1234-1 assume !(0 == ~E_1~0); 40789#L1239-1 assume !(0 == ~E_2~0); 40822#L1244-1 assume !(0 == ~E_3~0); 40823#L1249-1 assume !(0 == ~E_4~0); 41484#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 40718#L1259-1 assume !(0 == ~E_6~0); 40673#L1264-1 assume !(0 == ~E_7~0); 40674#L1269-1 assume !(0 == ~E_8~0); 42295#L1274-1 assume !(0 == ~E_9~0); 42230#L1279-1 assume !(0 == ~E_10~0); 40906#L1284-1 assume !(0 == ~E_11~0); 40907#L1289-1 assume !(0 == ~E_12~0); 41536#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41537#L566 assume 1 == ~m_pc~0; 40690#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 40691#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41845#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41846#L1455 assume !(0 != activate_threads_~tmp~1#1); 41136#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41137#L585 assume 1 == ~t1_pc~0; 40785#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40786#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41786#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41787#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 42255#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42253#L604 assume !(1 == ~t2_pc~0); 41865#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41866#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41399#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41400#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42037#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42038#L623 assume 1 == ~t3_pc~0; 41314#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40654#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41464#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41465#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 42072#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40687#L642 assume !(1 == ~t4_pc~0); 40688#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41153#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41154#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40759#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 40760#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41877#L661 assume 1 == ~t5_pc~0; 40924#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40925#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40886#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40887#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 41906#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41907#L680 assume !(1 == ~t6_pc~0); 41347#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41348#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41609#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41610#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 42138#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42251#L699 assume 1 == ~t7_pc~0; 41737#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41738#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40914#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40915#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 41639#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41538#L718 assume !(1 == ~t8_pc~0); 41539#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40900#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40901#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40942#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 40943#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41076#L737 assume 1 == ~t9_pc~0; 41941#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41211#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41812#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41813#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 41385#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41386#L756 assume 1 == ~t10_pc~0; 41965#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41631#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40617#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40618#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 41193#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41194#L775 assume !(1 == ~t11_pc~0); 41448#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 41449#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41070#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40834#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40835#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41021#L794 assume 1 == ~t12_pc~0; 40861#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40839#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42032#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 40987#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 40988#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41467#L1307 assume !(1 == ~M_E~0); 41468#L1307-2 assume !(1 == ~T1_E~0); 41579#L1312-1 assume !(1 == ~T2_E~0); 41498#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41499#L1322-1 assume !(1 == ~T4_E~0); 41202#L1327-1 assume !(1 == ~T5_E~0); 41203#L1332-1 assume !(1 == ~T6_E~0); 41741#L1337-1 assume !(1 == ~T7_E~0); 41703#L1342-1 assume !(1 == ~T8_E~0); 41704#L1347-1 assume !(1 == ~T9_E~0); 42101#L1352-1 assume !(1 == ~T10_E~0); 41974#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41365#L1362-1 assume !(1 == ~T12_E~0); 41366#L1367-1 assume !(1 == ~E_1~0); 41003#L1372-1 assume !(1 == ~E_2~0); 41004#L1377-1 assume !(1 == ~E_3~0); 41297#L1382-1 assume !(1 == ~E_4~0); 41298#L1387-1 assume !(1 == ~E_5~0); 41867#L1392-1 assume !(1 == ~E_6~0); 41317#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 41318#L1402-1 assume !(1 == ~E_8~0); 41014#L1407-1 assume !(1 == ~E_9~0); 41015#L1412-1 assume !(1 == ~E_10~0); 42030#L1417-1 assume !(1 == ~E_11~0); 42031#L1422-1 assume !(1 == ~E_12~0); 42249#L1427-1 assume { :end_inline_reset_delta_events } true; 40818#L1768-2 [2021-11-13 18:36:27,762 INFO L793 eck$LassoCheckResult]: Loop: 40818#L1768-2 assume !false; 40819#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41557#L1149 assume !false; 41929#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 42082#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 41208#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41114#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 41115#L976 assume !(0 != eval_~tmp~0#1); 42248#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42258#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42049#L1174-3 assume !(0 == ~M_E~0); 42042#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41791#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 41792#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41975#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41626#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40976#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40977#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41218#L1209-3 assume !(0 == ~T8_E~0); 40638#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40639#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41397#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41398#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41416#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40826#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40827#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41270#L1249-3 assume !(0 == ~E_4~0); 41729#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42201#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41843#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40832#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 40833#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42228#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41395#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41396#L1289-3 assume !(0 == ~E_12~0); 41384#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41060#L566-39 assume 1 == ~m_pc~0; 41061#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 41663#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41375#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41376#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41918#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41919#L585-39 assume !(1 == ~t1_pc~0); 41068#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 41069#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41144#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41145#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41951#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41644#L604-39 assume 1 == ~t2_pc~0; 41645#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41276#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41277#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41694#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41695#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41259#L623-39 assume !(1 == ~t3_pc~0); 40656#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 40657#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41935#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41111#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41112#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41883#L642-39 assume !(1 == ~t4_pc~0); 41456#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 41455#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40983#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40984#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42081#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41032#L661-39 assume !(1 == ~t5_pc~0); 40663#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 40664#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42024#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42025#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41938#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41939#L680-39 assume 1 == ~t6_pc~0; 40725#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40726#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41868#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41191#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41192#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42206#L699-39 assume 1 == ~t7_pc~0; 41628#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41350#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41351#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42034#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42155#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42153#L718-39 assume 1 == ~t8_pc~0; 41542#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41543#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41475#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41476#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 41778#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41747#L737-39 assume 1 == ~t9_pc~0; 41172#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41173#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41462#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42229#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42130#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42073#L756-39 assume !(1 == ~t10_pc~0); 41554#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 41555#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41299#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41300#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41432#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40772#L775-39 assume 1 == ~t11_pc~0; 40773#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41425#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41426#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42288#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41836#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41483#L794-39 assume !(1 == ~t12_pc~0); 41168#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 41169#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41989#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 41890#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40714#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40715#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42182#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42183#L1312-3 assume !(1 == ~T2_E~0); 42294#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41908#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41909#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40853#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40824#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 40825#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41571#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41696#L1352-3 assume !(1 == ~T10_E~0); 41697#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 42136#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42287#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42278#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40651#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40652#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41283#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41284#L1392-3 assume !(1 == ~E_6~0); 41999#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42245#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41662#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40938#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40939#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41587#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41588#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40948#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40949#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41815#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 41667#L1787 assume !(0 == start_simulation_~tmp~3#1); 41668#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 42191#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40919#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41714#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 41715#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41266#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41267#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 41268#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 40818#L1768-2 [2021-11-13 18:36:27,763 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:27,764 INFO L85 PathProgramCache]: Analyzing trace with hash -1368382701, now seen corresponding path program 1 times [2021-11-13 18:36:27,764 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:27,764 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280823118] [2021-11-13 18:36:27,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:27,765 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:27,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:27,833 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:27,833 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:27,833 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [280823118] [2021-11-13 18:36:27,834 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [280823118] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:27,834 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:27,834 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:36:27,834 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1261910694] [2021-11-13 18:36:27,835 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:27,836 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:27,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:27,838 INFO L85 PathProgramCache]: Analyzing trace with hash 1824468511, now seen corresponding path program 1 times [2021-11-13 18:36:27,838 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:27,838 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1503386422] [2021-11-13 18:36:27,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:27,839 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:27,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:27,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:27,924 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:27,924 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1503386422] [2021-11-13 18:36:27,925 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1503386422] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:27,925 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:27,925 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:27,925 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1600690076] [2021-11-13 18:36:27,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:27,926 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:27,926 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:27,927 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:36:27,927 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:36:27,927 INFO L87 Difference]: Start difference. First operand 1688 states and 2493 transitions. cyclomatic complexity: 806 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:27,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:27,979 INFO L93 Difference]: Finished difference Result 1688 states and 2488 transitions. [2021-11-13 18:36:27,980 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:36:27,981 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2488 transitions. [2021-11-13 18:36:27,993 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:28,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2488 transitions. [2021-11-13 18:36:28,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-13 18:36:28,008 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-13 18:36:28,008 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2488 transitions. [2021-11-13 18:36:28,011 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:28,012 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2488 transitions. [2021-11-13 18:36:28,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2488 transitions. [2021-11-13 18:36:28,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-13 18:36:28,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4739336492890995) internal successors, (2488), 1687 states have internal predecessors, (2488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:28,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2488 transitions. [2021-11-13 18:36:28,057 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2488 transitions. [2021-11-13 18:36:28,057 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2488 transitions. [2021-11-13 18:36:28,057 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-13 18:36:28,057 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2488 transitions. [2021-11-13 18:36:28,068 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:28,068 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:28,068 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:28,072 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:28,072 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:28,073 INFO L791 eck$LassoCheckResult]: Stem: 44797#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 44798#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 45651#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45143#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44950#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 44951#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45036#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45337#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45459#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45460#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44248#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44249#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45397#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44843#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44844#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44750#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44751#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 45139#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44492#L1174 assume !(0 == ~M_E~0); 44493#L1174-2 assume !(0 == ~T1_E~0); 44344#L1179-1 assume !(0 == ~T2_E~0); 44246#L1184-1 assume !(0 == ~T3_E~0); 44247#L1189-1 assume !(0 == ~T4_E~0); 44285#L1194-1 assume !(0 == ~T5_E~0); 44385#L1199-1 assume !(0 == ~T6_E~0); 45280#L1204-1 assume !(0 == ~T7_E~0); 45199#L1209-1 assume !(0 == ~T8_E~0); 45200#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45588#L1219-1 assume !(0 == ~T10_E~0); 45673#L1224-1 assume !(0 == ~T11_E~0); 44610#L1229-1 assume !(0 == ~T12_E~0); 44171#L1234-1 assume !(0 == ~E_1~0); 44172#L1239-1 assume !(0 == ~E_2~0); 44205#L1244-1 assume !(0 == ~E_3~0); 44206#L1249-1 assume !(0 == ~E_4~0); 44867#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 44101#L1259-1 assume !(0 == ~E_6~0); 44056#L1264-1 assume !(0 == ~E_7~0); 44057#L1269-1 assume !(0 == ~E_8~0); 45678#L1274-1 assume !(0 == ~E_9~0); 45613#L1279-1 assume !(0 == ~E_10~0); 44289#L1284-1 assume !(0 == ~E_11~0); 44290#L1289-1 assume !(0 == ~E_12~0); 44919#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44920#L566 assume 1 == ~m_pc~0; 44073#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 44074#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45228#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45229#L1455 assume !(0 != activate_threads_~tmp~1#1); 44519#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44520#L585 assume 1 == ~t1_pc~0; 44168#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44169#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45169#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45170#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 45638#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45636#L604 assume !(1 == ~t2_pc~0); 45248#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45249#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44782#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44783#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45420#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45421#L623 assume 1 == ~t3_pc~0; 44697#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44037#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44847#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44848#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 45455#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44070#L642 assume !(1 == ~t4_pc~0); 44071#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 44536#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44537#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44142#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 44143#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45260#L661 assume 1 == ~t5_pc~0; 44307#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44308#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44269#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44270#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 45289#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45290#L680 assume !(1 == ~t6_pc~0); 44730#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 44731#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44992#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44993#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 45521#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45634#L699 assume 1 == ~t7_pc~0; 45120#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45121#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44297#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44298#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 45022#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44921#L718 assume !(1 == ~t8_pc~0); 44922#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 44283#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44284#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44325#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 44326#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44459#L737 assume 1 == ~t9_pc~0; 45324#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44594#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45195#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45196#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 44768#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44769#L756 assume 1 == ~t10_pc~0; 45348#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45014#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44000#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44001#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 44576#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44577#L775 assume !(1 == ~t11_pc~0); 44831#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 44832#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44453#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44217#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 44218#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44404#L794 assume 1 == ~t12_pc~0; 44244#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44222#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45415#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 44370#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 44371#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44850#L1307 assume !(1 == ~M_E~0); 44851#L1307-2 assume !(1 == ~T1_E~0); 44962#L1312-1 assume !(1 == ~T2_E~0); 44881#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44882#L1322-1 assume !(1 == ~T4_E~0); 44585#L1327-1 assume !(1 == ~T5_E~0); 44586#L1332-1 assume !(1 == ~T6_E~0); 45124#L1337-1 assume !(1 == ~T7_E~0); 45086#L1342-1 assume !(1 == ~T8_E~0); 45087#L1347-1 assume !(1 == ~T9_E~0); 45484#L1352-1 assume !(1 == ~T10_E~0); 45357#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 44748#L1362-1 assume !(1 == ~T12_E~0); 44749#L1367-1 assume !(1 == ~E_1~0); 44386#L1372-1 assume !(1 == ~E_2~0); 44387#L1377-1 assume !(1 == ~E_3~0); 44680#L1382-1 assume !(1 == ~E_4~0); 44681#L1387-1 assume !(1 == ~E_5~0); 45250#L1392-1 assume !(1 == ~E_6~0); 44700#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 44701#L1402-1 assume !(1 == ~E_8~0); 44397#L1407-1 assume !(1 == ~E_9~0); 44398#L1412-1 assume !(1 == ~E_10~0); 45413#L1417-1 assume !(1 == ~E_11~0); 45414#L1422-1 assume !(1 == ~E_12~0); 45632#L1427-1 assume { :end_inline_reset_delta_events } true; 44201#L1768-2 [2021-11-13 18:36:28,074 INFO L793 eck$LassoCheckResult]: Loop: 44201#L1768-2 assume !false; 44202#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44940#L1149 assume !false; 45312#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45465#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44591#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44497#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 44498#L976 assume !(0 != eval_~tmp~0#1); 45631#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45641#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45432#L1174-3 assume !(0 == ~M_E~0); 45425#L1174-5 assume !(0 == ~T1_E~0); 45174#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45175#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45358#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45009#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44359#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44360#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44601#L1209-3 assume !(0 == ~T8_E~0); 44021#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44022#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44780#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44781#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 44799#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44209#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44210#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44653#L1249-3 assume !(0 == ~E_4~0); 45112#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 45584#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45226#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44215#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 44216#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45611#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44778#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44779#L1289-3 assume !(0 == ~E_12~0); 44767#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44443#L566-39 assume 1 == ~m_pc~0; 44444#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 45046#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44758#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44759#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45301#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45302#L585-39 assume !(1 == ~t1_pc~0); 44451#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 44452#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44527#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44528#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45334#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45027#L604-39 assume 1 == ~t2_pc~0; 45028#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44659#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44660#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45077#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45078#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44642#L623-39 assume 1 == ~t3_pc~0; 44038#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44040#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45318#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44494#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44495#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45266#L642-39 assume 1 == ~t4_pc~0; 44837#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44838#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44366#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44367#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45464#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44415#L661-39 assume 1 == ~t5_pc~0; 44416#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44047#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45407#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45408#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45321#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45322#L680-39 assume 1 == ~t6_pc~0; 44108#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44109#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45251#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44574#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44575#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45589#L699-39 assume 1 == ~t7_pc~0; 45011#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44733#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44734#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45417#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45538#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45536#L718-39 assume 1 == ~t8_pc~0; 44925#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44926#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44858#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44859#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 45161#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45130#L737-39 assume 1 == ~t9_pc~0; 44555#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44556#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44845#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45612#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45513#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45456#L756-39 assume 1 == ~t10_pc~0; 45457#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44938#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44682#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44683#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44815#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44155#L775-39 assume 1 == ~t11_pc~0; 44156#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 44808#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44809#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45671#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 45219#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44866#L794-39 assume !(1 == ~t12_pc~0); 44551#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 44552#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45372#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45273#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 44097#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44098#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 45565#L1307-5 assume !(1 == ~T1_E~0); 45566#L1312-3 assume !(1 == ~T2_E~0); 45677#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45291#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45292#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44236#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44207#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44208#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44954#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45079#L1352-3 assume !(1 == ~T10_E~0); 45080#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45519#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 45670#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45661#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44034#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44035#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44666#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44667#L1392-3 assume !(1 == ~E_6~0); 45382#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 45628#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45045#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 44321#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44322#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44970#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44971#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44331#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44332#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 45198#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 45050#L1787 assume !(0 == start_simulation_~tmp~3#1); 45051#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45574#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44302#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 45097#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 45098#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44649#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44650#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 44651#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 44201#L1768-2 [2021-11-13 18:36:28,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:28,075 INFO L85 PathProgramCache]: Analyzing trace with hash 1978532629, now seen corresponding path program 1 times [2021-11-13 18:36:28,075 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:28,075 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1750915672] [2021-11-13 18:36:28,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:28,076 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:28,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:28,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:28,120 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:28,120 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1750915672] [2021-11-13 18:36:28,120 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1750915672] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:28,120 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:28,121 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:36:28,121 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1202133669] [2021-11-13 18:36:28,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:28,122 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:28,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:28,123 INFO L85 PathProgramCache]: Analyzing trace with hash 599109159, now seen corresponding path program 1 times [2021-11-13 18:36:28,123 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:28,123 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [210774754] [2021-11-13 18:36:28,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:28,124 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:28,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:28,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:28,174 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:28,174 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [210774754] [2021-11-13 18:36:28,175 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [210774754] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:28,175 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:28,175 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:28,175 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2118842692] [2021-11-13 18:36:28,176 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:28,176 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:28,176 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:28,177 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:36:28,177 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:36:28,177 INFO L87 Difference]: Start difference. First operand 1688 states and 2488 transitions. cyclomatic complexity: 801 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:28,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:28,228 INFO L93 Difference]: Finished difference Result 1688 states and 2483 transitions. [2021-11-13 18:36:28,228 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:36:28,229 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2483 transitions. [2021-11-13 18:36:28,242 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:28,291 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2483 transitions. [2021-11-13 18:36:28,291 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-13 18:36:28,293 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-13 18:36:28,293 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2483 transitions. [2021-11-13 18:36:28,297 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:28,297 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2483 transitions. [2021-11-13 18:36:28,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2483 transitions. [2021-11-13 18:36:28,331 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-13 18:36:28,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4709715639810426) internal successors, (2483), 1687 states have internal predecessors, (2483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:28,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2483 transitions. [2021-11-13 18:36:28,341 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2483 transitions. [2021-11-13 18:36:28,341 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2483 transitions. [2021-11-13 18:36:28,341 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-13 18:36:28,342 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2483 transitions. [2021-11-13 18:36:28,355 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:28,355 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:28,356 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:28,359 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:28,359 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:28,360 INFO L791 eck$LassoCheckResult]: Stem: 48180#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 48181#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 49034#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48526#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48333#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 48334#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48419#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48720#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48842#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48843#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47631#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47632#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48780#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48226#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48227#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 48133#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 48134#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 48522#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47875#L1174 assume !(0 == ~M_E~0); 47876#L1174-2 assume !(0 == ~T1_E~0); 47727#L1179-1 assume !(0 == ~T2_E~0); 47629#L1184-1 assume !(0 == ~T3_E~0); 47630#L1189-1 assume !(0 == ~T4_E~0); 47668#L1194-1 assume !(0 == ~T5_E~0); 47768#L1199-1 assume !(0 == ~T6_E~0); 48663#L1204-1 assume !(0 == ~T7_E~0); 48582#L1209-1 assume !(0 == ~T8_E~0); 48583#L1214-1 assume !(0 == ~T9_E~0); 48971#L1219-1 assume !(0 == ~T10_E~0); 49056#L1224-1 assume !(0 == ~T11_E~0); 47993#L1229-1 assume !(0 == ~T12_E~0); 47554#L1234-1 assume !(0 == ~E_1~0); 47555#L1239-1 assume !(0 == ~E_2~0); 47588#L1244-1 assume !(0 == ~E_3~0); 47589#L1249-1 assume !(0 == ~E_4~0); 48250#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 47484#L1259-1 assume !(0 == ~E_6~0); 47439#L1264-1 assume !(0 == ~E_7~0); 47440#L1269-1 assume !(0 == ~E_8~0); 49061#L1274-1 assume !(0 == ~E_9~0); 48996#L1279-1 assume !(0 == ~E_10~0); 47672#L1284-1 assume !(0 == ~E_11~0); 47673#L1289-1 assume !(0 == ~E_12~0); 48302#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48303#L566 assume 1 == ~m_pc~0; 47456#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 47457#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48611#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48612#L1455 assume !(0 != activate_threads_~tmp~1#1); 47902#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47903#L585 assume 1 == ~t1_pc~0; 47551#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47552#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48552#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48553#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 49021#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49019#L604 assume !(1 == ~t2_pc~0); 48631#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 48632#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48165#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48166#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 48803#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48804#L623 assume 1 == ~t3_pc~0; 48080#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47420#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48230#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48231#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 48838#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47453#L642 assume !(1 == ~t4_pc~0); 47454#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47919#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47920#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47525#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 47526#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48643#L661 assume 1 == ~t5_pc~0; 47690#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47691#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47652#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47653#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 48672#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48673#L680 assume !(1 == ~t6_pc~0); 48113#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 48114#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48375#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48376#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 48904#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49017#L699 assume 1 == ~t7_pc~0; 48503#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48504#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47680#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47681#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 48405#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48304#L718 assume !(1 == ~t8_pc~0); 48305#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47666#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47667#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47708#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 47709#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47842#L737 assume 1 == ~t9_pc~0; 48707#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47977#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48578#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48579#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 48151#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48152#L756 assume 1 == ~t10_pc~0; 48731#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 48397#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47383#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47384#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 47959#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47960#L775 assume !(1 == ~t11_pc~0); 48214#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 48215#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47836#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47600#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 47601#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47787#L794 assume 1 == ~t12_pc~0; 47627#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 47605#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48798#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 47753#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 47754#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48233#L1307 assume !(1 == ~M_E~0); 48234#L1307-2 assume !(1 == ~T1_E~0); 48345#L1312-1 assume !(1 == ~T2_E~0); 48264#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48265#L1322-1 assume !(1 == ~T4_E~0); 47968#L1327-1 assume !(1 == ~T5_E~0); 47969#L1332-1 assume !(1 == ~T6_E~0); 48507#L1337-1 assume !(1 == ~T7_E~0); 48469#L1342-1 assume !(1 == ~T8_E~0); 48470#L1347-1 assume !(1 == ~T9_E~0); 48867#L1352-1 assume !(1 == ~T10_E~0); 48740#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 48131#L1362-1 assume !(1 == ~T12_E~0); 48132#L1367-1 assume !(1 == ~E_1~0); 47769#L1372-1 assume !(1 == ~E_2~0); 47770#L1377-1 assume !(1 == ~E_3~0); 48063#L1382-1 assume !(1 == ~E_4~0); 48064#L1387-1 assume !(1 == ~E_5~0); 48633#L1392-1 assume !(1 == ~E_6~0); 48083#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 48084#L1402-1 assume !(1 == ~E_8~0); 47780#L1407-1 assume !(1 == ~E_9~0); 47781#L1412-1 assume !(1 == ~E_10~0); 48796#L1417-1 assume !(1 == ~E_11~0); 48797#L1422-1 assume !(1 == ~E_12~0); 49015#L1427-1 assume { :end_inline_reset_delta_events } true; 47584#L1768-2 [2021-11-13 18:36:28,361 INFO L793 eck$LassoCheckResult]: Loop: 47584#L1768-2 assume !false; 47585#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48323#L1149 assume !false; 48695#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 48848#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47974#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47880#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 47881#L976 assume !(0 != eval_~tmp~0#1); 49014#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49024#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48815#L1174-3 assume !(0 == ~M_E~0); 48808#L1174-5 assume !(0 == ~T1_E~0); 48557#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48558#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48741#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48392#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47742#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47743#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47984#L1209-3 assume !(0 == ~T8_E~0); 47404#L1214-3 assume !(0 == ~T9_E~0); 47405#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 48163#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48164#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 48182#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47592#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47593#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48036#L1249-3 assume !(0 == ~E_4~0); 48495#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 48967#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 48609#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47598#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47599#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 48994#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 48161#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 48162#L1289-3 assume !(0 == ~E_12~0); 48150#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47826#L566-39 assume 1 == ~m_pc~0; 47827#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 48429#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48141#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48142#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 48684#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48685#L585-39 assume !(1 == ~t1_pc~0); 47834#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 47835#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47910#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47911#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48717#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48410#L604-39 assume 1 == ~t2_pc~0; 48411#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48042#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48043#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48460#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 48461#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48025#L623-39 assume 1 == ~t3_pc~0; 47421#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47423#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48701#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47877#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47878#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48649#L642-39 assume 1 == ~t4_pc~0; 48220#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48221#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47749#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47750#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48847#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47798#L661-39 assume !(1 == ~t5_pc~0); 47429#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 47430#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48790#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48791#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48704#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48705#L680-39 assume 1 == ~t6_pc~0; 47491#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47492#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48634#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47957#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47958#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48972#L699-39 assume 1 == ~t7_pc~0; 48394#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48116#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48117#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48800#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 48921#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48919#L718-39 assume 1 == ~t8_pc~0; 48308#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48309#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48241#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48242#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 48544#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48513#L737-39 assume 1 == ~t9_pc~0; 47938#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47939#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48228#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48995#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 48896#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48839#L756-39 assume !(1 == ~t10_pc~0); 48320#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 48321#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48065#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48066#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48198#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47538#L775-39 assume 1 == ~t11_pc~0; 47539#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48191#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48192#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49054#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48602#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48249#L794-39 assume 1 == ~t12_pc~0; 47941#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 47935#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48755#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 48656#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47480#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47481#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48948#L1307-5 assume !(1 == ~T1_E~0); 48949#L1312-3 assume !(1 == ~T2_E~0); 49060#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48674#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48675#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47619#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 47590#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47591#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 48337#L1347-3 assume !(1 == ~T9_E~0); 48462#L1352-3 assume !(1 == ~T10_E~0); 48463#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 48902#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 49053#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49044#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 47417#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 47418#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48049#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 48050#L1392-3 assume !(1 == ~E_6~0); 48765#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49011#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 48428#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47704#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47705#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 48353#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 48354#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47714#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47715#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 48581#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 48433#L1787 assume !(0 == start_simulation_~tmp~3#1); 48434#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 48957#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47685#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 48480#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 48481#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48032#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48033#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 48034#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 47584#L1768-2 [2021-11-13 18:36:28,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:28,362 INFO L85 PathProgramCache]: Analyzing trace with hash -1828387561, now seen corresponding path program 1 times [2021-11-13 18:36:28,362 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:28,363 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1878752221] [2021-11-13 18:36:28,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:28,363 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:28,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:28,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:28,416 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:28,416 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1878752221] [2021-11-13 18:36:28,417 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1878752221] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:28,417 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:28,417 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:36:28,417 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1775481074] [2021-11-13 18:36:28,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:28,418 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:28,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:28,419 INFO L85 PathProgramCache]: Analyzing trace with hash 258585354, now seen corresponding path program 1 times [2021-11-13 18:36:28,419 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:28,419 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1222689901] [2021-11-13 18:36:28,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:28,420 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:28,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:28,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:28,473 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:28,473 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1222689901] [2021-11-13 18:36:28,473 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1222689901] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:28,474 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:28,475 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:28,475 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1361817751] [2021-11-13 18:36:28,475 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:28,476 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:28,476 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:28,476 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:36:28,477 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:36:28,477 INFO L87 Difference]: Start difference. First operand 1688 states and 2483 transitions. cyclomatic complexity: 796 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:28,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:28,578 INFO L93 Difference]: Finished difference Result 1688 states and 2464 transitions. [2021-11-13 18:36:28,579 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:36:28,579 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2464 transitions. [2021-11-13 18:36:28,592 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:28,617 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2464 transitions. [2021-11-13 18:36:28,618 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-11-13 18:36:28,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-11-13 18:36:28,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2464 transitions. [2021-11-13 18:36:28,624 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:28,624 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2464 transitions. [2021-11-13 18:36:28,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2464 transitions. [2021-11-13 18:36:28,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-11-13 18:36:28,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4597156398104265) internal successors, (2464), 1687 states have internal predecessors, (2464), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:28,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2464 transitions. [2021-11-13 18:36:28,669 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2464 transitions. [2021-11-13 18:36:28,670 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2464 transitions. [2021-11-13 18:36:28,670 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-13 18:36:28,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2464 transitions. [2021-11-13 18:36:28,680 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-11-13 18:36:28,680 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:28,680 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:28,683 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:28,683 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:28,684 INFO L791 eck$LassoCheckResult]: Stem: 51562#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 51563#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 52417#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 51908#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51713#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 51714#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51799#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52105#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52224#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52225#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 51012#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 51013#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 52161#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 51606#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 51607#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 51515#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 51516#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 51903#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 51255#L1174 assume !(0 == ~M_E~0); 51256#L1174-2 assume !(0 == ~T1_E~0); 51107#L1179-1 assume !(0 == ~T2_E~0); 51010#L1184-1 assume !(0 == ~T3_E~0); 51011#L1189-1 assume !(0 == ~T4_E~0); 51049#L1194-1 assume !(0 == ~T5_E~0); 51150#L1199-1 assume !(0 == ~T6_E~0); 52044#L1204-1 assume !(0 == ~T7_E~0); 51963#L1209-1 assume !(0 == ~T8_E~0); 51964#L1214-1 assume !(0 == ~T9_E~0); 52354#L1219-1 assume !(0 == ~T10_E~0); 52439#L1224-1 assume !(0 == ~T11_E~0); 51374#L1229-1 assume !(0 == ~T12_E~0); 50937#L1234-1 assume !(0 == ~E_1~0); 50938#L1239-1 assume !(0 == ~E_2~0); 50971#L1244-1 assume !(0 == ~E_3~0); 50972#L1249-1 assume !(0 == ~E_4~0); 51630#L1254-1 assume !(0 == ~E_5~0); 50866#L1259-1 assume !(0 == ~E_6~0); 50821#L1264-1 assume !(0 == ~E_7~0); 50822#L1269-1 assume !(0 == ~E_8~0); 52444#L1274-1 assume !(0 == ~E_9~0); 52379#L1279-1 assume !(0 == ~E_10~0); 51053#L1284-1 assume !(0 == ~E_11~0); 51054#L1289-1 assume !(0 == ~E_12~0); 51682#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51683#L566 assume 1 == ~m_pc~0; 50838#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50839#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51992#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51993#L1455 assume !(0 != activate_threads_~tmp~1#1); 51282#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51283#L585 assume 1 == ~t1_pc~0; 50932#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50933#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51933#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51934#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 52404#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52402#L604 assume !(1 == ~t2_pc~0); 52012#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 52013#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51545#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51546#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52187#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52188#L623 assume 1 == ~t3_pc~0; 51460#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50803#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51610#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51611#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 52220#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50835#L642 assume !(1 == ~t4_pc~0); 50836#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51299#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51300#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50909#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 50910#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52024#L661 assume !(1 == ~t5_pc~0); 51072#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 51925#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51033#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51034#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 52053#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52054#L680 assume !(1 == ~t6_pc~0); 51493#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 51494#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51755#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51756#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 52287#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52400#L699 assume 1 == ~t7_pc~0; 51883#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 51884#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51061#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51062#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 51785#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51684#L718 assume !(1 == ~t8_pc~0); 51685#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 51047#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51048#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51088#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 51089#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51222#L737 assume 1 == ~t9_pc~0; 52088#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51357#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51959#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 51960#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 51531#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51532#L756 assume 1 == ~t10_pc~0; 52112#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 51777#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50766#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50767#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 51339#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51340#L775 assume !(1 == ~t11_pc~0); 51594#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 51595#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51216#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50981#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50982#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51167#L794 assume 1 == ~t12_pc~0; 51008#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50986#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52180#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 51133#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 51134#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51613#L1307 assume !(1 == ~M_E~0); 51614#L1307-2 assume !(1 == ~T1_E~0); 51725#L1312-1 assume !(1 == ~T2_E~0); 51644#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 51645#L1322-1 assume !(1 == ~T4_E~0); 51348#L1327-1 assume !(1 == ~T5_E~0); 51349#L1332-1 assume !(1 == ~T6_E~0); 51887#L1337-1 assume !(1 == ~T7_E~0); 51849#L1342-1 assume !(1 == ~T8_E~0); 51850#L1347-1 assume !(1 == ~T9_E~0); 52249#L1352-1 assume !(1 == ~T10_E~0); 52121#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 51511#L1362-1 assume !(1 == ~T12_E~0); 51512#L1367-1 assume !(1 == ~E_1~0); 51148#L1372-1 assume !(1 == ~E_2~0); 51149#L1377-1 assume !(1 == ~E_3~0); 51443#L1382-1 assume !(1 == ~E_4~0); 51444#L1387-1 assume !(1 == ~E_5~0); 52014#L1392-1 assume !(1 == ~E_6~0); 51463#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 51464#L1402-1 assume !(1 == ~E_8~0); 51160#L1407-1 assume !(1 == ~E_9~0); 51161#L1412-1 assume !(1 == ~E_10~0); 52178#L1417-1 assume !(1 == ~E_11~0); 52179#L1422-1 assume !(1 == ~E_12~0); 52398#L1427-1 assume { :end_inline_reset_delta_events } true; 50965#L1768-2 [2021-11-13 18:36:28,685 INFO L793 eck$LassoCheckResult]: Loop: 50965#L1768-2 assume !false; 50966#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51703#L1149 assume !false; 52076#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 52230#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 51354#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 51260#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 51261#L976 assume !(0 != eval_~tmp~0#1); 52397#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52407#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52197#L1174-3 assume !(0 == ~M_E~0); 52190#L1174-5 assume !(0 == ~T1_E~0); 51938#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 51939#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52122#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51772#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51122#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51123#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 51364#L1209-3 assume !(0 == ~T8_E~0); 50787#L1214-3 assume !(0 == ~T9_E~0); 50788#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51543#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 51544#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51560#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50973#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50974#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 51416#L1249-3 assume !(0 == ~E_4~0); 51875#L1254-3 assume !(0 == ~E_5~0); 52350#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51990#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50979#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50980#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 52377#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 51541#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51542#L1289-3 assume !(0 == ~E_12~0); 51530#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51206#L566-39 assume 1 == ~m_pc~0; 51207#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 51809#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51521#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51522#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52065#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52066#L585-39 assume 1 == ~t1_pc~0; 52177#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 51215#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51290#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51291#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52098#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51790#L604-39 assume !(1 == ~t2_pc~0); 51792#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 51422#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51423#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51840#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 51841#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51405#L623-39 assume 1 == ~t3_pc~0; 50804#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50806#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52082#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51257#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51258#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52030#L642-39 assume 1 == ~t4_pc~0; 51600#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51601#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51129#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51130#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 52229#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51178#L661-39 assume !(1 == ~t5_pc~0); 50811#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 50812#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52171#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52172#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 52085#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52086#L680-39 assume 1 == ~t6_pc~0; 50873#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50874#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52015#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51337#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 51338#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52355#L699-39 assume 1 == ~t7_pc~0; 51774#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 51496#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51497#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52182#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52304#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52302#L718-39 assume 1 == ~t8_pc~0; 51688#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 51689#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51621#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51622#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 51924#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51893#L737-39 assume 1 == ~t9_pc~0; 51318#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51319#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51608#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52378#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 52279#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52221#L756-39 assume !(1 == ~t10_pc~0); 51700#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 51701#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51445#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51446#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51578#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50920#L775-39 assume 1 == ~t11_pc~0; 50921#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 51571#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51572#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52437#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 51983#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51629#L794-39 assume !(1 == ~t12_pc~0); 51314#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 51315#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52136#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 52037#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 50862#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50863#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 52331#L1307-5 assume !(1 == ~T1_E~0); 52332#L1312-3 assume !(1 == ~T2_E~0); 52443#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52055#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52056#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 51000#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50969#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50970#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 51717#L1347-3 assume !(1 == ~T9_E~0); 51842#L1352-3 assume !(1 == ~T10_E~0); 51843#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52285#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 52436#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 52427#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50800#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50801#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51429#L1387-3 assume !(1 == ~E_5~0); 51430#L1392-3 assume !(1 == ~E_6~0); 52146#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 52394#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 51808#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51084#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51085#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 51733#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 51734#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 51094#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 51095#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 51962#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 51813#L1787 assume !(0 == start_simulation_~tmp~3#1); 51814#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 52340#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 51066#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 51860#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 51861#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51412#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51413#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 51414#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 50965#L1768-2 [2021-11-13 18:36:28,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:28,686 INFO L85 PathProgramCache]: Analyzing trace with hash 1565876984, now seen corresponding path program 1 times [2021-11-13 18:36:28,686 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:28,686 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1157385742] [2021-11-13 18:36:28,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:28,687 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:28,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:28,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:28,737 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:28,738 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1157385742] [2021-11-13 18:36:28,739 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1157385742] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:28,740 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:28,740 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:36:28,740 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1107886650] [2021-11-13 18:36:28,741 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:28,741 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:28,742 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:28,742 INFO L85 PathProgramCache]: Analyzing trace with hash 1594965101, now seen corresponding path program 1 times [2021-11-13 18:36:28,742 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:28,742 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1047425866] [2021-11-13 18:36:28,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:28,743 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:28,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:28,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:28,795 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:28,796 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1047425866] [2021-11-13 18:36:28,796 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1047425866] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:28,796 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:28,796 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:28,797 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1041459152] [2021-11-13 18:36:28,797 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:28,797 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:28,798 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:28,798 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:36:28,798 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:36:28,799 INFO L87 Difference]: Start difference. First operand 1688 states and 2464 transitions. cyclomatic complexity: 777 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:28,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:28,956 INFO L93 Difference]: Finished difference Result 3198 states and 4634 transitions. [2021-11-13 18:36:28,957 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:36:28,957 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3198 states and 4634 transitions. [2021-11-13 18:36:28,983 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3037 [2021-11-13 18:36:29,000 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3198 states to 3198 states and 4634 transitions. [2021-11-13 18:36:29,001 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3198 [2021-11-13 18:36:29,005 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3198 [2021-11-13 18:36:29,007 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3198 states and 4634 transitions. [2021-11-13 18:36:29,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:29,014 INFO L681 BuchiCegarLoop]: Abstraction has 3198 states and 4634 transitions. [2021-11-13 18:36:29,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3198 states and 4634 transitions. [2021-11-13 18:36:29,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3198 to 3106. [2021-11-13 18:36:29,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3106 states, 3106 states have (on average 1.4507405022537025) internal successors, (4506), 3105 states have internal predecessors, (4506), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:29,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3106 states to 3106 states and 4506 transitions. [2021-11-13 18:36:29,098 INFO L704 BuchiCegarLoop]: Abstraction has 3106 states and 4506 transitions. [2021-11-13 18:36:29,098 INFO L587 BuchiCegarLoop]: Abstraction has 3106 states and 4506 transitions. [2021-11-13 18:36:29,098 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-13 18:36:29,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3106 states and 4506 transitions. [2021-11-13 18:36:29,116 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2945 [2021-11-13 18:36:29,117 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:29,117 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:29,119 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:29,120 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:29,120 INFO L791 eck$LassoCheckResult]: Stem: 56447#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 56448#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 57333#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56797#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56602#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 56603#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56688#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 57000#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 57127#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 57128#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55902#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 55903#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 57061#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 56493#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 56494#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 56400#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 56401#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 56793#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 56143#L1174 assume !(0 == ~M_E~0); 56144#L1174-2 assume !(0 == ~T1_E~0); 55997#L1179-1 assume !(0 == ~T2_E~0); 55900#L1184-1 assume !(0 == ~T3_E~0); 55901#L1189-1 assume !(0 == ~T4_E~0); 55939#L1194-1 assume !(0 == ~T5_E~0); 56038#L1199-1 assume !(0 == ~T6_E~0); 56940#L1204-1 assume !(0 == ~T7_E~0); 56855#L1209-1 assume !(0 == ~T8_E~0); 56856#L1214-1 assume !(0 == ~T9_E~0); 57257#L1219-1 assume !(0 == ~T10_E~0); 57358#L1224-1 assume !(0 == ~T11_E~0); 56260#L1229-1 assume !(0 == ~T12_E~0); 55825#L1234-1 assume !(0 == ~E_1~0); 55826#L1239-1 assume !(0 == ~E_2~0); 55859#L1244-1 assume !(0 == ~E_3~0); 55860#L1249-1 assume !(0 == ~E_4~0); 56517#L1254-1 assume !(0 == ~E_5~0); 55756#L1259-1 assume !(0 == ~E_6~0); 55714#L1264-1 assume !(0 == ~E_7~0); 55715#L1269-1 assume !(0 == ~E_8~0); 57368#L1274-1 assume !(0 == ~E_9~0); 57283#L1279-1 assume !(0 == ~E_10~0); 55943#L1284-1 assume !(0 == ~E_11~0); 55944#L1289-1 assume !(0 == ~E_12~0); 56571#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56572#L566 assume !(1 == ~m_pc~0); 56997#L566-2 is_master_triggered_~__retres1~0#1 := 0; 56998#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56887#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56888#L1455 assume !(0 != activate_threads_~tmp~1#1); 56170#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56171#L585 assume 1 == ~t1_pc~0; 55822#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 55823#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56824#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56825#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 57312#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57310#L604 assume !(1 == ~t2_pc~0); 56907#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 56908#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56432#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56433#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 57088#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57089#L623 assume 1 == ~t3_pc~0; 56347#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55696#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56497#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 56498#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 57122#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55728#L642 assume !(1 == ~t4_pc~0); 55729#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56187#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56188#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55797#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 55798#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56919#L661 assume !(1 == ~t5_pc~0); 55962#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 56816#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55923#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55924#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 56949#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56950#L680 assume !(1 == ~t6_pc~0); 56380#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 56381#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56644#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56645#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 57190#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 57308#L699 assume 1 == ~t7_pc~0; 56774#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 56775#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55951#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55952#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 56674#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56573#L718 assume !(1 == ~t8_pc~0); 56574#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 55937#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55938#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 55978#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 55979#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 56110#L737 assume 1 == ~t9_pc~0; 56985#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 56246#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 56850#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56851#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 56418#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 56419#L756 assume 1 == ~t10_pc~0; 57012#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 56666#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 55659#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55660#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 56227#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56228#L775 assume !(1 == ~t11_pc~0); 56481#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 56482#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 56104#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55871#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 55872#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 56057#L794 assume 1 == ~t12_pc~0; 55898#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 55876#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 57083#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 56023#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 56024#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56500#L1307 assume !(1 == ~M_E~0); 56501#L1307-2 assume !(1 == ~T1_E~0); 56614#L1312-1 assume !(1 == ~T2_E~0); 56531#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 56532#L1322-1 assume !(1 == ~T4_E~0); 56237#L1327-1 assume !(1 == ~T5_E~0); 56238#L1332-1 assume !(1 == ~T6_E~0); 56778#L1337-1 assume !(1 == ~T7_E~0); 56738#L1342-1 assume !(1 == ~T8_E~0); 56739#L1347-1 assume !(1 == ~T9_E~0); 57152#L1352-1 assume !(1 == ~T10_E~0); 57020#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 56398#L1362-1 assume !(1 == ~T12_E~0); 56399#L1367-1 assume !(1 == ~E_1~0); 56039#L1372-1 assume !(1 == ~E_2~0); 56040#L1377-1 assume !(1 == ~E_3~0); 56330#L1382-1 assume !(1 == ~E_4~0); 56331#L1387-1 assume !(1 == ~E_5~0); 56909#L1392-1 assume !(1 == ~E_6~0); 56350#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 56351#L1402-1 assume !(1 == ~E_8~0); 56050#L1407-1 assume !(1 == ~E_9~0); 56051#L1412-1 assume !(1 == ~E_10~0); 57081#L1417-1 assume !(1 == ~E_11~0); 57082#L1422-1 assume !(1 == ~E_12~0); 57306#L1427-1 assume { :end_inline_reset_delta_events } true; 55855#L1768-2 [2021-11-13 18:36:29,121 INFO L793 eck$LassoCheckResult]: Loop: 55855#L1768-2 assume !false; 55856#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 56592#L1149 assume !false; 56973#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 57133#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 56243#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 56148#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 56149#L976 assume !(0 != eval_~tmp~0#1); 57302#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57319#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 57099#L1174-3 assume !(0 == ~M_E~0); 57093#L1174-5 assume !(0 == ~T1_E~0); 56829#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 56830#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57021#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 56661#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 56012#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 56013#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 56252#L1209-3 assume !(0 == ~T8_E~0); 55680#L1214-3 assume !(0 == ~T9_E~0); 55681#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 56430#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 56431#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 56449#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55863#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 55864#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 56303#L1249-3 assume !(0 == ~E_4~0); 56766#L1254-3 assume !(0 == ~E_5~0); 57253#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 56885#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 55869#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 55870#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 57281#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 56428#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 56429#L1289-3 assume !(0 == ~E_12~0); 56417#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56092#L566-39 assume !(1 == ~m_pc~0); 56093#L566-41 is_master_triggered_~__retres1~0#1 := 0; 56698#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56408#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56409#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 56961#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56962#L585-39 assume !(1 == ~t1_pc~0); 56102#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 56103#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56178#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56179#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 56995#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56679#L604-39 assume 1 == ~t2_pc~0; 56680#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 56309#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56310#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56729#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 56730#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56292#L623-39 assume 1 == ~t3_pc~0; 55697#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55699#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56979#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 56145#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 56146#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56925#L642-39 assume 1 == ~t4_pc~0; 56487#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 56488#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56019#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 56020#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 57132#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56068#L661-39 assume !(1 == ~t5_pc~0); 55704#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 55705#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57074#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 57075#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 56982#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56983#L680-39 assume 1 == ~t6_pc~0; 55763#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 55764#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56910#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56225#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 56226#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 57258#L699-39 assume 1 == ~t7_pc~0; 56663#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 56383#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 56384#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 57085#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 57206#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57204#L718-39 assume 1 == ~t8_pc~0; 56577#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 56578#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56508#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 56509#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 56815#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 56784#L737-39 assume !(1 == ~t9_pc~0); 56208#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 56207#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 56495#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 57282#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 57182#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57123#L756-39 assume 1 == ~t10_pc~0; 57124#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 56590#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 56332#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 56333#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 56465#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55810#L775-39 assume 1 == ~t11_pc~0; 55811#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 56458#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 56459#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 57356#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 56878#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 56516#L794-39 assume 1 == ~t12_pc~0; 56209#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 56203#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 57035#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 56932#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 55752#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55753#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 57234#L1307-5 assume !(1 == ~T1_E~0); 57235#L1312-3 assume !(1 == ~T2_E~0); 57367#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 56951#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56952#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 55890#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 55861#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 55862#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 56606#L1347-3 assume !(1 == ~T9_E~0); 56731#L1352-3 assume !(1 == ~T10_E~0); 56732#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 57188#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 57355#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 57344#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 55693#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 55694#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 56316#L1387-3 assume !(1 == ~E_5~0); 56317#L1392-3 assume !(1 == ~E_6~0); 57046#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 57299#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 56697#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 55974#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 55975#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 56622#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 56623#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 55984#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 55985#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 56854#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 56702#L1787 assume !(0 == start_simulation_~tmp~3#1); 56703#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 57243#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 55956#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 56749#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 56750#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 56299#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 56300#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 56301#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 55855#L1768-2 [2021-11-13 18:36:29,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:29,122 INFO L85 PathProgramCache]: Analyzing trace with hash 328223895, now seen corresponding path program 1 times [2021-11-13 18:36:29,122 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:29,122 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1600954008] [2021-11-13 18:36:29,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:29,123 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:29,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:29,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:29,176 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:29,176 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1600954008] [2021-11-13 18:36:29,176 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1600954008] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:29,176 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:29,177 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:29,177 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1306483518] [2021-11-13 18:36:29,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:29,178 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:29,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:29,178 INFO L85 PathProgramCache]: Analyzing trace with hash -33239315, now seen corresponding path program 1 times [2021-11-13 18:36:29,179 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:29,179 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1193545748] [2021-11-13 18:36:29,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:29,179 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:29,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:29,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:29,277 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:29,277 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1193545748] [2021-11-13 18:36:29,278 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1193545748] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:29,278 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:29,278 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:29,278 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1176354632] [2021-11-13 18:36:29,279 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:29,279 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:29,279 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:29,280 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:36:29,280 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:36:29,280 INFO L87 Difference]: Start difference. First operand 3106 states and 4506 transitions. cyclomatic complexity: 1402 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:29,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:29,719 INFO L93 Difference]: Finished difference Result 7410 states and 10665 transitions. [2021-11-13 18:36:29,719 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:36:29,720 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7410 states and 10665 transitions. [2021-11-13 18:36:29,778 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 7150 [2021-11-13 18:36:29,818 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7410 states to 7410 states and 10665 transitions. [2021-11-13 18:36:29,818 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7410 [2021-11-13 18:36:29,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7410 [2021-11-13 18:36:29,829 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7410 states and 10665 transitions. [2021-11-13 18:36:29,842 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:29,842 INFO L681 BuchiCegarLoop]: Abstraction has 7410 states and 10665 transitions. [2021-11-13 18:36:29,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7410 states and 10665 transitions. [2021-11-13 18:36:29,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7410 to 5835. [2021-11-13 18:36:29,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5835 states, 5835 states have (on average 1.443873179091688) internal successors, (8425), 5834 states have internal predecessors, (8425), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:30,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5835 states to 5835 states and 8425 transitions. [2021-11-13 18:36:30,004 INFO L704 BuchiCegarLoop]: Abstraction has 5835 states and 8425 transitions. [2021-11-13 18:36:30,004 INFO L587 BuchiCegarLoop]: Abstraction has 5835 states and 8425 transitions. [2021-11-13 18:36:30,005 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-13 18:36:30,005 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5835 states and 8425 transitions. [2021-11-13 18:36:30,033 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5674 [2021-11-13 18:36:30,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:30,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:30,038 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:30,038 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:30,039 INFO L791 eck$LassoCheckResult]: Stem: 66982#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 66983#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 67885#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67331#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67134#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 67135#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67221#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 67540#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67668#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 67669#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 66423#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 66424#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 67599#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 67027#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 67028#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 66935#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 66936#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 67328#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 66668#L1174 assume !(0 == ~M_E~0); 66669#L1174-2 assume !(0 == ~T1_E~0); 66520#L1179-1 assume !(0 == ~T2_E~0); 66421#L1184-1 assume !(0 == ~T3_E~0); 66422#L1189-1 assume !(0 == ~T4_E~0); 66461#L1194-1 assume !(0 == ~T5_E~0); 66561#L1199-1 assume !(0 == ~T6_E~0); 67476#L1204-1 assume !(0 == ~T7_E~0); 67390#L1209-1 assume !(0 == ~T8_E~0); 67391#L1214-1 assume !(0 == ~T9_E~0); 67804#L1219-1 assume !(0 == ~T10_E~0); 67907#L1224-1 assume !(0 == ~T11_E~0); 66790#L1229-1 assume !(0 == ~T12_E~0); 66347#L1234-1 assume !(0 == ~E_1~0); 66348#L1239-1 assume !(0 == ~E_2~0); 66383#L1244-1 assume !(0 == ~E_3~0); 66384#L1249-1 assume !(0 == ~E_4~0); 67050#L1254-1 assume !(0 == ~E_5~0); 66281#L1259-1 assume !(0 == ~E_6~0); 66239#L1264-1 assume !(0 == ~E_7~0); 66240#L1269-1 assume !(0 == ~E_8~0); 67916#L1274-1 assume !(0 == ~E_9~0); 67834#L1279-1 assume !(0 == ~E_10~0); 66464#L1284-1 assume !(0 == ~E_11~0); 66465#L1289-1 assume !(0 == ~E_12~0); 67103#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67104#L566 assume !(1 == ~m_pc~0); 67537#L566-2 is_master_triggered_~__retres1~0#1 := 0; 67538#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67422#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 67423#L1455 assume !(0 != activate_threads_~tmp~1#1); 66695#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66696#L585 assume !(1 == ~t1_pc~0); 66881#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 66882#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67360#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 67361#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 67866#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67864#L604 assume !(1 == ~t2_pc~0); 67442#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 67443#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66967#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66968#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 67628#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67629#L623 assume 1 == ~t3_pc~0; 66880#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66221#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67031#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67032#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 67663#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66253#L642 assume !(1 == ~t4_pc~0); 66254#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 66714#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66715#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66322#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 66323#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67454#L661 assume !(1 == ~t5_pc~0); 66485#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 67350#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66444#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66445#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 67487#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 67488#L680 assume !(1 == ~t6_pc~0); 66915#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 66916#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 67176#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 67177#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 67736#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67862#L699 assume 1 == ~t7_pc~0; 67308#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 67309#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66472#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66473#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 67207#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67105#L718 assume !(1 == ~t8_pc~0); 67106#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 66459#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66460#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66501#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 66502#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66635#L737 assume 1 == ~t9_pc~0; 67525#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 66775#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 67386#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 67387#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 66953#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66954#L756 assume 1 == ~t10_pc~0; 67551#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 67198#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66185#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 66186#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 66756#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66757#L775 assume !(1 == ~t11_pc~0); 67015#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 67016#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66629#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 66393#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 66394#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 66580#L794 assume 1 == ~t12_pc~0; 66420#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 66398#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 67623#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 66546#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 66547#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67034#L1307 assume !(1 == ~M_E~0); 67035#L1307-2 assume !(1 == ~T1_E~0); 67146#L1312-1 assume !(1 == ~T2_E~0); 67064#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 67065#L1322-1 assume !(1 == ~T4_E~0); 66766#L1327-1 assume !(1 == ~T5_E~0); 66767#L1332-1 assume !(1 == ~T6_E~0); 67312#L1337-1 assume !(1 == ~T7_E~0); 67271#L1342-1 assume !(1 == ~T8_E~0); 67272#L1347-1 assume !(1 == ~T9_E~0); 67694#L1352-1 assume !(1 == ~T10_E~0); 67560#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 66933#L1362-1 assume !(1 == ~T12_E~0); 66934#L1367-1 assume !(1 == ~E_1~0); 66562#L1372-1 assume !(1 == ~E_2~0); 66563#L1377-1 assume !(1 == ~E_3~0); 66863#L1382-1 assume !(1 == ~E_4~0); 66864#L1387-1 assume !(1 == ~E_5~0); 67444#L1392-1 assume !(1 == ~E_6~0); 66885#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 66886#L1402-1 assume !(1 == ~E_8~0); 66573#L1407-1 assume !(1 == ~E_9~0); 66574#L1412-1 assume !(1 == ~E_10~0); 67621#L1417-1 assume !(1 == ~E_11~0); 67622#L1422-1 assume !(1 == ~E_12~0); 67860#L1427-1 assume { :end_inline_reset_delta_events } true; 66377#L1768-2 [2021-11-13 18:36:30,039 INFO L793 eck$LassoCheckResult]: Loop: 66377#L1768-2 assume !false; 66378#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 67124#L1149 assume !false; 67511#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 67674#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 66772#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 66673#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 66674#L976 assume !(0 != eval_~tmp~0#1); 67856#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 67874#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 67639#L1174-3 assume !(0 == ~M_E~0); 67633#L1174-5 assume !(0 == ~T1_E~0); 67365#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67366#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67562#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67193#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 66535#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 66536#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 66781#L1209-3 assume !(0 == ~T8_E~0); 66206#L1214-3 assume !(0 == ~T9_E~0); 66207#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 66965#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 66966#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 66984#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 66385#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 66386#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 66836#L1249-3 assume !(0 == ~E_4~0); 67300#L1254-3 assume !(0 == ~E_5~0); 67800#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 67420#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 66391#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 66392#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 67832#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 66963#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 66964#L1289-3 assume !(0 == ~E_12~0); 66952#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66615#L566-39 assume !(1 == ~m_pc~0); 66616#L566-41 is_master_triggered_~__retres1~0#1 := 0; 67231#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66943#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66944#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 67497#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67498#L585-39 assume !(1 == ~t1_pc~0); 66627#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 66628#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66703#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66704#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 67535#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67212#L604-39 assume 1 == ~t2_pc~0; 67213#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 66842#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66843#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 67264#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 67265#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66822#L623-39 assume !(1 == ~t3_pc~0); 66225#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 66226#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67519#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 66670#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 66671#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67460#L642-39 assume !(1 == ~t4_pc~0); 67025#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 67024#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66542#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66543#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67673#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66593#L661-39 assume !(1 == ~t5_pc~0); 66229#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 66230#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67611#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 67612#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 67522#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 67523#L680-39 assume 1 == ~t6_pc~0; 66290#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 66291#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 67445#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66754#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66755#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67805#L699-39 assume 1 == ~t7_pc~0; 67195#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 66918#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66919#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 67625#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 67752#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67750#L718-39 assume 1 == ~t8_pc~0; 67110#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 67111#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 67042#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 67043#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 67348#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 67317#L737-39 assume !(1 == ~t9_pc~0); 66736#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 66735#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 67029#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 67833#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 67728#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 67664#L756-39 assume 1 == ~t10_pc~0; 67665#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 67119#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66865#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 66866#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 66999#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66333#L775-39 assume !(1 == ~t11_pc~0); 66335#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 66993#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66994#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 67905#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 67413#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 67047#L794-39 assume 1 == ~t12_pc~0; 66737#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 66726#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 67574#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 67467#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 66277#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66278#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 67780#L1307-5 assume !(1 == ~T1_E~0); 67781#L1312-3 assume !(1 == ~T2_E~0); 67915#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 67485#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 67486#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 66409#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 66381#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 66382#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 67138#L1347-3 assume !(1 == ~T9_E~0); 67262#L1352-3 assume !(1 == ~T10_E~0); 67263#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 67733#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 67904#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 67895#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 66215#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 66216#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66849#L1387-3 assume !(1 == ~E_5~0); 66850#L1392-3 assume !(1 == ~E_6~0); 67584#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 67853#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 67230#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 66497#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 66498#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 67152#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 67153#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 66505#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 66506#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 67389#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 67234#L1787 assume !(0 == start_simulation_~tmp~3#1); 67235#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 67790#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 66477#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 67282#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 67283#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 66830#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 66831#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 66832#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 66377#L1768-2 [2021-11-13 18:36:30,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:30,041 INFO L85 PathProgramCache]: Analyzing trace with hash -1540974218, now seen corresponding path program 1 times [2021-11-13 18:36:30,041 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:30,041 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328195959] [2021-11-13 18:36:30,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:30,041 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:30,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:30,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:30,100 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:30,101 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328195959] [2021-11-13 18:36:30,101 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1328195959] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:30,101 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:30,101 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 18:36:30,101 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [583888610] [2021-11-13 18:36:30,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:30,102 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:30,103 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:30,103 INFO L85 PathProgramCache]: Analyzing trace with hash -964336950, now seen corresponding path program 1 times [2021-11-13 18:36:30,103 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:30,103 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1025606658] [2021-11-13 18:36:30,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:30,104 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:30,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:30,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:30,149 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:30,149 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1025606658] [2021-11-13 18:36:30,149 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1025606658] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:30,149 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:30,149 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:30,150 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1145503273] [2021-11-13 18:36:30,150 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:30,151 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:30,151 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:30,152 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-13 18:36:30,152 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-13 18:36:30,152 INFO L87 Difference]: Start difference. First operand 5835 states and 8425 transitions. cyclomatic complexity: 2592 Second operand has 5 states, 5 states have (on average 29.6) internal successors, (148), 5 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:30,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:30,708 INFO L93 Difference]: Finished difference Result 16236 states and 23424 transitions. [2021-11-13 18:36:30,709 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-13 18:36:30,710 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16236 states and 23424 transitions. [2021-11-13 18:36:30,873 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 15874 [2021-11-13 18:36:30,945 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16236 states to 16236 states and 23424 transitions. [2021-11-13 18:36:30,945 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16236 [2021-11-13 18:36:30,966 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16236 [2021-11-13 18:36:30,966 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16236 states and 23424 transitions. [2021-11-13 18:36:30,985 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:30,986 INFO L681 BuchiCegarLoop]: Abstraction has 16236 states and 23424 transitions. [2021-11-13 18:36:31,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16236 states and 23424 transitions. [2021-11-13 18:36:31,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16236 to 5994. [2021-11-13 18:36:31,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5994 states, 5994 states have (on average 1.4320987654320987) internal successors, (8584), 5993 states have internal predecessors, (8584), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:31,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5994 states to 5994 states and 8584 transitions. [2021-11-13 18:36:31,157 INFO L704 BuchiCegarLoop]: Abstraction has 5994 states and 8584 transitions. [2021-11-13 18:36:31,157 INFO L587 BuchiCegarLoop]: Abstraction has 5994 states and 8584 transitions. [2021-11-13 18:36:31,157 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-13 18:36:31,157 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5994 states and 8584 transitions. [2021-11-13 18:36:31,186 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5830 [2021-11-13 18:36:31,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:31,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:31,190 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:31,190 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:31,190 INFO L791 eck$LassoCheckResult]: Stem: 89071#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 89072#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 90097#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 89446#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 89225#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 89226#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 89319#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 89658#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 89813#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 89814#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 88507#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 88508#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 89732#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 89116#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 89117#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 89024#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 89025#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 89442#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 88754#L1174 assume !(0 == ~M_E~0); 88755#L1174-2 assume !(0 == ~T1_E~0); 88605#L1179-1 assume !(0 == ~T2_E~0); 88505#L1184-1 assume !(0 == ~T3_E~0); 88506#L1189-1 assume !(0 == ~T4_E~0); 88546#L1194-1 assume !(0 == ~T5_E~0); 88647#L1199-1 assume !(0 == ~T6_E~0); 89593#L1204-1 assume !(0 == ~T7_E~0); 89507#L1209-1 assume !(0 == ~T8_E~0); 89508#L1214-1 assume !(0 == ~T9_E~0); 89983#L1219-1 assume !(0 == ~T10_E~0); 90127#L1224-1 assume !(0 == ~T11_E~0); 88875#L1229-1 assume !(0 == ~T12_E~0); 88431#L1234-1 assume !(0 == ~E_1~0); 88432#L1239-1 assume !(0 == ~E_2~0); 88465#L1244-1 assume !(0 == ~E_3~0); 88466#L1249-1 assume !(0 == ~E_4~0); 89139#L1254-1 assume !(0 == ~E_5~0); 88365#L1259-1 assume !(0 == ~E_6~0); 88323#L1264-1 assume !(0 == ~E_7~0); 88324#L1269-1 assume !(0 == ~E_8~0); 90143#L1274-1 assume !(0 == ~E_9~0); 90026#L1279-1 assume !(0 == ~E_10~0); 88549#L1284-1 assume !(0 == ~E_11~0); 88550#L1289-1 assume !(0 == ~E_12~0); 89193#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89194#L566 assume !(1 == ~m_pc~0); 89655#L566-2 is_master_triggered_~__retres1~0#1 := 0; 89656#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89538#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 89539#L1455 assume !(0 != activate_threads_~tmp~1#1); 88781#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88782#L585 assume !(1 == ~t1_pc~0); 88970#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 88971#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 89473#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 89474#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 90064#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 90061#L604 assume !(1 == ~t2_pc~0); 89558#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 89559#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 90040#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 89952#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 89769#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89770#L623 assume 1 == ~t3_pc~0; 88969#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 88305#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89120#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 89121#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 89808#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88337#L642 assume !(1 == ~t4_pc~0); 88338#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 88800#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88801#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 88406#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 88407#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 89570#L661 assume !(1 == ~t5_pc~0); 88570#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 89465#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88529#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 88530#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 89603#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 89604#L680 assume !(1 == ~t6_pc~0); 89004#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 89005#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 89270#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 89271#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 89893#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 90059#L699 assume 1 == ~t7_pc~0; 89415#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 89416#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 88557#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 88558#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 89302#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 89195#L718 assume !(1 == ~t8_pc~0); 89196#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 88544#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 88545#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 88586#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 88587#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88721#L737 assume 1 == ~t9_pc~0; 89643#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 88860#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 89500#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 89501#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 89042#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 89043#L756 assume 1 == ~t10_pc~0; 89672#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 89293#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 88269#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 88270#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 88841#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 88842#L775 assume !(1 == ~t11_pc~0); 89104#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 89105#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 88715#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 88477#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 88478#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 88666#L794 assume 1 == ~t12_pc~0; 88503#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 88482#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 89761#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 88631#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 88632#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89123#L1307 assume !(1 == ~M_E~0); 89124#L1307-2 assume !(1 == ~T1_E~0); 89237#L1312-1 assume !(1 == ~T2_E~0); 89154#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 89155#L1322-1 assume !(1 == ~T4_E~0); 88851#L1327-1 assume !(1 == ~T5_E~0); 88852#L1332-1 assume !(1 == ~T6_E~0); 89420#L1337-1 assume !(1 == ~T7_E~0); 89376#L1342-1 assume !(1 == ~T8_E~0); 89377#L1347-1 assume !(1 == ~T9_E~0); 89846#L1352-1 assume !(1 == ~T10_E~0); 89681#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 89022#L1362-1 assume !(1 == ~T12_E~0); 89023#L1367-1 assume !(1 == ~E_1~0); 88648#L1372-1 assume !(1 == ~E_2~0); 88649#L1377-1 assume !(1 == ~E_3~0); 88952#L1382-1 assume !(1 == ~E_4~0); 88953#L1387-1 assume !(1 == ~E_5~0); 89560#L1392-1 assume !(1 == ~E_6~0); 88974#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 88975#L1402-1 assume !(1 == ~E_8~0); 88659#L1407-1 assume !(1 == ~E_9~0); 88660#L1412-1 assume !(1 == ~E_10~0); 89759#L1417-1 assume !(1 == ~E_11~0); 89760#L1422-1 assume !(1 == ~E_12~0); 90054#L1427-1 assume { :end_inline_reset_delta_events } true; 88461#L1768-2 [2021-11-13 18:36:31,191 INFO L793 eck$LassoCheckResult]: Loop: 88461#L1768-2 assume !false; 88462#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 89215#L1149 assume !false; 89631#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 89825#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 88857#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 88759#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 88760#L976 assume !(0 != eval_~tmp~0#1); 90051#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 90077#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 89781#L1174-3 assume !(0 == ~M_E~0); 89782#L1174-5 assume !(0 == ~T1_E~0); 94005#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 94004#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 94003#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 94002#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 94001#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 94000#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 93999#L1209-3 assume !(0 == ~T8_E~0); 93998#L1214-3 assume !(0 == ~T9_E~0); 93997#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 93996#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 93995#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 93991#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 93990#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 93988#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 93890#L1249-3 assume !(0 == ~E_4~0); 93516#L1254-3 assume !(0 == ~E_5~0); 93145#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 93143#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 93129#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 93127#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 93126#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 93124#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 90049#L1289-3 assume !(0 == ~E_12~0); 89041#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88701#L566-39 assume !(1 == ~m_pc~0); 88702#L566-41 is_master_triggered_~__retres1~0#1 := 0; 93766#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 93765#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 89986#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 89616#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89617#L585-39 assume !(1 == ~t1_pc~0); 90010#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 88920#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88921#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 89970#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 89653#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 89309#L604-39 assume !(1 == ~t2_pc~0); 89311#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 94254#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94252#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 94250#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 94248#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94247#L623-39 assume !(1 == ~t3_pc~0); 88307#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 88308#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89637#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 88756#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 88757#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89576#L642-39 assume 1 == ~t4_pc~0; 89110#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 89111#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94179#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 89823#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 89824#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88677#L661-39 assume !(1 == ~t5_pc~0); 88313#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 88314#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 89746#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 89747#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 89640#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 89641#L680-39 assume 1 == ~t6_pc~0; 88372#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 88373#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 89561#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 88839#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 88840#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 89985#L699-39 assume !(1 == ~t7_pc~0); 89291#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 89007#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 89008#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 89992#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 89915#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 89913#L718-39 assume !(1 == ~t8_pc~0); 89201#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 89200#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 89131#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 89132#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 89464#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 89428#L737-39 assume 1 == ~t9_pc~0; 88819#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 88820#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 89118#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 90025#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 93876#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 93874#L756-39 assume 1 == ~t10_pc~0; 93872#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 93869#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 93867#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 93865#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 93862#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 93860#L775-39 assume !(1 == ~t11_pc~0); 93857#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 93854#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 93852#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 93849#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 93847#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 93845#L794-39 assume 1 == ~t12_pc~0; 93843#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 93840#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 93838#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 93836#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 93834#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93832#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 93830#L1307-5 assume !(1 == ~T1_E~0); 93828#L1312-3 assume !(1 == ~T2_E~0); 93826#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 93824#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 93822#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 93820#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 93818#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 93816#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 93768#L1347-3 assume !(1 == ~T9_E~0); 93767#L1352-3 assume !(1 == ~T10_E~0); 93462#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 93457#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 93311#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 93308#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 93306#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 93304#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 93302#L1387-3 assume !(1 == ~E_5~0); 93300#L1392-3 assume !(1 == ~E_6~0); 93298#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 93295#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 93293#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 93291#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 93289#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 93287#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 93144#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 93141#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 93128#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 93125#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 89333#L1787 assume !(0 == start_simulation_~tmp~3#1); 89334#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 89962#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 88562#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 89387#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 89388#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 88917#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 88918#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 88919#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 88461#L1768-2 [2021-11-13 18:36:31,192 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:31,192 INFO L85 PathProgramCache]: Analyzing trace with hash 1759299380, now seen corresponding path program 1 times [2021-11-13 18:36:31,192 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:31,192 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [916217946] [2021-11-13 18:36:31,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:31,193 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:31,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:31,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:31,254 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:31,254 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [916217946] [2021-11-13 18:36:31,254 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [916217946] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:31,254 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:31,254 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:31,255 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1248736579] [2021-11-13 18:36:31,255 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:31,256 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:31,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:31,259 INFO L85 PathProgramCache]: Analyzing trace with hash -1287724121, now seen corresponding path program 1 times [2021-11-13 18:36:31,259 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:31,260 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2133659062] [2021-11-13 18:36:31,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:31,260 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:31,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:31,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:31,307 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:31,308 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2133659062] [2021-11-13 18:36:31,308 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2133659062] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:31,308 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:31,308 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:31,308 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [379098094] [2021-11-13 18:36:31,309 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:31,310 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:31,310 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:31,311 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:36:31,311 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:36:31,311 INFO L87 Difference]: Start difference. First operand 5994 states and 8584 transitions. cyclomatic complexity: 2592 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:31,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:31,712 INFO L93 Difference]: Finished difference Result 14448 states and 20549 transitions. [2021-11-13 18:36:31,712 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:36:31,713 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14448 states and 20549 transitions. [2021-11-13 18:36:31,808 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 14080 [2021-11-13 18:36:32,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14448 states to 14448 states and 20549 transitions. [2021-11-13 18:36:32,017 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14448 [2021-11-13 18:36:32,059 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14448 [2021-11-13 18:36:32,060 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14448 states and 20549 transitions. [2021-11-13 18:36:32,075 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:32,075 INFO L681 BuchiCegarLoop]: Abstraction has 14448 states and 20549 transitions. [2021-11-13 18:36:32,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14448 states and 20549 transitions. [2021-11-13 18:36:32,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14448 to 11385. [2021-11-13 18:36:32,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11385 states, 11385 states have (on average 1.4263504611330697) internal successors, (16239), 11384 states have internal predecessors, (16239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:32,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11385 states to 11385 states and 16239 transitions. [2021-11-13 18:36:32,300 INFO L704 BuchiCegarLoop]: Abstraction has 11385 states and 16239 transitions. [2021-11-13 18:36:32,300 INFO L587 BuchiCegarLoop]: Abstraction has 11385 states and 16239 transitions. [2021-11-13 18:36:32,300 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-13 18:36:32,300 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11385 states and 16239 transitions. [2021-11-13 18:36:32,359 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 11220 [2021-11-13 18:36:32,360 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:32,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:32,363 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:32,363 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:32,364 INFO L791 eck$LassoCheckResult]: Stem: 109528#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 109529#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 110500#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 109901#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 109680#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 109681#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 109773#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 110117#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 110253#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 110254#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 108957#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 108958#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 110177#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 109572#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 109573#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 109480#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 109481#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 109896#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 109203#L1174 assume !(0 == ~M_E~0); 109204#L1174-2 assume !(0 == ~T1_E~0); 109054#L1179-1 assume !(0 == ~T2_E~0); 108955#L1184-1 assume !(0 == ~T3_E~0); 108956#L1189-1 assume !(0 == ~T4_E~0); 108995#L1194-1 assume !(0 == ~T5_E~0); 109096#L1199-1 assume !(0 == ~T6_E~0); 110050#L1204-1 assume !(0 == ~T7_E~0); 109962#L1209-1 assume !(0 == ~T8_E~0); 109963#L1214-1 assume !(0 == ~T9_E~0); 110406#L1219-1 assume !(0 == ~T10_E~0); 110529#L1224-1 assume !(0 == ~T11_E~0); 109332#L1229-1 assume !(0 == ~T12_E~0); 108883#L1234-1 assume !(0 == ~E_1~0); 108884#L1239-1 assume !(0 == ~E_2~0); 108917#L1244-1 assume !(0 == ~E_3~0); 108918#L1249-1 assume !(0 == ~E_4~0); 109595#L1254-1 assume !(0 == ~E_5~0); 108815#L1259-1 assume !(0 == ~E_6~0); 108774#L1264-1 assume !(0 == ~E_7~0); 108775#L1269-1 assume !(0 == ~E_8~0); 110545#L1274-1 assume !(0 == ~E_9~0); 110440#L1279-1 assume !(0 == ~E_10~0); 108998#L1284-1 assume !(0 == ~E_11~0); 108999#L1289-1 assume !(0 == ~E_12~0); 109650#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 109651#L566 assume !(1 == ~m_pc~0); 110110#L566-2 is_master_triggered_~__retres1~0#1 := 0; 110111#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 109994#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 109995#L1455 assume !(0 != activate_threads_~tmp~1#1); 109230#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 109231#L585 assume !(1 == ~t1_pc~0); 109424#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 109425#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 109928#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 109929#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 110472#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110470#L604 assume !(1 == ~t2_pc~0); 110015#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 110016#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 109511#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 109512#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 110213#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 110214#L623 assume !(1 == ~t3_pc~0); 108755#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 108756#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 109576#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 109577#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 110248#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 108788#L642 assume !(1 == ~t4_pc~0); 108789#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 109251#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 109252#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 108858#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 108859#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 110028#L661 assume !(1 == ~t5_pc~0); 109019#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 109918#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 108978#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 108979#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 110061#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 110062#L680 assume !(1 == ~t6_pc~0); 109458#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 109459#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 109728#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 109729#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 110323#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 110468#L699 assume 1 == ~t7_pc~0; 109874#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 109875#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 109006#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 109007#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 109759#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 109652#L718 assume !(1 == ~t8_pc~0); 109653#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 108993#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 108994#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 109037#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 109038#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 109170#L737 assume 1 == ~t9_pc~0; 110098#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 109317#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 109954#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 109955#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 109497#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 109498#L756 assume 1 == ~t10_pc~0; 110124#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 109750#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 108721#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 108722#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 109296#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 109297#L775 assume !(1 == ~t11_pc~0); 109559#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 109560#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 109167#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 108927#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 108928#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 109115#L794 assume 1 == ~t12_pc~0; 108954#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 108932#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 110204#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 109082#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 109083#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 109579#L1307 assume !(1 == ~M_E~0); 109580#L1307-2 assume !(1 == ~T1_E~0); 109696#L1312-1 assume !(1 == ~T2_E~0); 109611#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 109612#L1322-1 assume !(1 == ~T4_E~0); 109306#L1327-1 assume !(1 == ~T5_E~0); 109307#L1332-1 assume !(1 == ~T6_E~0); 109878#L1337-1 assume !(1 == ~T7_E~0); 109826#L1342-1 assume !(1 == ~T8_E~0); 109827#L1347-1 assume !(1 == ~T9_E~0); 110281#L1352-1 assume !(1 == ~T10_E~0); 110133#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 109476#L1362-1 assume !(1 == ~T12_E~0); 109477#L1367-1 assume !(1 == ~E_1~0); 109097#L1372-1 assume !(1 == ~E_2~0); 109098#L1377-1 assume !(1 == ~E_3~0); 109407#L1382-1 assume !(1 == ~E_4~0); 109408#L1387-1 assume !(1 == ~E_5~0); 110017#L1392-1 assume !(1 == ~E_6~0); 109430#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 109431#L1402-1 assume !(1 == ~E_8~0); 109113#L1407-1 assume !(1 == ~E_9~0); 109114#L1412-1 assume !(1 == ~E_10~0); 110202#L1417-1 assume !(1 == ~E_11~0); 110203#L1422-1 assume !(1 == ~E_12~0); 110465#L1427-1 assume { :end_inline_reset_delta_events } true; 108911#L1768-2 [2021-11-13 18:36:32,365 INFO L793 eck$LassoCheckResult]: Loop: 108911#L1768-2 assume !false; 108912#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 109672#L1149 assume !false; 110085#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 110259#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 109313#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 109214#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 109215#L976 assume !(0 != eval_~tmp~0#1); 110462#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 120011#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 120010#L1174-3 assume !(0 == ~M_E~0); 120009#L1174-5 assume !(0 == ~T1_E~0); 120007#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 120006#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 120005#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 120004#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 120003#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 120002#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 120001#L1209-3 assume !(0 == ~T8_E~0); 120000#L1214-3 assume !(0 == ~T9_E~0); 119996#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 119994#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 119992#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 119990#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 119987#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 119985#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 119984#L1249-3 assume !(0 == ~E_4~0); 119983#L1254-3 assume !(0 == ~E_5~0); 119982#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 119981#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 119979#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 119977#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 119975#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 119973#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 119971#L1289-3 assume !(0 == ~E_12~0); 109495#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 109496#L566-39 assume !(1 == ~m_pc~0); 119952#L566-41 is_master_triggered_~__retres1~0#1 := 0; 109784#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 109486#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 109487#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 110071#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 110072#L585-39 assume !(1 == ~t1_pc~0); 109162#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 109163#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 109238#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 109239#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 110107#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 109763#L604-39 assume !(1 == ~t2_pc~0); 109765#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 110393#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119583#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 109816#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 109817#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 109362#L623-39 assume !(1 == ~t3_pc~0); 109363#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 109842#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 110091#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 109205#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 109206#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 110034#L642-39 assume 1 == ~t4_pc~0; 109565#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 109566#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 109076#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 109077#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 110258#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 109123#L661-39 assume !(1 == ~t5_pc~0); 108762#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 108763#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 110190#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 110191#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 110094#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 110095#L680-39 assume 1 == ~t6_pc~0; 108822#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 108823#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 110018#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 109294#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 109295#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 110407#L699-39 assume 1 == ~t7_pc~0; 109747#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 109461#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 109462#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 110206#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 110342#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 110340#L718-39 assume 1 == ~t8_pc~0; 109656#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 109657#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 109587#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 109588#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 109916#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 109885#L737-39 assume 1 == ~t9_pc~0; 109272#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 109273#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 109574#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 110439#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 110314#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 110249#L756-39 assume !(1 == ~t10_pc~0); 109667#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 109668#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 109409#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 109410#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 109543#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 108869#L775-39 assume !(1 == ~t11_pc~0); 108871#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 109537#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 109538#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 110527#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 109985#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 109594#L794-39 assume !(1 == ~t12_pc~0); 109268#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 109269#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 110149#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 110042#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 108811#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 108812#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 110377#L1307-5 assume !(1 == ~T1_E~0); 110378#L1312-3 assume !(1 == ~T2_E~0); 110544#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 110059#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 110060#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 108943#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 108915#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 108916#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 109687#L1347-3 assume !(1 == ~T9_E~0); 109818#L1352-3 assume !(1 == ~T10_E~0); 109819#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 110321#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 110526#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 110514#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 108753#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 108754#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 109393#L1387-3 assume !(1 == ~E_5~0); 109394#L1392-3 assume !(1 == ~E_6~0); 110161#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 110457#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 109783#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 109031#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 109032#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 109705#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 109706#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 109041#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 109042#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 109957#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 109788#L1787 assume !(0 == start_simulation_~tmp~3#1); 109789#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 110389#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 109011#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 109839#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 109840#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 109374#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 109375#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 109376#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 108911#L1768-2 [2021-11-13 18:36:32,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:32,366 INFO L85 PathProgramCache]: Analyzing trace with hash -1613747565, now seen corresponding path program 1 times [2021-11-13 18:36:32,366 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:32,366 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1657788030] [2021-11-13 18:36:32,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:32,367 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:32,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:32,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:32,422 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:32,422 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1657788030] [2021-11-13 18:36:32,422 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1657788030] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:32,422 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:32,423 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:32,423 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [726973813] [2021-11-13 18:36:32,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:32,424 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:32,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:32,424 INFO L85 PathProgramCache]: Analyzing trace with hash -1765041561, now seen corresponding path program 1 times [2021-11-13 18:36:32,425 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:32,425 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [580199540] [2021-11-13 18:36:32,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:32,425 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:32,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:32,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:32,467 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:32,468 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [580199540] [2021-11-13 18:36:32,468 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [580199540] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:32,468 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:32,468 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:32,468 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [780141194] [2021-11-13 18:36:32,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:32,469 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:32,469 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:32,470 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:36:32,470 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:36:32,470 INFO L87 Difference]: Start difference. First operand 11385 states and 16239 transitions. cyclomatic complexity: 4856 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:33,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:33,097 INFO L93 Difference]: Finished difference Result 27422 states and 38870 transitions. [2021-11-13 18:36:33,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:36:33,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27422 states and 38870 transitions. [2021-11-13 18:36:33,271 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 26850 [2021-11-13 18:36:33,431 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27422 states to 27422 states and 38870 transitions. [2021-11-13 18:36:33,432 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27422 [2021-11-13 18:36:33,453 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27422 [2021-11-13 18:36:33,453 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27422 states and 38870 transitions. [2021-11-13 18:36:33,638 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:33,639 INFO L681 BuchiCegarLoop]: Abstraction has 27422 states and 38870 transitions. [2021-11-13 18:36:33,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27422 states and 38870 transitions. [2021-11-13 18:36:34,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27422 to 21736. [2021-11-13 18:36:34,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21736 states, 21736 states have (on average 1.4212366580787634) internal successors, (30892), 21735 states have internal predecessors, (30892), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:34,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21736 states to 21736 states and 30892 transitions. [2021-11-13 18:36:34,131 INFO L704 BuchiCegarLoop]: Abstraction has 21736 states and 30892 transitions. [2021-11-13 18:36:34,131 INFO L587 BuchiCegarLoop]: Abstraction has 21736 states and 30892 transitions. [2021-11-13 18:36:34,131 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-13 18:36:34,131 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21736 states and 30892 transitions. [2021-11-13 18:36:34,386 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 21568 [2021-11-13 18:36:34,386 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:34,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:34,390 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:34,390 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:34,391 INFO L791 eck$LassoCheckResult]: Stem: 148343#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 148344#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 149372#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 148726#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 148501#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 148502#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 148596#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 148958#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 149102#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 149103#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 147774#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 147775#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 149025#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 148387#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 148388#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 148294#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 148295#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 148721#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 148019#L1174 assume !(0 == ~M_E~0); 148020#L1174-2 assume !(0 == ~T1_E~0); 147871#L1179-1 assume !(0 == ~T2_E~0); 147772#L1184-1 assume !(0 == ~T3_E~0); 147773#L1189-1 assume !(0 == ~T4_E~0); 147812#L1194-1 assume !(0 == ~T5_E~0); 147912#L1199-1 assume !(0 == ~T6_E~0); 148883#L1204-1 assume !(0 == ~T7_E~0); 148789#L1209-1 assume !(0 == ~T8_E~0); 148790#L1214-1 assume !(0 == ~T9_E~0); 149262#L1219-1 assume !(0 == ~T10_E~0); 149405#L1224-1 assume !(0 == ~T11_E~0); 148141#L1229-1 assume !(0 == ~T12_E~0); 147700#L1234-1 assume !(0 == ~E_1~0); 147701#L1239-1 assume !(0 == ~E_2~0); 147734#L1244-1 assume !(0 == ~E_3~0); 147735#L1249-1 assume !(0 == ~E_4~0); 148414#L1254-1 assume !(0 == ~E_5~0); 147632#L1259-1 assume !(0 == ~E_6~0); 147591#L1264-1 assume !(0 == ~E_7~0); 147592#L1269-1 assume !(0 == ~E_8~0); 149424#L1274-1 assume !(0 == ~E_9~0); 149301#L1279-1 assume !(0 == ~E_10~0); 147815#L1284-1 assume !(0 == ~E_11~0); 147816#L1289-1 assume !(0 == ~E_12~0); 148467#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 148468#L566 assume !(1 == ~m_pc~0); 148952#L566-2 is_master_triggered_~__retres1~0#1 := 0; 148953#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 148824#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 148825#L1455 assume !(0 != activate_threads_~tmp~1#1); 148046#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 148047#L585 assume !(1 == ~t1_pc~0); 148233#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 148234#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 148754#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 148755#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 149344#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 149342#L604 assume !(1 == ~t2_pc~0); 148847#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 148848#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 149446#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 149234#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 149054#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 149055#L623 assume !(1 == ~t3_pc~0); 147572#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 147573#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 148391#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 148392#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 149095#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 147605#L642 assume !(1 == ~t4_pc~0); 147606#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 148065#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 148066#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 147675#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 147676#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 148861#L661 assume !(1 == ~t5_pc~0); 147836#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 148743#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 147795#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 147796#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 148895#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 148896#L680 assume !(1 == ~t6_pc~0); 148271#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 148272#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 148545#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 148546#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 149174#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 149339#L699 assume !(1 == ~t7_pc~0); 149340#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 148974#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 147823#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 147824#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 148580#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 148469#L718 assume !(1 == ~t8_pc~0); 148470#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 147810#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 147811#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 147854#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 147855#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 147986#L737 assume 1 == ~t9_pc~0; 148938#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 148126#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 148780#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 148781#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 148311#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 148312#L756 assume 1 == ~t10_pc~0; 148965#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 148571#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 147538#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 147539#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 148106#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 148107#L775 assume !(1 == ~t11_pc~0); 148375#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 148376#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 147983#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 147744#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 147745#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 147931#L794 assume 1 == ~t12_pc~0; 147771#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 147749#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 149048#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 147899#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 147900#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 148394#L1307 assume !(1 == ~M_E~0); 148395#L1307-2 assume !(1 == ~T1_E~0); 148514#L1312-1 assume !(1 == ~T2_E~0); 148428#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 148429#L1322-1 assume !(1 == ~T4_E~0); 148115#L1327-1 assume !(1 == ~T5_E~0); 148116#L1332-1 assume !(1 == ~T6_E~0); 148699#L1337-1 assume !(1 == ~T7_E~0); 148649#L1342-1 assume !(1 == ~T8_E~0); 148650#L1347-1 assume !(1 == ~T9_E~0); 149132#L1352-1 assume !(1 == ~T10_E~0); 148975#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 148290#L1362-1 assume !(1 == ~T12_E~0); 148291#L1367-1 assume !(1 == ~E_1~0); 147913#L1372-1 assume !(1 == ~E_2~0); 147914#L1377-1 assume !(1 == ~E_3~0); 148216#L1382-1 assume !(1 == ~E_4~0); 148217#L1387-1 assume !(1 == ~E_5~0); 148849#L1392-1 assume !(1 == ~E_6~0); 148240#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 148241#L1402-1 assume !(1 == ~E_8~0); 147929#L1407-1 assume !(1 == ~E_9~0); 147930#L1412-1 assume !(1 == ~E_10~0); 149046#L1417-1 assume !(1 == ~E_11~0); 149047#L1422-1 assume !(1 == ~E_12~0); 149337#L1427-1 assume { :end_inline_reset_delta_events } true; 147728#L1768-2 [2021-11-13 18:36:34,391 INFO L793 eck$LassoCheckResult]: Loop: 147728#L1768-2 assume !false; 147729#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 148493#L1149 assume !false; 148921#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 149108#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 148122#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 148024#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 148025#L976 assume !(0 != eval_~tmp~0#1); 149333#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 169267#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 169266#L1174-3 assume !(0 == ~M_E~0); 149064#L1174-5 assume !(0 == ~T1_E~0); 148759#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 148760#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 148976#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 148563#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 147886#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 147887#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 169260#L1209-3 assume !(0 == ~T8_E~0); 169255#L1214-3 assume !(0 == ~T9_E~0); 169254#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 169252#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 149445#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 148340#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 147736#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 147737#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 148189#L1249-3 assume !(0 == ~E_4~0); 148689#L1254-3 assume !(0 == ~E_5~0); 149258#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 148821#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 148822#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 169240#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 169239#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 169238#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 169237#L1289-3 assume !(0 == ~E_12~0); 169188#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 147969#L566-39 assume !(1 == ~m_pc~0); 147970#L566-41 is_master_triggered_~__retres1~0#1 := 0; 168260#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 168259#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 168258#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 168257#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 149284#L585-39 assume !(1 == ~t1_pc~0); 149285#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 169085#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 169083#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 169082#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 169081#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 169080#L604-39 assume 1 == ~t2_pc~0; 169078#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 169079#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 169084#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 169070#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 169068#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 169066#L623-39 assume !(1 == ~t3_pc~0); 166428#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 169063#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 169061#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 169059#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 169057#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 169055#L642-39 assume 1 == ~t4_pc~0; 169052#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 169050#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 169048#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 169046#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 169044#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 169040#L661-39 assume !(1 == ~t5_pc~0); 169038#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 169036#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 168917#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 149200#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 148935#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 148936#L680-39 assume 1 == ~t6_pc~0; 168808#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 168807#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 168806#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 168805#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 168804#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 168803#L699-39 assume !(1 == ~t7_pc~0); 160156#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 168802#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 168801#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 168800#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 168799#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 168798#L718-39 assume 1 == ~t8_pc~0; 168796#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 168795#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 168794#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 168793#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 168792#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 168791#L737-39 assume !(1 == ~t9_pc~0); 148087#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 148086#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 148389#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 149300#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 168786#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 168784#L756-39 assume !(1 == ~t10_pc~0); 148483#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 148484#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 148218#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 148219#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 148359#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 147686#L775-39 assume 1 == ~t11_pc~0; 147687#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 168777#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 168775#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 168774#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 168773#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 168772#L794-39 assume 1 == ~t12_pc~0; 148088#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 148078#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 148995#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 168766#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 168764#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 168762#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 168759#L1307-5 assume !(1 == ~T1_E~0); 168757#L1312-3 assume !(1 == ~T2_E~0); 168756#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 168755#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 168754#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 168753#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 168752#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 168751#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 168750#L1347-3 assume !(1 == ~T9_E~0); 168749#L1352-3 assume !(1 == ~T10_E~0); 149170#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 149171#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 149401#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 149402#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 147570#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 147571#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 148202#L1387-3 assume !(1 == ~E_5~0); 148203#L1392-3 assume !(1 == ~E_6~0); 149008#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 149328#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 148606#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 147848#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 147849#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 148520#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 148521#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 147858#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 147859#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 148784#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 148611#L1787 assume !(0 == start_simulation_~tmp~3#1); 148612#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 149245#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 147828#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 148661#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 148662#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 148183#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 148184#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 148185#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 147728#L1768-2 [2021-11-13 18:36:34,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:34,392 INFO L85 PathProgramCache]: Analyzing trace with hash 205978354, now seen corresponding path program 1 times [2021-11-13 18:36:34,393 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:34,393 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2103603131] [2021-11-13 18:36:34,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:34,402 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:34,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:34,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:34,476 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:34,476 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2103603131] [2021-11-13 18:36:34,476 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2103603131] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:34,476 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:34,476 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:34,477 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [959442914] [2021-11-13 18:36:34,477 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:34,477 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:34,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:34,478 INFO L85 PathProgramCache]: Analyzing trace with hash -227567286, now seen corresponding path program 1 times [2021-11-13 18:36:34,478 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:34,479 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [539727551] [2021-11-13 18:36:34,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:34,479 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:34,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:34,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:34,542 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:34,542 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [539727551] [2021-11-13 18:36:34,542 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [539727551] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:34,542 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:34,543 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:34,543 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1639140809] [2021-11-13 18:36:34,543 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:34,543 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:34,544 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:34,544 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:36:34,545 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:36:34,545 INFO L87 Difference]: Start difference. First operand 21736 states and 30892 transitions. cyclomatic complexity: 9158 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:35,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:35,210 INFO L93 Difference]: Finished difference Result 52303 states and 73893 transitions. [2021-11-13 18:36:35,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:36:35,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52303 states and 73893 transitions. [2021-11-13 18:36:35,693 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 51324 [2021-11-13 18:36:36,043 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52303 states to 52303 states and 73893 transitions. [2021-11-13 18:36:36,044 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52303 [2021-11-13 18:36:36,078 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52303 [2021-11-13 18:36:36,078 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52303 states and 73893 transitions. [2021-11-13 18:36:36,129 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:36,130 INFO L681 BuchiCegarLoop]: Abstraction has 52303 states and 73893 transitions. [2021-11-13 18:36:36,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52303 states and 73893 transitions. [2021-11-13 18:36:36,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52303 to 41583. [2021-11-13 18:36:36,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41583 states, 41583 states have (on average 1.4165644614385686) internal successors, (58905), 41582 states have internal predecessors, (58905), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:37,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41583 states to 41583 states and 58905 transitions. [2021-11-13 18:36:37,109 INFO L704 BuchiCegarLoop]: Abstraction has 41583 states and 58905 transitions. [2021-11-13 18:36:37,109 INFO L587 BuchiCegarLoop]: Abstraction has 41583 states and 58905 transitions. [2021-11-13 18:36:37,109 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-13 18:36:37,110 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41583 states and 58905 transitions. [2021-11-13 18:36:37,539 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 41408 [2021-11-13 18:36:37,544 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:37,544 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:37,550 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:37,550 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:37,550 INFO L791 eck$LassoCheckResult]: Stem: 222389#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 222390#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 223452#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 222790#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 222551#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 222552#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 222652#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 223022#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 223175#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 223176#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 221822#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 221823#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 223093#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 222436#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 222437#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 222341#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 222342#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 222786#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 222065#L1174 assume !(0 == ~M_E~0); 222066#L1174-2 assume !(0 == ~T1_E~0); 221918#L1179-1 assume !(0 == ~T2_E~0); 221820#L1184-1 assume !(0 == ~T3_E~0); 221821#L1189-1 assume !(0 == ~T4_E~0); 221859#L1194-1 assume !(0 == ~T5_E~0); 221960#L1199-1 assume !(0 == ~T6_E~0); 222948#L1204-1 assume !(0 == ~T7_E~0); 222850#L1209-1 assume !(0 == ~T8_E~0); 222851#L1214-1 assume !(0 == ~T9_E~0); 223342#L1219-1 assume !(0 == ~T10_E~0); 223497#L1224-1 assume !(0 == ~T11_E~0); 222189#L1229-1 assume !(0 == ~T12_E~0); 221747#L1234-1 assume !(0 == ~E_1~0); 221748#L1239-1 assume !(0 == ~E_2~0); 221780#L1244-1 assume !(0 == ~E_3~0); 221781#L1249-1 assume !(0 == ~E_4~0); 222462#L1254-1 assume !(0 == ~E_5~0); 221681#L1259-1 assume !(0 == ~E_6~0); 221640#L1264-1 assume !(0 == ~E_7~0); 221641#L1269-1 assume !(0 == ~E_8~0); 223523#L1274-1 assume !(0 == ~E_9~0); 223383#L1279-1 assume !(0 == ~E_10~0); 221862#L1284-1 assume !(0 == ~E_11~0); 221863#L1289-1 assume !(0 == ~E_12~0); 222518#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 222519#L566 assume !(1 == ~m_pc~0); 223017#L566-2 is_master_triggered_~__retres1~0#1 := 0; 223018#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 222884#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 222885#L1455 assume !(0 != activate_threads_~tmp~1#1); 222092#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 222093#L585 assume !(1 == ~t1_pc~0); 222284#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 222285#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 222817#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 222818#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 223427#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 223423#L604 assume !(1 == ~t2_pc~0); 222905#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 222906#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 223551#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 223308#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 223124#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 223125#L623 assume !(1 == ~t3_pc~0); 221621#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 221622#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 222441#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 222442#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 223170#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 221654#L642 assume !(1 == ~t4_pc~0); 221655#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 222109#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 222110#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 221722#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 221723#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 222921#L661 assume !(1 == ~t5_pc~0); 221883#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 222809#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 221842#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 221843#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 222958#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 222959#L680 assume !(1 == ~t6_pc~0); 222321#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 222322#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 222597#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 222598#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 223248#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 223420#L699 assume !(1 == ~t7_pc~0); 223421#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 223043#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 221870#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 221871#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 222636#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 222520#L718 assume !(1 == ~t8_pc~0); 222521#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 221857#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 221858#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 221899#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 221900#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 222031#L737 assume !(1 == ~t9_pc~0); 222173#L737-2 is_transmit9_triggered_~__retres1~9#1 := 0; 222174#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 222843#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 222844#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 222359#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 222360#L756 assume 1 == ~t10_pc~0; 223034#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 222625#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 221587#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 221588#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 222156#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 222157#L775 assume !(1 == ~t11_pc~0); 222424#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 222425#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 222025#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 221792#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 221793#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 221977#L794 assume 1 == ~t12_pc~0; 221818#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 221797#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 223120#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 221944#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 221945#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 222444#L1307 assume !(1 == ~M_E~0); 222445#L1307-2 assume !(1 == ~T1_E~0); 222566#L1312-1 assume !(1 == ~T2_E~0); 222477#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 222478#L1322-1 assume !(1 == ~T4_E~0); 222165#L1327-1 assume !(1 == ~T5_E~0); 222166#L1332-1 assume !(1 == ~T6_E~0); 222763#L1337-1 assume !(1 == ~T7_E~0); 222710#L1342-1 assume !(1 == ~T8_E~0); 222711#L1347-1 assume !(1 == ~T9_E~0); 223202#L1352-1 assume !(1 == ~T10_E~0); 223044#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 222339#L1362-1 assume !(1 == ~T12_E~0); 222340#L1367-1 assume !(1 == ~E_1~0); 221961#L1372-1 assume !(1 == ~E_2~0); 221962#L1377-1 assume !(1 == ~E_3~0); 222267#L1382-1 assume !(1 == ~E_4~0); 222268#L1387-1 assume !(1 == ~E_5~0); 222907#L1392-1 assume !(1 == ~E_6~0); 222288#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 222289#L1402-1 assume !(1 == ~E_8~0); 221971#L1407-1 assume !(1 == ~E_9~0); 221972#L1412-1 assume !(1 == ~E_10~0); 223118#L1417-1 assume !(1 == ~E_11~0); 223119#L1422-1 assume !(1 == ~E_12~0); 223414#L1427-1 assume { :end_inline_reset_delta_events } true; 223415#L1768-2 [2021-11-13 18:36:37,551 INFO L793 eck$LassoCheckResult]: Loop: 223415#L1768-2 assume !false; 261202#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 261198#L1149 assume !false; 261196#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 223355#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 222171#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 222070#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 222071#L976 assume !(0 != eval_~tmp~0#1); 223410#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 223435#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 223141#L1174-3 assume !(0 == ~M_E~0); 223135#L1174-5 assume !(0 == ~T1_E~0); 222822#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 222823#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 223045#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 222617#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 221933#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 221934#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 222180#L1209-3 assume !(0 == ~T8_E~0); 221608#L1214-3 assume !(0 == ~T9_E~0); 221609#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 222372#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 222373#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 222391#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 221784#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 221785#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 222239#L1249-3 assume !(0 == ~E_4~0); 222752#L1254-3 assume !(0 == ~E_5~0); 223337#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 222882#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 221790#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 221791#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 223381#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 222370#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 222371#L1289-3 assume !(0 == ~E_12~0); 222358#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 222011#L566-39 assume !(1 == ~m_pc~0); 222012#L566-41 is_master_triggered_~__retres1~0#1 := 0; 222663#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 222349#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 222350#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 222972#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 222973#L585-39 assume !(1 == ~t1_pc~0); 223363#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 261554#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 261553#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 261552#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 261551#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 261549#L604-39 assume 1 == ~t2_pc~0; 261547#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 261548#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 261555#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 261538#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 261536#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 222221#L623-39 assume !(1 == ~t3_pc~0); 222222#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 222996#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 222997#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 222067#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 222068#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 222928#L642-39 assume !(1 == ~t4_pc~0); 222432#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 222431#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 221940#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 221941#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 223180#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 221987#L661-39 assume !(1 == ~t5_pc~0); 221628#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 221629#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 223108#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 223109#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 223000#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 223001#L680-39 assume !(1 == ~t6_pc~0); 221690#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 221689#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 223272#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 261403#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 261401#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 223345#L699-39 assume !(1 == ~t7_pc~0); 223128#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 222324#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 222325#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 223121#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 223269#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 223266#L718-39 assume !(1 == ~t8_pc~0); 222526#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 222525#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 262075#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 262074#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 262073#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 262072#L737-39 assume !(1 == ~t9_pc~0); 260471#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 262069#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 262067#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 262065#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 262064#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 262062#L756-39 assume 1 == ~t10_pc~0; 262058#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 223480#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 222269#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 222270#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 222407#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 221733#L775-39 assume !(1 == ~t11_pc~0); 221735#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 222401#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 222402#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 223494#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 222875#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 222459#L794-39 assume 1 == ~t12_pc~0; 222130#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 222124#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 223060#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 222935#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 221677#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 221678#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 223371#L1307-5 assume !(1 == ~T1_E~0); 261326#L1312-3 assume !(1 == ~T2_E~0); 261324#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 261322#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 261320#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 261318#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 261316#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 261313#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 261311#L1347-3 assume !(1 == ~T9_E~0); 261309#L1352-3 assume !(1 == ~T10_E~0); 261307#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 261305#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 261302#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 261300#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 261298#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 261296#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 261294#L1387-3 assume !(1 == ~E_5~0); 261292#L1392-3 assume !(1 == ~E_6~0); 261290#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 261287#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 261285#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 261283#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 261281#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 261279#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 261278#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 261275#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 261262#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 261260#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 261258#L1787 assume !(0 == start_simulation_~tmp~3#1); 261255#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 261230#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 261222#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 261221#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 261218#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 261216#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 261214#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 261212#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 223415#L1768-2 [2021-11-13 18:36:37,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:37,552 INFO L85 PathProgramCache]: Analyzing trace with hash -1524358703, now seen corresponding path program 1 times [2021-11-13 18:36:37,552 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:37,552 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [234537941] [2021-11-13 18:36:37,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:37,552 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:37,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:37,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:37,619 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:37,620 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [234537941] [2021-11-13 18:36:37,621 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [234537941] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:37,621 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:37,621 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:37,621 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [682399367] [2021-11-13 18:36:37,622 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:37,624 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:37,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:37,625 INFO L85 PathProgramCache]: Analyzing trace with hash -737443737, now seen corresponding path program 1 times [2021-11-13 18:36:37,625 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:37,626 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [268559297] [2021-11-13 18:36:37,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:37,627 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:37,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:37,671 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:37,672 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:37,672 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [268559297] [2021-11-13 18:36:37,672 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [268559297] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:37,672 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:37,672 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:37,673 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1160787676] [2021-11-13 18:36:37,673 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:37,673 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:37,674 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:37,674 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:36:37,674 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:36:37,675 INFO L87 Difference]: Start difference. First operand 41583 states and 58905 transitions. cyclomatic complexity: 17324 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:38,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:38,661 INFO L93 Difference]: Finished difference Result 99950 states and 140774 transitions. [2021-11-13 18:36:38,662 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:36:38,662 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99950 states and 140774 transitions. [2021-11-13 18:36:39,427 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 98160 [2021-11-13 18:36:40,014 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99950 states to 99950 states and 140774 transitions. [2021-11-13 18:36:40,014 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99950 [2021-11-13 18:36:40,065 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99950 [2021-11-13 18:36:40,065 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99950 states and 140774 transitions. [2021-11-13 18:36:40,237 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:40,237 INFO L681 BuchiCegarLoop]: Abstraction has 99950 states and 140774 transitions. [2021-11-13 18:36:40,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99950 states and 140774 transitions. [2021-11-13 18:36:41,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99950 to 79582. [2021-11-13 18:36:41,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 79582 states, 79582 states have (on average 1.4122540272926039) internal successors, (112390), 79581 states have internal predecessors, (112390), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:41,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79582 states to 79582 states and 112390 transitions. [2021-11-13 18:36:41,854 INFO L704 BuchiCegarLoop]: Abstraction has 79582 states and 112390 transitions. [2021-11-13 18:36:41,854 INFO L587 BuchiCegarLoop]: Abstraction has 79582 states and 112390 transitions. [2021-11-13 18:36:41,854 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-13 18:36:41,854 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79582 states and 112390 transitions. [2021-11-13 18:36:42,099 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 79392 [2021-11-13 18:36:42,100 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:42,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:42,110 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:42,110 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:42,111 INFO L791 eck$LassoCheckResult]: Stem: 363933#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 363934#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 365034#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 364336#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 364096#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 364097#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 364197#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 364574#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 364732#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 364733#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 363365#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 363366#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 364652#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 363980#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 363981#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 363885#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 363886#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 364331#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 363610#L1174 assume !(0 == ~M_E~0); 363611#L1174-2 assume !(0 == ~T1_E~0); 363460#L1179-1 assume !(0 == ~T2_E~0); 363363#L1184-1 assume !(0 == ~T3_E~0); 363364#L1189-1 assume !(0 == ~T4_E~0); 363402#L1194-1 assume !(0 == ~T5_E~0); 363501#L1199-1 assume !(0 == ~T6_E~0); 364498#L1204-1 assume !(0 == ~T7_E~0); 364407#L1209-1 assume !(0 == ~T8_E~0); 364408#L1214-1 assume !(0 == ~T9_E~0); 364910#L1219-1 assume !(0 == ~T10_E~0); 365084#L1224-1 assume !(0 == ~T11_E~0); 363733#L1229-1 assume !(0 == ~T12_E~0); 363290#L1234-1 assume !(0 == ~E_1~0); 363291#L1239-1 assume !(0 == ~E_2~0); 363323#L1244-1 assume !(0 == ~E_3~0); 363324#L1249-1 assume !(0 == ~E_4~0); 364004#L1254-1 assume !(0 == ~E_5~0); 363224#L1259-1 assume !(0 == ~E_6~0); 363183#L1264-1 assume !(0 == ~E_7~0); 363184#L1269-1 assume !(0 == ~E_8~0); 365113#L1274-1 assume !(0 == ~E_9~0); 364959#L1279-1 assume !(0 == ~E_10~0); 363405#L1284-1 assume !(0 == ~E_11~0); 363406#L1289-1 assume !(0 == ~E_12~0); 364065#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 364066#L566 assume !(1 == ~m_pc~0); 364569#L566-2 is_master_triggered_~__retres1~0#1 := 0; 364570#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 364439#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 364440#L1455 assume !(0 != activate_threads_~tmp~1#1); 363636#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 363637#L585 assume !(1 == ~t1_pc~0); 363827#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 363828#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 364367#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 364368#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 365006#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 365003#L604 assume !(1 == ~t2_pc~0); 364462#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 364463#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 365139#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 364874#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 364682#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 364683#L623 assume !(1 == ~t3_pc~0); 363164#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 363165#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 363984#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 363985#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 364724#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 363197#L642 assume !(1 == ~t4_pc~0); 363198#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 363655#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 363656#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 363265#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 363266#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 364475#L661 assume !(1 == ~t5_pc~0); 363426#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 364356#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 363385#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 363386#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 364509#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 364510#L680 assume !(1 == ~t6_pc~0); 363865#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 363866#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 364143#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 364144#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 364813#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 365000#L699 assume !(1 == ~t7_pc~0); 365001#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 364595#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 363413#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 363414#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 364182#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 364067#L718 assume !(1 == ~t8_pc~0); 364068#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 363400#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 363401#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 363442#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 363443#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 363576#L737 assume !(1 == ~t9_pc~0); 363717#L737-2 is_transmit9_triggered_~__retres1~9#1 := 0; 363718#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 364397#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 364398#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 363904#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 363905#L756 assume !(1 == ~t10_pc~0); 364170#L756-2 is_transmit10_triggered_~__retres1~10#1 := 0; 364171#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 363130#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 363131#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 363699#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 363700#L775 assume !(1 == ~t11_pc~0); 363968#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 363969#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 363570#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 363335#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 363336#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 363520#L794 assume 1 == ~t12_pc~0; 363361#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 363340#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 364677#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 363486#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 363487#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 363987#L1307 assume !(1 == ~M_E~0); 363988#L1307-2 assume !(1 == ~T1_E~0); 364111#L1312-1 assume !(1 == ~T2_E~0); 364020#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 364021#L1322-1 assume !(1 == ~T4_E~0); 363708#L1327-1 assume !(1 == ~T5_E~0); 363709#L1332-1 assume !(1 == ~T6_E~0); 364304#L1337-1 assume !(1 == ~T7_E~0); 364255#L1342-1 assume !(1 == ~T8_E~0); 364256#L1347-1 assume !(1 == ~T9_E~0); 364770#L1352-1 assume !(1 == ~T10_E~0); 364596#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 363883#L1362-1 assume !(1 == ~T12_E~0); 363884#L1367-1 assume !(1 == ~E_1~0); 363502#L1372-1 assume !(1 == ~E_2~0); 363503#L1377-1 assume !(1 == ~E_3~0); 363810#L1382-1 assume !(1 == ~E_4~0); 363811#L1387-1 assume !(1 == ~E_5~0); 364464#L1392-1 assume !(1 == ~E_6~0); 363832#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 363833#L1402-1 assume !(1 == ~E_8~0); 363514#L1407-1 assume !(1 == ~E_9~0); 363515#L1412-1 assume !(1 == ~E_10~0); 364675#L1417-1 assume !(1 == ~E_11~0); 364676#L1422-1 assume !(1 == ~E_12~0); 364995#L1427-1 assume { :end_inline_reset_delta_events } true; 364996#L1768-2 [2021-11-13 18:36:42,111 INFO L793 eck$LassoCheckResult]: Loop: 364996#L1768-2 assume !false; 437049#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 437044#L1149 assume !false; 437042#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 437007#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 436999#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 436996#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 436992#L976 assume !(0 != eval_~tmp~0#1); 436993#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 442705#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 442704#L1174-3 assume !(0 == ~M_E~0); 442703#L1174-5 assume !(0 == ~T1_E~0); 442702#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 442701#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 442700#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 364163#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 363475#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 363476#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 363724#L1209-3 assume !(0 == ~T8_E~0); 363151#L1214-3 assume !(0 == ~T9_E~0); 363152#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 363916#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 363917#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 363935#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 363327#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 363328#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 442689#L1249-3 assume !(0 == ~E_4~0); 442687#L1254-3 assume !(0 == ~E_5~0); 442685#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 442683#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 442681#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 365062#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 364957#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 363914#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 363915#L1289-3 assume !(0 == ~E_12~0); 363902#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 363903#L566-39 assume !(1 == ~m_pc~0); 442669#L566-41 is_master_triggered_~__retres1~0#1 := 0; 442668#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 442667#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 442666#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 442659#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 442657#L585-39 assume !(1 == ~t1_pc~0); 440391#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 442656#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 442655#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 442654#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 364565#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 364186#L604-39 assume !(1 == ~t2_pc~0); 364188#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 364893#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 442664#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 442631#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 442628#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 442627#L623-39 assume !(1 == ~t3_pc~0); 435526#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 442626#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 442617#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 442616#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 442615#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 442612#L642-39 assume 1 == ~t4_pc~0; 442608#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 442605#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 442602#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 364741#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 364742#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 442565#L661-39 assume !(1 == ~t5_pc~0); 363171#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 363172#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 364665#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 364666#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 364550#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 364551#L680-39 assume !(1 == ~t6_pc~0); 363233#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 363232#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 364465#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 363697#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 363698#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 437236#L699-39 assume !(1 == ~t7_pc~0); 437234#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 437231#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 437229#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 437227#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 437225#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 437223#L718-39 assume 1 == ~t8_pc~0; 437220#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 437218#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 437216#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 437213#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 437211#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 437209#L737-39 assume !(1 == ~t9_pc~0); 434374#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 437206#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 437204#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 437201#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 437199#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 437197#L756-39 assume !(1 == ~t10_pc~0); 429912#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 437194#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 437192#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 437190#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 437188#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 437186#L775-39 assume !(1 == ~t11_pc~0); 437184#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 437181#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 437179#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 437177#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 437175#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 437173#L794-39 assume !(1 == ~t12_pc~0); 437170#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 437168#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 437166#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 437164#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 437162#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 437160#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 437158#L1307-5 assume !(1 == ~T1_E~0); 437156#L1312-3 assume !(1 == ~T2_E~0); 437154#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 437152#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 437150#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 437148#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 437146#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 437144#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 437142#L1347-3 assume !(1 == ~T9_E~0); 437141#L1352-3 assume !(1 == ~T10_E~0); 437140#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 437139#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 437138#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 437137#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 437136#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 437135#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 437134#L1387-3 assume !(1 == ~E_5~0); 437133#L1392-3 assume !(1 == ~E_6~0); 437132#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 437131#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 437130#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 437128#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 437126#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 437124#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 437122#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 437117#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 437103#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 437101#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 437098#L1787 assume !(0 == start_simulation_~tmp~3#1); 437095#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 437081#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 437074#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 437072#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 437070#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 437068#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 437066#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 437064#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 364996#L1768-2 [2021-11-13 18:36:42,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:42,112 INFO L85 PathProgramCache]: Analyzing trace with hash 1495505904, now seen corresponding path program 1 times [2021-11-13 18:36:42,113 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:42,113 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1762297911] [2021-11-13 18:36:42,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:42,113 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:42,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:42,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:42,172 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:42,172 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1762297911] [2021-11-13 18:36:42,172 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1762297911] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:42,172 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:42,172 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 18:36:42,173 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1714319582] [2021-11-13 18:36:42,173 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:42,173 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:42,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:42,174 INFO L85 PathProgramCache]: Analyzing trace with hash -1556235452, now seen corresponding path program 1 times [2021-11-13 18:36:42,174 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:42,174 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1988135699] [2021-11-13 18:36:42,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:42,175 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:42,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:42,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:42,214 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:42,214 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1988135699] [2021-11-13 18:36:42,214 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1988135699] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:42,214 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:42,214 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:42,215 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1174979342] [2021-11-13 18:36:42,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:42,215 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:42,215 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:42,216 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-13 18:36:42,216 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-13 18:36:42,216 INFO L87 Difference]: Start difference. First operand 79582 states and 112390 transitions. cyclomatic complexity: 32810 Second operand has 5 states, 5 states have (on average 29.6) internal successors, (148), 5 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:43,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:43,607 INFO L93 Difference]: Finished difference Result 177829 states and 253375 transitions. [2021-11-13 18:36:43,608 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-13 18:36:43,611 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 177829 states and 253375 transitions. [2021-11-13 18:36:44,843 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 177504 [2021-11-13 18:36:45,425 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 177829 states to 177829 states and 253375 transitions. [2021-11-13 18:36:45,425 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 177829 [2021-11-13 18:36:45,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 177829 [2021-11-13 18:36:45,518 INFO L73 IsDeterministic]: Start isDeterministic. Operand 177829 states and 253375 transitions. [2021-11-13 18:36:45,589 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:45,590 INFO L681 BuchiCegarLoop]: Abstraction has 177829 states and 253375 transitions. [2021-11-13 18:36:46,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177829 states and 253375 transitions. [2021-11-13 18:36:47,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177829 to 81697. [2021-11-13 18:36:47,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81697 states, 81697 states have (on average 1.4015814534193423) internal successors, (114505), 81696 states have internal predecessors, (114505), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:47,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81697 states to 81697 states and 114505 transitions. [2021-11-13 18:36:47,479 INFO L704 BuchiCegarLoop]: Abstraction has 81697 states and 114505 transitions. [2021-11-13 18:36:47,479 INFO L587 BuchiCegarLoop]: Abstraction has 81697 states and 114505 transitions. [2021-11-13 18:36:47,479 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-13 18:36:47,480 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81697 states and 114505 transitions. [2021-11-13 18:36:47,760 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 81504 [2021-11-13 18:36:47,760 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:47,760 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:47,770 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:47,770 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:47,771 INFO L791 eck$LassoCheckResult]: Stem: 621367#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 621368#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 622443#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 621764#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 621530#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 621531#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 621628#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 621998#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 622150#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 622151#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 620790#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 620791#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 622067#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 621412#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 621413#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 621319#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 621320#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 621759#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 621035#L1174 assume !(0 == ~M_E~0); 621036#L1174-2 assume !(0 == ~T1_E~0); 620885#L1179-1 assume !(0 == ~T2_E~0); 620788#L1184-1 assume !(0 == ~T3_E~0); 620789#L1189-1 assume !(0 == ~T4_E~0); 620827#L1194-1 assume !(0 == ~T5_E~0); 620927#L1199-1 assume !(0 == ~T6_E~0); 621922#L1204-1 assume !(0 == ~T7_E~0); 621831#L1209-1 assume !(0 == ~T8_E~0); 621832#L1214-1 assume !(0 == ~T9_E~0); 622318#L1219-1 assume !(0 == ~T10_E~0); 622492#L1224-1 assume !(0 == ~T11_E~0); 621163#L1229-1 assume !(0 == ~T12_E~0); 620717#L1234-1 assume !(0 == ~E_1~0); 620718#L1239-1 assume !(0 == ~E_2~0); 620750#L1244-1 assume !(0 == ~E_3~0); 620751#L1249-1 assume !(0 == ~E_4~0); 621439#L1254-1 assume !(0 == ~E_5~0); 620648#L1259-1 assume !(0 == ~E_6~0); 620607#L1264-1 assume !(0 == ~E_7~0); 620608#L1269-1 assume !(0 == ~E_8~0); 622516#L1274-1 assume !(0 == ~E_9~0); 622372#L1279-1 assume !(0 == ~E_10~0); 620830#L1284-1 assume !(0 == ~E_11~0); 620831#L1289-1 assume !(0 == ~E_12~0); 621497#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 621498#L566 assume !(1 == ~m_pc~0); 621992#L566-2 is_master_triggered_~__retres1~0#1 := 0; 621993#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 621865#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 621866#L1455 assume !(0 != activate_threads_~tmp~1#1); 621061#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 621062#L585 assume !(1 == ~t1_pc~0); 621256#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 621257#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 621792#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 621793#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 622419#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 622415#L604 assume !(1 == ~t2_pc~0); 621885#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 621886#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 622392#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 622287#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 622101#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 622102#L623 assume !(1 == ~t3_pc~0); 620588#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 620589#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 621417#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 621418#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 622143#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 620621#L642 assume !(1 == ~t4_pc~0); 620622#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 621081#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 621082#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 620691#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 620692#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 621899#L661 assume !(1 == ~t5_pc~0); 620851#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 621781#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 620810#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 620811#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 621935#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 621936#L680 assume !(1 == ~t6_pc~0); 621295#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 621296#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 621577#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 621578#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 622226#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 622412#L699 assume !(1 == ~t7_pc~0); 622413#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 622014#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 620838#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 620839#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 621613#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 621499#L718 assume !(1 == ~t8_pc~0); 621500#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 620825#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 620826#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 620869#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 620870#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 621002#L737 assume !(1 == ~t9_pc~0); 621147#L737-2 is_transmit9_triggered_~__retres1~9#1 := 0; 621148#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 621821#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 621822#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 621336#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 621337#L756 assume !(1 == ~t10_pc~0); 621602#L756-2 is_transmit10_triggered_~__retres1~10#1 := 0; 621603#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 620554#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 620555#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 621128#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 621129#L775 assume !(1 == ~t11_pc~0); 621400#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 621401#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 622329#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 620760#L1543 assume !(0 != activate_threads_~tmp___10~0#1); 620761#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 620946#L794 assume 1 == ~t12_pc~0; 620787#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 620765#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 622097#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 620913#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 620914#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 621420#L1307 assume !(1 == ~M_E~0); 621421#L1307-2 assume !(1 == ~T1_E~0); 621544#L1312-1 assume !(1 == ~T2_E~0); 621456#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 621457#L1322-1 assume !(1 == ~T4_E~0); 621137#L1327-1 assume !(1 == ~T5_E~0); 621138#L1332-1 assume !(1 == ~T6_E~0); 621736#L1337-1 assume !(1 == ~T7_E~0); 621685#L1342-1 assume !(1 == ~T8_E~0); 621686#L1347-1 assume !(1 == ~T9_E~0); 622180#L1352-1 assume !(1 == ~T10_E~0); 622015#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 621315#L1362-1 assume !(1 == ~T12_E~0); 621316#L1367-1 assume !(1 == ~E_1~0); 620928#L1372-1 assume !(1 == ~E_2~0); 620929#L1377-1 assume !(1 == ~E_3~0); 621239#L1382-1 assume !(1 == ~E_4~0); 621240#L1387-1 assume !(1 == ~E_5~0); 621887#L1392-1 assume !(1 == ~E_6~0); 621263#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 621264#L1402-1 assume !(1 == ~E_8~0); 620944#L1407-1 assume !(1 == ~E_9~0); 620945#L1412-1 assume !(1 == ~E_10~0); 622095#L1417-1 assume !(1 == ~E_11~0); 622096#L1422-1 assume !(1 == ~E_12~0); 622410#L1427-1 assume { :end_inline_reset_delta_events } true; 620744#L1768-2 [2021-11-13 18:36:47,772 INFO L793 eck$LassoCheckResult]: Loop: 620744#L1768-2 assume !false; 620745#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 621521#L1149 assume !false; 621959#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 622158#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 621144#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 621040#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 621041#L976 assume !(0 != eval_~tmp~0#1); 622408#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 622428#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 622114#L1174-3 assume !(0 == ~M_E~0); 622107#L1174-5 assume !(0 == ~T1_E~0); 621797#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 621798#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 622016#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 621596#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 620903#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 620904#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 621151#L1209-3 assume !(0 == ~T8_E~0); 620575#L1214-3 assume !(0 == ~T9_E~0); 620576#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 621348#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 621349#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 621365#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 620752#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 620753#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 702228#L1249-3 assume !(0 == ~E_4~0); 622442#L1254-3 assume !(0 == ~E_5~0); 622314#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 621862#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 620758#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 620759#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 622370#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 621346#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 621347#L1289-3 assume !(0 == ~E_12~0); 702104#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 702101#L566-39 assume !(1 == ~m_pc~0); 702095#L566-41 is_master_triggered_~__retres1~0#1 := 0; 702091#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 702058#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 622321#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 621945#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 621946#L585-39 assume !(1 == ~t1_pc~0); 699036#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 701803#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 621070#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 621071#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 621986#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 621620#L604-39 assume 1 == ~t2_pc~0; 621621#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 621751#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 701799#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 701743#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 621676#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 622123#L623-39 assume !(1 == ~t3_pc~0); 701027#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 701025#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 701023#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 701021#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 701018#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 701016#L642-39 assume !(1 == ~t4_pc~0); 701014#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 701011#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 701009#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 700840#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 700839#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 700837#L661-39 assume !(1 == ~t5_pc~0); 700836#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 700835#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 700833#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 700832#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 700831#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 700830#L680-39 assume 1 == ~t6_pc~0; 700828#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 700827#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 700826#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 700825#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 700824#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 700823#L699-39 assume !(1 == ~t7_pc~0); 698593#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 700822#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 700821#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 700819#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 700818#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 700817#L718-39 assume 1 == ~t8_pc~0; 700778#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 700776#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 700775#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 700772#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 700771#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 700770#L737-39 assume !(1 == ~t9_pc~0); 682391#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 700766#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 700764#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 700762#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 700760#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 700758#L756-39 assume !(1 == ~t10_pc~0); 666244#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 700754#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 699666#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 621382#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 621383#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 620703#L775-39 assume !(1 == ~t11_pc~0); 620705#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 699574#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 622542#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 622490#L1543-39 assume !(0 != activate_threads_~tmp___10~0#1); 621855#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 621438#L794-39 assume 1 == ~t12_pc~0; 621105#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 621095#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 622030#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 621913#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 620644#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 620645#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 622285#L1307-5 assume !(1 == ~T1_E~0); 622286#L1312-3 assume !(1 == ~T2_E~0); 622514#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 621933#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 621934#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 620776#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 620748#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 620749#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 621535#L1347-3 assume !(1 == ~T9_E~0); 621673#L1352-3 assume !(1 == ~T10_E~0); 621674#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 622222#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 622489#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 622470#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 620583#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 620584#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 621225#L1387-3 assume !(1 == ~E_5~0); 621226#L1392-3 assume !(1 == ~E_6~0); 622045#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 622399#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 621638#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 621639#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 699340#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 699339#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 699328#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 699325#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 699313#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 699309#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 621643#L1787 assume !(0 == start_simulation_~tmp~3#1); 621644#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 622300#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 620843#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 621699#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 621700#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 621206#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 621207#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 621208#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 620744#L1768-2 [2021-11-13 18:36:47,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:47,773 INFO L85 PathProgramCache]: Analyzing trace with hash -748477394, now seen corresponding path program 1 times [2021-11-13 18:36:47,773 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:47,773 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970481335] [2021-11-13 18:36:47,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:47,774 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:47,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:47,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:47,830 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:47,830 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1970481335] [2021-11-13 18:36:47,830 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1970481335] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:47,830 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:47,831 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:47,831 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1369961139] [2021-11-13 18:36:47,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:47,832 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:47,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:47,832 INFO L85 PathProgramCache]: Analyzing trace with hash -1656161402, now seen corresponding path program 1 times [2021-11-13 18:36:47,832 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:47,833 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1246067534] [2021-11-13 18:36:47,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:47,833 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:47,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:47,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:47,877 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:47,878 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1246067534] [2021-11-13 18:36:47,878 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1246067534] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:47,878 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:47,878 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:47,878 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [431937762] [2021-11-13 18:36:47,879 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:47,879 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:47,879 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:47,880 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:36:47,880 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:36:47,880 INFO L87 Difference]: Start difference. First operand 81697 states and 114505 transitions. cyclomatic complexity: 32810 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:49,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:49,726 INFO L93 Difference]: Finished difference Result 204016 states and 283878 transitions. [2021-11-13 18:36:49,726 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:36:49,726 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 204016 states and 283878 transitions. [2021-11-13 18:36:50,680 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 200512 [2021-11-13 18:36:52,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 204016 states to 204016 states and 283878 transitions. [2021-11-13 18:36:52,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 204016 [2021-11-13 18:36:52,099 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 204016 [2021-11-13 18:36:52,099 INFO L73 IsDeterministic]: Start isDeterministic. Operand 204016 states and 283878 transitions. [2021-11-13 18:36:52,181 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:52,181 INFO L681 BuchiCegarLoop]: Abstraction has 204016 states and 283878 transitions. [2021-11-13 18:36:52,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 204016 states and 283878 transitions. [2021-11-13 18:36:54,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 204016 to 162208. [2021-11-13 18:36:54,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 162208 states, 162208 states have (on average 1.394986683764056) internal successors, (226278), 162207 states have internal predecessors, (226278), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:55,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162208 states to 162208 states and 226278 transitions. [2021-11-13 18:36:55,507 INFO L704 BuchiCegarLoop]: Abstraction has 162208 states and 226278 transitions. [2021-11-13 18:36:55,507 INFO L587 BuchiCegarLoop]: Abstraction has 162208 states and 226278 transitions. [2021-11-13 18:36:55,507 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-11-13 18:36:55,507 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 162208 states and 226278 transitions. [2021-11-13 18:36:56,072 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 161984 [2021-11-13 18:36:56,073 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:36:56,073 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:36:56,087 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:56,087 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:36:56,088 INFO L791 eck$LassoCheckResult]: Stem: 907081#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 907082#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 908150#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 907469#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 907240#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 907241#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 907337#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 907697#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 907851#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 907852#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 906509#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 906510#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 907770#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 907127#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 907128#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 907033#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 907034#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 907465#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 906753#L1174 assume !(0 == ~M_E~0); 906754#L1174-2 assume !(0 == ~T1_E~0); 906604#L1179-1 assume !(0 == ~T2_E~0); 906507#L1184-1 assume !(0 == ~T3_E~0); 906508#L1189-1 assume !(0 == ~T4_E~0); 906546#L1194-1 assume !(0 == ~T5_E~0); 906646#L1199-1 assume !(0 == ~T6_E~0); 907628#L1204-1 assume !(0 == ~T7_E~0); 907535#L1209-1 assume !(0 == ~T8_E~0); 907536#L1214-1 assume !(0 == ~T9_E~0); 908021#L1219-1 assume !(0 == ~T10_E~0); 908195#L1224-1 assume !(0 == ~T11_E~0); 906880#L1229-1 assume !(0 == ~T12_E~0); 906436#L1234-1 assume !(0 == ~E_1~0); 906437#L1239-1 assume !(0 == ~E_2~0); 906468#L1244-1 assume !(0 == ~E_3~0); 906469#L1249-1 assume !(0 == ~E_4~0); 907153#L1254-1 assume !(0 == ~E_5~0); 906370#L1259-1 assume !(0 == ~E_6~0); 906329#L1264-1 assume !(0 == ~E_7~0); 906330#L1269-1 assume !(0 == ~E_8~0); 908222#L1274-1 assume !(0 == ~E_9~0); 908070#L1279-1 assume !(0 == ~E_10~0); 906549#L1284-1 assume !(0 == ~E_11~0); 906550#L1289-1 assume !(0 == ~E_12~0); 907209#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 907210#L566 assume !(1 == ~m_pc~0); 907694#L566-2 is_master_triggered_~__retres1~0#1 := 0; 907695#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 907569#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 907570#L1455 assume !(0 != activate_threads_~tmp~1#1); 906779#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 906780#L585 assume !(1 == ~t1_pc~0); 906974#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 906975#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 907498#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 907499#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 908117#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 908114#L604 assume !(1 == ~t2_pc~0); 907592#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 907593#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 908091#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 907989#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 907798#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 907799#L623 assume !(1 == ~t3_pc~0); 906310#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 906311#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 907132#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 907133#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 907843#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 906343#L642 assume !(1 == ~t4_pc~0); 906344#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 906796#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 906797#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 906410#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 906411#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 907604#L661 assume !(1 == ~t5_pc~0); 906570#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 907488#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 906529#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 906530#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 907639#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 907640#L680 assume !(1 == ~t6_pc~0); 907010#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 907011#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 907290#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 907291#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 907929#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 908107#L699 assume !(1 == ~t7_pc~0); 908108#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 907718#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 906557#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 906558#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 907323#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 907211#L718 assume !(1 == ~t8_pc~0); 907212#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 906544#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 906545#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 906586#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 906587#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 906721#L737 assume !(1 == ~t9_pc~0); 906864#L737-2 is_transmit9_triggered_~__retres1~9#1 := 0; 906865#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 907527#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 907528#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 907051#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 907052#L756 assume !(1 == ~t10_pc~0); 907313#L756-2 is_transmit10_triggered_~__retres1~10#1 := 0; 907314#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 906277#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 906278#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 906846#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 906847#L775 assume !(1 == ~t11_pc~0); 907115#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 907116#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 908253#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 906480#L1543 assume !(0 != activate_threads_~tmp___10~0#1); 906481#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 906665#L794 assume !(1 == ~t12_pc~0); 906484#L794-2 is_transmit12_triggered_~__retres1~12#1 := 0; 906485#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 907795#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 906630#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 906631#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 907135#L1307 assume !(1 == ~M_E~0); 907136#L1307-2 assume !(1 == ~T1_E~0); 907260#L1312-1 assume !(1 == ~T2_E~0); 907169#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 907170#L1322-1 assume !(1 == ~T4_E~0); 906856#L1327-1 assume !(1 == ~T5_E~0); 906857#L1332-1 assume !(1 == ~T6_E~0); 907442#L1337-1 assume !(1 == ~T7_E~0); 907392#L1342-1 assume !(1 == ~T8_E~0); 907393#L1347-1 assume !(1 == ~T9_E~0); 907885#L1352-1 assume !(1 == ~T10_E~0); 907719#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 907031#L1362-1 assume !(1 == ~T12_E~0); 907032#L1367-1 assume !(1 == ~E_1~0); 906647#L1372-1 assume !(1 == ~E_2~0); 906648#L1377-1 assume !(1 == ~E_3~0); 906957#L1382-1 assume !(1 == ~E_4~0); 906958#L1387-1 assume !(1 == ~E_5~0); 907594#L1392-1 assume !(1 == ~E_6~0); 906978#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 906979#L1402-1 assume !(1 == ~E_8~0); 906659#L1407-1 assume !(1 == ~E_9~0); 906660#L1412-1 assume !(1 == ~E_10~0); 907793#L1417-1 assume !(1 == ~E_11~0); 907794#L1422-1 assume !(1 == ~E_12~0); 908104#L1427-1 assume { :end_inline_reset_delta_events } true; 906464#L1768-2 [2021-11-13 18:36:56,088 INFO L793 eck$LassoCheckResult]: Loop: 906464#L1768-2 assume !false; 906465#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 907230#L1149 assume !false; 907665#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 907858#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1049140#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1049138#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 1049137#L976 assume !(0 != eval_~tmp~0#1); 908137#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 908126#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 908127#L1174-3 assume !(0 == ~M_E~0); 1067339#L1174-5 assume !(0 == ~T1_E~0); 1067337#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1067335#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1067328#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1067323#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1067303#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1067296#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1067291#L1209-3 assume !(0 == ~T8_E~0); 1067286#L1214-3 assume !(0 == ~T9_E~0); 907377#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 907063#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 907064#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 907083#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 906472#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 906473#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 906929#L1249-3 assume !(0 == ~E_4~0); 907432#L1254-3 assume !(0 == ~E_5~0); 908016#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 907566#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 906478#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 906479#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 908068#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 907061#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 907062#L1289-3 assume !(0 == ~E_12~0); 907050#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 906700#L566-39 assume !(1 == ~m_pc~0); 906701#L566-41 is_master_triggered_~__retres1~0#1 := 0; 907347#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 907041#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 907042#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 907651#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 907652#L585-39 assume !(1 == ~t1_pc~0); 908049#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1066124#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1066123#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1066122#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1066121#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1066120#L604-39 assume !(1 == ~t2_pc~0); 1066118#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1066116#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1066114#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1066113#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 1066111#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1066110#L623-39 assume !(1 == ~t3_pc~0); 1065218#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1066108#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1066107#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1066106#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1066105#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1066104#L642-39 assume 1 == ~t4_pc~0; 1066102#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1066100#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1066098#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1066096#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1066094#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1066090#L661-39 assume !(1 == ~t5_pc~0); 1066088#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1066087#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1066085#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1066083#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1066081#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1066079#L680-39 assume 1 == ~t6_pc~0; 1066074#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1066072#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1066026#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1066025#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1066024#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1061107#L699-39 assume !(1 == ~t7_pc~0); 1061105#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1061103#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1061101#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1061099#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1061097#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1061095#L718-39 assume 1 == ~t8_pc~0; 1061091#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1061089#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1061087#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1061085#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 1061083#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1061079#L737-39 assume !(1 == ~t9_pc~0); 1044181#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1061076#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1061074#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1061062#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1060195#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 907844#L756-39 assume !(1 == ~t10_pc~0); 907845#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 1061199#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1061198#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1061197#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1061196#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 906421#L775-39 assume !(1 == ~t11_pc~0); 906423#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 907140#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1066677#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 908192#L1543-39 assume !(0 != activate_threads_~tmp___10~0#1); 907559#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 907150#L794-39 assume !(1 == ~t12_pc~0); 906810#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 906811#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 907734#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 907618#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 906366#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 906367#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 907990#L1307-5 assume !(1 == ~T1_E~0); 907991#L1312-3 assume !(1 == ~T2_E~0); 908221#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 907641#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 907642#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 906498#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 906470#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 906471#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 907247#L1347-3 assume !(1 == ~T9_E~0); 907382#L1352-3 assume !(1 == ~T10_E~0); 907383#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 907927#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 908189#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 908175#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 906308#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 906309#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 906943#L1387-3 assume !(1 == ~E_5~0); 906944#L1392-3 assume !(1 == ~E_6~0); 907749#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 908097#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 907346#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 906582#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 906583#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 907268#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 907269#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 906592#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 906593#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 907530#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 907351#L1787 assume !(0 == start_simulation_~tmp~3#1); 907352#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 908004#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 906562#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 907407#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 907408#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 906923#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 906924#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 906925#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 906464#L1768-2 [2021-11-13 18:36:56,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:56,089 INFO L85 PathProgramCache]: Analyzing trace with hash 170497229, now seen corresponding path program 1 times [2021-11-13 18:36:56,090 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:56,090 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1896583203] [2021-11-13 18:36:56,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:56,090 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:56,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:56,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:56,156 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:56,156 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1896583203] [2021-11-13 18:36:56,156 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1896583203] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:56,157 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:56,157 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:36:56,157 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2090992338] [2021-11-13 18:36:56,157 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:56,158 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:36:56,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:36:56,159 INFO L85 PathProgramCache]: Analyzing trace with hash -644890653, now seen corresponding path program 1 times [2021-11-13 18:36:56,159 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:36:56,159 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1846367439] [2021-11-13 18:36:56,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:36:56,160 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:36:56,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:36:56,210 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:36:56,210 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:36:56,211 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1846367439] [2021-11-13 18:36:56,211 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1846367439] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:36:56,211 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:36:56,211 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:36:56,211 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [120403593] [2021-11-13 18:36:56,212 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:36:56,212 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:36:56,212 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:36:56,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:36:56,213 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:36:56,213 INFO L87 Difference]: Start difference. First operand 162208 states and 226278 transitions. cyclomatic complexity: 64072 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:36:56,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:36:56,871 INFO L93 Difference]: Finished difference Result 162208 states and 225892 transitions. [2021-11-13 18:36:56,872 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:36:56,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 162208 states and 225892 transitions. [2021-11-13 18:36:58,575 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 161984 [2021-11-13 18:36:58,997 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 162208 states to 162208 states and 225892 transitions. [2021-11-13 18:36:58,997 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 162208 [2021-11-13 18:36:59,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 162208 [2021-11-13 18:36:59,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 162208 states and 225892 transitions. [2021-11-13 18:36:59,167 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:36:59,167 INFO L681 BuchiCegarLoop]: Abstraction has 162208 states and 225892 transitions. [2021-11-13 18:36:59,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162208 states and 225892 transitions. [2021-11-13 18:37:01,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162208 to 162208. [2021-11-13 18:37:01,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 162208 states, 162208 states have (on average 1.3926070230814755) internal successors, (225892), 162207 states have internal predecessors, (225892), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:37:02,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162208 states to 162208 states and 225892 transitions. [2021-11-13 18:37:02,371 INFO L704 BuchiCegarLoop]: Abstraction has 162208 states and 225892 transitions. [2021-11-13 18:37:02,371 INFO L587 BuchiCegarLoop]: Abstraction has 162208 states and 225892 transitions. [2021-11-13 18:37:02,372 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-11-13 18:37:02,372 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 162208 states and 225892 transitions. [2021-11-13 18:37:02,879 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 161984 [2021-11-13 18:37:02,879 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:37:02,879 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:37:02,888 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:37:02,889 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:37:02,889 INFO L791 eck$LassoCheckResult]: Stem: 1231502#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1231503#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1232584#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1231883#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1231666#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 1231667#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1231756#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1232112#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1232274#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1232275#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1230932#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1230933#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1232187#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1231549#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1231550#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1231453#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1231454#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1231879#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1231174#L1174 assume !(0 == ~M_E~0); 1231175#L1174-2 assume !(0 == ~T1_E~0); 1231027#L1179-1 assume !(0 == ~T2_E~0); 1230930#L1184-1 assume !(0 == ~T3_E~0); 1230931#L1189-1 assume !(0 == ~T4_E~0); 1230969#L1194-1 assume !(0 == ~T5_E~0); 1231067#L1199-1 assume !(0 == ~T6_E~0); 1232044#L1204-1 assume !(0 == ~T7_E~0); 1231949#L1209-1 assume !(0 == ~T8_E~0); 1231950#L1214-1 assume !(0 == ~T9_E~0); 1232461#L1219-1 assume !(0 == ~T10_E~0); 1232636#L1224-1 assume !(0 == ~T11_E~0); 1231301#L1229-1 assume !(0 == ~T12_E~0); 1230859#L1234-1 assume !(0 == ~E_1~0); 1230860#L1239-1 assume !(0 == ~E_2~0); 1230891#L1244-1 assume !(0 == ~E_3~0); 1230892#L1249-1 assume !(0 == ~E_4~0); 1231578#L1254-1 assume !(0 == ~E_5~0); 1230793#L1259-1 assume !(0 == ~E_6~0); 1230752#L1264-1 assume !(0 == ~E_7~0); 1230753#L1269-1 assume !(0 == ~E_8~0); 1232661#L1274-1 assume !(0 == ~E_9~0); 1232506#L1279-1 assume !(0 == ~E_10~0); 1230972#L1284-1 assume !(0 == ~E_11~0); 1230973#L1289-1 assume !(0 == ~E_12~0); 1231633#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1231634#L566 assume !(1 == ~m_pc~0); 1232107#L566-2 is_master_triggered_~__retres1~0#1 := 0; 1232108#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1231985#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1231986#L1455 assume !(0 != activate_threads_~tmp~1#1); 1231200#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1231201#L585 assume !(1 == ~t1_pc~0); 1231394#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1231395#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1231912#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1231913#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 1232556#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1232552#L604 assume !(1 == ~t2_pc~0); 1232009#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1232010#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1232524#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1232426#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 1232221#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1232222#L623 assume !(1 == ~t3_pc~0); 1230733#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1230734#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1231554#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1231555#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 1232268#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1230766#L642 assume !(1 == ~t4_pc~0); 1230767#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1231219#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1231220#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1230833#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 1230834#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1232022#L661 assume !(1 == ~t5_pc~0); 1230993#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1231902#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1230952#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1230953#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 1232052#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1232053#L680 assume !(1 == ~t6_pc~0); 1231431#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1231432#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1231711#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1231712#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 1232358#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1232548#L699 assume !(1 == ~t7_pc~0); 1232549#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1232133#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1230980#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1230981#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 1231742#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1231635#L718 assume !(1 == ~t8_pc~0); 1231636#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1230967#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1230968#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1231009#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 1231010#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1231141#L737 assume !(1 == ~t9_pc~0); 1231284#L737-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1231285#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1231939#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1231940#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 1231471#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1231472#L756 assume !(1 == ~t10_pc~0); 1231733#L756-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1231734#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1230700#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1230701#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 1231265#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1231266#L775 assume !(1 == ~t11_pc~0); 1231537#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1231538#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1232695#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1230903#L1543 assume !(0 != activate_threads_~tmp___10~0#1); 1230904#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1231085#L794 assume !(1 == ~t12_pc~0); 1230907#L794-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1230908#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1232217#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1231053#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 1231054#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1231557#L1307 assume !(1 == ~M_E~0); 1231558#L1307-2 assume !(1 == ~T1_E~0); 1231681#L1312-1 assume !(1 == ~T2_E~0); 1231593#L1317-1 assume !(1 == ~T3_E~0); 1231594#L1322-1 assume !(1 == ~T4_E~0); 1231275#L1327-1 assume !(1 == ~T5_E~0); 1231276#L1332-1 assume !(1 == ~T6_E~0); 1231857#L1337-1 assume !(1 == ~T7_E~0); 1231810#L1342-1 assume !(1 == ~T8_E~0); 1231811#L1347-1 assume !(1 == ~T9_E~0); 1232309#L1352-1 assume !(1 == ~T10_E~0); 1232134#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1231451#L1362-1 assume !(1 == ~T12_E~0); 1231452#L1367-1 assume !(1 == ~E_1~0); 1231068#L1372-1 assume !(1 == ~E_2~0); 1231069#L1377-1 assume !(1 == ~E_3~0); 1231377#L1382-1 assume !(1 == ~E_4~0); 1231378#L1387-1 assume !(1 == ~E_5~0); 1232011#L1392-1 assume !(1 == ~E_6~0); 1231398#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1231399#L1402-1 assume !(1 == ~E_8~0); 1231079#L1407-1 assume !(1 == ~E_9~0); 1231080#L1412-1 assume !(1 == ~E_10~0); 1232215#L1417-1 assume !(1 == ~E_11~0); 1232216#L1422-1 assume !(1 == ~E_12~0); 1232542#L1427-1 assume { :end_inline_reset_delta_events } true; 1232543#L1768-2 [2021-11-13 18:37:02,890 INFO L793 eck$LassoCheckResult]: Loop: 1232543#L1768-2 assume !false; 1329440#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1327962#L1149 assume !false; 1329433#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1328062#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1328054#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1328052#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 1328048#L976 assume !(0 != eval_~tmp~0#1); 1328049#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1392771#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1392770#L1174-3 assume !(0 == ~M_E~0); 1392769#L1174-5 assume !(0 == ~T1_E~0); 1392768#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1392767#L1184-3 assume !(0 == ~T3_E~0); 1392766#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1392765#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1392763#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1392761#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1392759#L1209-3 assume !(0 == ~T8_E~0); 1392757#L1214-3 assume !(0 == ~T9_E~0); 1392755#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1392753#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1392750#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1392748#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1392746#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1392744#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1392742#L1249-3 assume !(0 == ~E_4~0); 1392740#L1254-3 assume !(0 == ~E_5~0); 1392739#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1392738#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1392736#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1392734#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1392732#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1392730#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1392728#L1289-3 assume !(0 == ~E_12~0); 1392727#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1392726#L566-39 assume !(1 == ~m_pc~0); 1392725#L566-41 is_master_triggered_~__retres1~0#1 := 0; 1392723#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1392722#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1392721#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1392720#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1232488#L585-39 assume !(1 == ~t1_pc~0); 1232489#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1392177#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1392175#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1392173#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1392171#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1392170#L604-39 assume 1 == ~t2_pc~0; 1392167#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1392165#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1392163#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1392084#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1392082#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1331546#L623-39 assume !(1 == ~t3_pc~0); 1331544#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1331542#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1331540#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1331537#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1331535#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1331531#L642-39 assume 1 == ~t4_pc~0; 1331532#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1331524#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1331525#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1331517#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1331518#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1331509#L661-39 assume !(1 == ~t5_pc~0); 1331510#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1331503#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1331504#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1373174#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1373172#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1331493#L680-39 assume 1 == ~t6_pc~0; 1331490#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1331488#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1331487#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1331485#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1331483#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1330020#L699-39 assume !(1 == ~t7_pc~0); 1330015#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1330011#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1330009#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1330006#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1330003#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1330000#L718-39 assume 1 == ~t8_pc~0; 1329996#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1329993#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1329987#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1329981#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 1329959#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1329949#L737-39 assume !(1 == ~t9_pc~0); 1322169#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1329938#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1329935#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1329928#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1329922#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1329916#L756-39 assume !(1 == ~t10_pc~0); 1327157#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 1329905#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1329897#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1329890#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1329883#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1329873#L775-39 assume !(1 == ~t11_pc~0); 1329863#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 1329855#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1329847#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1329839#L1543-39 assume !(0 != activate_threads_~tmp___10~0#1); 1329836#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1329834#L794-39 assume !(1 == ~t12_pc~0); 1328977#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 1329830#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1329828#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1329827#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1329822#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1329816#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1329809#L1307-5 assume !(1 == ~T1_E~0); 1329801#L1312-3 assume !(1 == ~T2_E~0); 1329794#L1317-3 assume !(1 == ~T3_E~0); 1329787#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1329781#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1329775#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1329768#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1329761#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1329754#L1347-3 assume !(1 == ~T9_E~0); 1329747#L1352-3 assume !(1 == ~T10_E~0); 1329741#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1329734#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1329726#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1329719#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1329712#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1329706#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1329700#L1387-3 assume !(1 == ~E_5~0); 1329697#L1392-3 assume !(1 == ~E_6~0); 1329695#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1329693#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1329688#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1329682#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1329676#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1329671#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1329665#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1329610#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1329597#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1329595#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1329584#L1787 assume !(0 == start_simulation_~tmp~3#1); 1329580#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1329496#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1329483#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1329477#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 1329469#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1329461#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1329454#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1329448#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 1232543#L1768-2 [2021-11-13 18:37:02,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:37:02,891 INFO L85 PathProgramCache]: Analyzing trace with hash -1634941105, now seen corresponding path program 1 times [2021-11-13 18:37:02,891 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:37:02,891 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1794141732] [2021-11-13 18:37:02,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:37:02,892 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:37:02,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:37:02,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:37:02,936 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:37:02,936 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1794141732] [2021-11-13 18:37:02,937 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1794141732] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:37:02,937 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:37:02,937 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:37:02,937 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [41968445] [2021-11-13 18:37:02,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:37:02,938 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:37:02,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:37:02,938 INFO L85 PathProgramCache]: Analyzing trace with hash 358357642, now seen corresponding path program 1 times [2021-11-13 18:37:02,939 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:37:02,939 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2018325257] [2021-11-13 18:37:02,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:37:02,939 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:37:02,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:37:02,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:37:02,972 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:37:02,973 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2018325257] [2021-11-13 18:37:02,973 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2018325257] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:37:02,973 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:37:02,973 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:37:02,973 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1185167313] [2021-11-13 18:37:02,973 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:37:02,974 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:37:02,974 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:37:02,974 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:37:02,974 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:37:02,975 INFO L87 Difference]: Start difference. First operand 162208 states and 225892 transitions. cyclomatic complexity: 63686 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:37:03,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:37:03,503 INFO L93 Difference]: Finished difference Result 162208 states and 225506 transitions. [2021-11-13 18:37:03,503 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:37:03,504 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 162208 states and 225506 transitions. [2021-11-13 18:37:05,188 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 161984 [2021-11-13 18:37:05,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 162208 states to 162208 states and 225506 transitions. [2021-11-13 18:37:05,652 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 162208 [2021-11-13 18:37:05,744 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 162208 [2021-11-13 18:37:05,744 INFO L73 IsDeterministic]: Start isDeterministic. Operand 162208 states and 225506 transitions. [2021-11-13 18:37:05,839 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:37:05,839 INFO L681 BuchiCegarLoop]: Abstraction has 162208 states and 225506 transitions. [2021-11-13 18:37:05,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162208 states and 225506 transitions. [2021-11-13 18:37:07,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162208 to 162208. [2021-11-13 18:37:07,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 162208 states, 162208 states have (on average 1.3902273623988952) internal successors, (225506), 162207 states have internal predecessors, (225506), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:37:08,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162208 states to 162208 states and 225506 transitions. [2021-11-13 18:37:08,308 INFO L704 BuchiCegarLoop]: Abstraction has 162208 states and 225506 transitions. [2021-11-13 18:37:08,309 INFO L587 BuchiCegarLoop]: Abstraction has 162208 states and 225506 transitions. [2021-11-13 18:37:08,309 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-11-13 18:37:08,309 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 162208 states and 225506 transitions. [2021-11-13 18:37:09,763 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 161984 [2021-11-13 18:37:09,763 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:37:09,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:37:09,781 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:37:09,782 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:37:09,782 INFO L791 eck$LassoCheckResult]: Stem: 1555924#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1555925#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1557036#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1556315#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1556088#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 1556089#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1556181#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1556549#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1556710#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1556711#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1555355#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1555356#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1556626#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1555971#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1555972#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1555874#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1555875#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1556311#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1555600#L1174 assume !(0 == ~M_E~0); 1555601#L1174-2 assume !(0 == ~T1_E~0); 1555450#L1179-1 assume !(0 == ~T2_E~0); 1555353#L1184-1 assume !(0 == ~T3_E~0); 1555354#L1189-1 assume !(0 == ~T4_E~0); 1555392#L1194-1 assume !(0 == ~T5_E~0); 1555490#L1199-1 assume !(0 == ~T6_E~0); 1556479#L1204-1 assume !(0 == ~T7_E~0); 1556379#L1209-1 assume !(0 == ~T8_E~0); 1556380#L1214-1 assume !(0 == ~T9_E~0); 1556897#L1219-1 assume !(0 == ~T10_E~0); 1557091#L1224-1 assume !(0 == ~T11_E~0); 1555722#L1229-1 assume !(0 == ~T12_E~0); 1555282#L1234-1 assume !(0 == ~E_1~0); 1555283#L1239-1 assume !(0 == ~E_2~0); 1555314#L1244-1 assume !(0 == ~E_3~0); 1555315#L1249-1 assume !(0 == ~E_4~0); 1555998#L1254-1 assume !(0 == ~E_5~0); 1555216#L1259-1 assume !(0 == ~E_6~0); 1555175#L1264-1 assume !(0 == ~E_7~0); 1555176#L1269-1 assume !(0 == ~E_8~0); 1557123#L1274-1 assume !(0 == ~E_9~0); 1556950#L1279-1 assume !(0 == ~E_10~0); 1555395#L1284-1 assume !(0 == ~E_11~0); 1555396#L1289-1 assume !(0 == ~E_12~0); 1556056#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1556057#L566 assume !(1 == ~m_pc~0); 1556546#L566-2 is_master_triggered_~__retres1~0#1 := 0; 1556547#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1556415#L578 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1556416#L1455 assume !(0 != activate_threads_~tmp~1#1); 1555626#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1555627#L585 assume !(1 == ~t1_pc~0); 1555815#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1555816#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1556344#L597 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1556345#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 1557007#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1557003#L604 assume !(1 == ~t2_pc~0); 1556440#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1556441#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1556977#L616 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1556864#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 1556658#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1556659#L623 assume !(1 == ~t3_pc~0); 1555156#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1555157#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1555976#L635 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1555977#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 1556703#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1555189#L642 assume !(1 == ~t4_pc~0); 1555190#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1555643#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1555644#L654 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1555256#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 1555257#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1556455#L661 assume !(1 == ~t5_pc~0); 1555416#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1556335#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1555375#L673 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1555376#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 1556488#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1556489#L680 assume !(1 == ~t6_pc~0); 1555852#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1555853#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1556133#L692 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1556134#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 1556799#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1556999#L699 assume !(1 == ~t7_pc~0); 1557000#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1556570#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1555403#L711 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1555404#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 1556166#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1556058#L718 assume !(1 == ~t8_pc~0); 1556059#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1555390#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1555391#L730 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1555432#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 1555433#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1555565#L737 assume !(1 == ~t9_pc~0); 1555706#L737-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1555707#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1556370#L749 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1556371#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 1555892#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1555893#L756 assume !(1 == ~t10_pc~0); 1556156#L756-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1556157#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1555123#L768 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1555124#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 1555689#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1555690#L775 assume !(1 == ~t11_pc~0); 1555959#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1555960#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1557159#L787 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1555326#L1543 assume !(0 != activate_threads_~tmp___10~0#1); 1555327#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1555509#L794 assume !(1 == ~t12_pc~0); 1555330#L794-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1555331#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1556653#L806 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1555476#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 1555477#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1555979#L1307 assume !(1 == ~M_E~0); 1555980#L1307-2 assume !(1 == ~T1_E~0); 1556103#L1312-1 assume !(1 == ~T2_E~0); 1556014#L1317-1 assume !(1 == ~T3_E~0); 1556015#L1322-1 assume !(1 == ~T4_E~0); 1555698#L1327-1 assume !(1 == ~T5_E~0); 1555699#L1332-1 assume !(1 == ~T6_E~0); 1556287#L1337-1 assume !(1 == ~T7_E~0); 1556237#L1342-1 assume !(1 == ~T8_E~0); 1556238#L1347-1 assume !(1 == ~T9_E~0); 1556750#L1352-1 assume !(1 == ~T10_E~0); 1556571#L1357-1 assume !(1 == ~T11_E~0); 1555872#L1362-1 assume !(1 == ~T12_E~0); 1555873#L1367-1 assume !(1 == ~E_1~0); 1555491#L1372-1 assume !(1 == ~E_2~0); 1555492#L1377-1 assume !(1 == ~E_3~0); 1555798#L1382-1 assume !(1 == ~E_4~0); 1555799#L1387-1 assume !(1 == ~E_5~0); 1556442#L1392-1 assume !(1 == ~E_6~0); 1555820#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1555821#L1402-1 assume !(1 == ~E_8~0); 1555503#L1407-1 assume !(1 == ~E_9~0); 1555504#L1412-1 assume !(1 == ~E_10~0); 1556651#L1417-1 assume !(1 == ~E_11~0); 1556652#L1422-1 assume !(1 == ~E_12~0); 1556996#L1427-1 assume { :end_inline_reset_delta_events } true; 1556997#L1768-2 [2021-11-13 18:37:09,783 INFO L793 eck$LassoCheckResult]: Loop: 1556997#L1768-2 assume !false; 1661476#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1661472#L1149 assume !false; 1661471#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1661459#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1661452#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1661450#L962 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 1661447#L976 assume !(0 != eval_~tmp~0#1); 1661448#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1710885#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1710883#L1174-3 assume !(0 == ~M_E~0); 1710881#L1174-5 assume !(0 == ~T1_E~0); 1710879#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1710877#L1184-3 assume !(0 == ~T3_E~0); 1710876#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1710875#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1710873#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1710871#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1710869#L1209-3 assume !(0 == ~T8_E~0); 1710867#L1214-3 assume !(0 == ~T9_E~0); 1710864#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1710862#L1224-3 assume !(0 == ~T11_E~0); 1710861#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1710860#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1710858#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1710857#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1710856#L1249-3 assume !(0 == ~E_4~0); 1710854#L1254-3 assume !(0 == ~E_5~0); 1710853#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1710852#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1710851#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1710850#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1710849#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1710848#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1710847#L1289-3 assume !(0 == ~E_12~0); 1710846#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1710844#L566-39 assume !(1 == ~m_pc~0); 1710842#L566-41 is_master_triggered_~__retres1~0#1 := 0; 1710840#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1710837#L578-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1710835#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1710833#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1710831#L585-39 assume !(1 == ~t1_pc~0); 1704731#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1710828#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1710825#L597-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1710823#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1710821#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1710819#L604-39 assume !(1 == ~t2_pc~0); 1710815#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1710811#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1710809#L616-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1710807#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 1710804#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1691198#L623-39 assume !(1 == ~t3_pc~0); 1691196#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1691194#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1691192#L635-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1691190#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1691187#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1691063#L642-39 assume !(1 == ~t4_pc~0); 1691059#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1691055#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1691053#L654-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1691050#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1691048#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1691042#L661-39 assume !(1 == ~t5_pc~0); 1691040#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1691038#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1691034#L673-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1691032#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1691030#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1691029#L680-39 assume !(1 == ~t6_pc~0); 1691027#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 1691024#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1691022#L692-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1691019#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1691015#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1684975#L699-39 assume !(1 == ~t7_pc~0); 1684972#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1684970#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1684967#L711-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1684965#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1684963#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1684961#L718-39 assume 1 == ~t8_pc~0; 1684957#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1684955#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1684951#L730-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1684947#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 1684944#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1661642#L737-39 assume !(1 == ~t9_pc~0); 1661641#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1661638#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1661636#L749-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1661634#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1661632#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1661630#L756-39 assume !(1 == ~t10_pc~0); 1641582#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 1661626#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1661623#L768-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1661620#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1661618#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1661616#L775-39 assume !(1 == ~t11_pc~0); 1661611#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 1661612#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1661606#L787-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1661604#L1543-39 assume !(0 != activate_threads_~tmp___10~0#1); 1661601#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1661599#L794-39 assume !(1 == ~t12_pc~0); 1661598#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 1661597#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1661596#L806-13 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1661595#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1661594#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1661593#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1661592#L1307-5 assume !(1 == ~T1_E~0); 1661591#L1312-3 assume !(1 == ~T2_E~0); 1661589#L1317-3 assume !(1 == ~T3_E~0); 1661587#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1661585#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1661583#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1661581#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1661579#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1661577#L1347-3 assume !(1 == ~T9_E~0); 1661575#L1352-3 assume !(1 == ~T10_E~0); 1661573#L1357-3 assume !(1 == ~T11_E~0); 1661571#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1661569#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1661567#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1661565#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1661563#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1661561#L1387-3 assume !(1 == ~E_5~0); 1661559#L1392-3 assume !(1 == ~E_6~0); 1661557#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1661555#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1661553#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1661551#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1661549#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1661547#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1661545#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1661535#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1661521#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1661518#L962-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1661514#L1787 assume !(0 == start_simulation_~tmp~3#1); 1661509#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1661500#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1661493#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1661492#L962-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 1661488#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1661485#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1661484#L1750 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1661481#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 1556997#L1768-2 [2021-11-13 18:37:09,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:37:09,783 INFO L85 PathProgramCache]: Analyzing trace with hash 1380162513, now seen corresponding path program 1 times [2021-11-13 18:37:09,783 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:37:09,783 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334542547] [2021-11-13 18:37:09,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:37:09,784 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:37:09,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:37:09,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:37:09,853 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:37:09,853 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1334542547] [2021-11-13 18:37:09,853 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1334542547] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:37:09,853 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:37:09,854 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:37:09,854 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [907147396] [2021-11-13 18:37:09,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:37:09,856 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:37:09,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:37:09,857 INFO L85 PathProgramCache]: Analyzing trace with hash 1786954921, now seen corresponding path program 1 times [2021-11-13 18:37:09,858 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:37:09,858 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1090705751] [2021-11-13 18:37:09,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:37:09,858 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:37:09,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:37:09,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:37:09,898 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:37:09,898 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1090705751] [2021-11-13 18:37:09,898 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1090705751] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:37:09,898 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:37:09,898 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:37:09,899 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [737533159] [2021-11-13 18:37:09,899 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:37:09,899 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:37:09,899 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:37:09,900 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:37:09,900 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:37:09,900 INFO L87 Difference]: Start difference. First operand 162208 states and 225506 transitions. cyclomatic complexity: 63300 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:37:10,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:37:10,422 INFO L93 Difference]: Finished difference Result 162208 states and 224448 transitions. [2021-11-13 18:37:10,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:37:10,423 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 162208 states and 224448 transitions. [2021-11-13 18:37:11,992 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 161984 [2021-11-13 18:37:12,449 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 162208 states to 162208 states and 224448 transitions. [2021-11-13 18:37:12,449 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 162208 [2021-11-13 18:37:12,543 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 162208 [2021-11-13 18:37:12,543 INFO L73 IsDeterministic]: Start isDeterministic. Operand 162208 states and 224448 transitions. [2021-11-13 18:37:12,620 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:37:12,620 INFO L681 BuchiCegarLoop]: Abstraction has 162208 states and 224448 transitions. [2021-11-13 18:37:12,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162208 states and 224448 transitions. [2021-11-13 18:37:14,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162208 to 162208. [2021-11-13 18:37:14,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 162208 states, 162208 states have (on average 1.3837048727559675) internal successors, (224448), 162207 states have internal predecessors, (224448), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:37:15,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162208 states to 162208 states and 224448 transitions. [2021-11-13 18:37:15,130 INFO L704 BuchiCegarLoop]: Abstraction has 162208 states and 224448 transitions. [2021-11-13 18:37:15,130 INFO L587 BuchiCegarLoop]: Abstraction has 162208 states and 224448 transitions. [2021-11-13 18:37:15,130 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-11-13 18:37:15,131 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 162208 states and 224448 transitions.