./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread/fib_unsafe-6.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 63182f13 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread/fib_unsafe-6.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4c475d56613186560380fd7710c1a393bef46e366024d2f60e26aa83cc625627 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-63182f1 [2021-11-13 18:23:35,860 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-13 18:23:35,863 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-13 18:23:35,897 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-13 18:23:35,898 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-13 18:23:35,903 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-13 18:23:35,906 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-13 18:23:35,910 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-13 18:23:35,913 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-13 18:23:35,919 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-13 18:23:35,920 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-13 18:23:35,923 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-13 18:23:35,923 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-13 18:23:35,927 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-13 18:23:35,930 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-13 18:23:35,932 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-13 18:23:35,934 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-13 18:23:35,936 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-13 18:23:35,942 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-13 18:23:35,952 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-13 18:23:35,954 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-13 18:23:35,956 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-13 18:23:35,959 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-13 18:23:35,960 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-13 18:23:35,969 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-13 18:23:35,970 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-13 18:23:35,970 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-13 18:23:35,972 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-13 18:23:35,973 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-13 18:23:35,975 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-13 18:23:35,975 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-13 18:23:35,976 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-13 18:23:35,978 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-13 18:23:35,980 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-13 18:23:35,981 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-13 18:23:35,982 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-13 18:23:35,983 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-13 18:23:35,983 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-13 18:23:35,983 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-13 18:23:35,984 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-13 18:23:35,985 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-13 18:23:35,986 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/config/svcomp-Reach-32bit-Automizer_Default.epf [2021-11-13 18:23:36,014 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-13 18:23:36,015 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-13 18:23:36,015 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-13 18:23:36,015 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-13 18:23:36,016 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2021-11-13 18:23:36,017 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2021-11-13 18:23:36,017 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-13 18:23:36,018 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-13 18:23:36,018 INFO L138 SettingsManager]: * Use SBE=true [2021-11-13 18:23:36,018 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-13 18:23:36,018 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-13 18:23:36,019 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-13 18:23:36,019 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-13 18:23:36,019 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-13 18:23:36,019 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2021-11-13 18:23:36,020 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2021-11-13 18:23:36,020 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2021-11-13 18:23:36,020 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-13 18:23:36,020 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-13 18:23:36,020 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-13 18:23:36,021 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2021-11-13 18:23:36,021 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-13 18:23:36,021 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-13 18:23:36,021 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2021-11-13 18:23:36,022 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-11-13 18:23:36,022 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-13 18:23:36,022 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2021-11-13 18:23:36,022 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2021-11-13 18:23:36,023 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-13 18:23:36,023 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2021-11-13 18:23:36,023 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2021-11-13 18:23:36,023 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2021-11-13 18:23:36,023 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2021-11-13 18:23:36,024 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-13 18:23:36,024 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4c475d56613186560380fd7710c1a393bef46e366024d2f60e26aa83cc625627 [2021-11-13 18:23:36,332 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-13 18:23:36,370 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-13 18:23:36,372 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-13 18:23:36,374 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-13 18:23:36,375 INFO L275 PluginConnector]: CDTParser initialized [2021-11-13 18:23:36,377 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/../../sv-benchmarks/c/pthread/fib_unsafe-6.i [2021-11-13 18:23:36,454 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/data/9a8b293d7/71a7bfc396554734bd1cf9636d472fcb/FLAGedd12c452 [2021-11-13 18:23:37,052 INFO L306 CDTParser]: Found 1 translation units. [2021-11-13 18:23:37,057 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/sv-benchmarks/c/pthread/fib_unsafe-6.i [2021-11-13 18:23:37,079 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/data/9a8b293d7/71a7bfc396554734bd1cf9636d472fcb/FLAGedd12c452 [2021-11-13 18:23:37,309 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/data/9a8b293d7/71a7bfc396554734bd1cf9636d472fcb [2021-11-13 18:23:37,311 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-13 18:23:37,312 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-13 18:23:37,317 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-13 18:23:37,318 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-13 18:23:37,321 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-13 18:23:37,322 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 06:23:37" (1/1) ... [2021-11-13 18:23:37,325 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5c91c51d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:23:37, skipping insertion in model container [2021-11-13 18:23:37,325 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 06:23:37" (1/1) ... [2021-11-13 18:23:37,334 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-13 18:23:37,399 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-13 18:23:37,792 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/sv-benchmarks/c/pthread/fib_unsafe-6.i[30811,30824] [2021-11-13 18:23:37,795 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-13 18:23:37,804 INFO L203 MainTranslator]: Completed pre-run [2021-11-13 18:23:37,883 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/sv-benchmarks/c/pthread/fib_unsafe-6.i[30811,30824] [2021-11-13 18:23:37,894 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-13 18:23:37,942 INFO L208 MainTranslator]: Completed translation [2021-11-13 18:23:37,943 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:23:37 WrapperNode [2021-11-13 18:23:37,943 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-13 18:23:37,944 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-13 18:23:37,945 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-13 18:23:37,945 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-13 18:23:37,953 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:23:37" (1/1) ... [2021-11-13 18:23:37,985 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:23:37" (1/1) ... [2021-11-13 18:23:38,030 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-13 18:23:38,031 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-13 18:23:38,032 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-13 18:23:38,032 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-13 18:23:38,041 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:23:37" (1/1) ... [2021-11-13 18:23:38,041 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:23:37" (1/1) ... [2021-11-13 18:23:38,044 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:23:37" (1/1) ... [2021-11-13 18:23:38,044 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:23:37" (1/1) ... [2021-11-13 18:23:38,050 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:23:37" (1/1) ... [2021-11-13 18:23:38,054 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:23:37" (1/1) ... [2021-11-13 18:23:38,068 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:23:37" (1/1) ... [2021-11-13 18:23:38,071 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-13 18:23:38,072 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-13 18:23:38,072 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-13 18:23:38,072 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-13 18:23:38,081 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:23:37" (1/1) ... [2021-11-13 18:23:38,087 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-11-13 18:23:38,097 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 [2021-11-13 18:23:38,109 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2021-11-13 18:23:38,128 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2021-11-13 18:23:38,157 INFO L130 BoogieDeclarations]: Found specification of procedure t1 [2021-11-13 18:23:38,158 INFO L138 BoogieDeclarations]: Found implementation of procedure t1 [2021-11-13 18:23:38,158 INFO L130 BoogieDeclarations]: Found specification of procedure t2 [2021-11-13 18:23:38,158 INFO L138 BoogieDeclarations]: Found implementation of procedure t2 [2021-11-13 18:23:38,158 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-11-13 18:23:38,158 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2021-11-13 18:23:38,158 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-13 18:23:38,158 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-11-13 18:23:38,159 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-13 18:23:38,159 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2021-11-13 18:23:38,159 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-13 18:23:38,159 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-13 18:23:38,161 WARN L209 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2021-11-13 18:23:38,476 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-13 18:23:38,476 INFO L299 CfgBuilder]: Removed 3 assume(true) statements. [2021-11-13 18:23:38,479 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 06:23:38 BoogieIcfgContainer [2021-11-13 18:23:38,486 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-13 18:23:38,488 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2021-11-13 18:23:38,488 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2021-11-13 18:23:38,523 INFO L275 PluginConnector]: TraceAbstraction initialized [2021-11-13 18:23:38,524 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 13.11 06:23:37" (1/3) ... [2021-11-13 18:23:38,524 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@472794e3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 13.11 06:23:38, skipping insertion in model container [2021-11-13 18:23:38,525 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:23:37" (2/3) ... [2021-11-13 18:23:38,525 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@472794e3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 13.11 06:23:38, skipping insertion in model container [2021-11-13 18:23:38,525 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 06:23:38" (3/3) ... [2021-11-13 18:23:38,527 INFO L111 eAbstractionObserver]: Analyzing ICFG fib_unsafe-6.i [2021-11-13 18:23:38,533 WARN L149 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2021-11-13 18:23:38,534 INFO L204 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2021-11-13 18:23:38,534 INFO L163 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2021-11-13 18:23:38,534 INFO L513 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2021-11-13 18:23:38,595 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,595 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,595 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,596 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,596 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,596 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,596 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,596 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,597 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,597 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,597 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,598 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,598 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,598 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,598 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,599 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,599 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,599 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,600 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,600 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,600 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,600 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,600 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,601 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,601 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,601 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,602 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,602 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,602 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,602 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,603 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,603 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,603 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,603 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,604 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,604 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,607 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,608 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,608 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,608 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,608 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,612 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,612 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,612 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,613 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,613 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-11-13 18:23:38,614 INFO L148 ThreadInstanceAdder]: Constructed 0 joinOtherThreadTransitions. [2021-11-13 18:23:38,715 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2021-11-13 18:23:38,732 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2021-11-13 18:23:38,733 INFO L340 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2021-11-13 18:23:38,757 INFO L74 FinitePrefix]: Start finitePrefix. Operand has 96 places, 96 transitions, 202 flow [2021-11-13 18:23:38,846 INFO L129 PetriNetUnfolder]: 7/94 cut-off events. [2021-11-13 18:23:38,846 INFO L130 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2021-11-13 18:23:38,852 INFO L84 FinitePrefix]: Finished finitePrefix Result has 101 conditions, 94 events. 7/94 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 73 event pairs, 0 based on Foata normal form. 0/86 useless extension candidates. Maximal degree in co-relation 64. Up to 2 conditions per place. [2021-11-13 18:23:38,852 INFO L82 GeneralOperation]: Start removeDead. Operand has 96 places, 96 transitions, 202 flow [2021-11-13 18:23:38,860 INFO L88 GeneralOperation]: Finished RemoveDead, result has has 94 places, 94 transitions, 194 flow [2021-11-13 18:23:38,900 INFO L129 PetriNetUnfolder]: 7/85 cut-off events. [2021-11-13 18:23:38,901 INFO L130 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2021-11-13 18:23:38,902 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-11-13 18:23:38,902 INFO L254 CegarLoopForPetriNet]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:23:38,903 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-11-13 18:23:38,911 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:23:38,911 INFO L85 PathProgramCache]: Analyzing trace with hash -1927097680, now seen corresponding path program 1 times [2021-11-13 18:23:38,920 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:23:38,921 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [196150917] [2021-11-13 18:23:38,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:23:38,923 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:23:39,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:23:39,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:23:39,254 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:23:39,254 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [196150917] [2021-11-13 18:23:39,256 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [196150917] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:23:39,256 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:23:39,256 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:23:39,258 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [875870341] [2021-11-13 18:23:39,259 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:23:39,269 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2021-11-13 18:23:39,269 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:23:39,306 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-11-13 18:23:39,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-11-13 18:23:39,319 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 89 out of 96 [2021-11-13 18:23:39,324 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 94 places, 94 transitions, 194 flow. Second operand has 2 states, 2 states have (on average 90.5) internal successors, (181), 2 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:39,325 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-11-13 18:23:39,326 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 89 of 96 [2021-11-13 18:23:39,327 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-11-13 18:23:39,380 INFO L129 PetriNetUnfolder]: 3/89 cut-off events. [2021-11-13 18:23:39,380 INFO L130 PetriNetUnfolder]: For 2/2 co-relation queries the response was YES. [2021-11-13 18:23:39,381 INFO L84 FinitePrefix]: Finished finitePrefix Result has 99 conditions, 89 events. 3/89 cut-off events. For 2/2 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 62 event pairs, 0 based on Foata normal form. 5/90 useless extension candidates. Maximal degree in co-relation 60. Up to 3 conditions per place. [2021-11-13 18:23:39,383 INFO L132 encePairwiseOnDemand]: 92/96 looper letters, 2 selfloop transitions, 0 changer transitions 0/89 dead transitions. [2021-11-13 18:23:39,383 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 94 places, 89 transitions, 188 flow [2021-11-13 18:23:39,387 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-11-13 18:23:39,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2021-11-13 18:23:39,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 184 transitions. [2021-11-13 18:23:39,402 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.9583333333333334 [2021-11-13 18:23:39,403 INFO L72 ComplementDD]: Start complementDD. Operand 2 states and 184 transitions. [2021-11-13 18:23:39,404 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2 states and 184 transitions. [2021-11-13 18:23:39,412 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:23:39,415 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 2 states and 184 transitions. [2021-11-13 18:23:39,422 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 3 states, 2 states have (on average 92.0) internal successors, (184), 2 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:39,431 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 3 states, 3 states have (on average 96.0) internal successors, (288), 3 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:39,431 INFO L81 ComplementDD]: Finished complementDD. Result has 3 states, 3 states have (on average 96.0) internal successors, (288), 3 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:39,433 INFO L186 Difference]: Start difference. First operand has 94 places, 94 transitions, 194 flow. Second operand 2 states and 184 transitions. [2021-11-13 18:23:39,435 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 94 places, 89 transitions, 188 flow [2021-11-13 18:23:39,442 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 92 places, 89 transitions, 186 flow, removed 0 selfloop flow, removed 2 redundant places. [2021-11-13 18:23:39,455 INFO L242 Difference]: Finished difference. Result has 92 places, 89 transitions, 182 flow [2021-11-13 18:23:39,457 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=182, PETRI_DIFFERENCE_MINUEND_PLACES=91, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=89, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=0, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=89, PETRI_DIFFERENCE_SUBTRAHEND_STATES=2, PETRI_FLOW=182, PETRI_PLACES=92, PETRI_TRANSITIONS=89} [2021-11-13 18:23:39,464 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, -2 predicate places. [2021-11-13 18:23:39,464 INFO L470 AbstractCegarLoop]: Abstraction has has 92 places, 89 transitions, 182 flow [2021-11-13 18:23:39,464 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 90.5) internal successors, (181), 2 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:39,465 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-11-13 18:23:39,465 INFO L254 CegarLoopForPetriNet]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:23:39,465 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2021-11-13 18:23:39,466 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-11-13 18:23:39,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:23:39,467 INFO L85 PathProgramCache]: Analyzing trace with hash 560415153, now seen corresponding path program 1 times [2021-11-13 18:23:39,467 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:23:39,467 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381550453] [2021-11-13 18:23:39,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:23:39,468 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:23:39,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:23:39,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:23:39,620 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:23:39,621 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [381550453] [2021-11-13 18:23:39,622 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [381550453] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:23:39,622 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:23:39,622 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:23:39,623 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1715271944] [2021-11-13 18:23:39,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:23:39,626 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2021-11-13 18:23:39,626 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:23:39,627 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:23:39,627 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:23:39,630 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 83 out of 96 [2021-11-13 18:23:39,630 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 92 places, 89 transitions, 182 flow. Second operand has 3 states, 3 states have (on average 84.66666666666667) internal successors, (254), 3 states have internal predecessors, (254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:39,630 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-11-13 18:23:39,631 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 83 of 96 [2021-11-13 18:23:39,631 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-11-13 18:23:39,730 INFO L129 PetriNetUnfolder]: 3/95 cut-off events. [2021-11-13 18:23:39,731 INFO L130 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2021-11-13 18:23:39,753 INFO L84 FinitePrefix]: Finished finitePrefix Result has 113 conditions, 95 events. 3/95 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 60 event pairs, 0 based on Foata normal form. 0/91 useless extension candidates. Maximal degree in co-relation 110. Up to 6 conditions per place. [2021-11-13 18:23:39,754 INFO L132 encePairwiseOnDemand]: 93/96 looper letters, 9 selfloop transitions, 2 changer transitions 0/92 dead transitions. [2021-11-13 18:23:39,754 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 94 places, 92 transitions, 210 flow [2021-11-13 18:23:39,755 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:23:39,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2021-11-13 18:23:39,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 261 transitions. [2021-11-13 18:23:39,758 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.90625 [2021-11-13 18:23:39,758 INFO L72 ComplementDD]: Start complementDD. Operand 3 states and 261 transitions. [2021-11-13 18:23:39,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3 states and 261 transitions. [2021-11-13 18:23:39,759 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:23:39,759 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 3 states and 261 transitions. [2021-11-13 18:23:39,761 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 4 states, 3 states have (on average 87.0) internal successors, (261), 3 states have internal predecessors, (261), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:39,765 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 4 states, 4 states have (on average 96.0) internal successors, (384), 4 states have internal predecessors, (384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:39,765 INFO L81 ComplementDD]: Finished complementDD. Result has 4 states, 4 states have (on average 96.0) internal successors, (384), 4 states have internal predecessors, (384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:39,766 INFO L186 Difference]: Start difference. First operand has 92 places, 89 transitions, 182 flow. Second operand 3 states and 261 transitions. [2021-11-13 18:23:39,766 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 94 places, 92 transitions, 210 flow [2021-11-13 18:23:39,768 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 94 places, 92 transitions, 210 flow, removed 0 selfloop flow, removed 0 redundant places. [2021-11-13 18:23:39,785 INFO L242 Difference]: Finished difference. Result has 95 places, 90 transitions, 194 flow [2021-11-13 18:23:39,786 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=182, PETRI_DIFFERENCE_MINUEND_PLACES=92, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=89, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=1, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=87, PETRI_DIFFERENCE_SUBTRAHEND_STATES=3, PETRI_FLOW=194, PETRI_PLACES=95, PETRI_TRANSITIONS=90} [2021-11-13 18:23:39,787 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, 1 predicate places. [2021-11-13 18:23:39,787 INFO L470 AbstractCegarLoop]: Abstraction has has 95 places, 90 transitions, 194 flow [2021-11-13 18:23:39,787 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 84.66666666666667) internal successors, (254), 3 states have internal predecessors, (254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:39,788 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-11-13 18:23:39,788 INFO L254 CegarLoopForPetriNet]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:23:39,788 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2021-11-13 18:23:39,788 INFO L402 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-11-13 18:23:39,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:23:39,789 INFO L85 PathProgramCache]: Analyzing trace with hash -951035470, now seen corresponding path program 1 times [2021-11-13 18:23:39,789 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:23:39,790 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [25427253] [2021-11-13 18:23:39,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:23:39,790 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:23:39,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:23:39,953 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:23:39,955 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:23:39,955 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [25427253] [2021-11-13 18:23:39,955 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [25427253] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-13 18:23:39,956 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1057191676] [2021-11-13 18:23:39,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:23:39,956 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-13 18:23:39,957 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 [2021-11-13 18:23:39,963 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-13 18:23:39,982 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2021-11-13 18:23:40,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:23:40,089 INFO L263 TraceCheckSpWp]: Trace formula consists of 145 conjuncts, 4 conjunts are in the unsatisfiable core [2021-11-13 18:23:40,106 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-13 18:23:40,341 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:23:40,341 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-13 18:23:40,498 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:23:40,499 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1057191676] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-13 18:23:40,499 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-13 18:23:40,499 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 10 [2021-11-13 18:23:40,500 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [403874476] [2021-11-13 18:23:40,500 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-13 18:23:40,502 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2021-11-13 18:23:40,503 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:23:40,504 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2021-11-13 18:23:40,505 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2021-11-13 18:23:40,509 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 81 out of 96 [2021-11-13 18:23:40,510 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 95 places, 90 transitions, 194 flow. Second operand has 10 states, 10 states have (on average 83.0) internal successors, (830), 10 states have internal predecessors, (830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:40,511 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-11-13 18:23:40,511 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 81 of 96 [2021-11-13 18:23:40,511 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-11-13 18:23:40,640 INFO L129 PetriNetUnfolder]: 3/104 cut-off events. [2021-11-13 18:23:40,640 INFO L130 PetriNetUnfolder]: For 3/3 co-relation queries the response was YES. [2021-11-13 18:23:40,641 INFO L84 FinitePrefix]: Finished finitePrefix Result has 138 conditions, 104 events. 3/104 cut-off events. For 3/3 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 51 event pairs, 0 based on Foata normal form. 2/103 useless extension candidates. Maximal degree in co-relation 133. Up to 6 conditions per place. [2021-11-13 18:23:40,642 INFO L132 encePairwiseOnDemand]: 90/96 looper letters, 10 selfloop transitions, 9 changer transitions 0/98 dead transitions. [2021-11-13 18:23:40,642 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 103 places, 98 transitions, 250 flow [2021-11-13 18:23:40,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-11-13 18:23:40,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9 states. [2021-11-13 18:23:40,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 750 transitions. [2021-11-13 18:23:40,653 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.8680555555555556 [2021-11-13 18:23:40,653 INFO L72 ComplementDD]: Start complementDD. Operand 9 states and 750 transitions. [2021-11-13 18:23:40,654 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 750 transitions. [2021-11-13 18:23:40,654 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:23:40,654 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 9 states and 750 transitions. [2021-11-13 18:23:40,658 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 10 states, 9 states have (on average 83.33333333333333) internal successors, (750), 9 states have internal predecessors, (750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:40,668 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 10 states, 10 states have (on average 96.0) internal successors, (960), 10 states have internal predecessors, (960), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:40,669 INFO L81 ComplementDD]: Finished complementDD. Result has 10 states, 10 states have (on average 96.0) internal successors, (960), 10 states have internal predecessors, (960), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:40,670 INFO L186 Difference]: Start difference. First operand has 95 places, 90 transitions, 194 flow. Second operand 9 states and 750 transitions. [2021-11-13 18:23:40,670 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 103 places, 98 transitions, 250 flow [2021-11-13 18:23:40,674 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 102 places, 98 transitions, 248 flow, removed 0 selfloop flow, removed 1 redundant places. [2021-11-13 18:23:40,703 INFO L242 Difference]: Finished difference. Result has 105 places, 96 transitions, 242 flow [2021-11-13 18:23:40,703 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=192, PETRI_DIFFERENCE_MINUEND_PLACES=94, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=90, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=5, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=84, PETRI_DIFFERENCE_SUBTRAHEND_STATES=9, PETRI_FLOW=242, PETRI_PLACES=105, PETRI_TRANSITIONS=96} [2021-11-13 18:23:40,704 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, 11 predicate places. [2021-11-13 18:23:40,704 INFO L470 AbstractCegarLoop]: Abstraction has has 105 places, 96 transitions, 242 flow [2021-11-13 18:23:40,705 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 83.0) internal successors, (830), 10 states have internal predecessors, (830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:40,705 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-11-13 18:23:40,705 INFO L254 CegarLoopForPetriNet]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:23:40,735 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2021-11-13 18:23:40,931 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-13 18:23:40,932 INFO L402 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-11-13 18:23:40,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:23:40,932 INFO L85 PathProgramCache]: Analyzing trace with hash 1666707666, now seen corresponding path program 2 times [2021-11-13 18:23:40,933 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:23:40,933 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [104517441] [2021-11-13 18:23:40,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:23:40,933 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:23:40,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:23:41,072 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:23:41,073 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:23:41,077 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [104517441] [2021-11-13 18:23:41,077 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [104517441] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-13 18:23:41,078 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [376040182] [2021-11-13 18:23:41,078 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-13 18:23:41,078 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-13 18:23:41,078 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 [2021-11-13 18:23:41,083 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-13 18:23:41,105 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2021-11-13 18:23:41,176 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-13 18:23:41,177 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-13 18:23:41,179 INFO L263 TraceCheckSpWp]: Trace formula consists of 169 conjuncts, 8 conjunts are in the unsatisfiable core [2021-11-13 18:23:41,184 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-13 18:23:41,397 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:23:41,397 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-13 18:23:41,624 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:23:41,625 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [376040182] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-13 18:23:41,625 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-13 18:23:41,625 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 18 [2021-11-13 18:23:41,626 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [62470814] [2021-11-13 18:23:41,626 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-13 18:23:41,626 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2021-11-13 18:23:41,627 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:23:41,627 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2021-11-13 18:23:41,628 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=216, Unknown=0, NotChecked=0, Total=306 [2021-11-13 18:23:41,631 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 81 out of 96 [2021-11-13 18:23:41,633 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 105 places, 96 transitions, 242 flow. Second operand has 18 states, 18 states have (on average 83.0) internal successors, (1494), 18 states have internal predecessors, (1494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:41,634 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-11-13 18:23:41,634 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 81 of 96 [2021-11-13 18:23:41,634 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-11-13 18:23:41,889 INFO L129 PetriNetUnfolder]: 3/132 cut-off events. [2021-11-13 18:23:41,889 INFO L130 PetriNetUnfolder]: For 30/30 co-relation queries the response was YES. [2021-11-13 18:23:41,891 INFO L84 FinitePrefix]: Finished finitePrefix Result has 231 conditions, 132 events. 3/132 cut-off events. For 30/30 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 51 event pairs, 0 based on Foata normal form. 4/133 useless extension candidates. Maximal degree in co-relation 224. Up to 11 conditions per place. [2021-11-13 18:23:41,892 INFO L132 encePairwiseOnDemand]: 90/96 looper letters, 14 selfloop transitions, 21 changer transitions 0/114 dead transitions. [2021-11-13 18:23:41,893 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 125 places, 114 transitions, 408 flow [2021-11-13 18:23:41,893 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-11-13 18:23:41,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2021-11-13 18:23:41,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 1740 transitions. [2021-11-13 18:23:41,900 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.8630952380952381 [2021-11-13 18:23:41,901 INFO L72 ComplementDD]: Start complementDD. Operand 21 states and 1740 transitions. [2021-11-13 18:23:41,901 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 1740 transitions. [2021-11-13 18:23:41,903 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:23:41,903 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 21 states and 1740 transitions. [2021-11-13 18:23:41,910 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 22 states, 21 states have (on average 82.85714285714286) internal successors, (1740), 21 states have internal predecessors, (1740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:41,917 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 22 states, 22 states have (on average 96.0) internal successors, (2112), 22 states have internal predecessors, (2112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:41,919 INFO L81 ComplementDD]: Finished complementDD. Result has 22 states, 22 states have (on average 96.0) internal successors, (2112), 22 states have internal predecessors, (2112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:41,919 INFO L186 Difference]: Start difference. First operand has 105 places, 96 transitions, 242 flow. Second operand 21 states and 1740 transitions. [2021-11-13 18:23:41,919 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 125 places, 114 transitions, 408 flow [2021-11-13 18:23:41,922 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 124 places, 114 transitions, 394 flow, removed 6 selfloop flow, removed 1 redundant places. [2021-11-13 18:23:41,926 INFO L242 Difference]: Finished difference. Result has 129 places, 109 transitions, 366 flow [2021-11-13 18:23:41,926 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=236, PETRI_DIFFERENCE_MINUEND_PLACES=104, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=96, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=10, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=85, PETRI_DIFFERENCE_SUBTRAHEND_STATES=21, PETRI_FLOW=366, PETRI_PLACES=129, PETRI_TRANSITIONS=109} [2021-11-13 18:23:41,927 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, 35 predicate places. [2021-11-13 18:23:41,928 INFO L470 AbstractCegarLoop]: Abstraction has has 129 places, 109 transitions, 366 flow [2021-11-13 18:23:41,929 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 83.0) internal successors, (1494), 18 states have internal predecessors, (1494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:41,929 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-11-13 18:23:41,929 INFO L254 CegarLoopForPetriNet]: trace histogram [7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:23:41,957 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2021-11-13 18:23:42,147 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-13 18:23:42,147 INFO L402 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-11-13 18:23:42,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:23:42,148 INFO L85 PathProgramCache]: Analyzing trace with hash -1283180782, now seen corresponding path program 3 times [2021-11-13 18:23:42,148 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:23:42,148 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [83417438] [2021-11-13 18:23:42,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:23:42,148 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:23:42,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:23:42,424 INFO L134 CoverageAnalysis]: Checked inductivity of 154 backedges. 0 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:23:42,424 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:23:42,425 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [83417438] [2021-11-13 18:23:42,425 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [83417438] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-13 18:23:42,425 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1619770084] [2021-11-13 18:23:42,425 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-13 18:23:42,426 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-13 18:23:42,427 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 [2021-11-13 18:23:42,435 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-13 18:23:42,437 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2021-11-13 18:23:42,533 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2021-11-13 18:23:42,533 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-13 18:23:42,535 INFO L263 TraceCheckSpWp]: Trace formula consists of 217 conjuncts, 16 conjunts are in the unsatisfiable core [2021-11-13 18:23:42,538 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-13 18:23:42,792 INFO L134 CoverageAnalysis]: Checked inductivity of 154 backedges. 0 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:23:42,792 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-13 18:23:43,264 INFO L134 CoverageAnalysis]: Checked inductivity of 154 backedges. 0 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:23:43,265 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1619770084] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-13 18:23:43,265 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-13 18:23:43,265 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17] total 31 [2021-11-13 18:23:43,265 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [797334865] [2021-11-13 18:23:43,265 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-13 18:23:43,266 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 31 states [2021-11-13 18:23:43,266 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:23:43,267 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2021-11-13 18:23:43,267 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=255, Invalid=675, Unknown=0, NotChecked=0, Total=930 [2021-11-13 18:23:43,281 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 81 out of 96 [2021-11-13 18:23:43,290 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 129 places, 109 transitions, 366 flow. Second operand has 31 states, 31 states have (on average 83.06451612903226) internal successors, (2575), 31 states have internal predecessors, (2575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:43,290 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-11-13 18:23:43,290 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 81 of 96 [2021-11-13 18:23:43,291 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-11-13 18:23:43,857 INFO L129 PetriNetUnfolder]: 3/181 cut-off events. [2021-11-13 18:23:43,858 INFO L130 PetriNetUnfolder]: For 236/236 co-relation queries the response was YES. [2021-11-13 18:23:43,860 INFO L84 FinitePrefix]: Finished finitePrefix Result has 427 conditions, 181 events. 3/181 cut-off events. For 236/236 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 51 event pairs, 0 based on Foata normal form. 7/185 useless extension candidates. Maximal degree in co-relation 415. Up to 25 conditions per place. [2021-11-13 18:23:43,861 INFO L132 encePairwiseOnDemand]: 90/96 looper letters, 21 selfloop transitions, 42 changer transitions 0/142 dead transitions. [2021-11-13 18:23:43,861 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 170 places, 142 transitions, 748 flow [2021-11-13 18:23:43,867 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2021-11-13 18:23:43,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2021-11-13 18:23:43,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 3472 transitions. [2021-11-13 18:23:43,881 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.8611111111111112 [2021-11-13 18:23:43,882 INFO L72 ComplementDD]: Start complementDD. Operand 42 states and 3472 transitions. [2021-11-13 18:23:43,882 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 3472 transitions. [2021-11-13 18:23:43,885 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:23:43,885 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 42 states and 3472 transitions. [2021-11-13 18:23:43,897 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 43 states, 42 states have (on average 82.66666666666667) internal successors, (3472), 42 states have internal predecessors, (3472), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:43,909 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 43 states, 43 states have (on average 96.0) internal successors, (4128), 43 states have internal predecessors, (4128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:43,911 INFO L81 ComplementDD]: Finished complementDD. Result has 43 states, 43 states have (on average 96.0) internal successors, (4128), 43 states have internal predecessors, (4128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:43,912 INFO L186 Difference]: Start difference. First operand has 129 places, 109 transitions, 366 flow. Second operand 42 states and 3472 transitions. [2021-11-13 18:23:43,912 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 170 places, 142 transitions, 748 flow [2021-11-13 18:23:43,921 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 164 places, 142 transitions, 710 flow, removed 13 selfloop flow, removed 6 redundant places. [2021-11-13 18:23:43,926 INFO L242 Difference]: Finished difference. Result has 172 places, 131 transitions, 614 flow [2021-11-13 18:23:43,926 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=342, PETRI_DIFFERENCE_MINUEND_PLACES=123, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=109, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=22, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=86, PETRI_DIFFERENCE_SUBTRAHEND_STATES=42, PETRI_FLOW=614, PETRI_PLACES=172, PETRI_TRANSITIONS=131} [2021-11-13 18:23:43,930 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, 78 predicate places. [2021-11-13 18:23:43,930 INFO L470 AbstractCegarLoop]: Abstraction has has 172 places, 131 transitions, 614 flow [2021-11-13 18:23:43,932 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 31 states, 31 states have (on average 83.06451612903226) internal successors, (2575), 31 states have internal predecessors, (2575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:23:43,932 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-11-13 18:23:43,932 INFO L254 CegarLoopForPetriNet]: trace histogram [14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:23:43,970 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2021-11-13 18:23:44,155 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-13 18:23:44,155 INFO L402 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-11-13 18:23:44,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:23:44,156 INFO L85 PathProgramCache]: Analyzing trace with hash 2049692625, now seen corresponding path program 4 times [2021-11-13 18:23:44,156 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:23:44,156 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [183382151] [2021-11-13 18:23:44,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:23:44,156 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:23:44,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:23:46,029 INFO L134 CoverageAnalysis]: Checked inductivity of 651 backedges. 0 proven. 651 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:23:46,030 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:23:46,030 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [183382151] [2021-11-13 18:23:46,030 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [183382151] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-13 18:23:46,030 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1689219246] [2021-11-13 18:23:46,031 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-13 18:23:46,031 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-13 18:23:46,031 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 [2021-11-13 18:23:46,052 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-13 18:23:46,053 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c57c60b-cc26-40b7-84c5-f855371b4e51/bin/uautomizer-YU5uOKAj3y/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2021-11-13 18:23:46,139 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-13 18:23:46,139 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-13 18:23:46,141 INFO L263 TraceCheckSpWp]: Trace formula consists of 282 conjuncts, 47 conjunts are in the unsatisfiable core [2021-11-13 18:23:46,148 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-13 18:23:50,568 INFO L134 CoverageAnalysis]: Checked inductivity of 651 backedges. 486 proven. 165 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:23:50,568 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-13 18:33:29,621 INFO L134 CoverageAnalysis]: Checked inductivity of 651 backedges. 0 proven. 649 refuted. 2 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:33:29,622 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1689219246] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-13 18:33:29,622 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-13 18:33:29,622 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 139 [2021-11-13 18:33:29,622 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1712885318] [2021-11-13 18:33:29,622 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-13 18:33:29,624 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 139 states [2021-11-13 18:33:29,624 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:33:29,625 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 139 interpolants. [2021-11-13 18:33:29,635 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1221, Invalid=17800, Unknown=161, NotChecked=0, Total=19182 [2021-11-13 18:33:29,646 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 68 out of 96 [2021-11-13 18:33:29,659 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 172 places, 131 transitions, 614 flow. Second operand has 139 states, 139 states have (on average 69.23741007194245) internal successors, (9624), 139 states have internal predecessors, (9624), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:33:29,659 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-11-13 18:33:29,660 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 68 of 96 [2021-11-13 18:33:29,660 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-11-13 18:37:02,323 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (* c_~i~0 (- 1))) (.cse15 (+ (* 2 c_~cur~0) c_~prev~0 3)) (.cse14 (* c_~j~0 (- 1))) (.cse1 (+ c_~prev~0 c_~cur~0 1))) (and (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= (div (+ .cse0 c_~cur~0 (- 3)) (- 2)) .cse1) (<= 1 c_~cur~0) (forall ((v_~cur~0_28 Int)) (or (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse2 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse2 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse2 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse3 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse3 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse3 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)))))) (< v_~cur~0_28 (+ c_~prev~0 c_~cur~0)))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse4 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse4 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse4 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse5 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse5 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse5 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~j~0_8 Int)) (or (and (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse6 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse6 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse6 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 v_~j~0_8) (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 (* 2 aux_mod_v_~cur~0_22_51) 11 v_~j~0_8) (+ (* 3 v_~prev~0_24) .cse7 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)))))) (< 1 v_~j~0_8))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~prev~0 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse8 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse9 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse10 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse10 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse10 c_~prev~0 c_~cur~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (<= 0 c_~prev~0) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse11 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse11 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse11 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (= c_~cur~0 1) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse12 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse12 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse12 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse13 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse13 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse13 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (<= (div (+ .cse14 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse15) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse0 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse15) (<= (div (+ .cse14 c_~cur~0 (- 3)) (- 2)) .cse1))) is different from false [2021-11-13 18:37:05,695 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse10 (* c_~j~0 (- 1))) (.cse14 (* c_~i~0 (- 1)))) (let ((.cse0 (div (+ .cse14 c_~cur~0 (- 3)) (- 2))) (.cse2 (+ c_~next~0 1)) (.cse11 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse23 (+ c_~next~0 c_~prev~0 2)) (.cse24 (div (+ .cse10 c_~next~0 (- 5)) (- 2))) (.cse22 (div (+ .cse14 c_~next~0 (- 5)) (- 2))) (.cse25 (+ c_~next~0 c_~cur~0 2)) (.cse21 (+ (* 2 c_~cur~0) c_~prev~0 3)) (.cse3 (div (+ .cse10 c_~cur~0 (- 3)) (- 2))) (.cse1 (+ c_~prev~0 c_~cur~0 1))) (and (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= .cse0 .cse1) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= .cse0 .cse2) (<= 1 c_~cur~0) (<= .cse3 .cse2) (forall ((v_~cur~0_28 Int)) (or (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse4 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse4 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse4 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse5 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse5 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse5 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)))))) (< v_~cur~0_28 (+ c_~prev~0 c_~cur~0)))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse6 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse6 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse6 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse7 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~j~0_8 Int)) (or (and (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse8 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 v_~j~0_8) (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 (* 2 aux_mod_v_~cur~0_22_51) 11 v_~j~0_8) (+ (* 3 v_~prev~0_24) .cse9 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)))))) (< 1 v_~j~0_8))) (<= (div (+ .cse10 (- 9) c_~next~0 c_~cur~0) (- 2)) .cse11) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse12 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse12 c_~prev~0 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse12 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse13 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse13 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse13 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (<= (div (+ (- 9) .cse14 c_~next~0 c_~cur~0) (- 2)) .cse11) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse15 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse15 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse15 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse16 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse16 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse16 c_~prev~0 c_~cur~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= 0 c_~prev~0) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse17 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse17 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse17 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (= c_~cur~0 1) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse18 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse18 c_~next~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse18 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse19 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse19 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse19 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse20 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse20 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse20 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (<= (div (+ .cse10 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse21) (<= .cse22 .cse23) (<= .cse24 .cse23) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= .cse24 .cse25) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse26 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse26 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse26 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse27 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse27 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse27 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (<= .cse22 .cse25) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse28 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse28 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< aux_div_v_~cur~0_22_51 (+ .cse28 c_~next~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (<= (div (+ .cse14 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse21) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse29 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse29 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse29 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (<= .cse3 .cse1) (forall ((v_~cur~0_28 Int)) (or (< v_~cur~0_28 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse30 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse30 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse30 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse31 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse31 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse31 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56)))))))) is different from false [2021-11-13 18:37:12,167 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse10 (* c_~j~0 (- 1))) (.cse14 (* c_~i~0 (- 1)))) (let ((.cse0 (div (+ .cse14 c_~cur~0 (- 3)) (- 2))) (.cse2 (+ c_~next~0 1)) (.cse11 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse23 (+ c_~next~0 c_~prev~0 2)) (.cse24 (div (+ .cse10 c_~next~0 (- 5)) (- 2))) (.cse22 (div (+ .cse14 c_~next~0 (- 5)) (- 2))) (.cse25 (+ c_~next~0 c_~cur~0 2)) (.cse21 (+ (* 2 c_~cur~0) c_~prev~0 3)) (.cse3 (div (+ .cse10 c_~cur~0 (- 3)) (- 2))) (.cse1 (+ c_~prev~0 c_~cur~0 1))) (and (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= .cse0 .cse1) (= c_~prev~0 0) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= .cse0 .cse2) (<= .cse3 .cse2) (forall ((v_~cur~0_28 Int)) (or (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse4 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse4 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse4 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse5 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse5 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse5 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)))))) (< v_~cur~0_28 (+ c_~prev~0 c_~cur~0)))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse6 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse6 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse6 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse7 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~j~0_8 Int)) (or (and (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse8 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 v_~j~0_8) (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 (* 2 aux_mod_v_~cur~0_22_51) 11 v_~j~0_8) (+ (* 3 v_~prev~0_24) .cse9 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)))))) (< 1 v_~j~0_8))) (<= (div (+ .cse10 (- 9) c_~next~0 c_~cur~0) (- 2)) .cse11) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse12 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse12 c_~prev~0 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse12 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse13 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse13 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse13 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (<= (div (+ (- 9) .cse14 c_~next~0 c_~cur~0) (- 2)) .cse11) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse15 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse15 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse15 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse16 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse16 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse16 c_~prev~0 c_~cur~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse17 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse17 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse17 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (= c_~cur~0 1) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse18 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse18 c_~next~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse18 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse19 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse19 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse19 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse20 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse20 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse20 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (<= (div (+ .cse10 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse21) (<= .cse22 .cse23) (<= .cse24 .cse23) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= .cse24 .cse25) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse26 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse26 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse26 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse27 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse27 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse27 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (<= .cse22 .cse25) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse28 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse28 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< aux_div_v_~cur~0_22_51 (+ .cse28 c_~next~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (<= (div (+ .cse14 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse21) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse29 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse29 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse29 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (<= .cse3 .cse1) (forall ((v_~cur~0_28 Int)) (or (< v_~cur~0_28 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse30 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse30 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse30 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse31 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse31 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse31 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56)))))))) is different from false [2021-11-13 18:37:14,585 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse1 (+ c_~next~0 1)) (.cse3 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse2 (* c_~j~0 (- 1))) (.cse0 (* c_~i~0 (- 1))) (.cse6 (+ c_~next~0 c_~cur~0 2))) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse0 c_~cur~0 (- 3)) (- 2)) .cse1) (<= (div (+ .cse2 c_~cur~0 (- 3)) (- 2)) .cse1) (<= (div (+ .cse2 (- 9) c_~next~0 c_~cur~0) (- 2)) .cse3) (<= (div (+ (- 9) .cse0 c_~next~0 c_~cur~0) (- 2)) .cse3) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse4 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse4 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse4 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse5 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse5 c_~next~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse5 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (<= (div (+ .cse2 c_~next~0 (- 5)) (- 2)) .cse6) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse7 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse8 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (<= (div (+ .cse0 c_~next~0 (- 5)) (- 2)) .cse6) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse9 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~next~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse10 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse10 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse10 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int)) (or (< v_~cur~0_28 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse11 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse11 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse11 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse12 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse12 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse12 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))))))) is different from false [2021-11-13 18:37:17,417 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse7 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse6 (* c_~j~0 (- 1))) (.cse18 (+ c_~next~0 c_~cur~0 2)) (.cse10 (* c_~i~0 (- 1))) (.cse17 (+ (* 2 c_~cur~0) c_~prev~0 3))) (and (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (= c_~prev~0 0) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~cur~0_28 Int)) (or (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse0 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse0 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse1 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse1 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse1 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)))))) (< v_~cur~0_28 (+ c_~prev~0 c_~cur~0)))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse2 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse2 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse2 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse3 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse3 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse3 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~j~0_8 Int)) (or (and (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse4 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse4 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse4 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse5 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 v_~j~0_8) (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse5 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 (* 2 aux_mod_v_~cur~0_22_51) 11 v_~j~0_8) (+ (* 3 v_~prev~0_24) .cse5 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)))))) (< 1 v_~j~0_8))) (<= (div (+ .cse6 (- 9) c_~next~0 c_~cur~0) (- 2)) .cse7) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~prev~0 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse8 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse9 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (<= (div (+ (- 9) .cse10 c_~next~0 c_~cur~0) (- 2)) .cse7) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse11 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse11 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse11 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse12 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse12 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse12 c_~prev~0 c_~cur~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse13 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse13 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse13 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (= c_~cur~0 1) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse14 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse14 c_~next~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse14 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse15 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse15 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse15 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse16 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse16 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse16 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (<= (div (+ .cse6 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse17) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse6 c_~next~0 (- 5)) (- 2)) .cse18) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse19 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse19 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse19 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse20 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse20 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse20 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (<= (div (+ .cse10 c_~next~0 (- 5)) (- 2)) .cse18) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse21 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse21 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< aux_div_v_~cur~0_22_51 (+ .cse21 c_~next~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (<= (div (+ .cse10 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse17) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse22 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse22 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse22 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int)) (or (< v_~cur~0_28 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse23 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse23 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse23 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse24 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse24 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse24 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))))))) is different from false [2021-11-13 18:37:19,884 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (* c_~i~0 (- 1))) (.cse1 (+ c_~next~0 1)) (.cse11 (* c_~j~0 (- 1))) (.cse9 (+ c_~next~0 c_~prev~0 2))) (and (< (div (+ (- 1) .cse0 c_~prev~0) (- 2)) .cse1) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse2 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse2 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse2 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~cur~0_26 (+ c_~next~0 c_~prev~0))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse3 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse3 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~cur~0_26 (+ c_~next~0 c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse3 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse4 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse4 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< aux_div_v_~cur~0_22_51 (+ .cse4 c_~next~0 v_~cur~0_28 1)) (< v_~cur~0_28 (+ c_~next~0 c_~prev~0)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((v_~cur~0_26 Int)) (or (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse5 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse5 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ .cse5 c_~prev~0 1)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~prev~0 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse6 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse6 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ .cse6 c_~prev~0 1)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~prev~0 v_~cur~0_26)))))) (< v_~cur~0_26 c_~next~0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~prev~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~cur~0_28 Int)) (or (< v_~cur~0_28 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_26 (+ c_~prev~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 (+ c_~prev~0 v_~cur~0_28 v_~cur~0_26)) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~prev~0 v_~cur~0_28 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse7 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_26 (+ c_~prev~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~prev~0_24 (+ c_~prev~0 v_~cur~0_28 v_~cur~0_26)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~prev~0 v_~cur~0_28 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse8 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_div_v_~cur~0_21_56 Int) (aux_mod_v_~cur~0_21_56 Int)) (or (<= (+ c_~prev~0 (* 5 aux_div_v_~cur~0_21_56)) (+ (* 2 c_~j~0) (* 2 aux_mod_v_~cur~0_21_56) 17)) (<= 2 aux_mod_v_~cur~0_21_56) (< (+ 7 c_~j~0 aux_mod_v_~cur~0_21_56) (+ (* 2 aux_div_v_~cur~0_21_56) c_~next~0 c_~prev~0)) (< aux_mod_v_~cur~0_21_56 0))) (forall ((aux_div_v_~cur~0_21_56 Int) (aux_mod_v_~cur~0_21_56 Int)) (or (< (+ 7 c_~i~0 aux_mod_v_~cur~0_21_56) (+ (* 2 aux_div_v_~cur~0_21_56) c_~next~0 c_~prev~0)) (<= 2 aux_mod_v_~cur~0_21_56) (<= (+ c_~prev~0 (* 5 aux_div_v_~cur~0_21_56)) (+ (* 2 aux_mod_v_~cur~0_21_56) 17 (* 2 c_~i~0))) (< aux_mod_v_~cur~0_21_56 0))) (<= (div (+ .cse0 c_~next~0 (- 5)) (- 2)) .cse9) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse10 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse10 c_~next~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_28 (+ c_~next~0 c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse10 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (< (div (+ .cse11 (- 1) c_~prev~0) (- 2)) .cse1) (<= (div (+ .cse11 c_~next~0 (- 5)) (- 2)) .cse9) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~prev~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) c_~prev~0) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) (* 3 c_~prev~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) c_~prev~0) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) (* 3 c_~prev~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ c_~next~0 c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))))) is different from false [2021-11-13 18:37:29,007 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse13 (* 2 c_~cur~0))) (let ((.cse12 (+ .cse13 c_~prev~0)) (.cse0 (* c_~i~0 (- 1))) (.cse11 (+ .cse13 c_~prev~0 3)) (.cse10 (* c_~j~0 (- 1))) (.cse1 (+ c_~prev~0 c_~cur~0 1))) (and (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= (div (+ .cse0 c_~cur~0 (- 3)) (- 2)) .cse1) (forall ((v_~cur~0_28 Int)) (or (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse2 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse2 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse2 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse3 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse3 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse3 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)))))) (< v_~cur~0_28 (+ c_~prev~0 c_~cur~0)))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse4 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse4 c_~prev~0 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse4 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse5 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse5 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse5 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse6 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse6 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse6 c_~prev~0 c_~cur~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse7 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse8 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse9 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (<= (div (+ .cse10 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse11) (< c_~i~0 .cse12) (< c_~j~0 .cse12) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse0 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse11) (<= (div (+ .cse10 c_~cur~0 (- 3)) (- 2)) .cse1)))) is different from false [2021-11-13 18:37:34,221 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse5 (* c_~j~0 (- 1))) (.cse22 (* 2 c_~cur~0)) (.cse0 (* c_~i~0 (- 1)))) (let ((.cse2 (div (+ .cse0 c_~cur~0 (- 3)) (- 2))) (.cse6 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse1 (+ c_~next~0 1)) (.cse11 (+ c_~next~0 c_~prev~0 2)) (.cse12 (+ .cse22 c_~prev~0)) (.cse13 (div (+ .cse5 c_~next~0 (- 5)) (- 2))) (.cse10 (div (+ .cse0 c_~next~0 (- 5)) (- 2))) (.cse15 (+ c_~next~0 c_~cur~0 2)) (.cse9 (+ .cse22 c_~prev~0 3)) (.cse14 (+ c_~next~0 c_~cur~0)) (.cse4 (div (+ .cse5 c_~cur~0 (- 3)) (- 2))) (.cse3 (+ c_~prev~0 c_~cur~0 1))) (and (< (div (+ (- 1) .cse0 c_~prev~0) (- 2)) .cse1) (<= .cse2 .cse3) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= .cse2 .cse1) (<= 1 c_~cur~0) (<= .cse4 .cse1) (<= (div (+ .cse5 (- 9) c_~next~0 c_~cur~0) (- 2)) .cse6) (<= (div (+ (- 9) .cse0 c_~next~0 c_~cur~0) (- 2)) .cse6) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse7 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= 0 c_~prev~0) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~next~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse8 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (<= (div (+ .cse5 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse9) (<= .cse10 .cse11) (< c_~i~0 .cse12) (< (div (+ .cse5 (- 1) c_~prev~0) (- 2)) .cse1) (<= .cse13 .cse11) (< c_~j~0 .cse12) (< c_~i~0 .cse14) (<= .cse13 .cse15) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse16 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse16 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse16 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse17 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse17 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse17 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (<= .cse10 .cse15) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse18 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse18 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< aux_div_v_~cur~0_22_51 (+ .cse18 c_~next~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (<= (div (+ .cse0 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse9) (< c_~j~0 .cse14) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse19 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse19 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse19 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (<= .cse4 .cse3) (forall ((v_~cur~0_28 Int)) (or (< v_~cur~0_28 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse20 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse20 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse20 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse21 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse21 c_~cur~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse21 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56)))))))) is different from false