./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.12.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0f8a17c6 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/bin/uautomizer-ZXIjhQolGL/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/bin/uautomizer-ZXIjhQolGL/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/bin/uautomizer-ZXIjhQolGL/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/bin/uautomizer-ZXIjhQolGL/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.12.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/bin/uautomizer-ZXIjhQolGL/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/bin/uautomizer-ZXIjhQolGL --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 962623ba1d780e7ad35b9b6d7f5839750bc2f361556d46080824a3701cf71595 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-0f8a17c [2021-11-19 05:20:40,868 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-19 05:20:40,871 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-19 05:20:40,926 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-19 05:20:40,927 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-19 05:20:40,931 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-19 05:20:40,933 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-19 05:20:40,937 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-19 05:20:40,939 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-19 05:20:40,945 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-19 05:20:40,946 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-19 05:20:40,948 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-19 05:20:40,949 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-19 05:20:40,951 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-19 05:20:40,953 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-19 05:20:40,958 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-19 05:20:40,960 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-19 05:20:40,961 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-19 05:20:40,963 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-19 05:20:40,971 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-19 05:20:40,973 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-19 05:20:40,974 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-19 05:20:40,978 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-19 05:20:40,979 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-19 05:20:40,989 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-19 05:20:40,989 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-19 05:20:40,990 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-19 05:20:40,992 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-19 05:20:40,992 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-19 05:20:40,994 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-19 05:20:40,994 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-19 05:20:40,995 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-19 05:20:40,997 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-19 05:20:40,999 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-19 05:20:41,000 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-19 05:20:41,001 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-19 05:20:41,002 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-19 05:20:41,002 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-19 05:20:41,002 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-19 05:20:41,003 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-19 05:20:41,004 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-19 05:20:41,005 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/bin/uautomizer-ZXIjhQolGL/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-19 05:20:41,050 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-19 05:20:41,051 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-19 05:20:41,051 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-19 05:20:41,052 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-19 05:20:41,054 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-19 05:20:41,054 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-19 05:20:41,054 INFO L138 SettingsManager]: * Use SBE=true [2021-11-19 05:20:41,054 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-19 05:20:41,055 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-19 05:20:41,055 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-19 05:20:41,056 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-19 05:20:41,056 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-19 05:20:41,056 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-19 05:20:41,057 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-19 05:20:41,057 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-19 05:20:41,057 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-19 05:20:41,057 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-19 05:20:41,057 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-19 05:20:41,058 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-19 05:20:41,058 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-19 05:20:41,058 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-19 05:20:41,058 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-19 05:20:41,059 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-19 05:20:41,059 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-19 05:20:41,059 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-19 05:20:41,059 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-19 05:20:41,061 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-19 05:20:41,061 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-19 05:20:41,061 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-19 05:20:41,062 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-19 05:20:41,062 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-19 05:20:41,062 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-19 05:20:41,063 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-19 05:20:41,064 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/bin/uautomizer-ZXIjhQolGL/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/bin/uautomizer-ZXIjhQolGL Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 962623ba1d780e7ad35b9b6d7f5839750bc2f361556d46080824a3701cf71595 [2021-11-19 05:20:41,368 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-19 05:20:41,389 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-19 05:20:41,392 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-19 05:20:41,393 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-19 05:20:41,394 INFO L275 PluginConnector]: CDTParser initialized [2021-11-19 05:20:41,395 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/bin/uautomizer-ZXIjhQolGL/../../sv-benchmarks/c/systemc/token_ring.12.cil-1.c [2021-11-19 05:20:41,468 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/bin/uautomizer-ZXIjhQolGL/data/80c793147/6c2a7231bf7d4cf59fe50a0a4a14959f/FLAG7e1668edc [2021-11-19 05:20:41,933 INFO L306 CDTParser]: Found 1 translation units. [2021-11-19 05:20:41,934 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/sv-benchmarks/c/systemc/token_ring.12.cil-1.c [2021-11-19 05:20:41,956 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/bin/uautomizer-ZXIjhQolGL/data/80c793147/6c2a7231bf7d4cf59fe50a0a4a14959f/FLAG7e1668edc [2021-11-19 05:20:42,272 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/bin/uautomizer-ZXIjhQolGL/data/80c793147/6c2a7231bf7d4cf59fe50a0a4a14959f [2021-11-19 05:20:42,275 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-19 05:20:42,277 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-19 05:20:42,278 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-19 05:20:42,279 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-19 05:20:42,282 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-19 05:20:42,283 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 05:20:42" (1/1) ... [2021-11-19 05:20:42,284 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@197adfb4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:20:42, skipping insertion in model container [2021-11-19 05:20:42,285 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 05:20:42" (1/1) ... [2021-11-19 05:20:42,292 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-19 05:20:42,338 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-19 05:20:42,528 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/sv-benchmarks/c/systemc/token_ring.12.cil-1.c[671,684] [2021-11-19 05:20:42,711 INFO L207 PostProcessor]: Analyzing one entry point: main [2021-11-19 05:20:42,737 INFO L203 MainTranslator]: Completed pre-run [2021-11-19 05:20:42,755 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/sv-benchmarks/c/systemc/token_ring.12.cil-1.c[671,684] [2021-11-19 05:20:42,850 INFO L207 PostProcessor]: Analyzing one entry point: main [2021-11-19 05:20:42,884 INFO L208 MainTranslator]: Completed translation [2021-11-19 05:20:42,885 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:20:42 WrapperNode [2021-11-19 05:20:42,885 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-19 05:20:42,886 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-19 05:20:42,887 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-19 05:20:42,887 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-19 05:20:42,895 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:20:42" (1/1) ... [2021-11-19 05:20:42,940 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:20:42" (1/1) ... [2021-11-19 05:20:43,103 INFO L137 Inliner]: procedures = 52, calls = 68, calls flagged for inlining = 63, calls inlined = 270, statements flattened = 4146 [2021-11-19 05:20:43,106 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-19 05:20:43,107 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-19 05:20:43,107 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-19 05:20:43,107 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-19 05:20:43,116 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:20:42" (1/1) ... [2021-11-19 05:20:43,116 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:20:42" (1/1) ... [2021-11-19 05:20:43,127 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:20:42" (1/1) ... [2021-11-19 05:20:43,127 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:20:42" (1/1) ... [2021-11-19 05:20:43,176 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:20:42" (1/1) ... [2021-11-19 05:20:43,218 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:20:42" (1/1) ... [2021-11-19 05:20:43,225 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:20:42" (1/1) ... [2021-11-19 05:20:43,236 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-19 05:20:43,237 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-19 05:20:43,238 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-19 05:20:43,238 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-19 05:20:43,239 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:20:42" (1/1) ... [2021-11-19 05:20:43,246 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-19 05:20:43,256 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/bin/uautomizer-ZXIjhQolGL/z3 [2021-11-19 05:20:43,267 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/bin/uautomizer-ZXIjhQolGL/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-19 05:20:43,299 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ec2e1ce0-a6a1-4325-8dcc-5d823f121917/bin/uautomizer-ZXIjhQolGL/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-19 05:20:43,313 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-11-19 05:20:43,313 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-19 05:20:43,313 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-19 05:20:43,313 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-19 05:20:43,484 INFO L236 CfgBuilder]: Building ICFG [2021-11-19 05:20:43,486 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-11-19 05:20:45,767 INFO L277 CfgBuilder]: Performing block encoding [2021-11-19 05:20:45,841 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-19 05:20:45,842 INFO L301 CfgBuilder]: Removed 15 assume(true) statements. [2021-11-19 05:20:45,848 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 05:20:45 BoogieIcfgContainer [2021-11-19 05:20:45,848 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-19 05:20:45,849 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-19 05:20:45,849 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-19 05:20:45,852 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-19 05:20:45,853 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-19 05:20:45,853 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 05:20:42" (1/3) ... [2021-11-19 05:20:45,854 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@21f48d93 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 05:20:45, skipping insertion in model container [2021-11-19 05:20:45,854 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-19 05:20:45,854 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:20:42" (2/3) ... [2021-11-19 05:20:45,855 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@21f48d93 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 05:20:45, skipping insertion in model container [2021-11-19 05:20:45,855 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-19 05:20:45,855 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 05:20:45" (3/3) ... [2021-11-19 05:20:45,856 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.12.cil-1.c [2021-11-19 05:20:45,925 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-19 05:20:45,926 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-19 05:20:45,926 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-19 05:20:45,926 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-19 05:20:45,926 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-19 05:20:45,926 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-19 05:20:45,926 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-19 05:20:45,926 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-19 05:20:45,997 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1798 states, 1797 states have (on average 1.4997217584863662) internal successors, (2695), 1797 states have internal predecessors, (2695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:46,099 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1631 [2021-11-19 05:20:46,099 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:46,099 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:46,118 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:46,118 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:46,119 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-19 05:20:46,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1798 states, 1797 states have (on average 1.4997217584863662) internal successors, (2695), 1797 states have internal predecessors, (2695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:46,149 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1631 [2021-11-19 05:20:46,149 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:46,149 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:46,155 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:46,155 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:46,165 INFO L791 eck$LassoCheckResult]: Stem: 437#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1725#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 125#L1778true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 113#L846true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1178#L853true assume !(1 == ~m_i~0);~m_st~0 := 2; 979#L853-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 271#L858-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3#L863-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 758#L868-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 885#L873-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1654#L878-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1613#L883-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1685#L888-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 384#L893-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 786#L898-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1787#L903-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 715#L908-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1404#L913-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 846#L1206true assume !(0 == ~M_E~0); 373#L1206-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1172#L1211-1true assume !(0 == ~T2_E~0); 1334#L1216-1true assume !(0 == ~T3_E~0); 261#L1221-1true assume !(0 == ~T4_E~0); 1255#L1226-1true assume !(0 == ~T5_E~0); 92#L1231-1true assume !(0 == ~T6_E~0); 1409#L1236-1true assume !(0 == ~T7_E~0); 1238#L1241-1true assume !(0 == ~T8_E~0); 296#L1246-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 417#L1251-1true assume !(0 == ~T10_E~0); 930#L1256-1true assume !(0 == ~T11_E~0); 8#L1261-1true assume !(0 == ~T12_E~0); 1624#L1266-1true assume !(0 == ~E_M~0); 1566#L1271-1true assume !(0 == ~E_1~0); 874#L1276-1true assume !(0 == ~E_2~0); 1556#L1281-1true assume !(0 == ~E_3~0); 807#L1286-1true assume 0 == ~E_4~0;~E_4~0 := 1; 212#L1291-1true assume !(0 == ~E_5~0); 1651#L1296-1true assume !(0 == ~E_6~0); 650#L1301-1true assume !(0 == ~E_7~0); 1116#L1306-1true assume !(0 == ~E_8~0); 1075#L1311-1true assume !(0 == ~E_9~0); 195#L1316-1true assume !(0 == ~E_10~0); 1490#L1321-1true assume !(0 == ~E_11~0); 662#L1326-1true assume 0 == ~E_12~0;~E_12~0 := 1; 121#L1331-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1782#L598true assume 1 == ~m_pc~0; 151#L599true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1207#L609true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1741#L610true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1432#L1497true assume !(0 != activate_threads_~tmp~1#1); 1686#L1497-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1295#L617true assume !(1 == ~t1_pc~0); 307#L617-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1731#L628true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 234#L629true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1479#L1505true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 726#L1505-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1325#L636true assume 1 == ~t2_pc~0; 292#L637true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 560#L647true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 204#L648true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1469#L1513true assume !(0 != activate_threads_~tmp___1~0#1); 757#L1513-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 492#L655true assume !(1 == ~t3_pc~0); 1439#L655-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1705#L666true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 136#L667true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1789#L1521true assume !(0 != activate_threads_~tmp___2~0#1); 1568#L1521-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1594#L674true assume 1 == ~t4_pc~0; 51#L675true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1663#L685true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 878#L686true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 205#L1529true assume !(0 != activate_threads_~tmp___3~0#1); 490#L1529-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1346#L693true assume !(1 == ~t5_pc~0); 616#L693-2true is_transmit5_triggered_~__retres1~5#1 := 0; 374#L704true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1115#L705true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1080#L1537true assume !(0 != activate_threads_~tmp___4~0#1); 425#L1537-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 387#L712true assume 1 == ~t6_pc~0; 907#L713true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 685#L723true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 952#L724true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1673#L1545true assume !(0 != activate_threads_~tmp___5~0#1); 774#L1545-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 769#L731true assume 1 == ~t7_pc~0; 123#L732true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 226#L742true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 868#L743true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1089#L1553true assume !(0 != activate_threads_~tmp___6~0#1); 995#L1553-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 182#L750true assume !(1 == ~t8_pc~0); 860#L750-2true is_transmit8_triggered_~__retres1~8#1 := 0; 277#L761true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1763#L762true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1102#L1561true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 348#L1561-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 724#L769true assume 1 == ~t9_pc~0; 1732#L770true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 103#L780true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 539#L781true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 926#L1569true assume !(0 != activate_threads_~tmp___8~0#1); 1365#L1569-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1019#L788true assume !(1 == ~t10_pc~0); 626#L788-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1241#L799true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 822#L800true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1141#L1577true assume !(0 != activate_threads_~tmp___9~0#1); 180#L1577-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1026#L807true assume 1 == ~t11_pc~0; 1218#L808true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 759#L818true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1278#L819true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1799#L1585true assume !(0 != activate_threads_~tmp___10~0#1); 1783#L1585-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1182#L826true assume !(1 == ~t12_pc~0); 388#L826-2true is_transmit12_triggered_~__retres1~12#1 := 0; 782#L837true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1610#L838true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1369#L1593true assume !(0 != activate_threads_~tmp___11~0#1); 486#L1593-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 430#L1344true assume !(1 == ~M_E~0); 521#L1344-2true assume !(1 == ~T1_E~0); 1747#L1349-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 655#L1354-1true assume !(1 == ~T3_E~0); 1007#L1359-1true assume !(1 == ~T4_E~0); 1587#L1364-1true assume !(1 == ~T5_E~0); 235#L1369-1true assume !(1 == ~T6_E~0); 983#L1374-1true assume !(1 == ~T7_E~0); 660#L1379-1true assume !(1 == ~T8_E~0); 713#L1384-1true assume !(1 == ~T9_E~0); 1769#L1389-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1246#L1394-1true assume !(1 == ~T11_E~0); 1674#L1399-1true assume !(1 == ~T12_E~0); 1470#L1404-1true assume !(1 == ~E_M~0); 298#L1409-1true assume !(1 == ~E_1~0); 1428#L1414-1true assume !(1 == ~E_2~0); 908#L1419-1true assume !(1 == ~E_3~0); 109#L1424-1true assume !(1 == ~E_4~0); 666#L1429-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1273#L1434-1true assume !(1 == ~E_6~0); 1658#L1439-1true assume !(1 == ~E_7~0); 134#L1444-1true assume !(1 == ~E_8~0); 854#L1449-1true assume !(1 == ~E_9~0); 351#L1454-1true assume !(1 == ~E_10~0); 1327#L1459-1true assume !(1 == ~E_11~0); 740#L1464-1true assume !(1 == ~E_12~0); 787#L1469-1true assume { :end_inline_reset_delta_events } true; 1521#L1815-2true [2021-11-19 05:20:46,170 INFO L793 eck$LassoCheckResult]: Loop: 1521#L1815-2true assume !false; 928#L1816true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 689#L1181true assume false; 1759#L1196true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 106#L846-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1653#L1206-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1670#L1206-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 739#L1211-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 173#L1216-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 500#L1221-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1032#L1226-3true assume !(0 == ~T5_E~0); 207#L1231-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 371#L1236-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1784#L1241-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1362#L1246-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1156#L1251-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 835#L1256-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 185#L1261-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 545#L1266-3true assume !(0 == ~E_M~0); 206#L1271-3true assume 0 == ~E_1~0;~E_1~0 := 1; 520#L1276-3true assume 0 == ~E_2~0;~E_2~0 := 1; 467#L1281-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1216#L1286-3true assume 0 == ~E_4~0;~E_4~0 := 1; 902#L1291-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1666#L1296-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1584#L1301-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1448#L1306-3true assume !(0 == ~E_8~0); 555#L1311-3true assume 0 == ~E_9~0;~E_9~0 := 1; 143#L1316-3true assume 0 == ~E_10~0;~E_10~0 := 1; 186#L1321-3true assume 0 == ~E_11~0;~E_11~0 := 1; 632#L1326-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1418#L1331-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 914#L598-42true assume !(1 == ~m_pc~0); 1054#L598-44true is_master_triggered_~__retres1~0#1 := 0; 1191#L609-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 227#L610-14true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1449#L1497-42true assume !(0 != activate_threads_~tmp~1#1); 1704#L1497-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 672#L617-42true assume 1 == ~t1_pc~0; 497#L618-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 415#L628-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 718#L629-14true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1440#L1505-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 258#L1505-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1424#L636-42true assume !(1 == ~t2_pc~0); 529#L636-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1745#L647-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 820#L648-14true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1101#L1513-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1003#L1513-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 856#L655-42true assume 1 == ~t3_pc~0; 1603#L656-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1064#L666-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 297#L667-14true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1758#L1521-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1214#L1521-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1112#L674-42true assume !(1 == ~t4_pc~0); 841#L674-44true is_transmit4_triggered_~__retres1~4#1 := 0; 775#L685-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84#L686-14true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 970#L1529-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 615#L1529-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1197#L693-42true assume !(1 == ~t5_pc~0); 1514#L693-44true is_transmit5_triggered_~__retres1~5#1 := 0; 881#L704-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1466#L705-14true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 877#L1537-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1159#L1537-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 355#L712-42true assume !(1 == ~t6_pc~0); 1591#L712-44true is_transmit6_triggered_~__retres1~6#1 := 0; 997#L723-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 735#L724-14true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1788#L1545-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 420#L1545-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1379#L731-42true assume !(1 == ~t7_pc~0); 255#L731-44true is_transmit7_triggered_~__retres1~7#1 := 0; 1383#L742-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1095#L743-14true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 366#L1553-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1061#L1553-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 210#L750-42true assume 1 == ~t8_pc~0; 542#L751-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1562#L761-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 896#L762-14true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 152#L1561-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1696#L1561-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 614#L769-42true assume 1 == ~t9_pc~0; 480#L770-14true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1119#L780-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1239#L781-14true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1596#L1569-42true assume !(0 != activate_threads_~tmp___8~0#1); 259#L1569-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 620#L788-42true assume !(1 == ~t10_pc~0); 906#L788-44true is_transmit10_triggered_~__retres1~10#1 := 0; 1699#L799-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 578#L800-14true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1677#L1577-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1626#L1577-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1542#L807-42true assume !(1 == ~t11_pc~0); 60#L807-44true is_transmit11_triggered_~__retres1~11#1 := 0; 544#L818-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 126#L819-14true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 127#L1585-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1155#L1585-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 257#L826-42true assume 1 == ~t12_pc~0; 1743#L827-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 986#L837-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1340#L838-14true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 253#L1593-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1487#L1593-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 838#L1344-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1225#L1344-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 776#L1349-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 334#L1354-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 790#L1359-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1662#L1364-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1553#L1369-3true assume !(1 == ~T6_E~0); 1272#L1374-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 213#L1379-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1162#L1384-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 333#L1389-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 514#L1394-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1727#L1399-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1293#L1404-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1232#L1409-3true assume !(1 == ~E_1~0); 1361#L1414-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1386#L1419-3true assume 1 == ~E_3~0;~E_3~0 := 2; 976#L1424-3true assume 1 == ~E_4~0;~E_4~0 := 2; 161#L1429-3true assume 1 == ~E_5~0;~E_5~0 := 2; 789#L1434-3true assume 1 == ~E_6~0;~E_6~0 := 2; 962#L1439-3true assume 1 == ~E_7~0;~E_7~0 := 2; 130#L1444-3true assume 1 == ~E_8~0;~E_8~0 := 2; 191#L1449-3true assume !(1 == ~E_9~0); 1447#L1454-3true assume 1 == ~E_10~0;~E_10~0 := 2; 785#L1459-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1775#L1464-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1268#L1469-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 676#L926-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 83#L993-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 403#L994-1true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1592#L1834true assume !(0 == start_simulation_~tmp~3#1); 1108#L1834-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 910#L926-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 584#L993-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 745#L994-2true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1252#L1789true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1597#L1796true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 76#L1797true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 977#L1847true assume !(0 != start_simulation_~tmp___0~1#1); 1521#L1815-2true [2021-11-19 05:20:46,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:46,178 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2021-11-19 05:20:46,187 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:46,188 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2037809523] [2021-11-19 05:20:46,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:46,189 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:46,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:46,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:46,550 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:46,550 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2037809523] [2021-11-19 05:20:46,551 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2037809523] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:46,551 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:46,551 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:46,553 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1407121976] [2021-11-19 05:20:46,553 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:46,558 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:20:46,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:46,559 INFO L85 PathProgramCache]: Analyzing trace with hash 1437628410, now seen corresponding path program 1 times [2021-11-19 05:20:46,559 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:46,571 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [928999264] [2021-11-19 05:20:46,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:46,572 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:46,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:46,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:46,632 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:46,632 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [928999264] [2021-11-19 05:20:46,632 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [928999264] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:46,632 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:46,632 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-19 05:20:46,633 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1494130545] [2021-11-19 05:20:46,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:46,660 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:20:46,661 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:20:46,702 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-11-19 05:20:46,703 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-11-19 05:20:46,709 INFO L87 Difference]: Start difference. First operand has 1798 states, 1797 states have (on average 1.4997217584863662) internal successors, (2695), 1797 states have internal predecessors, (2695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:46,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:20:46,791 INFO L93 Difference]: Finished difference Result 1796 states and 2661 transitions. [2021-11-19 05:20:46,792 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-11-19 05:20:46,798 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1796 states and 2661 transitions. [2021-11-19 05:20:46,820 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:46,845 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1796 states to 1790 states and 2655 transitions. [2021-11-19 05:20:46,847 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-19 05:20:46,850 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-19 05:20:46,851 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2655 transitions. [2021-11-19 05:20:46,862 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:20:46,862 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2655 transitions. [2021-11-19 05:20:46,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2655 transitions. [2021-11-19 05:20:46,957 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-19 05:20:46,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4832402234636872) internal successors, (2655), 1789 states have internal predecessors, (2655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:46,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2655 transitions. [2021-11-19 05:20:46,973 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2655 transitions. [2021-11-19 05:20:46,973 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2655 transitions. [2021-11-19 05:20:46,973 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-19 05:20:46,973 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2655 transitions. [2021-11-19 05:20:46,986 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:46,987 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:46,987 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:46,991 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:46,991 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:46,992 INFO L791 eck$LassoCheckResult]: Stem: 4447#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 4448#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 3871#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3841#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3842#L853 assume !(1 == ~m_i~0);~m_st~0 := 2; 5103#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4150#L858-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3603#L863-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3604#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4875#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5014#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5380#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5381#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4360#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4361#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4901#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4821#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4822#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4974#L1206 assume !(0 == ~M_E~0); 4339#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4340#L1211-1 assume !(0 == ~T2_E~0); 5233#L1216-1 assume !(0 == ~T3_E~0); 4132#L1221-1 assume !(0 == ~T4_E~0); 4133#L1226-1 assume !(0 == ~T5_E~0); 3795#L1231-1 assume !(0 == ~T6_E~0); 3796#L1236-1 assume !(0 == ~T7_E~0); 5264#L1241-1 assume !(0 == ~T8_E~0); 4194#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4195#L1251-1 assume !(0 == ~T10_E~0); 4415#L1256-1 assume !(0 == ~T11_E~0); 3615#L1261-1 assume !(0 == ~T12_E~0); 3616#L1266-1 assume !(0 == ~E_M~0); 5367#L1271-1 assume !(0 == ~E_1~0); 5002#L1276-1 assume !(0 == ~E_2~0); 5003#L1281-1 assume !(0 == ~E_3~0); 4928#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4036#L1291-1 assume !(0 == ~E_5~0); 4037#L1296-1 assume !(0 == ~E_6~0); 4743#L1301-1 assume !(0 == ~E_7~0); 4744#L1306-1 assume !(0 == ~E_8~0); 5176#L1311-1 assume !(0 == ~E_9~0); 3997#L1316-1 assume !(0 == ~E_10~0); 3998#L1321-1 assume !(0 == ~E_11~0); 4760#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 3861#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3862#L598 assume 1 == ~m_pc~0; 3921#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3922#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5246#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5338#L1497 assume !(0 != activate_threads_~tmp~1#1); 5339#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5295#L617 assume !(1 == ~t1_pc~0); 4217#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4218#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4077#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4078#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4838#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4839#L636 assume 1 == ~t2_pc~0; 4186#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4187#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4017#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4018#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 4874#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4537#L655 assume !(1 == ~t3_pc~0); 4538#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5251#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3891#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3892#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 5368#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5369#L674 assume 1 == ~t4_pc~0; 3711#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3712#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5009#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4019#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 4020#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4534#L693 assume !(1 == ~t5_pc~0); 4697#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4341#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4342#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5178#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 4427#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4364#L712 assume 1 == ~t6_pc~0; 4365#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4792#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4793#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5079#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 4890#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4888#L731 assume 1 == ~t7_pc~0; 3865#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3866#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4060#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4997#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 5116#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3975#L750 assume !(1 == ~t8_pc~0); 3646#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3645#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4161#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5191#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4298#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4299#L769 assume 1 == ~t9_pc~0; 4834#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3819#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3820#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4603#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 5055#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5136#L788 assume !(1 == ~t10_pc~0); 4711#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4712#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4943#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4944#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 3971#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3972#L807 assume 1 == ~t11_pc~0; 5145#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4723#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4876#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5287#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 5392#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5235#L826 assume !(1 == ~t12_pc~0); 4367#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4368#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4896#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5327#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 4527#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4436#L1344 assume !(1 == ~M_E~0); 4437#L1344-2 assume !(1 == ~T1_E~0); 4578#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4750#L1354-1 assume !(1 == ~T3_E~0); 4751#L1359-1 assume !(1 == ~T4_E~0); 5125#L1364-1 assume !(1 == ~T5_E~0); 4079#L1369-1 assume !(1 == ~T6_E~0); 4080#L1374-1 assume !(1 == ~T7_E~0); 4756#L1379-1 assume !(1 == ~T8_E~0); 4757#L1384-1 assume !(1 == ~T9_E~0); 4820#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5266#L1394-1 assume !(1 == ~T11_E~0); 5267#L1399-1 assume !(1 == ~T12_E~0); 5346#L1404-1 assume !(1 == ~E_M~0); 4198#L1409-1 assume !(1 == ~E_1~0); 4199#L1414-1 assume !(1 == ~E_2~0); 5036#L1419-1 assume !(1 == ~E_3~0); 3832#L1424-1 assume !(1 == ~E_4~0); 3833#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 4767#L1434-1 assume !(1 == ~E_6~0); 5285#L1439-1 assume !(1 == ~E_7~0); 3887#L1444-1 assume !(1 == ~E_8~0); 3888#L1449-1 assume !(1 == ~E_9~0); 4303#L1454-1 assume !(1 == ~E_10~0); 4304#L1459-1 assume !(1 == ~E_11~0); 4854#L1464-1 assume !(1 == ~E_12~0); 4855#L1469-1 assume { :end_inline_reset_delta_events } true; 4902#L1815-2 [2021-11-19 05:20:46,992 INFO L793 eck$LassoCheckResult]: Loop: 4902#L1815-2 assume !false; 5056#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4725#L1181 assume !false; 4796#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4748#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3606#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4335#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4886#L1008 assume !(0 != eval_~tmp~0#1); 4887#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3825#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3826#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5386#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4853#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3959#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3960#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4550#L1226-3 assume !(0 == ~T5_E~0); 4023#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4024#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4336#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5323#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5226#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4962#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3981#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 3982#L1266-3 assume !(0 == ~E_M~0); 4021#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4022#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4494#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4495#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5032#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5033#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5375#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5343#L1306-3 assume !(0 == ~E_8~0); 4619#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3905#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3906#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3983#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4718#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5043#L598-42 assume !(1 == ~m_pc~0); 5044#L598-44 is_master_triggered_~__retres1~0#1 := 0; 5158#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4061#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4062#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 5344#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4774#L617-42 assume 1 == ~t1_pc~0; 4546#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4411#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4412#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4826#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4126#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4127#L636-42 assume 1 == ~t2_pc~0; 5328#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4591#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4941#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4942#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5121#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4983#L655-42 assume !(1 == ~t3_pc~0); 4563#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4564#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4196#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4197#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5250#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5195#L674-42 assume !(1 == ~t4_pc~0); 4969#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 4891#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3780#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3781#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4695#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4696#L693-42 assume 1 == ~t5_pc~0; 4951#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4952#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5012#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5007#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5008#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4310#L712-42 assume !(1 == ~t6_pc~0); 4311#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 4637#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4845#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4846#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4419#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4420#L731-42 assume !(1 == ~t7_pc~0); 4118#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4119#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5186#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4327#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4328#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4031#L750-42 assume 1 == ~t8_pc~0; 4032#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4606#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5029#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3924#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3925#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4694#L769-42 assume 1 == ~t9_pc~0; 4516#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4517#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5200#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5265#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 4128#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4129#L788-42 assume 1 == ~t10_pc~0; 4702#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4916#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4646#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4647#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5384#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5362#L807-42 assume !(1 == ~t11_pc~0); 3732#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 3733#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3872#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3873#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3874#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4123#L826-42 assume 1 == ~t12_pc~0; 4124#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4316#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5108#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4113#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4114#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4965#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4966#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4892#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4273#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4274#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4906#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5364#L1369-3 assume !(1 == ~T6_E~0); 5284#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4038#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4039#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4271#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4272#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4570#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5293#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5256#L1409-3 assume !(1 == ~E_1~0); 5257#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5322#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5102#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3939#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3940#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4905#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3879#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3880#L1449-3 assume !(1 == ~E_9~0); 3989#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4899#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4900#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5281#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4779#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3778#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3779#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4395#L1834 assume !(0 == start_simulation_~tmp~3#1); 5015#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 5038#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4472#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4651#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4863#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5271#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3764#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 3765#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 4902#L1815-2 [2021-11-19 05:20:46,993 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:46,994 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2021-11-19 05:20:46,994 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:46,994 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [393440335] [2021-11-19 05:20:46,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:46,994 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:47,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:47,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:47,063 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:47,064 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [393440335] [2021-11-19 05:20:47,064 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [393440335] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:47,064 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:47,064 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:47,064 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1078827627] [2021-11-19 05:20:47,065 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:47,065 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:20:47,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:47,066 INFO L85 PathProgramCache]: Analyzing trace with hash 1784148501, now seen corresponding path program 1 times [2021-11-19 05:20:47,066 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:47,066 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290758582] [2021-11-19 05:20:47,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:47,067 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:47,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:47,240 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:47,241 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:47,241 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1290758582] [2021-11-19 05:20:47,241 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1290758582] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:47,241 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:47,241 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:47,242 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1910285635] [2021-11-19 05:20:47,242 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:47,242 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:20:47,243 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:20:47,243 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:20:47,243 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:20:47,244 INFO L87 Difference]: Start difference. First operand 1790 states and 2655 transitions. cyclomatic complexity: 866 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:47,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:20:47,339 INFO L93 Difference]: Finished difference Result 1790 states and 2654 transitions. [2021-11-19 05:20:47,340 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:20:47,341 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2654 transitions. [2021-11-19 05:20:47,357 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:47,373 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2654 transitions. [2021-11-19 05:20:47,373 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-19 05:20:47,375 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-19 05:20:47,376 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2654 transitions. [2021-11-19 05:20:47,378 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:20:47,379 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2654 transitions. [2021-11-19 05:20:47,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2654 transitions. [2021-11-19 05:20:47,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-19 05:20:47,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.48268156424581) internal successors, (2654), 1789 states have internal predecessors, (2654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:47,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2654 transitions. [2021-11-19 05:20:47,422 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2654 transitions. [2021-11-19 05:20:47,422 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2654 transitions. [2021-11-19 05:20:47,422 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-19 05:20:47,422 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2654 transitions. [2021-11-19 05:20:47,434 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:47,434 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:47,434 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:47,442 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:47,443 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:47,445 INFO L791 eck$LassoCheckResult]: Stem: 8034#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 8035#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 7458#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7428#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7429#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 8690#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7737#L858-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7190#L863-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7191#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8462#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8601#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8967#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8968#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7947#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7948#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8488#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8408#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8409#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8561#L1206 assume !(0 == ~M_E~0); 7926#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7927#L1211-1 assume !(0 == ~T2_E~0); 8820#L1216-1 assume !(0 == ~T3_E~0); 7719#L1221-1 assume !(0 == ~T4_E~0); 7720#L1226-1 assume !(0 == ~T5_E~0); 7382#L1231-1 assume !(0 == ~T6_E~0); 7383#L1236-1 assume !(0 == ~T7_E~0); 8851#L1241-1 assume !(0 == ~T8_E~0); 7781#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7782#L1251-1 assume !(0 == ~T10_E~0); 8002#L1256-1 assume !(0 == ~T11_E~0); 7202#L1261-1 assume !(0 == ~T12_E~0); 7203#L1266-1 assume !(0 == ~E_M~0); 8954#L1271-1 assume !(0 == ~E_1~0); 8589#L1276-1 assume !(0 == ~E_2~0); 8590#L1281-1 assume !(0 == ~E_3~0); 8515#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 7623#L1291-1 assume !(0 == ~E_5~0); 7624#L1296-1 assume !(0 == ~E_6~0); 8330#L1301-1 assume !(0 == ~E_7~0); 8331#L1306-1 assume !(0 == ~E_8~0); 8763#L1311-1 assume !(0 == ~E_9~0); 7584#L1316-1 assume !(0 == ~E_10~0); 7585#L1321-1 assume !(0 == ~E_11~0); 8347#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 7448#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7449#L598 assume 1 == ~m_pc~0; 7508#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7509#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8833#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8925#L1497 assume !(0 != activate_threads_~tmp~1#1); 8926#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8882#L617 assume !(1 == ~t1_pc~0); 7804#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7805#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7664#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7665#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8425#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8426#L636 assume 1 == ~t2_pc~0; 7773#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7774#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7604#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7605#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 8461#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8124#L655 assume !(1 == ~t3_pc~0); 8125#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8838#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7478#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7479#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 8955#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8956#L674 assume 1 == ~t4_pc~0; 7298#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7299#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8596#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7606#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 7607#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8121#L693 assume !(1 == ~t5_pc~0); 8284#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7928#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7929#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8765#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 8014#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7951#L712 assume 1 == ~t6_pc~0; 7952#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8379#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8380#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8666#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 8477#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8475#L731 assume 1 == ~t7_pc~0; 7452#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7453#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7647#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8584#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 8703#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7562#L750 assume !(1 == ~t8_pc~0); 7233#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7232#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7748#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8778#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7885#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7886#L769 assume 1 == ~t9_pc~0; 8421#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7406#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7407#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8190#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 8642#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8723#L788 assume !(1 == ~t10_pc~0); 8298#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8299#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8530#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8531#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 7558#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7559#L807 assume 1 == ~t11_pc~0; 8732#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8310#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8463#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8874#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 8979#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8822#L826 assume !(1 == ~t12_pc~0); 7954#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 7955#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8483#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8914#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 8114#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8023#L1344 assume !(1 == ~M_E~0); 8024#L1344-2 assume !(1 == ~T1_E~0); 8165#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8337#L1354-1 assume !(1 == ~T3_E~0); 8338#L1359-1 assume !(1 == ~T4_E~0); 8712#L1364-1 assume !(1 == ~T5_E~0); 7666#L1369-1 assume !(1 == ~T6_E~0); 7667#L1374-1 assume !(1 == ~T7_E~0); 8343#L1379-1 assume !(1 == ~T8_E~0); 8344#L1384-1 assume !(1 == ~T9_E~0); 8407#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8853#L1394-1 assume !(1 == ~T11_E~0); 8854#L1399-1 assume !(1 == ~T12_E~0); 8933#L1404-1 assume !(1 == ~E_M~0); 7785#L1409-1 assume !(1 == ~E_1~0); 7786#L1414-1 assume !(1 == ~E_2~0); 8623#L1419-1 assume !(1 == ~E_3~0); 7419#L1424-1 assume !(1 == ~E_4~0); 7420#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 8354#L1434-1 assume !(1 == ~E_6~0); 8872#L1439-1 assume !(1 == ~E_7~0); 7474#L1444-1 assume !(1 == ~E_8~0); 7475#L1449-1 assume !(1 == ~E_9~0); 7890#L1454-1 assume !(1 == ~E_10~0); 7891#L1459-1 assume !(1 == ~E_11~0); 8441#L1464-1 assume !(1 == ~E_12~0); 8442#L1469-1 assume { :end_inline_reset_delta_events } true; 8489#L1815-2 [2021-11-19 05:20:47,445 INFO L793 eck$LassoCheckResult]: Loop: 8489#L1815-2 assume !false; 8643#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8312#L1181 assume !false; 8383#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8335#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7193#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7922#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8473#L1008 assume !(0 != eval_~tmp~0#1); 8474#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7412#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7413#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8973#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8440#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7546#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7547#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8137#L1226-3 assume !(0 == ~T5_E~0); 7610#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7611#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7923#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8910#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8813#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8549#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7568#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 7569#L1266-3 assume !(0 == ~E_M~0); 7608#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7609#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8081#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8082#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8619#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8620#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8962#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8930#L1306-3 assume !(0 == ~E_8~0); 8206#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7492#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7493#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7570#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 8305#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8630#L598-42 assume !(1 == ~m_pc~0); 8631#L598-44 is_master_triggered_~__retres1~0#1 := 0; 8745#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7648#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7649#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 8931#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8361#L617-42 assume 1 == ~t1_pc~0; 8133#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7998#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7999#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8413#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7713#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7714#L636-42 assume !(1 == ~t2_pc~0); 8177#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 8178#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8528#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8529#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8708#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8570#L655-42 assume !(1 == ~t3_pc~0); 8150#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 8151#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7783#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7784#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8837#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8782#L674-42 assume !(1 == ~t4_pc~0); 8556#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 8478#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7367#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7368#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8282#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8283#L693-42 assume 1 == ~t5_pc~0; 8538#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8539#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8599#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8594#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8595#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7897#L712-42 assume !(1 == ~t6_pc~0); 7898#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 8224#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8432#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8433#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8006#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8007#L731-42 assume !(1 == ~t7_pc~0); 7705#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 7706#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8773#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7914#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7915#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7618#L750-42 assume 1 == ~t8_pc~0; 7619#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8193#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8616#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7511#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7512#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8281#L769-42 assume 1 == ~t9_pc~0; 8103#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8104#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8787#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8852#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 7715#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7716#L788-42 assume 1 == ~t10_pc~0; 8289#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8503#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8233#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8234#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8971#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8949#L807-42 assume !(1 == ~t11_pc~0); 7319#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 7320#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7459#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7460#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7461#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7710#L826-42 assume !(1 == ~t12_pc~0); 7712#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 7903#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8695#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7700#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 7701#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8552#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8553#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8479#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7860#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7861#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8493#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8951#L1369-3 assume !(1 == ~T6_E~0); 8871#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7625#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7626#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7858#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7859#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8157#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8880#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8843#L1409-3 assume !(1 == ~E_1~0); 8844#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8909#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8689#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7526#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7527#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8492#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7466#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7467#L1449-3 assume !(1 == ~E_9~0); 7576#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8486#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8487#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8868#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8366#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7365#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7366#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 7982#L1834 assume !(0 == start_simulation_~tmp~3#1); 8602#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8625#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 8059#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 8238#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 8450#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8858#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7351#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 7352#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 8489#L1815-2 [2021-11-19 05:20:47,446 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:47,446 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2021-11-19 05:20:47,447 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:47,447 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1107355393] [2021-11-19 05:20:47,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:47,447 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:47,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:47,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:47,532 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:47,532 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1107355393] [2021-11-19 05:20:47,532 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1107355393] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:47,532 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:47,532 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:47,533 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [467585225] [2021-11-19 05:20:47,533 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:47,533 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:20:47,534 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:47,534 INFO L85 PathProgramCache]: Analyzing trace with hash 1198130711, now seen corresponding path program 1 times [2021-11-19 05:20:47,534 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:47,534 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116532351] [2021-11-19 05:20:47,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:47,535 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:47,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:47,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:47,614 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:47,614 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1116532351] [2021-11-19 05:20:47,615 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1116532351] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:47,615 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:47,615 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:47,615 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1913721210] [2021-11-19 05:20:47,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:47,616 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:20:47,616 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:20:47,617 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:20:47,617 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:20:47,617 INFO L87 Difference]: Start difference. First operand 1790 states and 2654 transitions. cyclomatic complexity: 865 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:47,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:20:47,660 INFO L93 Difference]: Finished difference Result 1790 states and 2653 transitions. [2021-11-19 05:20:47,660 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:20:47,662 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2653 transitions. [2021-11-19 05:20:47,680 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:47,696 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2653 transitions. [2021-11-19 05:20:47,696 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-19 05:20:47,698 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-19 05:20:47,698 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2653 transitions. [2021-11-19 05:20:47,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:20:47,701 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2653 transitions. [2021-11-19 05:20:47,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2653 transitions. [2021-11-19 05:20:47,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-19 05:20:47,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.482122905027933) internal successors, (2653), 1789 states have internal predecessors, (2653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:47,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2653 transitions. [2021-11-19 05:20:47,766 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2653 transitions. [2021-11-19 05:20:47,766 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2653 transitions. [2021-11-19 05:20:47,766 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-19 05:20:47,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2653 transitions. [2021-11-19 05:20:47,780 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:47,780 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:47,780 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:47,783 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:47,783 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:47,784 INFO L791 eck$LassoCheckResult]: Stem: 11621#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11622#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11045#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11015#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11016#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 12277#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11324#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10777#L863-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10778#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12049#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12188#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12554#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12555#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11534#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11535#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12075#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 11995#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11996#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12148#L1206 assume !(0 == ~M_E~0); 11513#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11514#L1211-1 assume !(0 == ~T2_E~0); 12407#L1216-1 assume !(0 == ~T3_E~0); 11306#L1221-1 assume !(0 == ~T4_E~0); 11307#L1226-1 assume !(0 == ~T5_E~0); 10969#L1231-1 assume !(0 == ~T6_E~0); 10970#L1236-1 assume !(0 == ~T7_E~0); 12438#L1241-1 assume !(0 == ~T8_E~0); 11368#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11369#L1251-1 assume !(0 == ~T10_E~0); 11589#L1256-1 assume !(0 == ~T11_E~0); 10789#L1261-1 assume !(0 == ~T12_E~0); 10790#L1266-1 assume !(0 == ~E_M~0); 12541#L1271-1 assume !(0 == ~E_1~0); 12176#L1276-1 assume !(0 == ~E_2~0); 12177#L1281-1 assume !(0 == ~E_3~0); 12102#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 11210#L1291-1 assume !(0 == ~E_5~0); 11211#L1296-1 assume !(0 == ~E_6~0); 11917#L1301-1 assume !(0 == ~E_7~0); 11918#L1306-1 assume !(0 == ~E_8~0); 12350#L1311-1 assume !(0 == ~E_9~0); 11171#L1316-1 assume !(0 == ~E_10~0); 11172#L1321-1 assume !(0 == ~E_11~0); 11934#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 11035#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11036#L598 assume 1 == ~m_pc~0; 11095#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11096#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12420#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12512#L1497 assume !(0 != activate_threads_~tmp~1#1); 12513#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12469#L617 assume !(1 == ~t1_pc~0); 11391#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11392#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11251#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11252#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12012#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12013#L636 assume 1 == ~t2_pc~0; 11360#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11361#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11191#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11192#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 12048#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11711#L655 assume !(1 == ~t3_pc~0); 11712#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12425#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11065#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11066#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 12542#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12543#L674 assume 1 == ~t4_pc~0; 10885#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10886#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12183#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11193#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 11194#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11708#L693 assume !(1 == ~t5_pc~0); 11871#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11515#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11516#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12352#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 11601#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11538#L712 assume 1 == ~t6_pc~0; 11539#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11966#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11967#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12253#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 12064#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12062#L731 assume 1 == ~t7_pc~0; 11039#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11040#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11234#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12171#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 12290#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11149#L750 assume !(1 == ~t8_pc~0); 10820#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10819#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11335#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12365#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11472#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11473#L769 assume 1 == ~t9_pc~0; 12008#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10993#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10994#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11777#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 12229#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12310#L788 assume !(1 == ~t10_pc~0); 11885#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11886#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12117#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12118#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 11145#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 11146#L807 assume 1 == ~t11_pc~0; 12319#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11897#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12050#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12461#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 12566#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12409#L826 assume !(1 == ~t12_pc~0); 11541#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11542#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12070#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12501#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 11701#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11610#L1344 assume !(1 == ~M_E~0); 11611#L1344-2 assume !(1 == ~T1_E~0); 11752#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11924#L1354-1 assume !(1 == ~T3_E~0); 11925#L1359-1 assume !(1 == ~T4_E~0); 12299#L1364-1 assume !(1 == ~T5_E~0); 11253#L1369-1 assume !(1 == ~T6_E~0); 11254#L1374-1 assume !(1 == ~T7_E~0); 11930#L1379-1 assume !(1 == ~T8_E~0); 11931#L1384-1 assume !(1 == ~T9_E~0); 11994#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12440#L1394-1 assume !(1 == ~T11_E~0); 12441#L1399-1 assume !(1 == ~T12_E~0); 12520#L1404-1 assume !(1 == ~E_M~0); 11372#L1409-1 assume !(1 == ~E_1~0); 11373#L1414-1 assume !(1 == ~E_2~0); 12210#L1419-1 assume !(1 == ~E_3~0); 11006#L1424-1 assume !(1 == ~E_4~0); 11007#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 11941#L1434-1 assume !(1 == ~E_6~0); 12459#L1439-1 assume !(1 == ~E_7~0); 11061#L1444-1 assume !(1 == ~E_8~0); 11062#L1449-1 assume !(1 == ~E_9~0); 11477#L1454-1 assume !(1 == ~E_10~0); 11478#L1459-1 assume !(1 == ~E_11~0); 12028#L1464-1 assume !(1 == ~E_12~0); 12029#L1469-1 assume { :end_inline_reset_delta_events } true; 12076#L1815-2 [2021-11-19 05:20:47,785 INFO L793 eck$LassoCheckResult]: Loop: 12076#L1815-2 assume !false; 12230#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11899#L1181 assume !false; 11970#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11922#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10780#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11509#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12060#L1008 assume !(0 != eval_~tmp~0#1); 12061#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10999#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11000#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12560#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12027#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11133#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11134#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11724#L1226-3 assume !(0 == ~T5_E~0); 11197#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11198#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11510#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12497#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12400#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12136#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11155#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11156#L1266-3 assume !(0 == ~E_M~0); 11195#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11196#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11668#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11669#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12206#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12207#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12549#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12517#L1306-3 assume !(0 == ~E_8~0); 11793#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11079#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11080#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11157#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11892#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12217#L598-42 assume !(1 == ~m_pc~0); 12218#L598-44 is_master_triggered_~__retres1~0#1 := 0; 12332#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11235#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11236#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 12518#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11948#L617-42 assume 1 == ~t1_pc~0; 11720#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11585#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11586#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12000#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11300#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11301#L636-42 assume !(1 == ~t2_pc~0); 11764#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 11765#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12115#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12116#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12295#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12157#L655-42 assume !(1 == ~t3_pc~0); 11737#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 11738#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11370#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11371#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12424#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12369#L674-42 assume 1 == ~t4_pc~0; 12370#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12065#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10954#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10955#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11869#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11870#L693-42 assume 1 == ~t5_pc~0; 12125#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12126#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12186#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12181#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12182#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11484#L712-42 assume !(1 == ~t6_pc~0); 11485#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 11811#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12019#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12020#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11593#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11594#L731-42 assume 1 == ~t7_pc~0; 11457#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11293#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12360#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11501#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11502#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11205#L750-42 assume 1 == ~t8_pc~0; 11206#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11780#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12203#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11098#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11099#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11868#L769-42 assume 1 == ~t9_pc~0; 11690#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11691#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12374#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12439#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 11302#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11303#L788-42 assume 1 == ~t10_pc~0; 11876#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12090#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11820#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11821#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12558#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12536#L807-42 assume 1 == ~t11_pc~0; 12225#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10907#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11046#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11047#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11048#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11297#L826-42 assume 1 == ~t12_pc~0; 11298#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11490#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12282#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11287#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 11288#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12139#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12140#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12066#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11447#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11448#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12080#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12538#L1369-3 assume !(1 == ~T6_E~0); 12458#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11212#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11213#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11445#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11446#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11744#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12467#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12430#L1409-3 assume !(1 == ~E_1~0); 12431#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12496#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12276#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11113#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11114#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12079#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11053#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11054#L1449-3 assume !(1 == ~E_9~0); 11163#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12073#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12074#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12455#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11953#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10952#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10953#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11569#L1834 assume !(0 == start_simulation_~tmp~3#1); 12189#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 12212#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11646#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11825#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 12037#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12445#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10938#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 10939#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 12076#L1815-2 [2021-11-19 05:20:47,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:47,785 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2021-11-19 05:20:47,787 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:47,787 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [512245237] [2021-11-19 05:20:47,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:47,788 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:47,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:47,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:47,842 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:47,842 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [512245237] [2021-11-19 05:20:47,843 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [512245237] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:47,843 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:47,844 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:47,847 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [349402418] [2021-11-19 05:20:47,847 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:47,848 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:20:47,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:47,848 INFO L85 PathProgramCache]: Analyzing trace with hash -1380802157, now seen corresponding path program 1 times [2021-11-19 05:20:47,849 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:47,853 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2057754594] [2021-11-19 05:20:47,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:47,854 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:47,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:47,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:47,932 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:47,932 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2057754594] [2021-11-19 05:20:47,933 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2057754594] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:47,933 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:47,933 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:47,934 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56806569] [2021-11-19 05:20:47,934 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:47,935 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:20:47,935 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:20:47,936 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:20:47,937 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:20:47,937 INFO L87 Difference]: Start difference. First operand 1790 states and 2653 transitions. cyclomatic complexity: 864 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:47,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:20:47,988 INFO L93 Difference]: Finished difference Result 1790 states and 2652 transitions. [2021-11-19 05:20:47,989 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:20:47,990 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2652 transitions. [2021-11-19 05:20:48,007 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:48,023 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2652 transitions. [2021-11-19 05:20:48,023 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-19 05:20:48,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-19 05:20:48,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2652 transitions. [2021-11-19 05:20:48,029 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:20:48,029 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2652 transitions. [2021-11-19 05:20:48,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2652 transitions. [2021-11-19 05:20:48,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-19 05:20:48,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.481564245810056) internal successors, (2652), 1789 states have internal predecessors, (2652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:48,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2652 transitions. [2021-11-19 05:20:48,072 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2652 transitions. [2021-11-19 05:20:48,072 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2652 transitions. [2021-11-19 05:20:48,072 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-19 05:20:48,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2652 transitions. [2021-11-19 05:20:48,084 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:48,085 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:48,085 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:48,087 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:48,087 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:48,088 INFO L791 eck$LassoCheckResult]: Stem: 15208#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 15209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 14632#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14602#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14603#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 15864#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14911#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14364#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14365#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 15636#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15775#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16141#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16142#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15121#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15122#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15662#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15582#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 15583#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15735#L1206 assume !(0 == ~M_E~0); 15100#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15101#L1211-1 assume !(0 == ~T2_E~0); 15994#L1216-1 assume !(0 == ~T3_E~0); 14893#L1221-1 assume !(0 == ~T4_E~0); 14894#L1226-1 assume !(0 == ~T5_E~0); 14556#L1231-1 assume !(0 == ~T6_E~0); 14557#L1236-1 assume !(0 == ~T7_E~0); 16025#L1241-1 assume !(0 == ~T8_E~0); 14955#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14956#L1251-1 assume !(0 == ~T10_E~0); 15176#L1256-1 assume !(0 == ~T11_E~0); 14376#L1261-1 assume !(0 == ~T12_E~0); 14377#L1266-1 assume !(0 == ~E_M~0); 16128#L1271-1 assume !(0 == ~E_1~0); 15763#L1276-1 assume !(0 == ~E_2~0); 15764#L1281-1 assume !(0 == ~E_3~0); 15689#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 14797#L1291-1 assume !(0 == ~E_5~0); 14798#L1296-1 assume !(0 == ~E_6~0); 15504#L1301-1 assume !(0 == ~E_7~0); 15505#L1306-1 assume !(0 == ~E_8~0); 15937#L1311-1 assume !(0 == ~E_9~0); 14758#L1316-1 assume !(0 == ~E_10~0); 14759#L1321-1 assume !(0 == ~E_11~0); 15521#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 14622#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14623#L598 assume 1 == ~m_pc~0; 14682#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14683#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16007#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16099#L1497 assume !(0 != activate_threads_~tmp~1#1); 16100#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16056#L617 assume !(1 == ~t1_pc~0); 14978#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14979#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14838#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14839#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15599#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15600#L636 assume 1 == ~t2_pc~0; 14947#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14948#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14778#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14779#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 15635#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15298#L655 assume !(1 == ~t3_pc~0); 15299#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16012#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14652#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14653#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 16129#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16130#L674 assume 1 == ~t4_pc~0; 14472#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14473#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15770#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14780#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 14781#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15295#L693 assume !(1 == ~t5_pc~0); 15458#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15102#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15103#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15939#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 15188#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15125#L712 assume 1 == ~t6_pc~0; 15126#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15553#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15554#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15840#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 15651#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15649#L731 assume 1 == ~t7_pc~0; 14626#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14627#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14821#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15758#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 15877#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14736#L750 assume !(1 == ~t8_pc~0); 14407#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14406#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14922#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15952#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15059#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15060#L769 assume 1 == ~t9_pc~0; 15595#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14580#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14581#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 15364#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 15816#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15897#L788 assume !(1 == ~t10_pc~0); 15472#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 15473#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15704#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15705#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 14732#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14733#L807 assume 1 == ~t11_pc~0; 15906#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15484#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15637#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16048#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 16153#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15996#L826 assume !(1 == ~t12_pc~0); 15128#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 15129#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15657#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16088#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 15288#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15197#L1344 assume !(1 == ~M_E~0); 15198#L1344-2 assume !(1 == ~T1_E~0); 15339#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15511#L1354-1 assume !(1 == ~T3_E~0); 15512#L1359-1 assume !(1 == ~T4_E~0); 15886#L1364-1 assume !(1 == ~T5_E~0); 14840#L1369-1 assume !(1 == ~T6_E~0); 14841#L1374-1 assume !(1 == ~T7_E~0); 15517#L1379-1 assume !(1 == ~T8_E~0); 15518#L1384-1 assume !(1 == ~T9_E~0); 15581#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16027#L1394-1 assume !(1 == ~T11_E~0); 16028#L1399-1 assume !(1 == ~T12_E~0); 16107#L1404-1 assume !(1 == ~E_M~0); 14959#L1409-1 assume !(1 == ~E_1~0); 14960#L1414-1 assume !(1 == ~E_2~0); 15797#L1419-1 assume !(1 == ~E_3~0); 14593#L1424-1 assume !(1 == ~E_4~0); 14594#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 15528#L1434-1 assume !(1 == ~E_6~0); 16046#L1439-1 assume !(1 == ~E_7~0); 14648#L1444-1 assume !(1 == ~E_8~0); 14649#L1449-1 assume !(1 == ~E_9~0); 15064#L1454-1 assume !(1 == ~E_10~0); 15065#L1459-1 assume !(1 == ~E_11~0); 15615#L1464-1 assume !(1 == ~E_12~0); 15616#L1469-1 assume { :end_inline_reset_delta_events } true; 15663#L1815-2 [2021-11-19 05:20:48,088 INFO L793 eck$LassoCheckResult]: Loop: 15663#L1815-2 assume !false; 15817#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15486#L1181 assume !false; 15557#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15509#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14367#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15096#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 15647#L1008 assume !(0 != eval_~tmp~0#1); 15648#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14586#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14587#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16147#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15614#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14720#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14721#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15311#L1226-3 assume !(0 == ~T5_E~0); 14784#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14785#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15097#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16084#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15987#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15723#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14742#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14743#L1266-3 assume !(0 == ~E_M~0); 14782#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14783#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15255#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15256#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15793#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15794#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16136#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16104#L1306-3 assume !(0 == ~E_8~0); 15380#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14666#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14667#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14744#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 15479#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15804#L598-42 assume !(1 == ~m_pc~0); 15805#L598-44 is_master_triggered_~__retres1~0#1 := 0; 15919#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14822#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14823#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 16105#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15535#L617-42 assume 1 == ~t1_pc~0; 15307#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15172#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15173#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15587#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14887#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14888#L636-42 assume !(1 == ~t2_pc~0); 15351#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 15352#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15702#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15703#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15882#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15744#L655-42 assume 1 == ~t3_pc~0; 15745#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15325#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14957#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14958#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16011#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15956#L674-42 assume !(1 == ~t4_pc~0); 15730#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 15652#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14541#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14542#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15456#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15457#L693-42 assume 1 == ~t5_pc~0; 15712#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15713#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15773#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15768#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15769#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15071#L712-42 assume !(1 == ~t6_pc~0); 15072#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 15398#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15606#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15607#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15180#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15181#L731-42 assume 1 == ~t7_pc~0; 15044#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14880#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15947#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15088#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15089#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14792#L750-42 assume 1 == ~t8_pc~0; 14793#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15367#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15790#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14685#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14686#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15455#L769-42 assume 1 == ~t9_pc~0; 15277#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15278#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15961#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16026#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 14889#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14890#L788-42 assume 1 == ~t10_pc~0; 15463#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15677#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15407#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15408#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16145#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16123#L807-42 assume 1 == ~t11_pc~0; 15812#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14494#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14633#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14634#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14635#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 14884#L826-42 assume 1 == ~t12_pc~0; 14885#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 15077#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15869#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14874#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 14875#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15726#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15727#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15653#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15034#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15035#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15667#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16125#L1369-3 assume !(1 == ~T6_E~0); 16045#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14799#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14800#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15032#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15033#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15331#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16054#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16017#L1409-3 assume !(1 == ~E_1~0); 16018#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16083#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15863#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14700#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14701#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15666#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14640#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14641#L1449-3 assume !(1 == ~E_9~0); 14750#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15660#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 15661#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16042#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15540#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14539#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14540#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 15156#L1834 assume !(0 == start_simulation_~tmp~3#1); 15776#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15799#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 15233#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15412#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 15624#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16032#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14525#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 14526#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 15663#L1815-2 [2021-11-19 05:20:48,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:48,089 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2021-11-19 05:20:48,089 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:48,089 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615856659] [2021-11-19 05:20:48,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:48,090 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:48,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:48,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:48,136 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:48,137 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1615856659] [2021-11-19 05:20:48,137 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1615856659] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:48,137 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:48,137 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:48,137 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1940029861] [2021-11-19 05:20:48,138 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:48,138 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:20:48,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:48,138 INFO L85 PathProgramCache]: Analyzing trace with hash 1846949459, now seen corresponding path program 1 times [2021-11-19 05:20:48,139 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:48,139 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2136542023] [2021-11-19 05:20:48,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:48,139 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:48,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:48,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:48,226 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:48,226 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2136542023] [2021-11-19 05:20:48,228 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2136542023] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:48,228 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:48,229 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:48,229 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1256639220] [2021-11-19 05:20:48,229 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:48,229 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:20:48,230 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:20:48,230 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:20:48,230 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:20:48,230 INFO L87 Difference]: Start difference. First operand 1790 states and 2652 transitions. cyclomatic complexity: 863 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:48,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:20:48,272 INFO L93 Difference]: Finished difference Result 1790 states and 2651 transitions. [2021-11-19 05:20:48,272 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:20:48,274 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2651 transitions. [2021-11-19 05:20:48,292 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:48,308 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2651 transitions. [2021-11-19 05:20:48,308 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-19 05:20:48,310 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-19 05:20:48,310 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2651 transitions. [2021-11-19 05:20:48,313 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:20:48,313 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2651 transitions. [2021-11-19 05:20:48,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2651 transitions. [2021-11-19 05:20:48,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-19 05:20:48,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4810055865921787) internal successors, (2651), 1789 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:48,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2651 transitions. [2021-11-19 05:20:48,357 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2651 transitions. [2021-11-19 05:20:48,357 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2651 transitions. [2021-11-19 05:20:48,357 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-19 05:20:48,358 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2651 transitions. [2021-11-19 05:20:48,367 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:48,368 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:48,368 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:48,371 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:48,371 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:48,371 INFO L791 eck$LassoCheckResult]: Stem: 18797#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18798#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 18221#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18194#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18195#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 19451#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18498#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17951#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17952#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19223#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 19362#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19728#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19729#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18710#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18711#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19249#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19169#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 19170#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19322#L1206 assume !(0 == ~M_E~0); 18687#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18688#L1211-1 assume !(0 == ~T2_E~0); 19581#L1216-1 assume !(0 == ~T3_E~0); 18480#L1221-1 assume !(0 == ~T4_E~0); 18481#L1226-1 assume !(0 == ~T5_E~0); 18145#L1231-1 assume !(0 == ~T6_E~0); 18146#L1236-1 assume !(0 == ~T7_E~0); 19612#L1241-1 assume !(0 == ~T8_E~0); 18542#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18543#L1251-1 assume !(0 == ~T10_E~0); 18763#L1256-1 assume !(0 == ~T11_E~0); 17963#L1261-1 assume !(0 == ~T12_E~0); 17964#L1266-1 assume !(0 == ~E_M~0); 19715#L1271-1 assume !(0 == ~E_1~0); 19350#L1276-1 assume !(0 == ~E_2~0); 19351#L1281-1 assume !(0 == ~E_3~0); 19278#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 18384#L1291-1 assume !(0 == ~E_5~0); 18385#L1296-1 assume !(0 == ~E_6~0); 19091#L1301-1 assume !(0 == ~E_7~0); 19092#L1306-1 assume !(0 == ~E_8~0); 19524#L1311-1 assume !(0 == ~E_9~0); 18345#L1316-1 assume !(0 == ~E_10~0); 18346#L1321-1 assume !(0 == ~E_11~0); 19108#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 18211#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18212#L598 assume 1 == ~m_pc~0; 18269#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18270#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19594#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19686#L1497 assume !(0 != activate_threads_~tmp~1#1); 19687#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19643#L617 assume !(1 == ~t1_pc~0); 18565#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18566#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18425#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18426#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19186#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19187#L636 assume 1 == ~t2_pc~0; 18534#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18535#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18365#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18366#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 19222#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18886#L655 assume !(1 == ~t3_pc~0); 18887#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19599#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18239#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18240#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 19716#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19717#L674 assume 1 == ~t4_pc~0; 18059#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18060#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19357#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18369#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 18370#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18882#L693 assume !(1 == ~t5_pc~0); 19045#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 18692#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18693#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19526#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 18775#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18712#L712 assume 1 == ~t6_pc~0; 18713#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19140#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19141#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19427#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 19238#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19236#L731 assume 1 == ~t7_pc~0; 18213#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18214#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18410#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19346#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 19464#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18323#L750 assume !(1 == ~t8_pc~0); 17994#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17993#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18509#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19539#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18646#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18647#L769 assume 1 == ~t9_pc~0; 19184#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18167#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18168#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18951#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 19403#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19484#L788 assume !(1 == ~t10_pc~0); 19059#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19060#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19293#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19294#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 18321#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18322#L807 assume 1 == ~t11_pc~0; 19493#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19071#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19224#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19635#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 19740#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19583#L826 assume !(1 == ~t12_pc~0); 18717#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 18718#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19244#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19675#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 18875#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18784#L1344 assume !(1 == ~M_E~0); 18785#L1344-2 assume !(1 == ~T1_E~0); 18926#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19099#L1354-1 assume !(1 == ~T3_E~0); 19100#L1359-1 assume !(1 == ~T4_E~0); 19473#L1364-1 assume !(1 == ~T5_E~0); 18427#L1369-1 assume !(1 == ~T6_E~0); 18428#L1374-1 assume !(1 == ~T7_E~0); 19106#L1379-1 assume !(1 == ~T8_E~0); 19107#L1384-1 assume !(1 == ~T9_E~0); 19168#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19614#L1394-1 assume !(1 == ~T11_E~0); 19615#L1399-1 assume !(1 == ~T12_E~0); 19694#L1404-1 assume !(1 == ~E_M~0); 18546#L1409-1 assume !(1 == ~E_1~0); 18547#L1414-1 assume !(1 == ~E_2~0); 19384#L1419-1 assume !(1 == ~E_3~0); 18180#L1424-1 assume !(1 == ~E_4~0); 18181#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 19118#L1434-1 assume !(1 == ~E_6~0); 19633#L1439-1 assume !(1 == ~E_7~0); 18235#L1444-1 assume !(1 == ~E_8~0); 18236#L1449-1 assume !(1 == ~E_9~0); 18651#L1454-1 assume !(1 == ~E_10~0); 18652#L1459-1 assume !(1 == ~E_11~0); 19202#L1464-1 assume !(1 == ~E_12~0); 19203#L1469-1 assume { :end_inline_reset_delta_events } true; 19250#L1815-2 [2021-11-19 05:20:48,372 INFO L793 eck$LassoCheckResult]: Loop: 19250#L1815-2 assume !false; 19404#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19073#L1181 assume !false; 19144#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19096#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17954#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18684#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19234#L1008 assume !(0 != eval_~tmp~0#1); 19235#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18175#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18176#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19734#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19201#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18307#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18308#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18898#L1226-3 assume !(0 == ~T5_E~0); 18371#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18372#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18683#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19671#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19574#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19310#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18329#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18330#L1266-3 assume !(0 == ~E_M~0); 18367#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18368#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18842#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18843#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19380#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19381#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19723#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19691#L1306-3 assume !(0 == ~E_8~0); 18967#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18253#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18254#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18331#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 19065#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19391#L598-42 assume !(1 == ~m_pc~0); 19392#L598-44 is_master_triggered_~__retres1~0#1 := 0; 19506#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18408#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18409#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 19692#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19122#L617-42 assume 1 == ~t1_pc~0; 18894#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18759#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18760#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19174#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18474#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18475#L636-42 assume !(1 == ~t2_pc~0); 18938#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 18939#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19289#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19290#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19469#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19331#L655-42 assume 1 == ~t3_pc~0; 19332#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18912#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18544#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18545#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19598#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19543#L674-42 assume !(1 == ~t4_pc~0); 19317#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 19239#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18128#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18129#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19043#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19044#L693-42 assume 1 == ~t5_pc~0; 19299#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19300#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19360#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19355#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19356#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18658#L712-42 assume !(1 == ~t6_pc~0); 18659#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 18985#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19193#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19194#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18767#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18768#L731-42 assume !(1 == ~t7_pc~0); 18466#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 18467#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19534#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18675#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18676#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18379#L750-42 assume 1 == ~t8_pc~0; 18380#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18954#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19377#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18272#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18273#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19042#L769-42 assume 1 == ~t9_pc~0; 18864#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18865#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19548#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19613#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 18476#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18477#L788-42 assume 1 == ~t10_pc~0; 19050#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19264#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18994#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18995#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19732#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19710#L807-42 assume !(1 == ~t11_pc~0); 18080#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 18081#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18219#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18220#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18222#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18471#L826-42 assume 1 == ~t12_pc~0; 18472#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 18664#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19456#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18461#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18462#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19313#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19314#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19240#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18621#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18622#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19254#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19712#L1369-3 assume !(1 == ~T6_E~0); 19632#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18386#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18387#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18619#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18620#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18918#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19641#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19604#L1409-3 assume !(1 == ~E_1~0); 19605#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19670#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19450#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18287#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18288#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19253#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18227#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18228#L1449-3 assume !(1 == ~E_9~0); 18337#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19247#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 19248#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 19629#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19127#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18126#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18127#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 18743#L1834 assume !(0 == start_simulation_~tmp~3#1); 19363#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19386#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18820#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18999#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19211#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19619#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18112#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 18113#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 19250#L1815-2 [2021-11-19 05:20:48,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:48,378 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2021-11-19 05:20:48,378 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:48,378 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2043182105] [2021-11-19 05:20:48,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:48,378 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:48,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:48,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:48,414 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:48,414 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2043182105] [2021-11-19 05:20:48,414 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2043182105] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:48,414 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:48,415 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:48,415 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1976227107] [2021-11-19 05:20:48,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:48,417 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:20:48,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:48,420 INFO L85 PathProgramCache]: Analyzing trace with hash -112792235, now seen corresponding path program 1 times [2021-11-19 05:20:48,420 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:48,425 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [555190752] [2021-11-19 05:20:48,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:48,425 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:48,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:48,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:48,474 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:48,475 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [555190752] [2021-11-19 05:20:48,475 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [555190752] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:48,475 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:48,475 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:48,475 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [532712525] [2021-11-19 05:20:48,476 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:48,476 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:20:48,477 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:20:48,477 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:20:48,478 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:20:48,478 INFO L87 Difference]: Start difference. First operand 1790 states and 2651 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:48,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:20:48,518 INFO L93 Difference]: Finished difference Result 1790 states and 2650 transitions. [2021-11-19 05:20:48,519 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:20:48,520 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2650 transitions. [2021-11-19 05:20:48,537 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:48,552 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2650 transitions. [2021-11-19 05:20:48,552 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-19 05:20:48,554 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-19 05:20:48,554 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2650 transitions. [2021-11-19 05:20:48,557 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:20:48,557 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2650 transitions. [2021-11-19 05:20:48,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2650 transitions. [2021-11-19 05:20:48,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-19 05:20:48,620 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4804469273743017) internal successors, (2650), 1789 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:48,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2650 transitions. [2021-11-19 05:20:48,628 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2650 transitions. [2021-11-19 05:20:48,628 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2650 transitions. [2021-11-19 05:20:48,628 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-19 05:20:48,628 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2650 transitions. [2021-11-19 05:20:48,637 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:48,637 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:48,638 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:48,640 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:48,640 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:48,641 INFO L791 eck$LassoCheckResult]: Stem: 22382#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 22383#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 21808#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21778#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21779#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 23038#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22085#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21538#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21539#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22810#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22949#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 23315#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23316#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22297#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22298#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22836#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22756#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22757#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22909#L1206 assume !(0 == ~M_E~0); 22274#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22275#L1211-1 assume !(0 == ~T2_E~0); 23168#L1216-1 assume !(0 == ~T3_E~0); 22067#L1221-1 assume !(0 == ~T4_E~0); 22068#L1226-1 assume !(0 == ~T5_E~0); 21732#L1231-1 assume !(0 == ~T6_E~0); 21733#L1236-1 assume !(0 == ~T7_E~0); 23199#L1241-1 assume !(0 == ~T8_E~0); 22129#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22130#L1251-1 assume !(0 == ~T10_E~0); 22350#L1256-1 assume !(0 == ~T11_E~0); 21550#L1261-1 assume !(0 == ~T12_E~0); 21551#L1266-1 assume !(0 == ~E_M~0); 23302#L1271-1 assume !(0 == ~E_1~0); 22937#L1276-1 assume !(0 == ~E_2~0); 22938#L1281-1 assume !(0 == ~E_3~0); 22865#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 21971#L1291-1 assume !(0 == ~E_5~0); 21972#L1296-1 assume !(0 == ~E_6~0); 22678#L1301-1 assume !(0 == ~E_7~0); 22679#L1306-1 assume !(0 == ~E_8~0); 23111#L1311-1 assume !(0 == ~E_9~0); 21932#L1316-1 assume !(0 == ~E_10~0); 21933#L1321-1 assume !(0 == ~E_11~0); 22695#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 21798#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21799#L598 assume 1 == ~m_pc~0; 21856#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21857#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23181#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23273#L1497 assume !(0 != activate_threads_~tmp~1#1); 23274#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23230#L617 assume !(1 == ~t1_pc~0); 22152#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22153#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22012#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22013#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22773#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22774#L636 assume 1 == ~t2_pc~0; 22121#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22122#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21952#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21953#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 22809#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22472#L655 assume !(1 == ~t3_pc~0); 22473#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23186#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21826#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21827#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 23303#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23304#L674 assume 1 == ~t4_pc~0; 21646#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21647#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22944#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21954#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 21955#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22469#L693 assume !(1 == ~t5_pc~0); 22632#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 22279#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22280#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23113#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 22362#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22299#L712 assume 1 == ~t6_pc~0; 22300#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22727#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22728#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23014#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 22825#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22823#L731 assume 1 == ~t7_pc~0; 21800#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21801#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21995#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22933#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 23051#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21910#L750 assume !(1 == ~t8_pc~0); 21581#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 21580#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22096#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23126#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22233#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22234#L769 assume 1 == ~t9_pc~0; 22771#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21754#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21755#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22538#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 22990#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23071#L788 assume !(1 == ~t10_pc~0); 22646#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22647#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22879#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22880#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 21906#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21907#L807 assume 1 == ~t11_pc~0; 23080#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22658#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22811#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23222#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 23327#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 23170#L826 assume !(1 == ~t12_pc~0); 22304#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22305#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22831#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23262#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 22462#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22371#L1344 assume !(1 == ~M_E~0); 22372#L1344-2 assume !(1 == ~T1_E~0); 22513#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22686#L1354-1 assume !(1 == ~T3_E~0); 22687#L1359-1 assume !(1 == ~T4_E~0); 23060#L1364-1 assume !(1 == ~T5_E~0); 22014#L1369-1 assume !(1 == ~T6_E~0); 22015#L1374-1 assume !(1 == ~T7_E~0); 22693#L1379-1 assume !(1 == ~T8_E~0); 22694#L1384-1 assume !(1 == ~T9_E~0); 22755#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 23201#L1394-1 assume !(1 == ~T11_E~0); 23202#L1399-1 assume !(1 == ~T12_E~0); 23281#L1404-1 assume !(1 == ~E_M~0); 22133#L1409-1 assume !(1 == ~E_1~0); 22134#L1414-1 assume !(1 == ~E_2~0); 22971#L1419-1 assume !(1 == ~E_3~0); 21767#L1424-1 assume !(1 == ~E_4~0); 21768#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22705#L1434-1 assume !(1 == ~E_6~0); 23220#L1439-1 assume !(1 == ~E_7~0); 21822#L1444-1 assume !(1 == ~E_8~0); 21823#L1449-1 assume !(1 == ~E_9~0); 22238#L1454-1 assume !(1 == ~E_10~0); 22239#L1459-1 assume !(1 == ~E_11~0); 22789#L1464-1 assume !(1 == ~E_12~0); 22790#L1469-1 assume { :end_inline_reset_delta_events } true; 22837#L1815-2 [2021-11-19 05:20:48,641 INFO L793 eck$LassoCheckResult]: Loop: 22837#L1815-2 assume !false; 22991#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22660#L1181 assume !false; 22731#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22683#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21541#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22270#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22821#L1008 assume !(0 != eval_~tmp~0#1); 22822#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21762#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21763#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23321#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22788#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21894#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21895#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22485#L1226-3 assume !(0 == ~T5_E~0); 21958#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21959#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22271#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23259#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23161#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22897#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21918#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21919#L1266-3 assume !(0 == ~E_M~0); 21956#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21957#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22429#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22430#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22967#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22968#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23310#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23278#L1306-3 assume !(0 == ~E_8~0); 22554#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21840#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21841#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 21920#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22653#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22978#L598-42 assume !(1 == ~m_pc~0); 22979#L598-44 is_master_triggered_~__retres1~0#1 := 0; 23093#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21996#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21997#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 23279#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22709#L617-42 assume 1 == ~t1_pc~0; 22482#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22346#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22347#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22761#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22061#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22062#L636-42 assume !(1 == ~t2_pc~0); 22524#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 22525#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22875#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22876#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23056#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22915#L655-42 assume !(1 == ~t3_pc~0); 22497#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 22498#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22131#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22132#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23185#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23130#L674-42 assume !(1 == ~t4_pc~0); 22904#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 22826#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21715#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21716#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22630#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22631#L693-42 assume 1 == ~t5_pc~0; 22886#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22887#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22946#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22941#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22942#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22245#L712-42 assume !(1 == ~t6_pc~0); 22246#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 22572#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22780#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22781#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22354#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22355#L731-42 assume !(1 == ~t7_pc~0); 22053#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 22054#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23121#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22262#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22263#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21966#L750-42 assume !(1 == ~t8_pc~0); 21968#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 22541#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22964#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21859#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21860#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22629#L769-42 assume 1 == ~t9_pc~0; 22450#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22451#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23135#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23200#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 22063#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22064#L788-42 assume 1 == ~t10_pc~0; 22637#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22851#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22581#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22582#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23319#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23296#L807-42 assume !(1 == ~t11_pc~0); 21667#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 21668#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21806#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21807#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21809#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22058#L826-42 assume 1 == ~t12_pc~0; 22059#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 22251#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23043#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22048#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22049#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22900#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22901#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22827#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22208#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22209#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22841#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23299#L1369-3 assume !(1 == ~T6_E~0); 23219#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21973#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21974#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22206#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22207#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22505#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 23228#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23191#L1409-3 assume !(1 == ~E_1~0); 23192#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23257#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23037#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21874#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21875#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22840#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21814#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21815#L1449-3 assume !(1 == ~E_9~0); 21924#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22833#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 22834#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 23216#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22714#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21713#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21714#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 22330#L1834 assume !(0 == start_simulation_~tmp~3#1); 22950#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22973#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22407#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22586#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 22798#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23206#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21699#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 21700#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 22837#L1815-2 [2021-11-19 05:20:48,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:48,642 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2021-11-19 05:20:48,642 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:48,642 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885665805] [2021-11-19 05:20:48,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:48,643 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:48,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:48,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:48,677 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:48,678 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [885665805] [2021-11-19 05:20:48,678 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [885665805] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:48,678 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:48,678 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:48,678 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1247553856] [2021-11-19 05:20:48,678 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:48,679 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:20:48,679 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:48,679 INFO L85 PathProgramCache]: Analyzing trace with hash -1085730025, now seen corresponding path program 1 times [2021-11-19 05:20:48,679 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:48,680 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [779770914] [2021-11-19 05:20:48,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:48,680 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:48,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:48,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:48,743 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:48,744 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [779770914] [2021-11-19 05:20:48,744 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [779770914] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:48,744 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:48,744 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:48,744 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [265659898] [2021-11-19 05:20:48,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:48,745 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:20:48,745 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:20:48,745 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:20:48,746 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:20:48,746 INFO L87 Difference]: Start difference. First operand 1790 states and 2650 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:48,786 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:20:48,786 INFO L93 Difference]: Finished difference Result 1790 states and 2649 transitions. [2021-11-19 05:20:48,787 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:20:48,789 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2649 transitions. [2021-11-19 05:20:48,803 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:48,818 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2649 transitions. [2021-11-19 05:20:48,818 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-19 05:20:48,822 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-19 05:20:48,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2649 transitions. [2021-11-19 05:20:48,825 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:20:48,825 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2649 transitions. [2021-11-19 05:20:48,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2649 transitions. [2021-11-19 05:20:48,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-19 05:20:48,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4798882681564245) internal successors, (2649), 1789 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:48,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2649 transitions. [2021-11-19 05:20:48,870 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2649 transitions. [2021-11-19 05:20:48,870 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2649 transitions. [2021-11-19 05:20:48,870 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-19 05:20:48,870 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2649 transitions. [2021-11-19 05:20:48,880 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:48,880 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:48,880 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:48,883 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:48,883 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:48,883 INFO L791 eck$LassoCheckResult]: Stem: 25969#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25970#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 25395#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25363#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25364#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 26625#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25672#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25125#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25126#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26397#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26536#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26902#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26903#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25884#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25885#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26423#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26343#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26344#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26496#L1206 assume !(0 == ~M_E~0); 25861#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25862#L1211-1 assume !(0 == ~T2_E~0); 26755#L1216-1 assume !(0 == ~T3_E~0); 25654#L1221-1 assume !(0 == ~T4_E~0); 25655#L1226-1 assume !(0 == ~T5_E~0); 25317#L1231-1 assume !(0 == ~T6_E~0); 25318#L1236-1 assume !(0 == ~T7_E~0); 26786#L1241-1 assume !(0 == ~T8_E~0); 25716#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25717#L1251-1 assume !(0 == ~T10_E~0); 25937#L1256-1 assume !(0 == ~T11_E~0); 25137#L1261-1 assume !(0 == ~T12_E~0); 25138#L1266-1 assume !(0 == ~E_M~0); 26889#L1271-1 assume !(0 == ~E_1~0); 26524#L1276-1 assume !(0 == ~E_2~0); 26525#L1281-1 assume !(0 == ~E_3~0); 26450#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 25558#L1291-1 assume !(0 == ~E_5~0); 25559#L1296-1 assume !(0 == ~E_6~0); 26265#L1301-1 assume !(0 == ~E_7~0); 26266#L1306-1 assume !(0 == ~E_8~0); 26698#L1311-1 assume !(0 == ~E_9~0); 25519#L1316-1 assume !(0 == ~E_10~0); 25520#L1321-1 assume !(0 == ~E_11~0); 26282#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 25383#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25384#L598 assume 1 == ~m_pc~0; 25443#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25444#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26768#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26860#L1497 assume !(0 != activate_threads_~tmp~1#1); 26861#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26817#L617 assume !(1 == ~t1_pc~0); 25739#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25740#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25599#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25600#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26360#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26361#L636 assume 1 == ~t2_pc~0; 25708#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25709#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25539#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25540#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 26396#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26059#L655 assume !(1 == ~t3_pc~0); 26060#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26773#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25413#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25414#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 26890#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26891#L674 assume 1 == ~t4_pc~0; 25233#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25234#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26531#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25541#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 25542#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26056#L693 assume !(1 == ~t5_pc~0); 26219#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25864#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25865#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26700#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 25949#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25886#L712 assume 1 == ~t6_pc~0; 25887#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26314#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26315#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26601#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 26412#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26410#L731 assume 1 == ~t7_pc~0; 25387#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25388#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25582#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26519#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 26638#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25497#L750 assume !(1 == ~t8_pc~0); 25168#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25167#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25683#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26713#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25820#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25821#L769 assume 1 == ~t9_pc~0; 26358#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25341#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25342#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26125#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 26577#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26658#L788 assume !(1 == ~t10_pc~0); 26233#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 26234#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26466#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26467#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 25493#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25494#L807 assume 1 == ~t11_pc~0; 26667#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26245#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26398#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26809#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 26914#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26757#L826 assume !(1 == ~t12_pc~0); 25889#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 25890#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26418#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26849#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 26049#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25958#L1344 assume !(1 == ~M_E~0); 25959#L1344-2 assume !(1 == ~T1_E~0); 26100#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26273#L1354-1 assume !(1 == ~T3_E~0); 26274#L1359-1 assume !(1 == ~T4_E~0); 26647#L1364-1 assume !(1 == ~T5_E~0); 25601#L1369-1 assume !(1 == ~T6_E~0); 25602#L1374-1 assume !(1 == ~T7_E~0); 26280#L1379-1 assume !(1 == ~T8_E~0); 26281#L1384-1 assume !(1 == ~T9_E~0); 26342#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26788#L1394-1 assume !(1 == ~T11_E~0); 26789#L1399-1 assume !(1 == ~T12_E~0); 26868#L1404-1 assume !(1 == ~E_M~0); 25720#L1409-1 assume !(1 == ~E_1~0); 25721#L1414-1 assume !(1 == ~E_2~0); 26558#L1419-1 assume !(1 == ~E_3~0); 25354#L1424-1 assume !(1 == ~E_4~0); 25355#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26289#L1434-1 assume !(1 == ~E_6~0); 26807#L1439-1 assume !(1 == ~E_7~0); 25409#L1444-1 assume !(1 == ~E_8~0); 25410#L1449-1 assume !(1 == ~E_9~0); 25825#L1454-1 assume !(1 == ~E_10~0); 25826#L1459-1 assume !(1 == ~E_11~0); 26376#L1464-1 assume !(1 == ~E_12~0); 26377#L1469-1 assume { :end_inline_reset_delta_events } true; 26424#L1815-2 [2021-11-19 05:20:48,884 INFO L793 eck$LassoCheckResult]: Loop: 26424#L1815-2 assume !false; 26578#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26247#L1181 assume !false; 26318#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26270#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25128#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25857#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26408#L1008 assume !(0 != eval_~tmp~0#1); 26409#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25349#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25350#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26908#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26375#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25481#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25482#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26072#L1226-3 assume !(0 == ~T5_E~0); 25545#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25546#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25858#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26846#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26748#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26484#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25503#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25504#L1266-3 assume !(0 == ~E_M~0); 25543#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25544#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26016#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26017#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26554#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26555#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26897#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26865#L1306-3 assume !(0 == ~E_8~0); 26141#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25427#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25428#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25505#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 26240#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26565#L598-42 assume !(1 == ~m_pc~0); 26566#L598-44 is_master_triggered_~__retres1~0#1 := 0; 26680#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25583#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25584#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 26866#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26296#L617-42 assume 1 == ~t1_pc~0; 26069#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25933#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25934#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26348#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25648#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25649#L636-42 assume !(1 == ~t2_pc~0); 26112#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 26113#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26463#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26464#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26643#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26505#L655-42 assume !(1 == ~t3_pc~0); 26089#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 26090#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25718#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25719#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26772#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26717#L674-42 assume !(1 == ~t4_pc~0); 26491#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 26413#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25302#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25303#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26217#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26218#L693-42 assume 1 == ~t5_pc~0; 26476#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26477#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26534#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26529#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26530#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25832#L712-42 assume !(1 == ~t6_pc~0); 25833#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 26160#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26367#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26368#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25941#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25942#L731-42 assume !(1 == ~t7_pc~0); 25637#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 25638#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26708#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25849#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25850#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25550#L750-42 assume !(1 == ~t8_pc~0); 25552#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 26128#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26551#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25446#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25447#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26216#L769-42 assume 1 == ~t9_pc~0; 26036#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26037#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26722#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26787#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 25650#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25651#L788-42 assume 1 == ~t10_pc~0; 26224#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26435#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26168#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26169#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26906#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26882#L807-42 assume !(1 == ~t11_pc~0); 25254#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 25255#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25393#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25394#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25396#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25645#L826-42 assume 1 == ~t12_pc~0; 25646#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 25838#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26630#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25635#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25636#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26487#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26488#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26414#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25795#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25796#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26428#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26886#L1369-3 assume !(1 == ~T6_E~0); 26806#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25560#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25561#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25793#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25794#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26092#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26815#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26778#L1409-3 assume !(1 == ~E_1~0); 26779#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26844#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26624#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25461#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25462#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26427#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25399#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25400#L1449-3 assume !(1 == ~E_9~0); 25511#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26420#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 26421#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 26803#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26301#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25300#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25301#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 25917#L1834 assume !(0 == start_simulation_~tmp~3#1); 26537#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26560#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25994#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 26173#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 26385#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26793#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25286#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 25287#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 26424#L1815-2 [2021-11-19 05:20:48,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:48,885 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2021-11-19 05:20:48,885 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:48,885 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [861233814] [2021-11-19 05:20:48,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:48,885 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:48,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:48,929 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:48,929 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:48,929 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [861233814] [2021-11-19 05:20:48,929 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [861233814] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:48,931 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:48,931 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:48,931 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743539043] [2021-11-19 05:20:48,931 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:48,932 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:20:48,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:48,932 INFO L85 PathProgramCache]: Analyzing trace with hash -1085730025, now seen corresponding path program 2 times [2021-11-19 05:20:48,932 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:48,932 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [579477260] [2021-11-19 05:20:48,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:48,933 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:48,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:48,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:48,981 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:48,983 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [579477260] [2021-11-19 05:20:48,985 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [579477260] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:48,985 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:48,986 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:48,986 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [461460129] [2021-11-19 05:20:48,986 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:48,986 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:20:48,987 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:20:48,987 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:20:48,987 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:20:48,987 INFO L87 Difference]: Start difference. First operand 1790 states and 2649 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:49,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:20:49,067 INFO L93 Difference]: Finished difference Result 1790 states and 2648 transitions. [2021-11-19 05:20:49,067 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:20:49,069 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2648 transitions. [2021-11-19 05:20:49,082 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:49,097 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2648 transitions. [2021-11-19 05:20:49,097 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-19 05:20:49,099 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-19 05:20:49,099 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2648 transitions. [2021-11-19 05:20:49,102 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:20:49,102 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2648 transitions. [2021-11-19 05:20:49,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2648 transitions. [2021-11-19 05:20:49,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-19 05:20:49,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4793296089385475) internal successors, (2648), 1789 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:49,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2648 transitions. [2021-11-19 05:20:49,152 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2648 transitions. [2021-11-19 05:20:49,152 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2648 transitions. [2021-11-19 05:20:49,152 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-19 05:20:49,152 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2648 transitions. [2021-11-19 05:20:49,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:49,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:49,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:49,163 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:49,163 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:49,164 INFO L791 eck$LassoCheckResult]: Stem: 29556#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 29557#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 28980#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28950#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28951#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 30212#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29259#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28712#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28713#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29984#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30123#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30489#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30490#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29469#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29470#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 30010#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29930#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29931#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30083#L1206 assume !(0 == ~M_E~0); 29448#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29449#L1211-1 assume !(0 == ~T2_E~0); 30342#L1216-1 assume !(0 == ~T3_E~0); 29241#L1221-1 assume !(0 == ~T4_E~0); 29242#L1226-1 assume !(0 == ~T5_E~0); 28904#L1231-1 assume !(0 == ~T6_E~0); 28905#L1236-1 assume !(0 == ~T7_E~0); 30373#L1241-1 assume !(0 == ~T8_E~0); 29303#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29304#L1251-1 assume !(0 == ~T10_E~0); 29524#L1256-1 assume !(0 == ~T11_E~0); 28724#L1261-1 assume !(0 == ~T12_E~0); 28725#L1266-1 assume !(0 == ~E_M~0); 30476#L1271-1 assume !(0 == ~E_1~0); 30111#L1276-1 assume !(0 == ~E_2~0); 30112#L1281-1 assume !(0 == ~E_3~0); 30037#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 29145#L1291-1 assume !(0 == ~E_5~0); 29146#L1296-1 assume !(0 == ~E_6~0); 29852#L1301-1 assume !(0 == ~E_7~0); 29853#L1306-1 assume !(0 == ~E_8~0); 30285#L1311-1 assume !(0 == ~E_9~0); 29106#L1316-1 assume !(0 == ~E_10~0); 29107#L1321-1 assume !(0 == ~E_11~0); 29869#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 28970#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28971#L598 assume 1 == ~m_pc~0; 29030#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29031#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30355#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30447#L1497 assume !(0 != activate_threads_~tmp~1#1); 30448#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30404#L617 assume !(1 == ~t1_pc~0); 29326#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29327#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29186#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29187#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29947#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29948#L636 assume 1 == ~t2_pc~0; 29295#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29296#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29126#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29127#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 29983#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29646#L655 assume !(1 == ~t3_pc~0); 29647#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30360#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29000#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29001#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 30477#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30478#L674 assume 1 == ~t4_pc~0; 28820#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28821#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30118#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29128#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 29129#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29643#L693 assume !(1 == ~t5_pc~0); 29806#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 29450#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29451#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30287#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 29536#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29473#L712 assume 1 == ~t6_pc~0; 29474#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29901#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29902#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30188#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 29999#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29997#L731 assume 1 == ~t7_pc~0; 28974#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28975#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29169#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30106#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 30225#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29084#L750 assume !(1 == ~t8_pc~0); 28755#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 28754#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29270#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30300#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29407#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29408#L769 assume 1 == ~t9_pc~0; 29945#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28928#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28929#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29712#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 30164#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30245#L788 assume !(1 == ~t10_pc~0); 29820#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29821#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30052#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30053#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 29080#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29081#L807 assume 1 == ~t11_pc~0; 30254#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29832#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29985#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30396#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 30501#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30344#L826 assume !(1 == ~t12_pc~0); 29476#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29477#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30005#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30436#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 29636#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29545#L1344 assume !(1 == ~M_E~0); 29546#L1344-2 assume !(1 == ~T1_E~0); 29687#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29859#L1354-1 assume !(1 == ~T3_E~0); 29860#L1359-1 assume !(1 == ~T4_E~0); 30234#L1364-1 assume !(1 == ~T5_E~0); 29188#L1369-1 assume !(1 == ~T6_E~0); 29189#L1374-1 assume !(1 == ~T7_E~0); 29865#L1379-1 assume !(1 == ~T8_E~0); 29866#L1384-1 assume !(1 == ~T9_E~0); 29929#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30375#L1394-1 assume !(1 == ~T11_E~0); 30376#L1399-1 assume !(1 == ~T12_E~0); 30455#L1404-1 assume !(1 == ~E_M~0); 29307#L1409-1 assume !(1 == ~E_1~0); 29308#L1414-1 assume !(1 == ~E_2~0); 30145#L1419-1 assume !(1 == ~E_3~0); 28941#L1424-1 assume !(1 == ~E_4~0); 28942#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 29876#L1434-1 assume !(1 == ~E_6~0); 30394#L1439-1 assume !(1 == ~E_7~0); 28996#L1444-1 assume !(1 == ~E_8~0); 28997#L1449-1 assume !(1 == ~E_9~0); 29412#L1454-1 assume !(1 == ~E_10~0); 29413#L1459-1 assume !(1 == ~E_11~0); 29963#L1464-1 assume !(1 == ~E_12~0); 29964#L1469-1 assume { :end_inline_reset_delta_events } true; 30011#L1815-2 [2021-11-19 05:20:49,164 INFO L793 eck$LassoCheckResult]: Loop: 30011#L1815-2 assume !false; 30165#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29834#L1181 assume !false; 29905#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29857#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28715#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29444#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29995#L1008 assume !(0 != eval_~tmp~0#1); 29996#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28934#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28935#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30495#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29962#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29068#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29069#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29659#L1226-3 assume !(0 == ~T5_E~0); 29132#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29133#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29445#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30432#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30335#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30071#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29090#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29091#L1266-3 assume !(0 == ~E_M~0); 29130#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29131#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29603#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29604#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30141#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30142#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30484#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30452#L1306-3 assume !(0 == ~E_8~0); 29728#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29014#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29015#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29092#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29827#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30152#L598-42 assume !(1 == ~m_pc~0); 30153#L598-44 is_master_triggered_~__retres1~0#1 := 0; 30267#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29170#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29171#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 30453#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29883#L617-42 assume 1 == ~t1_pc~0; 29655#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29520#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29521#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29935#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29235#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29236#L636-42 assume !(1 == ~t2_pc~0); 29699#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 29700#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30050#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30051#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30230#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30092#L655-42 assume !(1 == ~t3_pc~0); 29672#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 29673#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29305#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29306#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30359#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30304#L674-42 assume 1 == ~t4_pc~0; 30305#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30000#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28889#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28890#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29804#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29805#L693-42 assume 1 == ~t5_pc~0; 30060#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30061#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30121#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30116#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30117#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29419#L712-42 assume !(1 == ~t6_pc~0); 29420#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 29746#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29954#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29955#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29528#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29529#L731-42 assume 1 == ~t7_pc~0; 29392#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29228#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30295#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29436#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29437#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29140#L750-42 assume 1 == ~t8_pc~0; 29141#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29715#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30138#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29033#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29034#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29803#L769-42 assume 1 == ~t9_pc~0; 29625#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29626#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30309#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30374#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 29237#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29238#L788-42 assume 1 == ~t10_pc~0; 29811#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30025#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29755#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29756#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30493#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30471#L807-42 assume 1 == ~t11_pc~0; 30160#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28842#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28981#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28982#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28983#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29232#L826-42 assume 1 == ~t12_pc~0; 29233#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 29425#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30217#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29222#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29223#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30074#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30075#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30001#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29382#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29383#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30015#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30473#L1369-3 assume !(1 == ~T6_E~0); 30393#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29147#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29148#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29380#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29381#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29679#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30402#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30365#L1409-3 assume !(1 == ~E_1~0); 30366#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30431#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30211#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29048#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29049#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30014#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28988#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28989#L1449-3 assume !(1 == ~E_9~0); 29098#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30008#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 30009#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 30390#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29888#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28887#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28888#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 29504#L1834 assume !(0 == start_simulation_~tmp~3#1); 30124#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 30147#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29582#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29760#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 29972#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30380#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28873#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 28874#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 30011#L1815-2 [2021-11-19 05:20:49,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:49,165 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2021-11-19 05:20:49,165 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:49,165 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799954815] [2021-11-19 05:20:49,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:49,165 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:49,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:49,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:49,200 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:49,200 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [799954815] [2021-11-19 05:20:49,200 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [799954815] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:49,200 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:49,200 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:49,201 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [440615475] [2021-11-19 05:20:49,201 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:49,201 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:20:49,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:49,202 INFO L85 PathProgramCache]: Analyzing trace with hash -1380802157, now seen corresponding path program 2 times [2021-11-19 05:20:49,202 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:49,202 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [703387215] [2021-11-19 05:20:49,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:49,203 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:49,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:49,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:49,246 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:49,246 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [703387215] [2021-11-19 05:20:49,246 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [703387215] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:49,246 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:49,246 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:49,247 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1781295045] [2021-11-19 05:20:49,247 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:49,247 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:20:49,247 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:20:49,248 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:20:49,248 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:20:49,248 INFO L87 Difference]: Start difference. First operand 1790 states and 2648 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:49,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:20:49,287 INFO L93 Difference]: Finished difference Result 1790 states and 2647 transitions. [2021-11-19 05:20:49,287 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:20:49,288 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2647 transitions. [2021-11-19 05:20:49,298 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:49,311 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2647 transitions. [2021-11-19 05:20:49,311 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-19 05:20:49,313 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-19 05:20:49,313 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2647 transitions. [2021-11-19 05:20:49,316 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:20:49,316 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2647 transitions. [2021-11-19 05:20:49,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2647 transitions. [2021-11-19 05:20:49,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-19 05:20:49,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4787709497206705) internal successors, (2647), 1789 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:49,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2647 transitions. [2021-11-19 05:20:49,356 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2647 transitions. [2021-11-19 05:20:49,356 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2647 transitions. [2021-11-19 05:20:49,356 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-19 05:20:49,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2647 transitions. [2021-11-19 05:20:49,365 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:49,365 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:49,365 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:49,368 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:49,368 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:49,369 INFO L791 eck$LassoCheckResult]: Stem: 33143#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 33144#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 32567#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32537#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32538#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 33799#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32846#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32299#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32300#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33571#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33710#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34076#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34077#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33056#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33057#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33597#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33517#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33518#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33670#L1206 assume !(0 == ~M_E~0); 33035#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33036#L1211-1 assume !(0 == ~T2_E~0); 33929#L1216-1 assume !(0 == ~T3_E~0); 32828#L1221-1 assume !(0 == ~T4_E~0); 32829#L1226-1 assume !(0 == ~T5_E~0); 32491#L1231-1 assume !(0 == ~T6_E~0); 32492#L1236-1 assume !(0 == ~T7_E~0); 33960#L1241-1 assume !(0 == ~T8_E~0); 32890#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32891#L1251-1 assume !(0 == ~T10_E~0); 33111#L1256-1 assume !(0 == ~T11_E~0); 32311#L1261-1 assume !(0 == ~T12_E~0); 32312#L1266-1 assume !(0 == ~E_M~0); 34063#L1271-1 assume !(0 == ~E_1~0); 33698#L1276-1 assume !(0 == ~E_2~0); 33699#L1281-1 assume !(0 == ~E_3~0); 33624#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 32732#L1291-1 assume !(0 == ~E_5~0); 32733#L1296-1 assume !(0 == ~E_6~0); 33439#L1301-1 assume !(0 == ~E_7~0); 33440#L1306-1 assume !(0 == ~E_8~0); 33872#L1311-1 assume !(0 == ~E_9~0); 32693#L1316-1 assume !(0 == ~E_10~0); 32694#L1321-1 assume !(0 == ~E_11~0); 33456#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 32557#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32558#L598 assume 1 == ~m_pc~0; 32617#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32618#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33942#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34034#L1497 assume !(0 != activate_threads_~tmp~1#1); 34035#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33991#L617 assume !(1 == ~t1_pc~0); 32913#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32914#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32773#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32774#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33534#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33535#L636 assume 1 == ~t2_pc~0; 32882#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32883#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32713#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32714#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 33570#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33233#L655 assume !(1 == ~t3_pc~0); 33234#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33947#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32587#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32588#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 34064#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34065#L674 assume 1 == ~t4_pc~0; 32407#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32408#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33705#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32715#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 32716#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33230#L693 assume !(1 == ~t5_pc~0); 33393#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 33037#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33038#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33874#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 33123#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33060#L712 assume 1 == ~t6_pc~0; 33061#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33488#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33489#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33775#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 33586#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33584#L731 assume 1 == ~t7_pc~0; 32561#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32562#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32756#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33693#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 33812#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32671#L750 assume !(1 == ~t8_pc~0); 32342#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32341#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32857#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33887#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32994#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32995#L769 assume 1 == ~t9_pc~0; 33530#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32515#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32516#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33299#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 33751#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33832#L788 assume !(1 == ~t10_pc~0); 33407#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 33408#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33639#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33640#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 32667#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32668#L807 assume 1 == ~t11_pc~0; 33841#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33419#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33572#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33983#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 34088#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33931#L826 assume !(1 == ~t12_pc~0); 33063#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33064#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33592#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34023#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 33223#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33132#L1344 assume !(1 == ~M_E~0); 33133#L1344-2 assume !(1 == ~T1_E~0); 33274#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33446#L1354-1 assume !(1 == ~T3_E~0); 33447#L1359-1 assume !(1 == ~T4_E~0); 33821#L1364-1 assume !(1 == ~T5_E~0); 32775#L1369-1 assume !(1 == ~T6_E~0); 32776#L1374-1 assume !(1 == ~T7_E~0); 33452#L1379-1 assume !(1 == ~T8_E~0); 33453#L1384-1 assume !(1 == ~T9_E~0); 33516#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33962#L1394-1 assume !(1 == ~T11_E~0); 33963#L1399-1 assume !(1 == ~T12_E~0); 34042#L1404-1 assume !(1 == ~E_M~0); 32894#L1409-1 assume !(1 == ~E_1~0); 32895#L1414-1 assume !(1 == ~E_2~0); 33732#L1419-1 assume !(1 == ~E_3~0); 32528#L1424-1 assume !(1 == ~E_4~0); 32529#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 33463#L1434-1 assume !(1 == ~E_6~0); 33981#L1439-1 assume !(1 == ~E_7~0); 32583#L1444-1 assume !(1 == ~E_8~0); 32584#L1449-1 assume !(1 == ~E_9~0); 32999#L1454-1 assume !(1 == ~E_10~0); 33000#L1459-1 assume !(1 == ~E_11~0); 33550#L1464-1 assume !(1 == ~E_12~0); 33551#L1469-1 assume { :end_inline_reset_delta_events } true; 33598#L1815-2 [2021-11-19 05:20:49,369 INFO L793 eck$LassoCheckResult]: Loop: 33598#L1815-2 assume !false; 33752#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33421#L1181 assume !false; 33492#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33444#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32302#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33031#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 33582#L1008 assume !(0 != eval_~tmp~0#1); 33583#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32521#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32522#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34082#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33549#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32655#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32656#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33246#L1226-3 assume !(0 == ~T5_E~0); 32719#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32720#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33032#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 34019#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33922#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33658#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32677#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32678#L1266-3 assume !(0 == ~E_M~0); 32717#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32718#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33190#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33191#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33728#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33729#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34071#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34039#L1306-3 assume !(0 == ~E_8~0); 33315#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32601#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32602#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32679#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 33414#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33739#L598-42 assume !(1 == ~m_pc~0); 33740#L598-44 is_master_triggered_~__retres1~0#1 := 0; 33854#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32757#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32758#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 34040#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33470#L617-42 assume 1 == ~t1_pc~0; 33242#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33107#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33108#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33522#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32822#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32823#L636-42 assume !(1 == ~t2_pc~0); 33286#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 33287#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33637#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33638#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33817#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33679#L655-42 assume 1 == ~t3_pc~0; 33680#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33260#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32892#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32893#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33946#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33891#L674-42 assume !(1 == ~t4_pc~0); 33665#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 33587#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32476#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32477#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33391#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33392#L693-42 assume !(1 == ~t5_pc~0); 33649#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 33648#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33708#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33703#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33704#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33006#L712-42 assume 1 == ~t6_pc~0; 33008#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33333#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33541#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33542#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33115#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33116#L731-42 assume 1 == ~t7_pc~0; 32979#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32815#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33882#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33023#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33024#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32727#L750-42 assume 1 == ~t8_pc~0; 32728#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33302#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33725#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32620#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32621#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33390#L769-42 assume 1 == ~t9_pc~0; 33212#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33213#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33896#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33961#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 32824#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32825#L788-42 assume 1 == ~t10_pc~0; 33398#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33612#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33342#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33343#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34080#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34058#L807-42 assume 1 == ~t11_pc~0; 33747#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32429#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32568#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32569#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32570#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32819#L826-42 assume 1 == ~t12_pc~0; 32820#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 33012#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33804#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32809#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32810#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33661#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33662#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33588#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32969#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32970#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33602#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34060#L1369-3 assume !(1 == ~T6_E~0); 33980#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32734#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32735#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32967#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32968#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33266#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33989#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33952#L1409-3 assume !(1 == ~E_1~0); 33953#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34018#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33798#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32635#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32636#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33601#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32575#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32576#L1449-3 assume !(1 == ~E_9~0); 32685#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33595#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33596#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33977#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33475#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32474#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32475#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 33091#L1834 assume !(0 == start_simulation_~tmp~3#1); 33711#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33734#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 33168#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33347#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 33559#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33967#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32460#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32461#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 33598#L1815-2 [2021-11-19 05:20:49,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:49,370 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2021-11-19 05:20:49,370 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:49,370 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667902280] [2021-11-19 05:20:49,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:49,371 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:49,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:49,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:49,432 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:49,432 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1667902280] [2021-11-19 05:20:49,433 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1667902280] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:49,433 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:49,433 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:49,433 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1750410506] [2021-11-19 05:20:49,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:49,435 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:20:49,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:49,435 INFO L85 PathProgramCache]: Analyzing trace with hash -1098284653, now seen corresponding path program 1 times [2021-11-19 05:20:49,435 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:49,436 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1417624872] [2021-11-19 05:20:49,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:49,436 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:49,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:49,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:49,496 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:49,496 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1417624872] [2021-11-19 05:20:49,497 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1417624872] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:49,497 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:49,497 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:49,497 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1059492838] [2021-11-19 05:20:49,497 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:49,498 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:20:49,498 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:20:49,498 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:20:49,498 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:20:49,499 INFO L87 Difference]: Start difference. First operand 1790 states and 2647 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:49,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:20:49,541 INFO L93 Difference]: Finished difference Result 1790 states and 2646 transitions. [2021-11-19 05:20:49,542 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:20:49,542 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2646 transitions. [2021-11-19 05:20:49,554 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:49,577 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2646 transitions. [2021-11-19 05:20:49,577 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-19 05:20:49,579 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-19 05:20:49,579 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2646 transitions. [2021-11-19 05:20:49,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:20:49,582 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2646 transitions. [2021-11-19 05:20:49,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2646 transitions. [2021-11-19 05:20:49,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-19 05:20:49,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4782122905027932) internal successors, (2646), 1789 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:49,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2646 transitions. [2021-11-19 05:20:49,629 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2646 transitions. [2021-11-19 05:20:49,630 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2646 transitions. [2021-11-19 05:20:49,630 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-19 05:20:49,630 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2646 transitions. [2021-11-19 05:20:49,638 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:49,639 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:49,639 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:49,642 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:49,642 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:49,642 INFO L791 eck$LassoCheckResult]: Stem: 36730#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 36731#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 36154#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36124#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36125#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 37386#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36433#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35886#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35887#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37158#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37297#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37663#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37664#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36643#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36644#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 37184#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37104#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37105#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37257#L1206 assume !(0 == ~M_E~0); 36622#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36623#L1211-1 assume !(0 == ~T2_E~0); 37516#L1216-1 assume !(0 == ~T3_E~0); 36415#L1221-1 assume !(0 == ~T4_E~0); 36416#L1226-1 assume !(0 == ~T5_E~0); 36078#L1231-1 assume !(0 == ~T6_E~0); 36079#L1236-1 assume !(0 == ~T7_E~0); 37547#L1241-1 assume !(0 == ~T8_E~0); 36477#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36478#L1251-1 assume !(0 == ~T10_E~0); 36698#L1256-1 assume !(0 == ~T11_E~0); 35898#L1261-1 assume !(0 == ~T12_E~0); 35899#L1266-1 assume !(0 == ~E_M~0); 37650#L1271-1 assume !(0 == ~E_1~0); 37285#L1276-1 assume !(0 == ~E_2~0); 37286#L1281-1 assume !(0 == ~E_3~0); 37211#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 36319#L1291-1 assume !(0 == ~E_5~0); 36320#L1296-1 assume !(0 == ~E_6~0); 37026#L1301-1 assume !(0 == ~E_7~0); 37027#L1306-1 assume !(0 == ~E_8~0); 37459#L1311-1 assume !(0 == ~E_9~0); 36280#L1316-1 assume !(0 == ~E_10~0); 36281#L1321-1 assume !(0 == ~E_11~0); 37043#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 36144#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36145#L598 assume 1 == ~m_pc~0; 36204#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36205#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37529#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37621#L1497 assume !(0 != activate_threads_~tmp~1#1); 37622#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37578#L617 assume !(1 == ~t1_pc~0); 36500#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36501#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36360#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36361#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37121#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37122#L636 assume 1 == ~t2_pc~0; 36469#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36470#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36300#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36301#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 37157#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36820#L655 assume !(1 == ~t3_pc~0); 36821#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37534#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36174#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36175#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 37651#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37652#L674 assume 1 == ~t4_pc~0; 35994#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35995#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37292#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36302#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 36303#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36817#L693 assume !(1 == ~t5_pc~0); 36980#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36624#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36625#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37461#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 36710#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36647#L712 assume 1 == ~t6_pc~0; 36648#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37075#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37076#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37362#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 37173#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37171#L731 assume 1 == ~t7_pc~0; 36148#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36149#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36343#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37280#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 37399#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36258#L750 assume !(1 == ~t8_pc~0); 35929#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35928#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36444#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37474#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36581#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36582#L769 assume 1 == ~t9_pc~0; 37117#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36102#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36103#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36886#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 37338#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37419#L788 assume !(1 == ~t10_pc~0); 36994#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36995#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37226#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37227#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 36254#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36255#L807 assume 1 == ~t11_pc~0; 37428#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37006#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37159#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37570#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 37675#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37518#L826 assume !(1 == ~t12_pc~0); 36650#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 36651#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37179#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37610#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 36810#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36719#L1344 assume !(1 == ~M_E~0); 36720#L1344-2 assume !(1 == ~T1_E~0); 36861#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37033#L1354-1 assume !(1 == ~T3_E~0); 37034#L1359-1 assume !(1 == ~T4_E~0); 37408#L1364-1 assume !(1 == ~T5_E~0); 36362#L1369-1 assume !(1 == ~T6_E~0); 36363#L1374-1 assume !(1 == ~T7_E~0); 37039#L1379-1 assume !(1 == ~T8_E~0); 37040#L1384-1 assume !(1 == ~T9_E~0); 37103#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37549#L1394-1 assume !(1 == ~T11_E~0); 37550#L1399-1 assume !(1 == ~T12_E~0); 37629#L1404-1 assume !(1 == ~E_M~0); 36481#L1409-1 assume !(1 == ~E_1~0); 36482#L1414-1 assume !(1 == ~E_2~0); 37319#L1419-1 assume !(1 == ~E_3~0); 36115#L1424-1 assume !(1 == ~E_4~0); 36116#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 37050#L1434-1 assume !(1 == ~E_6~0); 37568#L1439-1 assume !(1 == ~E_7~0); 36170#L1444-1 assume !(1 == ~E_8~0); 36171#L1449-1 assume !(1 == ~E_9~0); 36586#L1454-1 assume !(1 == ~E_10~0); 36587#L1459-1 assume !(1 == ~E_11~0); 37137#L1464-1 assume !(1 == ~E_12~0); 37138#L1469-1 assume { :end_inline_reset_delta_events } true; 37185#L1815-2 [2021-11-19 05:20:49,643 INFO L793 eck$LassoCheckResult]: Loop: 37185#L1815-2 assume !false; 37339#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37008#L1181 assume !false; 37079#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37031#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 35889#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36618#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37169#L1008 assume !(0 != eval_~tmp~0#1); 37170#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36108#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36109#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37669#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37136#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36242#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36243#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36833#L1226-3 assume !(0 == ~T5_E~0); 36306#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36307#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36619#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37606#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37509#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37245#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36264#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 36265#L1266-3 assume !(0 == ~E_M~0); 36304#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36305#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36777#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36778#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37315#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37316#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37658#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37626#L1306-3 assume !(0 == ~E_8~0); 36902#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36188#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36189#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36266#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 37001#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37326#L598-42 assume 1 == ~m_pc~0; 37328#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37441#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36344#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36345#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 37627#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37057#L617-42 assume 1 == ~t1_pc~0; 36829#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36694#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36695#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37109#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36409#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36410#L636-42 assume !(1 == ~t2_pc~0); 36873#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 36874#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37224#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37225#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37404#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37266#L655-42 assume 1 == ~t3_pc~0; 37267#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36847#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36479#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36480#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37533#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37478#L674-42 assume !(1 == ~t4_pc~0); 37252#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 37174#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36063#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36064#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36978#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36979#L693-42 assume 1 == ~t5_pc~0; 37234#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37235#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37295#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37290#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37291#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36593#L712-42 assume !(1 == ~t6_pc~0); 36594#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 36920#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37128#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37129#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36702#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36703#L731-42 assume !(1 == ~t7_pc~0); 36401#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 36402#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37469#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36610#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36611#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36314#L750-42 assume 1 == ~t8_pc~0; 36315#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36889#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37312#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36207#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36208#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36977#L769-42 assume !(1 == ~t9_pc~0); 36801#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 36800#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37483#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37548#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 36411#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36412#L788-42 assume 1 == ~t10_pc~0; 36985#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37199#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36929#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36930#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37667#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37645#L807-42 assume 1 == ~t11_pc~0; 37334#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36016#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36155#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36156#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36157#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36406#L826-42 assume 1 == ~t12_pc~0; 36407#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36599#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37391#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36396#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36397#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37248#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37249#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37175#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36556#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36557#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37189#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37647#L1369-3 assume !(1 == ~T6_E~0); 37567#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36321#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36322#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36554#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36555#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36853#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 37576#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37539#L1409-3 assume !(1 == ~E_1~0); 37540#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37605#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37385#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36222#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36223#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37188#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36162#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36163#L1449-3 assume !(1 == ~E_9~0); 36272#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37182#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37183#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37564#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37062#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36061#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36062#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 36678#L1834 assume !(0 == start_simulation_~tmp~3#1); 37298#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37321#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36755#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36934#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 37146#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37554#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36047#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 36048#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 37185#L1815-2 [2021-11-19 05:20:49,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:49,644 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2021-11-19 05:20:49,644 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:49,644 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1545444835] [2021-11-19 05:20:49,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:49,645 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:49,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:49,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:49,680 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:49,680 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1545444835] [2021-11-19 05:20:49,680 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1545444835] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:49,680 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:49,680 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:49,681 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1052817240] [2021-11-19 05:20:49,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:49,681 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:20:49,681 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:49,682 INFO L85 PathProgramCache]: Analyzing trace with hash -1147501804, now seen corresponding path program 1 times [2021-11-19 05:20:49,682 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:49,682 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1631639464] [2021-11-19 05:20:49,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:49,682 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:49,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:49,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:49,728 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:49,728 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1631639464] [2021-11-19 05:20:49,728 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1631639464] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:49,728 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:49,729 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:49,729 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [701630095] [2021-11-19 05:20:49,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:49,729 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:20:49,730 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:20:49,730 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:20:49,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:20:49,730 INFO L87 Difference]: Start difference. First operand 1790 states and 2646 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:49,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:20:49,775 INFO L93 Difference]: Finished difference Result 1790 states and 2645 transitions. [2021-11-19 05:20:49,775 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:20:49,776 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2645 transitions. [2021-11-19 05:20:49,787 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:49,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2645 transitions. [2021-11-19 05:20:49,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-19 05:20:49,800 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-19 05:20:49,800 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2645 transitions. [2021-11-19 05:20:49,803 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:20:49,804 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2645 transitions. [2021-11-19 05:20:49,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2645 transitions. [2021-11-19 05:20:49,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-19 05:20:49,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4776536312849162) internal successors, (2645), 1789 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:49,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2645 transitions. [2021-11-19 05:20:49,843 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2645 transitions. [2021-11-19 05:20:49,843 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2645 transitions. [2021-11-19 05:20:49,843 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-19 05:20:49,844 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2645 transitions. [2021-11-19 05:20:49,852 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:49,852 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:49,852 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:49,854 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:49,855 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:49,855 INFO L791 eck$LassoCheckResult]: Stem: 40317#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 40318#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 39741#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39711#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39712#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 40973#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40020#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39473#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39474#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40745#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40884#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41250#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41251#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40230#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40231#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40771#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40691#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40692#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40844#L1206 assume !(0 == ~M_E~0); 40209#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40210#L1211-1 assume !(0 == ~T2_E~0); 41103#L1216-1 assume !(0 == ~T3_E~0); 40002#L1221-1 assume !(0 == ~T4_E~0); 40003#L1226-1 assume !(0 == ~T5_E~0); 39665#L1231-1 assume !(0 == ~T6_E~0); 39666#L1236-1 assume !(0 == ~T7_E~0); 41134#L1241-1 assume !(0 == ~T8_E~0); 40064#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40065#L1251-1 assume !(0 == ~T10_E~0); 40285#L1256-1 assume !(0 == ~T11_E~0); 39485#L1261-1 assume !(0 == ~T12_E~0); 39486#L1266-1 assume !(0 == ~E_M~0); 41237#L1271-1 assume !(0 == ~E_1~0); 40872#L1276-1 assume !(0 == ~E_2~0); 40873#L1281-1 assume !(0 == ~E_3~0); 40798#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 39906#L1291-1 assume !(0 == ~E_5~0); 39907#L1296-1 assume !(0 == ~E_6~0); 40613#L1301-1 assume !(0 == ~E_7~0); 40614#L1306-1 assume !(0 == ~E_8~0); 41046#L1311-1 assume !(0 == ~E_9~0); 39867#L1316-1 assume !(0 == ~E_10~0); 39868#L1321-1 assume !(0 == ~E_11~0); 40630#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 39731#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39732#L598 assume 1 == ~m_pc~0; 39791#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39792#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41116#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41208#L1497 assume !(0 != activate_threads_~tmp~1#1); 41209#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41165#L617 assume !(1 == ~t1_pc~0); 40087#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40088#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39947#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39948#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40708#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40709#L636 assume 1 == ~t2_pc~0; 40056#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40057#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39887#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39888#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 40744#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40407#L655 assume !(1 == ~t3_pc~0); 40408#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41121#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39761#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39762#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 41238#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41239#L674 assume 1 == ~t4_pc~0; 39581#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39582#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40879#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39889#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 39890#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40404#L693 assume !(1 == ~t5_pc~0); 40567#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 40211#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40212#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41048#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 40297#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40234#L712 assume 1 == ~t6_pc~0; 40235#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40662#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40663#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40949#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 40760#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40758#L731 assume 1 == ~t7_pc~0; 39735#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39736#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39930#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40867#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 40986#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39845#L750 assume !(1 == ~t8_pc~0); 39516#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39515#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40031#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41061#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40168#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40169#L769 assume 1 == ~t9_pc~0; 40704#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39689#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39690#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40473#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 40925#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41006#L788 assume !(1 == ~t10_pc~0); 40581#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40582#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40813#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40814#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 39841#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39842#L807 assume 1 == ~t11_pc~0; 41015#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40593#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40746#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41157#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 41262#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41105#L826 assume !(1 == ~t12_pc~0); 40237#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40238#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40766#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41197#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 40397#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40306#L1344 assume !(1 == ~M_E~0); 40307#L1344-2 assume !(1 == ~T1_E~0); 40448#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40620#L1354-1 assume !(1 == ~T3_E~0); 40621#L1359-1 assume !(1 == ~T4_E~0); 40995#L1364-1 assume !(1 == ~T5_E~0); 39949#L1369-1 assume !(1 == ~T6_E~0); 39950#L1374-1 assume !(1 == ~T7_E~0); 40626#L1379-1 assume !(1 == ~T8_E~0); 40627#L1384-1 assume !(1 == ~T9_E~0); 40690#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41136#L1394-1 assume !(1 == ~T11_E~0); 41137#L1399-1 assume !(1 == ~T12_E~0); 41216#L1404-1 assume !(1 == ~E_M~0); 40068#L1409-1 assume !(1 == ~E_1~0); 40069#L1414-1 assume !(1 == ~E_2~0); 40906#L1419-1 assume !(1 == ~E_3~0); 39702#L1424-1 assume !(1 == ~E_4~0); 39703#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 40637#L1434-1 assume !(1 == ~E_6~0); 41155#L1439-1 assume !(1 == ~E_7~0); 39757#L1444-1 assume !(1 == ~E_8~0); 39758#L1449-1 assume !(1 == ~E_9~0); 40173#L1454-1 assume !(1 == ~E_10~0); 40174#L1459-1 assume !(1 == ~E_11~0); 40724#L1464-1 assume !(1 == ~E_12~0); 40725#L1469-1 assume { :end_inline_reset_delta_events } true; 40772#L1815-2 [2021-11-19 05:20:49,856 INFO L793 eck$LassoCheckResult]: Loop: 40772#L1815-2 assume !false; 40926#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40595#L1181 assume !false; 40666#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40618#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39476#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40205#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40756#L1008 assume !(0 != eval_~tmp~0#1); 40757#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39695#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39696#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41256#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40723#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39829#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39830#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40420#L1226-3 assume !(0 == ~T5_E~0); 39893#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39894#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40206#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41193#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41096#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40832#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 39851#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39852#L1266-3 assume !(0 == ~E_M~0); 39891#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39892#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40364#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40365#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40902#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40903#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41245#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41213#L1306-3 assume !(0 == ~E_8~0); 40489#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39775#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39776#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39853#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40588#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40913#L598-42 assume !(1 == ~m_pc~0); 40914#L598-44 is_master_triggered_~__retres1~0#1 := 0; 41028#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39931#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39932#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 41214#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40644#L617-42 assume 1 == ~t1_pc~0; 40416#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40281#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40282#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40696#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39996#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39997#L636-42 assume !(1 == ~t2_pc~0); 40460#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 40461#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40811#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40812#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40991#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40853#L655-42 assume !(1 == ~t3_pc~0); 40433#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 40434#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40066#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40067#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41120#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41065#L674-42 assume !(1 == ~t4_pc~0); 40839#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 40761#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39650#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39651#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40565#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40566#L693-42 assume 1 == ~t5_pc~0; 40821#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40822#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40882#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40877#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40878#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40180#L712-42 assume !(1 == ~t6_pc~0); 40181#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 40507#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40715#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40716#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40289#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40290#L731-42 assume !(1 == ~t7_pc~0); 39988#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 39989#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41056#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40197#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40198#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39901#L750-42 assume 1 == ~t8_pc~0; 39902#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40476#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40899#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39794#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39795#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40564#L769-42 assume 1 == ~t9_pc~0; 40386#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40387#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41070#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41135#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 39998#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39999#L788-42 assume 1 == ~t10_pc~0; 40572#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 40786#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40516#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40517#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41254#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41232#L807-42 assume !(1 == ~t11_pc~0); 39602#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 39603#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39742#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39743#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39744#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39993#L826-42 assume 1 == ~t12_pc~0; 39994#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40186#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40978#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39983#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 39984#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40835#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40836#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40762#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40143#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40144#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40776#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41234#L1369-3 assume !(1 == ~T6_E~0); 41154#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 39908#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 39909#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40141#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40142#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40440#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 41163#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41126#L1409-3 assume !(1 == ~E_1~0); 41127#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41192#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40972#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39809#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39810#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40775#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39749#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39750#L1449-3 assume !(1 == ~E_9~0); 39859#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40769#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40770#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41151#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40649#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39648#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39649#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 40265#L1834 assume !(0 == start_simulation_~tmp~3#1); 40885#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40908#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40342#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40521#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 40733#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41141#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39634#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 39635#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 40772#L1815-2 [2021-11-19 05:20:49,856 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:49,856 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2021-11-19 05:20:49,856 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:49,857 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [607042656] [2021-11-19 05:20:49,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:49,857 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:49,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:49,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:49,886 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:49,886 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [607042656] [2021-11-19 05:20:49,886 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [607042656] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:49,886 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:49,886 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:49,886 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1910549228] [2021-11-19 05:20:49,887 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:49,887 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:20:49,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:49,887 INFO L85 PathProgramCache]: Analyzing trace with hash 2071608406, now seen corresponding path program 1 times [2021-11-19 05:20:49,888 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:49,888 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1006425057] [2021-11-19 05:20:49,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:49,888 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:49,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:49,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:49,944 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:49,944 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1006425057] [2021-11-19 05:20:49,944 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1006425057] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:49,945 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:49,945 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:49,945 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [849451004] [2021-11-19 05:20:49,945 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:49,945 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:20:49,946 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:20:49,946 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:20:49,946 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:20:49,946 INFO L87 Difference]: Start difference. First operand 1790 states and 2645 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:49,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:20:49,984 INFO L93 Difference]: Finished difference Result 1790 states and 2644 transitions. [2021-11-19 05:20:49,984 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:20:49,985 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2644 transitions. [2021-11-19 05:20:49,995 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:50,004 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2644 transitions. [2021-11-19 05:20:50,004 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2021-11-19 05:20:50,006 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2021-11-19 05:20:50,006 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2644 transitions. [2021-11-19 05:20:50,009 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:20:50,010 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2644 transitions. [2021-11-19 05:20:50,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2644 transitions. [2021-11-19 05:20:50,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2021-11-19 05:20:50,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4770949720670392) internal successors, (2644), 1789 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:50,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2644 transitions. [2021-11-19 05:20:50,049 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2644 transitions. [2021-11-19 05:20:50,049 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2644 transitions. [2021-11-19 05:20:50,049 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-19 05:20:50,049 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2644 transitions. [2021-11-19 05:20:50,057 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2021-11-19 05:20:50,057 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:50,057 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:50,060 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:50,060 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:50,060 INFO L791 eck$LassoCheckResult]: Stem: 43904#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 43905#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 43328#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43298#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43299#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 44560#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43607#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43060#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43061#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44332#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44471#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44837#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44838#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 43817#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43818#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44358#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44278#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 44279#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44431#L1206 assume !(0 == ~M_E~0); 43796#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 43797#L1211-1 assume !(0 == ~T2_E~0); 44690#L1216-1 assume !(0 == ~T3_E~0); 43589#L1221-1 assume !(0 == ~T4_E~0); 43590#L1226-1 assume !(0 == ~T5_E~0); 43252#L1231-1 assume !(0 == ~T6_E~0); 43253#L1236-1 assume !(0 == ~T7_E~0); 44721#L1241-1 assume !(0 == ~T8_E~0); 43651#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43652#L1251-1 assume !(0 == ~T10_E~0); 43872#L1256-1 assume !(0 == ~T11_E~0); 43072#L1261-1 assume !(0 == ~T12_E~0); 43073#L1266-1 assume !(0 == ~E_M~0); 44824#L1271-1 assume !(0 == ~E_1~0); 44459#L1276-1 assume !(0 == ~E_2~0); 44460#L1281-1 assume !(0 == ~E_3~0); 44385#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 43493#L1291-1 assume !(0 == ~E_5~0); 43494#L1296-1 assume !(0 == ~E_6~0); 44200#L1301-1 assume !(0 == ~E_7~0); 44201#L1306-1 assume !(0 == ~E_8~0); 44633#L1311-1 assume !(0 == ~E_9~0); 43454#L1316-1 assume !(0 == ~E_10~0); 43455#L1321-1 assume !(0 == ~E_11~0); 44217#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 43318#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43319#L598 assume 1 == ~m_pc~0; 43378#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43379#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44703#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44795#L1497 assume !(0 != activate_threads_~tmp~1#1); 44796#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44752#L617 assume !(1 == ~t1_pc~0); 43674#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43675#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43534#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43535#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44295#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44296#L636 assume 1 == ~t2_pc~0; 43643#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43644#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43474#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43475#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 44331#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43994#L655 assume !(1 == ~t3_pc~0); 43995#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44708#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43348#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43349#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 44825#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44826#L674 assume 1 == ~t4_pc~0; 43168#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43169#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44466#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43476#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 43477#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43991#L693 assume !(1 == ~t5_pc~0); 44154#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 43798#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43799#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44635#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 43884#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43821#L712 assume 1 == ~t6_pc~0; 43822#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44249#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44250#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44536#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 44347#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44345#L731 assume 1 == ~t7_pc~0; 43322#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43323#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43517#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44454#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 44573#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43432#L750 assume !(1 == ~t8_pc~0); 43103#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 43102#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43618#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44648#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43755#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43756#L769 assume 1 == ~t9_pc~0; 44291#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43276#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43277#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44060#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 44512#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44593#L788 assume !(1 == ~t10_pc~0); 44168#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 44169#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44400#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44401#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 43428#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43429#L807 assume 1 == ~t11_pc~0; 44602#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 44180#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44333#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44744#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 44849#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44692#L826 assume !(1 == ~t12_pc~0); 43824#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 43825#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44353#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44784#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 43984#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43893#L1344 assume !(1 == ~M_E~0); 43894#L1344-2 assume !(1 == ~T1_E~0); 44035#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44207#L1354-1 assume !(1 == ~T3_E~0); 44208#L1359-1 assume !(1 == ~T4_E~0); 44582#L1364-1 assume !(1 == ~T5_E~0); 43536#L1369-1 assume !(1 == ~T6_E~0); 43537#L1374-1 assume !(1 == ~T7_E~0); 44213#L1379-1 assume !(1 == ~T8_E~0); 44214#L1384-1 assume !(1 == ~T9_E~0); 44277#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44723#L1394-1 assume !(1 == ~T11_E~0); 44724#L1399-1 assume !(1 == ~T12_E~0); 44803#L1404-1 assume !(1 == ~E_M~0); 43655#L1409-1 assume !(1 == ~E_1~0); 43656#L1414-1 assume !(1 == ~E_2~0); 44493#L1419-1 assume !(1 == ~E_3~0); 43289#L1424-1 assume !(1 == ~E_4~0); 43290#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 44224#L1434-1 assume !(1 == ~E_6~0); 44742#L1439-1 assume !(1 == ~E_7~0); 43344#L1444-1 assume !(1 == ~E_8~0); 43345#L1449-1 assume !(1 == ~E_9~0); 43760#L1454-1 assume !(1 == ~E_10~0); 43761#L1459-1 assume !(1 == ~E_11~0); 44311#L1464-1 assume !(1 == ~E_12~0); 44312#L1469-1 assume { :end_inline_reset_delta_events } true; 44359#L1815-2 [2021-11-19 05:20:50,061 INFO L793 eck$LassoCheckResult]: Loop: 44359#L1815-2 assume !false; 44513#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44182#L1181 assume !false; 44253#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44205#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43063#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43792#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44343#L1008 assume !(0 != eval_~tmp~0#1); 44344#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43282#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43283#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44843#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44310#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 43416#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43417#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44007#L1226-3 assume !(0 == ~T5_E~0); 43480#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43481#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43793#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44780#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44683#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44419#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43438#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43439#L1266-3 assume !(0 == ~E_M~0); 43478#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43479#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43951#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43952#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44489#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44490#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44832#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44800#L1306-3 assume !(0 == ~E_8~0); 44076#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43362#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 43363#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43440#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 44175#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44500#L598-42 assume !(1 == ~m_pc~0); 44501#L598-44 is_master_triggered_~__retres1~0#1 := 0; 44615#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43518#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43519#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 44801#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44231#L617-42 assume 1 == ~t1_pc~0; 44003#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43868#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43869#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44283#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43583#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43584#L636-42 assume 1 == ~t2_pc~0; 44785#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44048#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44398#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44399#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44578#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44440#L655-42 assume !(1 == ~t3_pc~0); 44020#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 44021#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43653#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43654#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44707#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44652#L674-42 assume !(1 == ~t4_pc~0); 44426#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 44348#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43237#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43238#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44152#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44153#L693-42 assume 1 == ~t5_pc~0; 44408#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44409#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44469#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44464#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44465#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43767#L712-42 assume !(1 == ~t6_pc~0); 43768#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 44094#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44302#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44303#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43876#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43877#L731-42 assume !(1 == ~t7_pc~0); 43575#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 43576#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44643#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43784#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43785#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43488#L750-42 assume 1 == ~t8_pc~0; 43489#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44063#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44486#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43381#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43382#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44151#L769-42 assume 1 == ~t9_pc~0; 43973#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43974#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44657#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44722#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 43585#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43586#L788-42 assume !(1 == ~t10_pc~0); 44160#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 44373#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44103#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44104#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44841#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44819#L807-42 assume !(1 == ~t11_pc~0); 43189#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 43190#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43329#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43330#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43331#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43580#L826-42 assume 1 == ~t12_pc~0; 43581#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43773#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44565#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43570#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43571#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44422#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44423#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44349#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43730#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43731#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44363#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44821#L1369-3 assume !(1 == ~T6_E~0); 44741#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 43495#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 43496#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 43728#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43729#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 44027#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 44750#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44713#L1409-3 assume !(1 == ~E_1~0); 44714#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44779#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44559#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43396#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43397#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44362#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43336#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43337#L1449-3 assume !(1 == ~E_9~0); 43446#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44356#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44357#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44738#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44236#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43235#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43236#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43852#L1834 assume !(0 == start_simulation_~tmp~3#1); 44472#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44495#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43929#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44108#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 44320#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44728#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43221#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 43222#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 44359#L1815-2 [2021-11-19 05:20:50,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:50,062 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2021-11-19 05:20:50,062 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:50,062 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [78808616] [2021-11-19 05:20:50,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:50,062 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:50,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:50,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:50,102 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:50,102 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [78808616] [2021-11-19 05:20:50,103 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [78808616] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:50,103 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:50,103 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:50,103 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [164889747] [2021-11-19 05:20:50,103 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:50,104 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:20:50,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:50,104 INFO L85 PathProgramCache]: Analyzing trace with hash 2024415830, now seen corresponding path program 1 times [2021-11-19 05:20:50,104 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:50,104 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [655444736] [2021-11-19 05:20:50,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:50,105 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:50,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:50,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:50,145 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:50,145 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [655444736] [2021-11-19 05:20:50,145 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [655444736] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:50,145 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:50,145 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:50,145 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [164252245] [2021-11-19 05:20:50,145 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:50,146 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:20:50,146 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:20:50,146 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-19 05:20:50,146 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-19 05:20:50,147 INFO L87 Difference]: Start difference. First operand 1790 states and 2644 transitions. cyclomatic complexity: 855 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:50,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:20:50,287 INFO L93 Difference]: Finished difference Result 3324 states and 4894 transitions. [2021-11-19 05:20:50,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-19 05:20:50,288 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3324 states and 4894 transitions. [2021-11-19 05:20:50,307 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3135 [2021-11-19 05:20:50,324 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3324 states to 3324 states and 4894 transitions. [2021-11-19 05:20:50,325 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3324 [2021-11-19 05:20:50,328 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3324 [2021-11-19 05:20:50,328 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3324 states and 4894 transitions. [2021-11-19 05:20:50,333 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:20:50,333 INFO L681 BuchiCegarLoop]: Abstraction has 3324 states and 4894 transitions. [2021-11-19 05:20:50,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3324 states and 4894 transitions. [2021-11-19 05:20:50,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3324 to 3324. [2021-11-19 05:20:50,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3324 states, 3324 states have (on average 1.4723225030084235) internal successors, (4894), 3323 states have internal predecessors, (4894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:50,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3324 states to 3324 states and 4894 transitions. [2021-11-19 05:20:50,419 INFO L704 BuchiCegarLoop]: Abstraction has 3324 states and 4894 transitions. [2021-11-19 05:20:50,419 INFO L587 BuchiCegarLoop]: Abstraction has 3324 states and 4894 transitions. [2021-11-19 05:20:50,419 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-19 05:20:50,419 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3324 states and 4894 transitions. [2021-11-19 05:20:50,433 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3135 [2021-11-19 05:20:50,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:50,433 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:50,436 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:50,436 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:50,436 INFO L791 eck$LassoCheckResult]: Stem: 49030#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 49031#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 48452#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48422#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48423#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 49692#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48731#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48184#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48185#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49459#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49601#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49971#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49972#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48942#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48943#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49485#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49405#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 49406#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49561#L1206 assume !(0 == ~M_E~0); 48921#L1206-2 assume !(0 == ~T1_E~0); 48922#L1211-1 assume !(0 == ~T2_E~0); 49823#L1216-1 assume !(0 == ~T3_E~0); 48713#L1221-1 assume !(0 == ~T4_E~0); 48714#L1226-1 assume !(0 == ~T5_E~0); 48376#L1231-1 assume !(0 == ~T6_E~0); 48377#L1236-1 assume !(0 == ~T7_E~0); 49854#L1241-1 assume !(0 == ~T8_E~0); 48775#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48776#L1251-1 assume !(0 == ~T10_E~0); 48997#L1256-1 assume !(0 == ~T11_E~0); 48196#L1261-1 assume !(0 == ~T12_E~0); 48197#L1266-1 assume !(0 == ~E_M~0); 49958#L1271-1 assume !(0 == ~E_1~0); 49589#L1276-1 assume !(0 == ~E_2~0); 49590#L1281-1 assume !(0 == ~E_3~0); 49515#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 48617#L1291-1 assume !(0 == ~E_5~0); 48618#L1296-1 assume !(0 == ~E_6~0); 49327#L1301-1 assume !(0 == ~E_7~0); 49328#L1306-1 assume !(0 == ~E_8~0); 49765#L1311-1 assume !(0 == ~E_9~0); 48578#L1316-1 assume !(0 == ~E_10~0); 48579#L1321-1 assume !(0 == ~E_11~0); 49344#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 48442#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48443#L598 assume 1 == ~m_pc~0; 48502#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 48503#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49836#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49929#L1497 assume !(0 != activate_threads_~tmp~1#1); 49930#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49886#L617 assume !(1 == ~t1_pc~0); 48798#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48799#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48658#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48659#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49422#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49423#L636 assume 1 == ~t2_pc~0; 48767#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48768#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48598#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48599#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 49458#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49120#L655 assume !(1 == ~t3_pc~0); 49121#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49841#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48472#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48473#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 49959#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49960#L674 assume 1 == ~t4_pc~0; 48292#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48293#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49596#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48600#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 48601#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49117#L693 assume !(1 == ~t5_pc~0); 49281#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 48923#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48924#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49767#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 49009#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48946#L712 assume 1 == ~t6_pc~0; 48947#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49376#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49377#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49668#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 49474#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49472#L731 assume 1 == ~t7_pc~0; 48446#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48447#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48641#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49584#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 49705#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48556#L750 assume !(1 == ~t8_pc~0); 48227#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 48226#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48742#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49780#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 48879#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48880#L769 assume 1 == ~t9_pc~0; 49418#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48400#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48401#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49187#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 49644#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49725#L788 assume !(1 == ~t10_pc~0); 49295#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49296#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49530#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49531#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 48552#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48553#L807 assume 1 == ~t11_pc~0; 49734#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49307#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49460#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49878#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 49986#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49825#L826 assume !(1 == ~t12_pc~0); 48949#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 48950#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49480#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49918#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 49110#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49018#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 49019#L1344-2 assume !(1 == ~T1_E~0); 49161#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50033#L1354-1 assume !(1 == ~T3_E~0); 50032#L1359-1 assume !(1 == ~T4_E~0); 50031#L1364-1 assume !(1 == ~T5_E~0); 50030#L1369-1 assume !(1 == ~T6_E~0); 50029#L1374-1 assume !(1 == ~T7_E~0); 50028#L1379-1 assume !(1 == ~T8_E~0); 50027#L1384-1 assume !(1 == ~T9_E~0); 50026#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50025#L1394-1 assume !(1 == ~T11_E~0); 50024#L1399-1 assume !(1 == ~T12_E~0); 50023#L1404-1 assume !(1 == ~E_M~0); 50022#L1409-1 assume !(1 == ~E_1~0); 50021#L1414-1 assume !(1 == ~E_2~0); 50020#L1419-1 assume !(1 == ~E_3~0); 50019#L1424-1 assume !(1 == ~E_4~0); 50018#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 50017#L1434-1 assume !(1 == ~E_6~0); 50016#L1439-1 assume !(1 == ~E_7~0); 50015#L1444-1 assume !(1 == ~E_8~0); 50014#L1449-1 assume !(1 == ~E_9~0); 50013#L1454-1 assume !(1 == ~E_10~0); 50012#L1459-1 assume !(1 == ~E_11~0); 50011#L1464-1 assume !(1 == ~E_12~0); 50010#L1469-1 assume { :end_inline_reset_delta_events } true; 50008#L1815-2 [2021-11-19 05:20:50,436 INFO L793 eck$LassoCheckResult]: Loop: 50008#L1815-2 assume !false; 50007#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50003#L1181 assume !false; 50002#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 49999#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 48916#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 48917#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49470#L1008 assume !(0 != eval_~tmp~0#1); 49471#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 48406#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48407#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49987#L1206-5 assume !(0 == ~T1_E~0); 50211#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50210#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50209#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50208#L1226-3 assume !(0 == ~T5_E~0); 50207#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50206#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50205#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50204#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50203#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 50202#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 50201#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 50200#L1266-3 assume !(0 == ~E_M~0); 50199#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50198#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50197#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50196#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50195#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50194#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50193#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50192#L1306-3 assume !(0 == ~E_8~0); 50191#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50190#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50189#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 50188#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 50187#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50186#L598-42 assume 1 == ~m_pc~0; 50184#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 50183#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50182#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50181#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 50180#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50179#L617-42 assume 1 == ~t1_pc~0; 50177#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50176#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50175#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50174#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50173#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50172#L636-42 assume 1 == ~t2_pc~0; 50170#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50169#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50168#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50167#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50166#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50165#L655-42 assume 1 == ~t3_pc~0; 50163#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50162#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50161#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50160#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50159#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50158#L674-42 assume !(1 == ~t4_pc~0); 50156#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 50155#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50154#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50153#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50152#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50151#L693-42 assume 1 == ~t5_pc~0; 50149#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50148#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50147#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50146#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50145#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50144#L712-42 assume !(1 == ~t6_pc~0); 50142#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 50141#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50140#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50139#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50138#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50137#L731-42 assume 1 == ~t7_pc~0; 50135#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50134#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50133#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50132#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50131#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50130#L750-42 assume !(1 == ~t8_pc~0); 50128#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 50127#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50126#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50125#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50124#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50123#L769-42 assume 1 == ~t9_pc~0; 50121#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50120#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50119#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50118#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 50117#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50116#L788-42 assume 1 == ~t10_pc~0; 49500#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49501#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49230#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49231#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49975#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49953#L807-42 assume 1 == ~t11_pc~0; 49640#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48314#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48453#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48454#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48455#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48704#L826-42 assume 1 == ~t12_pc~0; 48705#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 48897#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49697#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 48694#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 48695#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49552#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49553#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49476#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48854#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48855#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49490#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49955#L1369-3 assume !(1 == ~T6_E~0); 49875#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48619#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 48620#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 48852#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48853#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49153#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 49884#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49846#L1409-3 assume !(1 == ~E_1~0); 49847#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49913#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49691#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48520#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 48521#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49489#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 48460#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 48461#L1449-3 assume !(1 == ~E_9~0); 48570#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49483#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49484#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 49871#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 49872#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 50054#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 50053#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 50052#L1834 assume !(0 == start_simulation_~tmp~3#1); 49602#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 50047#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 50038#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 50037#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 50036#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50035#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50034#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 50009#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 50008#L1815-2 [2021-11-19 05:20:50,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:50,437 INFO L85 PathProgramCache]: Analyzing trace with hash 282356976, now seen corresponding path program 1 times [2021-11-19 05:20:50,437 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:50,437 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [955872697] [2021-11-19 05:20:50,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:50,438 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:50,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:50,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:50,474 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:50,474 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [955872697] [2021-11-19 05:20:50,474 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [955872697] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:50,474 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:50,474 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:50,475 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [312943828] [2021-11-19 05:20:50,475 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:50,475 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:20:50,475 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:50,476 INFO L85 PathProgramCache]: Analyzing trace with hash -588806508, now seen corresponding path program 1 times [2021-11-19 05:20:50,476 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:50,476 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1923209996] [2021-11-19 05:20:50,476 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:50,476 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:50,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:50,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:50,525 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:50,526 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1923209996] [2021-11-19 05:20:50,526 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1923209996] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:50,526 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:50,526 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:50,526 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [261332966] [2021-11-19 05:20:50,526 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:50,527 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:20:50,527 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:20:50,527 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-19 05:20:50,527 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-19 05:20:50,528 INFO L87 Difference]: Start difference. First operand 3324 states and 4894 transitions. cyclomatic complexity: 1572 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:50,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:20:50,715 INFO L93 Difference]: Finished difference Result 6382 states and 9375 transitions. [2021-11-19 05:20:50,716 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-19 05:20:50,716 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6382 states and 9375 transitions. [2021-11-19 05:20:50,749 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6151 [2021-11-19 05:20:50,776 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6382 states to 6382 states and 9375 transitions. [2021-11-19 05:20:50,776 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6382 [2021-11-19 05:20:50,782 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6382 [2021-11-19 05:20:50,782 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6382 states and 9375 transitions. [2021-11-19 05:20:50,790 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:20:50,791 INFO L681 BuchiCegarLoop]: Abstraction has 6382 states and 9375 transitions. [2021-11-19 05:20:50,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6382 states and 9375 transitions. [2021-11-19 05:20:50,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6382 to 6382. [2021-11-19 05:20:50,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6382 states, 6382 states have (on average 1.4689752428705736) internal successors, (9375), 6381 states have internal predecessors, (9375), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:50,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6382 states to 6382 states and 9375 transitions. [2021-11-19 05:20:50,930 INFO L704 BuchiCegarLoop]: Abstraction has 6382 states and 9375 transitions. [2021-11-19 05:20:50,930 INFO L587 BuchiCegarLoop]: Abstraction has 6382 states and 9375 transitions. [2021-11-19 05:20:50,930 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-19 05:20:50,930 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6382 states and 9375 transitions. [2021-11-19 05:20:50,956 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6151 [2021-11-19 05:20:50,957 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:50,957 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:50,960 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:50,960 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:50,960 INFO L791 eck$LassoCheckResult]: Stem: 58749#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 58750#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 58169#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 58139#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 58140#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 59423#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58448#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 57900#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 57901#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59190#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 59332#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59736#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59737#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 58659#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 58660#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 59216#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59135#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 59136#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59290#L1206 assume !(0 == ~M_E~0); 58637#L1206-2 assume !(0 == ~T1_E~0); 58638#L1211-1 assume !(0 == ~T2_E~0); 59567#L1216-1 assume !(0 == ~T3_E~0); 58430#L1221-1 assume !(0 == ~T4_E~0); 58431#L1226-1 assume !(0 == ~T5_E~0); 58092#L1231-1 assume !(0 == ~T6_E~0); 58093#L1236-1 assume !(0 == ~T7_E~0); 59604#L1241-1 assume !(0 == ~T8_E~0); 58492#L1246-1 assume !(0 == ~T9_E~0); 58493#L1251-1 assume !(0 == ~T10_E~0); 58716#L1256-1 assume !(0 == ~T11_E~0); 57912#L1261-1 assume !(0 == ~T12_E~0); 57913#L1266-1 assume !(0 == ~E_M~0); 59719#L1271-1 assume !(0 == ~E_1~0); 59320#L1276-1 assume !(0 == ~E_2~0); 59321#L1281-1 assume !(0 == ~E_3~0); 59243#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 58334#L1291-1 assume !(0 == ~E_5~0); 58335#L1296-1 assume !(0 == ~E_6~0); 59052#L1301-1 assume !(0 == ~E_7~0); 59053#L1306-1 assume !(0 == ~E_8~0); 59503#L1311-1 assume !(0 == ~E_9~0); 58295#L1316-1 assume !(0 == ~E_10~0); 58296#L1321-1 assume !(0 == ~E_11~0); 59069#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 58159#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58160#L598 assume 1 == ~m_pc~0; 58219#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 58220#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59583#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59688#L1497 assume !(0 != activate_threads_~tmp~1#1); 59689#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59637#L617 assume !(1 == ~t1_pc~0); 58515#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 58516#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58375#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58376#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 59152#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59153#L636 assume 1 == ~t2_pc~0; 58484#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58485#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58315#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58316#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 59189#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58842#L655 assume !(1 == ~t3_pc~0); 58843#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59588#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58189#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58190#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 59720#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59721#L674 assume 1 == ~t4_pc~0; 58008#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 58009#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59327#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58317#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 58318#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58839#L693 assume !(1 == ~t5_pc~0); 59006#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 58639#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58640#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59505#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 58728#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58663#L712 assume 1 == ~t6_pc~0; 58664#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59103#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59104#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59399#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 59205#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59203#L731 assume 1 == ~t7_pc~0; 58163#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 58164#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58358#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59315#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 59437#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58273#L750 assume !(1 == ~t8_pc~0); 57943#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 57942#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58459#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59519#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 58596#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58597#L769 assume 1 == ~t9_pc~0; 59148#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58117#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58118#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58909#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 59375#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59459#L788 assume !(1 == ~t10_pc~0); 59020#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 59021#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59258#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59259#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 58269#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58270#L807 assume 1 == ~t11_pc~0; 59469#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 59032#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59191#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59629#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 59759#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59570#L826 assume !(1 == ~t12_pc~0); 58666#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 58667#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 59211#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 59671#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 58832#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58737#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 58738#L1344-2 assume !(1 == ~T1_E~0); 58884#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59059#L1354-1 assume !(1 == ~T3_E~0); 59060#L1359-1 assume !(1 == ~T4_E~0); 59728#L1364-1 assume !(1 == ~T5_E~0); 59729#L1369-1 assume !(1 == ~T6_E~0); 59852#L1374-1 assume !(1 == ~T7_E~0); 59065#L1379-1 assume !(1 == ~T8_E~0); 59066#L1384-1 assume !(1 == ~T9_E~0); 59838#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 59835#L1394-1 assume !(1 == ~T11_E~0); 59832#L1399-1 assume !(1 == ~T12_E~0); 59830#L1404-1 assume !(1 == ~E_M~0); 59828#L1409-1 assume !(1 == ~E_1~0); 59825#L1414-1 assume !(1 == ~E_2~0); 59823#L1419-1 assume !(1 == ~E_3~0); 59821#L1424-1 assume !(1 == ~E_4~0); 59819#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 59817#L1434-1 assume !(1 == ~E_6~0); 59815#L1439-1 assume !(1 == ~E_7~0); 59812#L1444-1 assume !(1 == ~E_8~0); 59810#L1449-1 assume !(1 == ~E_9~0); 59808#L1454-1 assume !(1 == ~E_10~0); 59806#L1459-1 assume !(1 == ~E_11~0); 59804#L1464-1 assume !(1 == ~E_12~0); 59800#L1469-1 assume { :end_inline_reset_delta_events } true; 59792#L1815-2 [2021-11-19 05:20:50,961 INFO L793 eck$LassoCheckResult]: Loop: 59792#L1815-2 assume !false; 59786#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59781#L1181 assume !false; 59780#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 59777#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 59766#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 59765#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 59763#L1008 assume !(0 != eval_~tmp~0#1); 59762#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59761#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 59760#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 59744#L1206-5 assume !(0 == ~T1_E~0); 59168#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 58257#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 58258#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 58855#L1226-3 assume !(0 == ~T5_E~0); 58321#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 58322#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 58634#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59667#L1246-3 assume !(0 == ~T9_E~0); 59558#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 59278#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 58279#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 58280#L1266-3 assume !(0 == ~E_M~0); 58319#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 58320#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 58799#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 58800#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 59351#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 59352#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 59727#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 59694#L1306-3 assume !(0 == ~E_8~0); 58926#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 58203#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 58204#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 58281#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 59027#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59362#L598-42 assume !(1 == ~m_pc~0); 59363#L598-44 is_master_triggered_~__retres1~0#1 := 0; 59484#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58359#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58360#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 59695#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59083#L617-42 assume 1 == ~t1_pc~0; 58851#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58712#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58713#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59140#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58424#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58425#L636-42 assume !(1 == ~t2_pc~0); 58896#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 58897#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59256#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59257#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 59442#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59299#L655-42 assume 1 == ~t3_pc~0; 59300#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58869#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58494#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58495#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59587#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59524#L674-42 assume !(1 == ~t4_pc~0); 59285#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 59206#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58077#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58078#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 59004#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59005#L693-42 assume 1 == ~t5_pc~0; 59267#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59268#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59330#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59325#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 59326#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58608#L712-42 assume !(1 == ~t6_pc~0); 58609#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 58944#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59160#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59161#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58720#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58721#L731-42 assume !(1 == ~t7_pc~0); 58416#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 58417#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59514#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58625#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 58626#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58329#L750-42 assume 1 == ~t8_pc~0; 58330#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 58912#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59348#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58222#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 58223#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59003#L769-42 assume 1 == ~t9_pc~0; 58821#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58822#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59529#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59605#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 58426#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58427#L788-42 assume 1 == ~t10_pc~0; 59011#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 59231#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58953#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58954#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 61854#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61852#L807-42 assume !(1 == ~t11_pc~0); 61849#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 61847#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61845#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 61843#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 61840#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 61838#L826-42 assume 1 == ~t12_pc~0; 61835#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 61833#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60258#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58411#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 58412#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59281#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 59282#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 60178#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60176#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60153#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60150#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 60148#L1369-3 assume !(1 == ~T6_E~0); 60126#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 58336#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 58337#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60083#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 60081#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 60078#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 60076#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 60074#L1409-3 assume !(1 == ~E_1~0); 60072#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 60070#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 60068#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 60065#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 60063#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 60061#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 60059#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 60057#L1449-3 assume !(1 == ~E_9~0); 60055#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 60052#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 60050#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 60048#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60045#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 60032#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 60030#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 60027#L1834 assume !(0 == start_simulation_~tmp~3#1); 59333#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60021#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 60011#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 60009#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 60007#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60005#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60002#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 59799#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 59792#L1815-2 [2021-11-19 05:20:50,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:50,962 INFO L85 PathProgramCache]: Analyzing trace with hash 1144190578, now seen corresponding path program 1 times [2021-11-19 05:20:50,962 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:50,962 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [723084015] [2021-11-19 05:20:50,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:50,962 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:50,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:50,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:50,999 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:50,999 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [723084015] [2021-11-19 05:20:50,999 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [723084015] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:50,999 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:51,000 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:51,000 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1753824455] [2021-11-19 05:20:51,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:51,000 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:20:51,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:51,001 INFO L85 PathProgramCache]: Analyzing trace with hash 1712715865, now seen corresponding path program 1 times [2021-11-19 05:20:51,001 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:51,001 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [753170604] [2021-11-19 05:20:51,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:51,002 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:51,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:51,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:51,041 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:51,041 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [753170604] [2021-11-19 05:20:51,041 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [753170604] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:51,041 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:51,041 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:51,042 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [94230152] [2021-11-19 05:20:51,042 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:51,042 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:20:51,042 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:20:51,043 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-19 05:20:51,043 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-19 05:20:51,043 INFO L87 Difference]: Start difference. First operand 6382 states and 9375 transitions. cyclomatic complexity: 2997 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:51,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:20:51,345 INFO L93 Difference]: Finished difference Result 12090 states and 17730 transitions. [2021-11-19 05:20:51,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-19 05:20:51,345 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12090 states and 17730 transitions. [2021-11-19 05:20:51,397 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11811 [2021-11-19 05:20:51,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12090 states to 12090 states and 17730 transitions. [2021-11-19 05:20:51,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12090 [2021-11-19 05:20:51,449 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12090 [2021-11-19 05:20:51,450 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12090 states and 17730 transitions. [2021-11-19 05:20:51,460 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:20:51,460 INFO L681 BuchiCegarLoop]: Abstraction has 12090 states and 17730 transitions. [2021-11-19 05:20:51,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12090 states and 17730 transitions. [2021-11-19 05:20:51,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12090 to 12086. [2021-11-19 05:20:51,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12086 states, 12086 states have (on average 1.4666556346185669) internal successors, (17726), 12085 states have internal predecessors, (17726), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:51,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12086 states to 12086 states and 17726 transitions. [2021-11-19 05:20:51,666 INFO L704 BuchiCegarLoop]: Abstraction has 12086 states and 17726 transitions. [2021-11-19 05:20:51,666 INFO L587 BuchiCegarLoop]: Abstraction has 12086 states and 17726 transitions. [2021-11-19 05:20:51,666 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-19 05:20:51,666 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12086 states and 17726 transitions. [2021-11-19 05:20:51,767 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11811 [2021-11-19 05:20:51,767 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:51,767 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:51,770 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:51,770 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:51,771 INFO L791 eck$LassoCheckResult]: Stem: 77233#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 77234#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 76653#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76626#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76627#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 77905#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76933#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76382#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76383#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77668#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 77813#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 78233#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 78234#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 77145#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 77146#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 77695#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 77613#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 77614#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77772#L1206 assume !(0 == ~M_E~0); 77122#L1206-2 assume !(0 == ~T1_E~0); 77123#L1211-1 assume !(0 == ~T2_E~0); 78054#L1216-1 assume !(0 == ~T3_E~0); 76915#L1221-1 assume !(0 == ~T4_E~0); 76916#L1226-1 assume !(0 == ~T5_E~0); 76576#L1231-1 assume !(0 == ~T6_E~0); 76577#L1236-1 assume !(0 == ~T7_E~0); 78090#L1241-1 assume !(0 == ~T8_E~0); 76977#L1246-1 assume !(0 == ~T9_E~0); 76978#L1251-1 assume !(0 == ~T10_E~0); 77198#L1256-1 assume !(0 == ~T11_E~0); 76394#L1261-1 assume !(0 == ~T12_E~0); 76395#L1266-1 assume !(0 == ~E_M~0); 78214#L1271-1 assume !(0 == ~E_1~0); 77801#L1276-1 assume !(0 == ~E_2~0); 77802#L1281-1 assume !(0 == ~E_3~0); 77726#L1286-1 assume !(0 == ~E_4~0); 76818#L1291-1 assume !(0 == ~E_5~0); 76819#L1296-1 assume !(0 == ~E_6~0); 77532#L1301-1 assume !(0 == ~E_7~0); 77533#L1306-1 assume !(0 == ~E_8~0); 77990#L1311-1 assume !(0 == ~E_9~0); 76779#L1316-1 assume !(0 == ~E_10~0); 76780#L1321-1 assume !(0 == ~E_11~0); 77549#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 76643#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76644#L598 assume 1 == ~m_pc~0; 76702#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 76703#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78070#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 78177#L1497 assume !(0 != activate_threads_~tmp~1#1); 78178#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78127#L617 assume !(1 == ~t1_pc~0); 77000#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 77001#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76859#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76860#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77630#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77631#L636 assume 1 == ~t2_pc~0; 76969#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76970#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76799#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76800#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 77667#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77322#L655 assume !(1 == ~t3_pc~0); 77323#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 78075#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76672#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76673#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 78215#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78216#L674 assume 1 == ~t4_pc~0; 76490#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76491#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77808#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76803#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 76804#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77318#L693 assume !(1 == ~t5_pc~0); 77484#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 77127#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77128#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77992#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 77210#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77147#L712 assume 1 == ~t6_pc~0; 77148#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 77582#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77583#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77879#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 77684#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77682#L731 assume 1 == ~t7_pc~0; 76645#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 76646#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76844#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77797#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 77922#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76756#L750 assume !(1 == ~t8_pc~0); 76425#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 76424#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76944#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78008#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 77081#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77082#L769 assume 1 == ~t9_pc~0; 77628#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 76598#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76599#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 77387#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 77855#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77947#L788 assume !(1 == ~t10_pc~0); 77498#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 77499#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77741#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 77742#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 76754#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 76755#L807 assume 1 == ~t11_pc~0; 77957#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 77511#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77669#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 78119#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 78258#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 78056#L826 assume !(1 == ~t12_pc~0); 77152#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 77153#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77690#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 78164#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 77311#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77219#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 77220#L1344-2 assume !(1 == ~T1_E~0); 77362#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78433#L1354-1 assume !(1 == ~T3_E~0); 78431#L1359-1 assume !(1 == ~T4_E~0); 78430#L1364-1 assume !(1 == ~T5_E~0); 76861#L1369-1 assume !(1 == ~T6_E~0); 76862#L1374-1 assume !(1 == ~T7_E~0); 77547#L1379-1 assume !(1 == ~T8_E~0); 77548#L1384-1 assume !(1 == ~T9_E~0); 78406#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 78400#L1394-1 assume !(1 == ~T11_E~0); 78395#L1399-1 assume !(1 == ~T12_E~0); 78390#L1404-1 assume !(1 == ~E_M~0); 78385#L1409-1 assume !(1 == ~E_1~0); 78373#L1414-1 assume !(1 == ~E_2~0); 78356#L1419-1 assume !(1 == ~E_3~0); 78352#L1424-1 assume !(1 == ~E_4~0); 78347#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 78344#L1434-1 assume !(1 == ~E_6~0); 78334#L1439-1 assume !(1 == ~E_7~0); 78318#L1444-1 assume !(1 == ~E_8~0); 78315#L1449-1 assume !(1 == ~E_9~0); 78312#L1454-1 assume !(1 == ~E_10~0); 78309#L1459-1 assume !(1 == ~E_11~0); 78306#L1464-1 assume !(1 == ~E_12~0); 78301#L1469-1 assume { :end_inline_reset_delta_events } true; 78292#L1815-2 [2021-11-19 05:20:51,771 INFO L793 eck$LassoCheckResult]: Loop: 78292#L1815-2 assume !false; 78286#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 78281#L1181 assume !false; 78280#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 78277#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 78266#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 78265#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 78263#L1008 assume !(0 != eval_~tmp~0#1); 78262#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 78261#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78259#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 78260#L1206-5 assume !(0 == ~T1_E~0); 79312#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 79310#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 79308#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 79249#L1226-3 assume !(0 == ~T5_E~0); 79247#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 79245#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 79243#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 79241#L1246-3 assume !(0 == ~T9_E~0); 79239#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 79237#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 79235#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 79233#L1266-3 assume !(0 == ~E_M~0); 79231#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 79229#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 79227#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 79166#L1286-3 assume !(0 == ~E_4~0); 79165#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 79095#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 79093#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 79091#L1306-3 assume !(0 == ~E_8~0); 79082#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 79075#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 79067#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 79052#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 79039#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79037#L598-42 assume !(1 == ~m_pc~0); 79027#L598-44 is_master_triggered_~__retres1~0#1 := 0; 79020#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79013#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 79007#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 79000#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78996#L617-42 assume 1 == ~t1_pc~0; 78967#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 78964#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78962#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 78960#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 78958#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78956#L636-42 assume 1 == ~t2_pc~0; 78953#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 78952#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78950#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78948#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78946#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78944#L655-42 assume 1 == ~t3_pc~0; 78941#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 78934#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78929#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78891#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78888#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78886#L674-42 assume !(1 == ~t4_pc~0); 78883#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 78881#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78826#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 78824#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 78822#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78820#L693-42 assume 1 == ~t5_pc~0; 78817#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 78816#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78815#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78758#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 78755#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78750#L712-42 assume 1 == ~t6_pc~0; 78745#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 78740#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 78735#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78730#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 78726#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78722#L731-42 assume !(1 == ~t7_pc~0); 78717#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 78712#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78707#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 78702#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 78698#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78694#L750-42 assume 1 == ~t8_pc~0; 78689#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 78684#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78679#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78674#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 78670#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78666#L769-42 assume !(1 == ~t9_pc~0); 78661#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 78656#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78651#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 78646#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 78642#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 78638#L788-42 assume !(1 == ~t10_pc~0); 78633#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 78628#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78622#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 78620#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 78608#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 78605#L807-42 assume 1 == ~t11_pc~0; 78603#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 78596#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76651#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76652#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 78546#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 78544#L826-42 assume 1 == ~t12_pc~0; 78541#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 78538#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 78536#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 78524#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 78517#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78510#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 77763#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 78079#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78491#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78484#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 78480#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 78476#L1369-3 assume !(1 == ~T6_E~0); 78472#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 78468#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 78464#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 78459#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 78456#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 78452#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 78450#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 78435#L1409-3 assume !(1 == ~E_1~0); 78434#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 78426#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78421#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 78415#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 78411#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 78405#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 78399#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 78394#L1449-3 assume !(1 == ~E_9~0); 78389#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 78384#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 78380#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 78379#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 78368#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 78353#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 78348#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 78345#L1834 assume !(0 == start_simulation_~tmp~3#1); 77814#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 78329#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 78317#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 78314#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 78311#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78308#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 78305#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 78300#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 78292#L1815-2 [2021-11-19 05:20:51,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:51,772 INFO L85 PathProgramCache]: Analyzing trace with hash -1221844492, now seen corresponding path program 1 times [2021-11-19 05:20:51,773 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:51,773 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [524659260] [2021-11-19 05:20:51,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:51,773 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:51,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:51,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:51,819 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:51,819 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [524659260] [2021-11-19 05:20:51,819 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [524659260] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:51,820 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:51,820 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:51,820 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1976683101] [2021-11-19 05:20:51,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:51,821 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:20:51,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:51,821 INFO L85 PathProgramCache]: Analyzing trace with hash -1846173670, now seen corresponding path program 1 times [2021-11-19 05:20:51,822 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:51,822 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1122679093] [2021-11-19 05:20:51,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:51,822 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:51,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:51,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:51,872 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:51,872 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1122679093] [2021-11-19 05:20:51,872 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1122679093] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:51,872 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:51,873 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:51,873 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [582268398] [2021-11-19 05:20:51,873 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:51,873 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:20:51,874 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:20:51,874 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-19 05:20:51,874 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-19 05:20:51,875 INFO L87 Difference]: Start difference. First operand 12086 states and 17726 transitions. cyclomatic complexity: 5648 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:52,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:20:52,193 INFO L93 Difference]: Finished difference Result 23058 states and 33757 transitions. [2021-11-19 05:20:52,194 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-19 05:20:52,194 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23058 states and 33757 transitions. [2021-11-19 05:20:52,309 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22759 [2021-11-19 05:20:52,408 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23058 states to 23058 states and 33757 transitions. [2021-11-19 05:20:52,409 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23058 [2021-11-19 05:20:52,439 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23058 [2021-11-19 05:20:52,439 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23058 states and 33757 transitions. [2021-11-19 05:20:52,462 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:20:52,462 INFO L681 BuchiCegarLoop]: Abstraction has 23058 states and 33757 transitions. [2021-11-19 05:20:52,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23058 states and 33757 transitions. [2021-11-19 05:20:52,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23058 to 23050. [2021-11-19 05:20:52,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23050 states, 23050 states have (on average 1.4641648590021692) internal successors, (33749), 23049 states have internal predecessors, (33749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:53,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23050 states to 23050 states and 33749 transitions. [2021-11-19 05:20:53,007 INFO L704 BuchiCegarLoop]: Abstraction has 23050 states and 33749 transitions. [2021-11-19 05:20:53,007 INFO L587 BuchiCegarLoop]: Abstraction has 23050 states and 33749 transitions. [2021-11-19 05:20:53,008 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-19 05:20:53,008 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23050 states and 33749 transitions. [2021-11-19 05:20:53,076 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22759 [2021-11-19 05:20:53,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:53,077 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:53,079 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:53,080 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:53,080 INFO L791 eck$LassoCheckResult]: Stem: 112383#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 112384#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 111808#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 111778#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 111779#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 113052#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 112085#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 111536#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 111537#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 112817#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 112961#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 113349#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 113350#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 112297#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 112298#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 112844#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 112762#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 112763#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 112919#L1206 assume !(0 == ~M_E~0); 112274#L1206-2 assume !(0 == ~T1_E~0); 112275#L1211-1 assume !(0 == ~T2_E~0); 113186#L1216-1 assume !(0 == ~T3_E~0); 112067#L1221-1 assume !(0 == ~T4_E~0); 112068#L1226-1 assume !(0 == ~T5_E~0); 111731#L1231-1 assume !(0 == ~T6_E~0); 111732#L1236-1 assume !(0 == ~T7_E~0); 113220#L1241-1 assume !(0 == ~T8_E~0); 112129#L1246-1 assume !(0 == ~T9_E~0); 112130#L1251-1 assume !(0 == ~T10_E~0); 112350#L1256-1 assume !(0 == ~T11_E~0); 111548#L1261-1 assume !(0 == ~T12_E~0); 111549#L1266-1 assume !(0 == ~E_M~0); 113335#L1271-1 assume !(0 == ~E_1~0); 112949#L1276-1 assume !(0 == ~E_2~0); 112950#L1281-1 assume !(0 == ~E_3~0); 112871#L1286-1 assume !(0 == ~E_4~0); 111971#L1291-1 assume !(0 == ~E_5~0); 111972#L1296-1 assume !(0 == ~E_6~0); 112681#L1301-1 assume !(0 == ~E_7~0); 112682#L1306-1 assume !(0 == ~E_8~0); 113128#L1311-1 assume !(0 == ~E_9~0); 111932#L1316-1 assume !(0 == ~E_10~0); 111933#L1321-1 assume !(0 == ~E_11~0); 112698#L1326-1 assume !(0 == ~E_12~0); 111798#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 111799#L598 assume 1 == ~m_pc~0; 111856#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 111857#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 113201#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 113299#L1497 assume !(0 != activate_threads_~tmp~1#1); 113300#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 113253#L617 assume !(1 == ~t1_pc~0); 112152#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 112153#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112012#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 112013#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 112779#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112780#L636 assume 1 == ~t2_pc~0; 112121#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 112122#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 111952#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 111953#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 112816#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112473#L655 assume !(1 == ~t3_pc~0); 112474#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 113206#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 111826#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 111827#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 113336#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 113337#L674 assume 1 == ~t4_pc~0; 111644#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 111645#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112956#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 111954#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 111955#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 112470#L693 assume !(1 == ~t5_pc~0); 112634#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 112279#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 112280#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 113130#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 112362#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 112299#L712 assume 1 == ~t6_pc~0; 112300#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 112731#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 112732#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 113028#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 112833#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 112831#L731 assume 1 == ~t7_pc~0; 111800#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 111801#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 111995#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 112945#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 113065#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 111910#L750 assume !(1 == ~t8_pc~0); 111579#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 111578#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 112096#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 113143#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 112233#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 112234#L769 assume 1 == ~t9_pc~0; 112777#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 111753#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 111754#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 112539#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 113004#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 113086#L788 assume !(1 == ~t10_pc~0); 112648#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 112649#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 112888#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 112889#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 111906#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 111907#L807 assume 1 == ~t11_pc~0; 113095#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 112661#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 112818#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 113244#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 113373#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 113189#L826 assume !(1 == ~t12_pc~0); 112304#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 112305#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 112839#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 113286#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 112463#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112371#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 112372#L1344-2 assume !(1 == ~T1_E~0); 112514#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 113733#L1354-1 assume !(1 == ~T3_E~0); 113731#L1359-1 assume !(1 == ~T4_E~0); 113729#L1364-1 assume !(1 == ~T5_E~0); 113727#L1369-1 assume !(1 == ~T6_E~0); 113692#L1374-1 assume !(1 == ~T7_E~0); 113687#L1379-1 assume !(1 == ~T8_E~0); 113682#L1384-1 assume !(1 == ~T9_E~0); 113648#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 113644#L1394-1 assume !(1 == ~T11_E~0); 113621#L1399-1 assume !(1 == ~T12_E~0); 113619#L1404-1 assume !(1 == ~E_M~0); 113597#L1409-1 assume !(1 == ~E_1~0); 113572#L1414-1 assume !(1 == ~E_2~0); 113570#L1419-1 assume !(1 == ~E_3~0); 113568#L1424-1 assume !(1 == ~E_4~0); 113567#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 113563#L1434-1 assume !(1 == ~E_6~0); 113561#L1439-1 assume !(1 == ~E_7~0); 113560#L1444-1 assume !(1 == ~E_8~0); 113559#L1449-1 assume !(1 == ~E_9~0); 113557#L1454-1 assume !(1 == ~E_10~0); 113443#L1459-1 assume !(1 == ~E_11~0); 113428#L1464-1 assume !(1 == ~E_12~0); 113415#L1469-1 assume { :end_inline_reset_delta_events } true; 113407#L1815-2 [2021-11-19 05:20:53,081 INFO L793 eck$LassoCheckResult]: Loop: 113407#L1815-2 assume !false; 113401#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 113396#L1181 assume !false; 113395#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 113392#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 113381#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 113380#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 113378#L1008 assume !(0 != eval_~tmp~0#1); 113377#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 113376#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 113374#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 113375#L1206-5 assume !(0 == ~T1_E~0); 130490#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 130487#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 130485#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 130483#L1226-3 assume !(0 == ~T5_E~0); 130481#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 130479#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 130477#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 130474#L1246-3 assume !(0 == ~T9_E~0); 130472#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 130470#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 130468#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 130466#L1266-3 assume !(0 == ~E_M~0); 130464#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 130461#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 130459#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 130457#L1286-3 assume !(0 == ~E_4~0); 130455#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 130453#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 130451#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 130448#L1306-3 assume !(0 == ~E_8~0); 130446#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 130444#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 130442#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 130440#L1326-3 assume !(0 == ~E_12~0); 130436#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 130434#L598-42 assume !(1 == ~m_pc~0); 130432#L598-44 is_master_triggered_~__retres1~0#1 := 0; 130430#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 130429#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 130428#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 130427#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 130426#L617-42 assume !(1 == ~t1_pc~0); 130425#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 130423#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 130422#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 130421#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 130420#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 130419#L636-42 assume 1 == ~t2_pc~0; 130417#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 130416#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 130415#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 130414#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 130413#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 130412#L655-42 assume !(1 == ~t3_pc~0); 130411#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 130408#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 130405#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 130403#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 130401#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 130399#L674-42 assume 1 == ~t4_pc~0; 130397#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 130394#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130391#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 130389#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 130387#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 130385#L693-42 assume !(1 == ~t5_pc~0); 130383#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 130380#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130377#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 130375#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 130373#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 130371#L712-42 assume 1 == ~t6_pc~0; 130369#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 130366#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 130363#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 130361#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 130359#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 130357#L731-42 assume !(1 == ~t7_pc~0); 130355#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 130352#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 130349#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 130347#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 130345#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 130343#L750-42 assume 1 == ~t8_pc~0; 130341#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 130338#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 130335#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 130333#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 130331#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 130329#L769-42 assume !(1 == ~t9_pc~0); 130327#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 130324#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 130321#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 130319#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 130317#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 130315#L788-42 assume !(1 == ~t10_pc~0); 130313#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 130310#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 130307#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 130305#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 130303#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 128877#L807-42 assume !(1 == ~t11_pc~0); 128873#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 128871#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 128869#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 128867#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 128641#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 128638#L826-42 assume 1 == ~t12_pc~0; 128635#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 128633#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 128631#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 128626#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 128615#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 128607#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 112910#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 128561#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 128558#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 128556#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 128551#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 128549#L1369-3 assume !(1 == ~T6_E~0); 128546#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 128271#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 113795#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 113753#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 113711#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 113709#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 113675#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 113673#L1409-3 assume !(1 == ~E_1~0); 113671#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 113669#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 113667#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 113636#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 113613#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 113610#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 113588#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 113586#L1449-3 assume !(1 == ~E_9~0); 113584#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 113582#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 113553#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 113549#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 113546#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 113533#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 113531#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 113529#L1834 assume !(0 == start_simulation_~tmp~3#1); 112962#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 113522#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 113512#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 113510#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 113441#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 113439#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 113425#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 113414#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 113407#L1815-2 [2021-11-19 05:20:53,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:53,081 INFO L85 PathProgramCache]: Analyzing trace with hash 931262326, now seen corresponding path program 1 times [2021-11-19 05:20:53,082 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:53,082 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1443092529] [2021-11-19 05:20:53,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:53,082 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:53,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:53,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:53,129 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:53,129 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1443092529] [2021-11-19 05:20:53,129 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1443092529] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:53,129 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:53,130 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-19 05:20:53,130 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707649294] [2021-11-19 05:20:53,130 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:53,130 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:20:53,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:53,131 INFO L85 PathProgramCache]: Analyzing trace with hash -627164961, now seen corresponding path program 1 times [2021-11-19 05:20:53,131 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:53,131 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983505852] [2021-11-19 05:20:53,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:53,132 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:53,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:53,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:53,175 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:53,176 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1983505852] [2021-11-19 05:20:53,176 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1983505852] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:53,176 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:53,176 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:53,176 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [946741803] [2021-11-19 05:20:53,176 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:53,177 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:20:53,177 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:20:53,177 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:20:53,178 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:20:53,178 INFO L87 Difference]: Start difference. First operand 23050 states and 33749 transitions. cyclomatic complexity: 10715 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:53,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:20:53,653 INFO L93 Difference]: Finished difference Result 45471 states and 66152 transitions. [2021-11-19 05:20:53,653 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:20:53,654 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45471 states and 66152 transitions. [2021-11-19 05:20:53,859 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 45165 [2021-11-19 05:20:54,168 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45471 states to 45471 states and 66152 transitions. [2021-11-19 05:20:54,169 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45471 [2021-11-19 05:20:54,243 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45471 [2021-11-19 05:20:54,243 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45471 states and 66152 transitions. [2021-11-19 05:20:54,277 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:20:54,277 INFO L681 BuchiCegarLoop]: Abstraction has 45471 states and 66152 transitions. [2021-11-19 05:20:54,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45471 states and 66152 transitions. [2021-11-19 05:20:55,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45471 to 44031. [2021-11-19 05:20:55,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44031 states, 44031 states have (on average 1.4562467352547068) internal successors, (64120), 44030 states have internal predecessors, (64120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:55,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44031 states to 44031 states and 64120 transitions. [2021-11-19 05:20:55,692 INFO L704 BuchiCegarLoop]: Abstraction has 44031 states and 64120 transitions. [2021-11-19 05:20:55,692 INFO L587 BuchiCegarLoop]: Abstraction has 44031 states and 64120 transitions. [2021-11-19 05:20:55,692 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-19 05:20:55,692 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44031 states and 64120 transitions. [2021-11-19 05:20:55,878 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43725 [2021-11-19 05:20:55,878 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:55,878 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:20:55,881 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:55,881 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:20:55,882 INFO L791 eck$LassoCheckResult]: Stem: 180913#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 180914#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 180331#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 180301#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 180302#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 181633#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 180612#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 180064#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 180065#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 181381#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 181537#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 182028#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 182029#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 180825#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 180826#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 181411#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 181318#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 181319#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 181496#L1206 assume !(0 == ~M_E~0); 180804#L1206-2 assume !(0 == ~T1_E~0); 180805#L1211-1 assume !(0 == ~T2_E~0); 181799#L1216-1 assume !(0 == ~T3_E~0); 180594#L1221-1 assume !(0 == ~T4_E~0); 180595#L1226-1 assume !(0 == ~T5_E~0); 180255#L1231-1 assume !(0 == ~T6_E~0); 180256#L1236-1 assume !(0 == ~T7_E~0); 181841#L1241-1 assume !(0 == ~T8_E~0); 180656#L1246-1 assume !(0 == ~T9_E~0); 180657#L1251-1 assume !(0 == ~T10_E~0); 180880#L1256-1 assume !(0 == ~T11_E~0); 180076#L1261-1 assume !(0 == ~T12_E~0); 180077#L1266-1 assume !(0 == ~E_M~0); 182007#L1271-1 assume !(0 == ~E_1~0); 181524#L1276-1 assume !(0 == ~E_2~0); 181525#L1281-1 assume !(0 == ~E_3~0); 181441#L1286-1 assume !(0 == ~E_4~0); 180495#L1291-1 assume !(0 == ~E_5~0); 180496#L1296-1 assume !(0 == ~E_6~0); 181228#L1301-1 assume !(0 == ~E_7~0); 181229#L1306-1 assume !(0 == ~E_8~0); 181728#L1311-1 assume !(0 == ~E_9~0); 180457#L1316-1 assume !(0 == ~E_10~0); 180458#L1321-1 assume !(0 == ~E_11~0); 181247#L1326-1 assume !(0 == ~E_12~0); 180321#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 180322#L598 assume !(1 == ~m_pc~0); 181032#L598-2 is_master_triggered_~__retres1~0#1 := 0; 181033#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 181820#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 181953#L1497 assume !(0 != activate_threads_~tmp~1#1); 181954#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 181885#L617 assume !(1 == ~t1_pc~0); 180679#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 180680#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 180536#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 180537#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 181336#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 181337#L636 assume 1 == ~t2_pc~0; 180648#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 180649#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 180476#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 180477#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 181380#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 181003#L655 assume !(1 == ~t3_pc~0); 181004#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 181826#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 180351#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 180352#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 182008#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 182009#L674 assume 1 == ~t4_pc~0; 180171#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 180172#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 181532#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 180478#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 180479#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 181000#L693 assume !(1 == ~t5_pc~0); 181178#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 180806#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 180807#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 181731#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 180892#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 180829#L712 assume 1 == ~t6_pc~0; 180830#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 181281#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 181282#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 181608#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 181400#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 181398#L731 assume 1 == ~t7_pc~0; 180325#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 180326#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 180519#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 181519#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 181649#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 180435#L750 assume !(1 == ~t8_pc~0); 180107#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 180106#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 180623#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 181747#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 180760#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 180761#L769 assume 1 == ~t9_pc~0; 181332#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 180279#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 180280#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 181080#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 181584#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 181681#L788 assume !(1 == ~t10_pc~0); 181194#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 181195#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 181456#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 181457#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 180431#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 180432#L807 assume 1 == ~t11_pc~0; 181690#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 181207#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 181382#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 181874#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 182081#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 181803#L826 assume !(1 == ~t12_pc~0); 180832#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 180833#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 181406#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 181929#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 180993#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 180901#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 180902#L1344-2 assume !(1 == ~T1_E~0); 181051#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 203575#L1354-1 assume !(1 == ~T3_E~0); 203561#L1359-1 assume !(1 == ~T4_E~0); 203559#L1364-1 assume !(1 == ~T5_E~0); 203549#L1369-1 assume !(1 == ~T6_E~0); 203542#L1374-1 assume !(1 == ~T7_E~0); 181243#L1379-1 assume !(1 == ~T8_E~0); 181244#L1384-1 assume !(1 == ~T9_E~0); 181317#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 181843#L1394-1 assume !(1 == ~T11_E~0); 181844#L1399-1 assume !(1 == ~T12_E~0); 181967#L1404-1 assume !(1 == ~E_M~0); 180660#L1409-1 assume !(1 == ~E_1~0); 180661#L1414-1 assume !(1 == ~E_2~0); 181562#L1419-1 assume !(1 == ~E_3~0); 180292#L1424-1 assume !(1 == ~E_4~0); 180293#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 216349#L1434-1 assume !(1 == ~E_6~0); 216346#L1439-1 assume !(1 == ~E_7~0); 216344#L1444-1 assume !(1 == ~E_8~0); 216342#L1449-1 assume !(1 == ~E_9~0); 216340#L1454-1 assume !(1 == ~E_10~0); 216307#L1459-1 assume !(1 == ~E_11~0); 216306#L1464-1 assume !(1 == ~E_12~0); 216293#L1469-1 assume { :end_inline_reset_delta_events } true; 216285#L1815-2 [2021-11-19 05:20:55,882 INFO L793 eck$LassoCheckResult]: Loop: 216285#L1815-2 assume !false; 216279#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 216274#L1181 assume !false; 216273#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 216270#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 216259#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 216258#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 216256#L1008 assume !(0 != eval_~tmp~0#1); 216257#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 223873#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 223872#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 223871#L1206-5 assume !(0 == ~T1_E~0); 223870#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 223869#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 223868#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 223571#L1226-3 assume !(0 == ~T5_E~0); 223570#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 223569#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 223568#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 223567#L1246-3 assume !(0 == ~T9_E~0); 223566#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 223565#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 223564#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 223563#L1266-3 assume !(0 == ~E_M~0); 223562#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 223560#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 223558#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 223556#L1286-3 assume !(0 == ~E_4~0); 223554#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 223552#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 223550#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 223547#L1306-3 assume !(0 == ~E_8~0); 223545#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 223543#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 223541#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 223539#L1326-3 assume !(0 == ~E_12~0); 223537#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 223534#L598-42 assume !(1 == ~m_pc~0); 223532#L598-44 is_master_triggered_~__retres1~0#1 := 0; 223530#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 223528#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 223526#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 223524#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 223523#L617-42 assume !(1 == ~t1_pc~0); 223522#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 223518#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 223516#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 223514#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 223486#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 181950#L636-42 assume !(1 == ~t2_pc~0); 181065#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 181066#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 181454#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 181455#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 217973#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 217970#L655-42 assume !(1 == ~t3_pc~0); 217968#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 217965#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 217963#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 217961#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 217959#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 217956#L674-42 assume 1 == ~t4_pc~0; 217953#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 217950#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 217948#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 217946#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 217943#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 217941#L693-42 assume !(1 == ~t5_pc~0); 217939#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 217936#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 217934#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 217932#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 217929#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 217927#L712-42 assume 1 == ~t6_pc~0; 217925#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 217922#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 217920#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 217918#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 217915#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 217913#L731-42 assume !(1 == ~t7_pc~0); 217911#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 217908#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 217906#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 217904#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 217901#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 217899#L750-42 assume 1 == ~t8_pc~0; 217897#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 217894#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 217892#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 217890#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 217887#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 217886#L769-42 assume !(1 == ~t9_pc~0); 217885#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 217883#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 217882#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 217881#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 217880#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 217879#L788-42 assume !(1 == ~t10_pc~0); 217877#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 217874#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 217871#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 217869#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 217867#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 217865#L807-42 assume 1 == ~t11_pc~0; 217863#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 217860#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 217857#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 217855#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 217853#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 217851#L826-42 assume !(1 == ~t12_pc~0); 217849#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 217846#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 217843#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 217841#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 217839#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 217837#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 181485#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 217097#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 217095#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 217093#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 217091#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 217089#L1369-3 assume !(1 == ~T6_E~0); 217087#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 217085#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 217083#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 209231#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 217081#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 217079#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 217077#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 217075#L1409-3 assume !(1 == ~E_1~0); 217073#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 217071#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 216958#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 216954#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 216952#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 216950#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 216948#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 216930#L1449-3 assume !(1 == ~E_9~0); 216920#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 216911#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 216903#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 216897#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 216566#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 216553#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 216551#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 216549#L1834 assume !(0 == start_simulation_~tmp~3#1); 181539#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 216334#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 216324#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 216322#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 216320#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 216318#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 216303#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 216292#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 216285#L1815-2 [2021-11-19 05:20:55,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:55,883 INFO L85 PathProgramCache]: Analyzing trace with hash 1218722231, now seen corresponding path program 1 times [2021-11-19 05:20:55,884 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:55,884 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [779443620] [2021-11-19 05:20:55,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:55,884 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:55,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:55,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:55,932 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:55,932 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [779443620] [2021-11-19 05:20:55,932 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [779443620] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:55,932 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:55,933 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-19 05:20:55,933 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320185192] [2021-11-19 05:20:55,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:55,933 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:20:55,934 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:20:55,934 INFO L85 PathProgramCache]: Analyzing trace with hash 887658464, now seen corresponding path program 1 times [2021-11-19 05:20:55,934 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:20:55,934 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2124730374] [2021-11-19 05:20:55,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:20:55,935 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:20:55,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:20:55,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:20:55,974 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:20:55,975 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2124730374] [2021-11-19 05:20:55,975 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2124730374] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:20:55,975 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:20:55,975 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:20:55,975 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [549778131] [2021-11-19 05:20:55,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:20:55,976 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:20:55,976 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:20:55,977 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-19 05:20:55,977 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-19 05:20:55,977 INFO L87 Difference]: Start difference. First operand 44031 states and 64120 transitions. cyclomatic complexity: 20121 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:57,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:20:57,083 INFO L93 Difference]: Finished difference Result 125727 states and 182708 transitions. [2021-11-19 05:20:57,083 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-19 05:20:57,084 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 125727 states and 182708 transitions. [2021-11-19 05:20:57,842 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 124920 [2021-11-19 05:20:58,464 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 125727 states to 125727 states and 182708 transitions. [2021-11-19 05:20:58,464 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125727 [2021-11-19 05:20:58,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125727 [2021-11-19 05:20:58,517 INFO L73 IsDeterministic]: Start isDeterministic. Operand 125727 states and 182708 transitions. [2021-11-19 05:20:58,841 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:20:58,841 INFO L681 BuchiCegarLoop]: Abstraction has 125727 states and 182708 transitions. [2021-11-19 05:20:58,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125727 states and 182708 transitions. [2021-11-19 05:20:59,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125727 to 45240. [2021-11-19 05:20:59,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45240 states, 45240 states have (on average 1.444053934571176) internal successors, (65329), 45239 states have internal predecessors, (65329), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:20:59,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45240 states to 45240 states and 65329 transitions. [2021-11-19 05:20:59,861 INFO L704 BuchiCegarLoop]: Abstraction has 45240 states and 65329 transitions. [2021-11-19 05:20:59,861 INFO L587 BuchiCegarLoop]: Abstraction has 45240 states and 65329 transitions. [2021-11-19 05:20:59,861 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-19 05:20:59,861 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45240 states and 65329 transitions. [2021-11-19 05:20:59,997 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 44931 [2021-11-19 05:20:59,998 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:20:59,998 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:21:00,001 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:21:00,001 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:21:00,002 INFO L791 eck$LassoCheckResult]: Stem: 350700#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 350701#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 350106#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 350079#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 350080#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 351436#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 350385#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 349835#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 349836#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 351185#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 351340#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 351878#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 351879#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 350607#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 350608#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 351217#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 351125#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 351126#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 351300#L1206 assume !(0 == ~M_E~0); 350583#L1206-2 assume !(0 == ~T1_E~0); 350584#L1211-1 assume !(0 == ~T2_E~0); 351616#L1216-1 assume !(0 == ~T3_E~0); 350367#L1221-1 assume !(0 == ~T4_E~0); 350368#L1226-1 assume !(0 == ~T5_E~0); 350029#L1231-1 assume !(0 == ~T6_E~0); 350030#L1236-1 assume !(0 == ~T7_E~0); 351663#L1241-1 assume !(0 == ~T8_E~0); 350431#L1246-1 assume !(0 == ~T9_E~0); 350432#L1251-1 assume !(0 == ~T10_E~0); 350663#L1256-1 assume !(0 == ~T11_E~0); 349847#L1261-1 assume !(0 == ~T12_E~0); 349848#L1266-1 assume !(0 == ~E_M~0); 351855#L1271-1 assume !(0 == ~E_1~0); 351328#L1276-1 assume !(0 == ~E_2~0); 351329#L1281-1 assume !(0 == ~E_3~0); 351249#L1286-1 assume !(0 == ~E_4~0); 350268#L1291-1 assume !(0 == ~E_5~0); 350269#L1296-1 assume !(0 == ~E_6~0); 351032#L1301-1 assume !(0 == ~E_7~0); 351033#L1306-1 assume !(0 == ~E_8~0); 351527#L1311-1 assume !(0 == ~E_9~0); 350230#L1316-1 assume !(0 == ~E_10~0); 350231#L1321-1 assume !(0 == ~E_11~0); 351051#L1326-1 assume !(0 == ~E_12~0); 350096#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 350097#L598 assume !(1 == ~m_pc~0); 350826#L598-2 is_master_triggered_~__retres1~0#1 := 0; 350827#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 351639#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 351795#L1497 assume !(0 != activate_threads_~tmp~1#1); 351796#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 351711#L617 assume !(1 == ~t1_pc~0); 350455#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 350456#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 351919#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 351817#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 351144#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 351145#L636 assume 1 == ~t2_pc~0; 350423#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 350424#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 350249#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 350250#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 351184#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 350796#L655 assume !(1 == ~t3_pc~0); 350797#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 351645#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 350125#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 350126#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 351857#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 351858#L674 assume 1 == ~t4_pc~0; 349942#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 349943#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 351335#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 350253#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 350254#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 350792#L693 assume !(1 == ~t5_pc~0); 350979#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 350589#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 350590#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 351532#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 350675#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 350609#L712 assume 1 == ~t6_pc~0; 350610#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 351087#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 351088#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 351410#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 351202#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 351199#L731 assume 1 == ~t7_pc~0; 350098#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 350099#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 350294#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 351324#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 351449#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 350208#L750 assume !(1 == ~t8_pc~0); 349878#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 349877#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 350396#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 351545#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 350538#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 350539#L769 assume 1 == ~t9_pc~0; 351142#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 350051#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 350052#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 350874#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 351384#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 351474#L788 assume !(1 == ~t10_pc~0); 350996#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 350997#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 351265#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 351266#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 350204#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 350205#L807 assume 1 == ~t11_pc~0; 351483#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 351011#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 351186#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 351700#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 351934#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 351619#L826 assume !(1 == ~t12_pc~0); 350614#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 350615#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 351212#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 351764#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 350785#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 350686#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 350687#L1344-2 assume !(1 == ~T1_E~0); 350847#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 351041#L1354-1 assume !(1 == ~T3_E~0); 351042#L1359-1 assume !(1 == ~T4_E~0); 353735#L1364-1 assume !(1 == ~T5_E~0); 353733#L1369-1 assume !(1 == ~T6_E~0); 353731#L1374-1 assume !(1 == ~T7_E~0); 353729#L1379-1 assume !(1 == ~T8_E~0); 353727#L1384-1 assume !(1 == ~T9_E~0); 353725#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 353722#L1394-1 assume !(1 == ~T11_E~0); 353720#L1399-1 assume !(1 == ~T12_E~0); 353718#L1404-1 assume !(1 == ~E_M~0); 353381#L1409-1 assume !(1 == ~E_1~0); 352893#L1414-1 assume !(1 == ~E_2~0); 352891#L1419-1 assume !(1 == ~E_3~0); 352889#L1424-1 assume !(1 == ~E_4~0); 352886#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 352884#L1434-1 assume !(1 == ~E_6~0); 352882#L1439-1 assume !(1 == ~E_7~0); 352670#L1444-1 assume !(1 == ~E_8~0); 352669#L1449-1 assume !(1 == ~E_9~0); 352559#L1454-1 assume !(1 == ~E_10~0); 352527#L1459-1 assume !(1 == ~E_11~0); 352510#L1464-1 assume !(1 == ~E_12~0); 352497#L1469-1 assume { :end_inline_reset_delta_events } true; 352489#L1815-2 [2021-11-19 05:21:00,003 INFO L793 eck$LassoCheckResult]: Loop: 352489#L1815-2 assume !false; 352483#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 352478#L1181 assume !false; 352477#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 352474#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 352463#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 352462#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 352460#L1008 assume !(0 != eval_~tmp~0#1); 352459#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 352458#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 352455#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 352456#L1206-5 assume !(0 == ~T1_E~0); 365738#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 365737#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 365736#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 365735#L1226-3 assume !(0 == ~T5_E~0); 365734#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 365733#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 365494#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 365484#L1246-3 assume !(0 == ~T9_E~0); 365473#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 365466#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 365461#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 365444#L1266-3 assume !(0 == ~E_M~0); 365443#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 365442#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 365441#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 365440#L1286-3 assume !(0 == ~E_4~0); 365439#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 365438#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 365437#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 365436#L1306-3 assume !(0 == ~E_8~0); 365435#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 365434#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 365433#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 365432#L1326-3 assume !(0 == ~E_12~0); 365431#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 365430#L598-42 assume !(1 == ~m_pc~0); 365429#L598-44 is_master_triggered_~__retres1~0#1 := 0; 365428#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 365427#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 365426#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 365425#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 365424#L617-42 assume !(1 == ~t1_pc~0); 365423#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 365421#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 365419#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 365417#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 365414#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 365412#L636-42 assume !(1 == ~t2_pc~0); 365409#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 365406#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 365404#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 365402#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 365400#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 365398#L655-42 assume !(1 == ~t3_pc~0); 365395#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 365392#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 365390#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 365388#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 365386#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 365382#L674-42 assume 1 == ~t4_pc~0; 365380#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 365377#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 365376#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 365375#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 365374#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 365373#L693-42 assume !(1 == ~t5_pc~0); 365372#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 365370#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 365369#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 365368#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 365367#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 365366#L712-42 assume 1 == ~t6_pc~0; 365365#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 365363#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 365362#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 365361#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 365360#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 365359#L731-42 assume 1 == ~t7_pc~0; 365357#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 365356#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 365355#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 365354#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 365353#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 365352#L750-42 assume 1 == ~t8_pc~0; 365351#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 365349#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 365348#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 365347#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 365346#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 365345#L769-42 assume !(1 == ~t9_pc~0); 365344#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 365342#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 365340#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 365338#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 365336#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 365334#L788-42 assume !(1 == ~t10_pc~0); 365332#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 365329#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 365327#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 365326#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 365324#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 365322#L807-42 assume !(1 == ~t11_pc~0); 365319#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 365317#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 365315#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 365313#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 365312#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 356040#L826-42 assume !(1 == ~t12_pc~0); 356037#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 356034#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 356032#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 356030#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 356028#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 355146#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 352811#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 354436#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 353879#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 353714#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 353365#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 353360#L1369-3 assume !(1 == ~T6_E~0); 353359#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 353358#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 352786#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 352782#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 352780#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 352778#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 352776#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 352774#L1409-3 assume !(1 == ~E_1~0); 352772#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 352770#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 352766#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 352762#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 352760#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 352758#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 352756#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 352754#L1449-3 assume !(1 == ~E_9~0); 352752#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 352750#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 352749#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 352746#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 352744#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 352732#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 352731#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 352614#L1834 assume !(0 == start_simulation_~tmp~3#1); 352611#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 352554#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 352526#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 352524#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 352522#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 352521#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 352507#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 352496#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 352489#L1815-2 [2021-11-19 05:21:00,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:21:00,004 INFO L85 PathProgramCache]: Analyzing trace with hash -1724859847, now seen corresponding path program 1 times [2021-11-19 05:21:00,004 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:21:00,004 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [626919553] [2021-11-19 05:21:00,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:21:00,005 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:21:00,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:21:00,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:21:00,048 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:21:00,048 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [626919553] [2021-11-19 05:21:00,049 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [626919553] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:21:00,049 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:21:00,049 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:21:00,049 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [947657782] [2021-11-19 05:21:00,049 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:21:00,050 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:21:00,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:21:00,050 INFO L85 PathProgramCache]: Analyzing trace with hash 798824546, now seen corresponding path program 1 times [2021-11-19 05:21:00,051 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:21:00,051 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341496262] [2021-11-19 05:21:00,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:21:00,051 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:21:00,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:21:00,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:21:00,093 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:21:00,093 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1341496262] [2021-11-19 05:21:00,093 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1341496262] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:21:00,093 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:21:00,093 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:21:00,094 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489575765] [2021-11-19 05:21:00,094 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:21:00,094 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:21:00,094 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:21:00,095 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-19 05:21:00,095 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-19 05:21:00,096 INFO L87 Difference]: Start difference. First operand 45240 states and 65329 transitions. cyclomatic complexity: 20121 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:21:01,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:21:01,099 INFO L93 Difference]: Finished difference Result 110480 states and 158451 transitions. [2021-11-19 05:21:01,100 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-19 05:21:01,100 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 110480 states and 158451 transitions. [2021-11-19 05:21:01,548 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 108556 [2021-11-19 05:21:02,296 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 110480 states to 110480 states and 158451 transitions. [2021-11-19 05:21:02,297 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 110480 [2021-11-19 05:21:02,354 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 110480 [2021-11-19 05:21:02,354 INFO L73 IsDeterministic]: Start isDeterministic. Operand 110480 states and 158451 transitions. [2021-11-19 05:21:02,395 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:21:02,395 INFO L681 BuchiCegarLoop]: Abstraction has 110480 states and 158451 transitions. [2021-11-19 05:21:02,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110480 states and 158451 transitions. [2021-11-19 05:21:03,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110480 to 86664. [2021-11-19 05:21:03,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 86664 states, 86664 states have (on average 1.4383481030185543) internal successors, (124653), 86663 states have internal predecessors, (124653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:21:03,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86664 states to 86664 states and 124653 transitions. [2021-11-19 05:21:03,446 INFO L704 BuchiCegarLoop]: Abstraction has 86664 states and 124653 transitions. [2021-11-19 05:21:03,446 INFO L587 BuchiCegarLoop]: Abstraction has 86664 states and 124653 transitions. [2021-11-19 05:21:03,446 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-19 05:21:03,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 86664 states and 124653 transitions. [2021-11-19 05:21:04,045 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 86340 [2021-11-19 05:21:04,045 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:21:04,045 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:21:04,049 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:21:04,071 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:21:04,072 INFO L791 eck$LassoCheckResult]: Stem: 506403#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 506404#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 505829#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 505799#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 505800#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 507103#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 506106#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 505565#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 505566#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 506865#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 507008#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 507458#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 507459#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 506315#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 506316#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 506894#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 506808#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 506809#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 506968#L1206 assume !(0 == ~M_E~0); 506294#L1206-2 assume !(0 == ~T1_E~0); 506295#L1211-1 assume !(0 == ~T2_E~0); 507259#L1216-1 assume !(0 == ~T3_E~0); 506088#L1221-1 assume !(0 == ~T4_E~0); 506089#L1226-1 assume !(0 == ~T5_E~0); 505754#L1231-1 assume !(0 == ~T6_E~0); 505755#L1236-1 assume !(0 == ~T7_E~0); 507297#L1241-1 assume !(0 == ~T8_E~0); 506147#L1246-1 assume !(0 == ~T9_E~0); 506148#L1251-1 assume !(0 == ~T10_E~0); 506370#L1256-1 assume !(0 == ~T11_E~0); 505577#L1261-1 assume !(0 == ~T12_E~0); 505578#L1266-1 assume !(0 == ~E_M~0); 507443#L1271-1 assume !(0 == ~E_1~0); 506996#L1276-1 assume !(0 == ~E_2~0); 506997#L1281-1 assume !(0 == ~E_3~0); 506921#L1286-1 assume !(0 == ~E_4~0); 505990#L1291-1 assume !(0 == ~E_5~0); 505991#L1296-1 assume !(0 == ~E_6~0); 506724#L1301-1 assume !(0 == ~E_7~0); 506725#L1306-1 assume !(0 == ~E_8~0); 507186#L1311-1 assume !(0 == ~E_9~0); 505952#L1316-1 assume !(0 == ~E_10~0); 505953#L1321-1 assume !(0 == ~E_11~0); 506741#L1326-1 assume !(0 == ~E_12~0); 505819#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 505820#L598 assume !(1 == ~m_pc~0); 506526#L598-2 is_master_triggered_~__retres1~0#1 := 0; 506527#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 507276#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 507400#L1497 assume !(0 != activate_threads_~tmp~1#1); 507401#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 507333#L617 assume !(1 == ~t1_pc~0); 506170#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 506171#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 507505#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 507418#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 506827#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 506828#L636 assume !(1 == ~t2_pc~0); 507349#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 506597#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 505971#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 505972#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 506864#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 506497#L655 assume !(1 == ~t3_pc~0); 506498#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 507281#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 505849#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 505850#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 507444#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 507445#L674 assume 1 == ~t4_pc~0; 505670#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 505671#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 507003#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 505973#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 505974#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 506494#L693 assume !(1 == ~t5_pc~0); 506673#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 506296#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 506297#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 507189#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 506382#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 506319#L712 assume 1 == ~t6_pc~0; 506320#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 506776#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 506777#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 507075#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 506882#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 506879#L731 assume 1 == ~t7_pc~0; 505823#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 505824#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 506014#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 506991#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 507117#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 505930#L750 assume !(1 == ~t8_pc~0); 505608#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 505607#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 506117#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 507202#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 506250#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 506251#L769 assume 1 == ~t9_pc~0; 506823#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 505777#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 505778#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 506573#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 507051#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 507141#L788 assume !(1 == ~t10_pc~0); 506687#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 506688#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 506936#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 506937#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 505926#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 505927#L807 assume 1 == ~t11_pc~0; 507150#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 506703#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 506866#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 507324#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 507501#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 507264#L826 assume !(1 == ~t12_pc~0); 506322#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 506323#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 506889#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 507373#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 506487#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 506391#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 506392#L1344-2 assume !(1 == ~T1_E~0); 506545#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 506731#L1354-1 assume !(1 == ~T3_E~0); 506732#L1359-1 assume !(1 == ~T4_E~0); 507129#L1364-1 assume !(1 == ~T5_E~0); 506033#L1369-1 assume !(1 == ~T6_E~0); 506034#L1374-1 assume !(1 == ~T7_E~0); 506737#L1379-1 assume !(1 == ~T8_E~0); 506738#L1384-1 assume !(1 == ~T9_E~0); 506807#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 507301#L1394-1 assume !(1 == ~T11_E~0); 507302#L1399-1 assume !(1 == ~T12_E~0); 507414#L1404-1 assume !(1 == ~E_M~0); 507415#L1409-1 assume !(1 == ~E_1~0); 507395#L1414-1 assume !(1 == ~E_2~0); 507396#L1419-1 assume !(1 == ~E_3~0); 505790#L1424-1 assume !(1 == ~E_4~0); 505791#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 506748#L1434-1 assume !(1 == ~E_6~0); 507322#L1439-1 assume !(1 == ~E_7~0); 505845#L1444-1 assume !(1 == ~E_8~0); 505846#L1449-1 assume !(1 == ~E_9~0); 506256#L1454-1 assume !(1 == ~E_10~0); 506257#L1459-1 assume !(1 == ~E_11~0); 506844#L1464-1 assume !(1 == ~E_12~0); 506845#L1469-1 assume { :end_inline_reset_delta_events } true; 586014#L1815-2 [2021-11-19 05:21:04,073 INFO L793 eck$LassoCheckResult]: Loop: 586014#L1815-2 assume !false; 586013#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 586008#L1181 assume !false; 586007#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 586002#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 585991#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 585990#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 585984#L1008 assume !(0 != eval_~tmp~0#1); 585985#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 586354#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 586352#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 586350#L1206-5 assume !(0 == ~T1_E~0); 586348#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 586346#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 586344#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 586341#L1226-3 assume !(0 == ~T5_E~0); 586339#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 586337#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 586335#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 586333#L1246-3 assume !(0 == ~T9_E~0); 586331#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 586328#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 586326#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 586324#L1266-3 assume !(0 == ~E_M~0); 586322#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 586320#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 586318#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 586315#L1286-3 assume !(0 == ~E_4~0); 586313#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 586311#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 586309#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 586307#L1306-3 assume !(0 == ~E_8~0); 586305#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 586302#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 586300#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 586298#L1326-3 assume !(0 == ~E_12~0); 586296#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 586294#L598-42 assume !(1 == ~m_pc~0); 586292#L598-44 is_master_triggered_~__retres1~0#1 := 0; 586289#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 586287#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 586285#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 586283#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 586281#L617-42 assume !(1 == ~t1_pc~0); 586277#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 586274#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 586272#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 586270#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 586267#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 586265#L636-42 assume !(1 == ~t2_pc~0); 578192#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 586261#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 586259#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 586257#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 586255#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 586253#L655-42 assume 1 == ~t3_pc~0; 586250#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 586247#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 586245#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 586243#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 586241#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 586239#L674-42 assume !(1 == ~t4_pc~0); 586236#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 586235#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 586234#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 586233#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 586232#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 586231#L693-42 assume 1 == ~t5_pc~0; 586229#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 586228#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 586227#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 586226#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 586225#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 586224#L712-42 assume !(1 == ~t6_pc~0); 586222#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 586220#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 586219#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 586218#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 586217#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 586216#L731-42 assume 1 == ~t7_pc~0; 586212#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 586210#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 586208#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 586206#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 586204#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 586200#L750-42 assume !(1 == ~t8_pc~0); 586197#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 586195#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 586193#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 586190#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 586188#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 586186#L769-42 assume 1 == ~t9_pc~0; 586184#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 586182#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 586180#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 586178#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 586176#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 586174#L788-42 assume 1 == ~t10_pc~0; 586170#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 586168#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 586166#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 586164#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 586162#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 586160#L807-42 assume !(1 == ~t11_pc~0); 586156#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 586154#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 586152#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 586150#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 586148#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 586146#L826-42 assume 1 == ~t12_pc~0; 586142#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 586140#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 586138#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 586136#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 586134#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 586132#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 506959#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 586126#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 586124#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 586122#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 586120#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 586118#L1369-3 assume !(1 == ~T6_E~0); 586115#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 586113#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 586111#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 586108#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 586106#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 586104#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 586101#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 586099#L1409-3 assume !(1 == ~E_1~0); 586097#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 586095#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 586093#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 560269#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 586089#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 586087#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 586085#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 586083#L1449-3 assume !(1 == ~E_9~0); 586081#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 586079#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 586076#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 566455#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 586070#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 586057#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 586054#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 586052#L1834 assume !(0 == start_simulation_~tmp~3#1); 507009#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 586038#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 586028#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 586027#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 586024#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 586022#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 586020#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 586019#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 586014#L1815-2 [2021-11-19 05:21:04,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:21:04,074 INFO L85 PathProgramCache]: Analyzing trace with hash -607674886, now seen corresponding path program 1 times [2021-11-19 05:21:04,074 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:21:04,074 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [218666470] [2021-11-19 05:21:04,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:21:04,074 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:21:04,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:21:04,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:21:04,123 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:21:04,123 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [218666470] [2021-11-19 05:21:04,124 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [218666470] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:21:04,124 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:21:04,124 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-19 05:21:04,124 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [693849198] [2021-11-19 05:21:04,127 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:21:04,127 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:21:04,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:21:04,128 INFO L85 PathProgramCache]: Analyzing trace with hash -424213728, now seen corresponding path program 1 times [2021-11-19 05:21:04,128 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:21:04,128 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [947712336] [2021-11-19 05:21:04,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:21:04,129 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:21:04,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:21:04,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:21:04,172 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:21:04,172 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [947712336] [2021-11-19 05:21:04,172 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [947712336] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:21:04,173 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:21:04,173 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:21:04,173 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [825569027] [2021-11-19 05:21:04,173 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:21:04,174 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:21:04,174 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:21:04,174 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:21:04,174 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:21:04,175 INFO L87 Difference]: Start difference. First operand 86664 states and 124653 transitions. cyclomatic complexity: 38021 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:21:04,819 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:21:04,819 INFO L93 Difference]: Finished difference Result 166183 states and 238114 transitions. [2021-11-19 05:21:04,819 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:21:04,820 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 166183 states and 238114 transitions. [2021-11-19 05:21:05,950 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 165700 [2021-11-19 05:21:06,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 166183 states to 166183 states and 238114 transitions. [2021-11-19 05:21:06,320 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 166183 [2021-11-19 05:21:06,400 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 166183 [2021-11-19 05:21:06,400 INFO L73 IsDeterministic]: Start isDeterministic. Operand 166183 states and 238114 transitions. [2021-11-19 05:21:06,463 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:21:06,463 INFO L681 BuchiCegarLoop]: Abstraction has 166183 states and 238114 transitions. [2021-11-19 05:21:06,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166183 states and 238114 transitions. [2021-11-19 05:21:07,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166183 to 166055. [2021-11-19 05:21:07,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 166055 states, 166055 states have (on average 1.4331757550209268) internal successors, (237986), 166054 states have internal predecessors, (237986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:21:09,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166055 states to 166055 states and 237986 transitions. [2021-11-19 05:21:09,039 INFO L704 BuchiCegarLoop]: Abstraction has 166055 states and 237986 transitions. [2021-11-19 05:21:09,039 INFO L587 BuchiCegarLoop]: Abstraction has 166055 states and 237986 transitions. [2021-11-19 05:21:09,039 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-19 05:21:09,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 166055 states and 237986 transitions. [2021-11-19 05:21:09,387 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 165572 [2021-11-19 05:21:09,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:21:09,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:21:09,389 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:21:09,390 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:21:09,390 INFO L791 eck$LassoCheckResult]: Stem: 759279#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 759280#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 758681#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 758651#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 758652#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 760067#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 758966#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 758419#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 758420#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 759792#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 759954#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 760585#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 760586#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 759185#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 759186#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 759825#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 759725#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 759726#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 759911#L1206 assume !(0 == ~M_E~0); 759164#L1206-2 assume !(0 == ~T1_E~0); 759165#L1211-1 assume !(0 == ~T2_E~0); 760256#L1216-1 assume !(0 == ~T3_E~0); 758947#L1221-1 assume !(0 == ~T4_E~0); 758948#L1226-1 assume !(0 == ~T5_E~0); 758606#L1231-1 assume !(0 == ~T6_E~0); 758607#L1236-1 assume !(0 == ~T7_E~0); 760308#L1241-1 assume !(0 == ~T8_E~0); 759008#L1246-1 assume !(0 == ~T9_E~0); 759009#L1251-1 assume !(0 == ~T10_E~0); 759244#L1256-1 assume !(0 == ~T11_E~0); 758431#L1261-1 assume !(0 == ~T12_E~0); 758432#L1266-1 assume !(0 == ~E_M~0); 760556#L1271-1 assume !(0 == ~E_1~0); 759939#L1276-1 assume !(0 == ~E_2~0); 759940#L1281-1 assume !(0 == ~E_3~0); 759856#L1286-1 assume !(0 == ~E_4~0); 758847#L1291-1 assume !(0 == ~E_5~0); 758848#L1296-1 assume !(0 == ~E_6~0); 759629#L1301-1 assume !(0 == ~E_7~0); 759630#L1306-1 assume !(0 == ~E_8~0); 760167#L1311-1 assume !(0 == ~E_9~0); 758808#L1316-1 assume !(0 == ~E_10~0); 758809#L1321-1 assume !(0 == ~E_11~0); 759647#L1326-1 assume !(0 == ~E_12~0); 758671#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 758672#L598 assume !(1 == ~m_pc~0); 759409#L598-2 is_master_triggered_~__retres1~0#1 := 0; 759410#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 760280#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 760468#L1497 assume !(0 != activate_threads_~tmp~1#1); 760469#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 760367#L617 assume !(1 == ~t1_pc~0); 759033#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 759034#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 760679#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 760498#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 759744#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 759745#L636 assume !(1 == ~t2_pc~0); 760392#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 759484#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 758828#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 758829#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 759791#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 759378#L655 assume !(1 == ~t3_pc~0); 759379#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 760286#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 758701#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 758702#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 760558#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 760559#L674 assume !(1 == ~t4_pc~0); 760261#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 760262#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 759946#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 758830#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 758831#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 759375#L693 assume !(1 == ~t5_pc~0); 759573#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 759166#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 759167#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 760171#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 759256#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 759189#L712 assume 1 == ~t6_pc~0; 759190#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 759686#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 759687#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 760035#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 759811#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 759805#L731 assume 1 == ~t7_pc~0; 758675#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 758676#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 758872#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 759934#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 760083#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 758785#L750 assume !(1 == ~t8_pc~0); 758462#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 758461#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 758979#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 760187#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 759118#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 759119#L769 assume 1 == ~t9_pc~0; 759740#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 758629#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 758630#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 759457#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 760005#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 760109#L788 assume !(1 == ~t10_pc~0); 759590#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 759591#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 759872#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 759873#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 758781#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 758782#L807 assume 1 == ~t11_pc~0; 760120#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 759607#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 759793#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 760351#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 760674#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 760260#L826 assume !(1 == ~t12_pc~0); 759192#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 759193#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 759820#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 760426#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 759368#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 759265#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 759266#L1344-2 assume !(1 == ~T1_E~0); 759430#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 759636#L1354-1 assume !(1 == ~T3_E~0); 759637#L1359-1 assume !(1 == ~T4_E~0); 760094#L1364-1 assume !(1 == ~T5_E~0); 758891#L1369-1 assume !(1 == ~T6_E~0); 758892#L1374-1 assume !(1 == ~T7_E~0); 759643#L1379-1 assume !(1 == ~T8_E~0); 759644#L1384-1 assume !(1 == ~T9_E~0); 759722#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 760314#L1394-1 assume !(1 == ~T11_E~0); 760315#L1399-1 assume !(1 == ~T12_E~0); 760489#L1404-1 assume !(1 == ~E_M~0); 759012#L1409-1 assume !(1 == ~E_1~0); 759013#L1414-1 assume !(1 == ~E_2~0); 759980#L1419-1 assume !(1 == ~E_3~0); 758642#L1424-1 assume !(1 == ~E_4~0); 758643#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 759654#L1434-1 assume !(1 == ~E_6~0); 760345#L1439-1 assume !(1 == ~E_7~0); 758697#L1444-1 assume !(1 == ~E_8~0); 758698#L1449-1 assume !(1 == ~E_9~0); 759124#L1454-1 assume !(1 == ~E_10~0); 759125#L1459-1 assume !(1 == ~E_11~0); 759764#L1464-1 assume !(1 == ~E_12~0); 759765#L1469-1 assume { :end_inline_reset_delta_events } true; 759826#L1815-2 [2021-11-19 05:21:09,390 INFO L793 eck$LassoCheckResult]: Loop: 759826#L1815-2 assume !false; 838378#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 838372#L1181 assume !false; 838370#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 838362#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 838350#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 838348#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 838344#L1008 assume !(0 != eval_~tmp~0#1); 838345#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 839567#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 839563#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 839557#L1206-5 assume !(0 == ~T1_E~0); 839552#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 839548#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 839544#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 839540#L1226-3 assume !(0 == ~T5_E~0); 839536#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 839531#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 839526#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 839522#L1246-3 assume !(0 == ~T9_E~0); 839518#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 839514#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 839510#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 839504#L1266-3 assume !(0 == ~E_M~0); 839499#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 839495#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 839491#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 839487#L1286-3 assume !(0 == ~E_4~0); 839483#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 839477#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 839472#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 839468#L1306-3 assume !(0 == ~E_8~0); 839464#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 839460#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 839456#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 839450#L1326-3 assume !(0 == ~E_12~0); 839445#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 839441#L598-42 assume !(1 == ~m_pc~0); 839437#L598-44 is_master_triggered_~__retres1~0#1 := 0; 839433#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 839429#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 839423#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 839418#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 839414#L617-42 assume 1 == ~t1_pc~0; 839409#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 839404#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 839399#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 839392#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 839387#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 761110#L636-42 assume !(1 == ~t2_pc~0); 761108#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 761106#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 761104#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 761102#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 761100#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 761098#L655-42 assume !(1 == ~t3_pc~0); 761096#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 761095#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 835854#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 835786#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 835785#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 835784#L674-42 assume !(1 == ~t4_pc~0); 761079#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 761076#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 761072#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 761070#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 761066#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 761063#L693-42 assume !(1 == ~t5_pc~0); 761061#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 761058#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 761056#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 761054#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 761052#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 761049#L712-42 assume 1 == ~t6_pc~0; 761047#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 761044#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 761042#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 761040#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 761038#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 761035#L731-42 assume !(1 == ~t7_pc~0); 761033#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 761030#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 761028#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 761026#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 761024#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 761021#L750-42 assume 1 == ~t8_pc~0; 761019#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 761016#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 761014#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 761012#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 761010#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 761007#L769-42 assume !(1 == ~t9_pc~0); 761005#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 761002#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 761000#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 760998#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 760996#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 760993#L788-42 assume !(1 == ~t10_pc~0); 760991#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 760988#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 760986#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 760984#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 760982#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 760979#L807-42 assume 1 == ~t11_pc~0; 760977#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 760974#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 760972#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 760970#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 760968#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 760965#L826-42 assume !(1 == ~t12_pc~0); 760963#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 760960#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 760958#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 760956#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 760954#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 760951#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 760949#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 760947#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 760945#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 760943#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 760941#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 760938#L1369-3 assume !(1 == ~T6_E~0); 760936#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 760934#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 760932#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 760930#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 760928#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 760925#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 760923#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 760920#L1409-3 assume !(1 == ~E_1~0); 760921#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 760915#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 760912#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 760908#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 760906#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 760904#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 760902#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 760900#L1449-3 assume !(1 == ~E_9~0); 760898#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 760896#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 760894#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 760890#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 760827#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 760801#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 760798#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 760790#L1834 assume !(0 == start_simulation_~tmp~3#1); 760791#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 838402#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 838392#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 838390#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 838388#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 838386#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 838383#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 838381#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 759826#L1815-2 [2021-11-19 05:21:09,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:21:09,391 INFO L85 PathProgramCache]: Analyzing trace with hash 852319035, now seen corresponding path program 1 times [2021-11-19 05:21:09,392 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:21:09,392 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636066700] [2021-11-19 05:21:09,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:21:09,392 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:21:09,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:21:09,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:21:09,465 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:21:09,466 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1636066700] [2021-11-19 05:21:09,466 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1636066700] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:21:09,466 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:21:09,466 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:21:09,466 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1981322985] [2021-11-19 05:21:09,466 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:21:09,467 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:21:09,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:21:09,467 INFO L85 PathProgramCache]: Analyzing trace with hash 1279764000, now seen corresponding path program 1 times [2021-11-19 05:21:09,468 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:21:09,468 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1210250301] [2021-11-19 05:21:09,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:21:09,468 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:21:09,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:21:09,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:21:09,509 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:21:09,509 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1210250301] [2021-11-19 05:21:09,510 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1210250301] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:21:09,510 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:21:09,510 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:21:09,510 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1985004269] [2021-11-19 05:21:09,510 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:21:09,511 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:21:09,511 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:21:09,511 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-19 05:21:09,512 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-19 05:21:09,512 INFO L87 Difference]: Start difference. First operand 166055 states and 237986 transitions. cyclomatic complexity: 71995 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:21:11,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:21:11,539 INFO L93 Difference]: Finished difference Result 402782 states and 573743 transitions. [2021-11-19 05:21:11,540 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-19 05:21:11,540 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 402782 states and 573743 transitions. [2021-11-19 05:21:13,878 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 395708 [2021-11-19 05:21:15,294 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 402782 states to 402782 states and 573743 transitions. [2021-11-19 05:21:15,294 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 402782 [2021-11-19 05:21:15,433 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 402782 [2021-11-19 05:21:15,433 INFO L73 IsDeterministic]: Start isDeterministic. Operand 402782 states and 573743 transitions. [2021-11-19 05:21:15,552 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:21:15,553 INFO L681 BuchiCegarLoop]: Abstraction has 402782 states and 573743 transitions. [2021-11-19 05:21:15,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 402782 states and 573743 transitions. [2021-11-19 05:21:18,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 402782 to 317986. [2021-11-19 05:21:18,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 317986 states, 317986 states have (on average 1.4283993634939902) internal successors, (454211), 317985 states have internal predecessors, (454211), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:21:20,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317986 states to 317986 states and 454211 transitions. [2021-11-19 05:21:20,174 INFO L704 BuchiCegarLoop]: Abstraction has 317986 states and 454211 transitions. [2021-11-19 05:21:20,175 INFO L587 BuchiCegarLoop]: Abstraction has 317986 states and 454211 transitions. [2021-11-19 05:21:20,175 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-19 05:21:20,175 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 317986 states and 454211 transitions. [2021-11-19 05:21:20,872 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 317312 [2021-11-19 05:21:20,873 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:21:20,873 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:21:20,875 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:21:20,876 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:21:20,876 INFO L791 eck$LassoCheckResult]: Stem: 1328101#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1328102#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1327529#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1327502#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1327503#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 1328810#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1327803#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1327266#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1327267#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1328564#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1328713#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1329215#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1329216#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1328012#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1328013#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1328594#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1328507#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1328508#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1328674#L1206 assume !(0 == ~M_E~0); 1327988#L1206-2 assume !(0 == ~T1_E~0); 1327989#L1211-1 assume !(0 == ~T2_E~0); 1328986#L1216-1 assume !(0 == ~T3_E~0); 1327785#L1221-1 assume !(0 == ~T4_E~0); 1327786#L1226-1 assume !(0 == ~T5_E~0); 1327454#L1231-1 assume !(0 == ~T6_E~0); 1327455#L1236-1 assume !(0 == ~T7_E~0); 1329033#L1241-1 assume !(0 == ~T8_E~0); 1327844#L1246-1 assume !(0 == ~T9_E~0); 1327845#L1251-1 assume !(0 == ~T10_E~0); 1328066#L1256-1 assume !(0 == ~T11_E~0); 1327278#L1261-1 assume !(0 == ~T12_E~0); 1327279#L1266-1 assume !(0 == ~E_M~0); 1329192#L1271-1 assume !(0 == ~E_1~0); 1328701#L1276-1 assume !(0 == ~E_2~0); 1328702#L1281-1 assume !(0 == ~E_3~0); 1328624#L1286-1 assume !(0 == ~E_4~0); 1327689#L1291-1 assume !(0 == ~E_5~0); 1327690#L1296-1 assume !(0 == ~E_6~0); 1328418#L1301-1 assume !(0 == ~E_7~0); 1328419#L1306-1 assume !(0 == ~E_8~0); 1328910#L1311-1 assume !(0 == ~E_9~0); 1327651#L1316-1 assume !(0 == ~E_10~0); 1327652#L1321-1 assume !(0 == ~E_11~0); 1328435#L1326-1 assume !(0 == ~E_12~0); 1327519#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1327520#L598 assume !(1 == ~m_pc~0); 1328219#L598-2 is_master_triggered_~__retres1~0#1 := 0; 1328220#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1329005#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1329146#L1497 assume !(0 != activate_threads_~tmp~1#1); 1329147#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1329076#L617 assume !(1 == ~t1_pc~0); 1327866#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1327867#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1329261#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1329159#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 1328525#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1328526#L636 assume !(1 == ~t2_pc~0); 1329097#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1328288#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1327670#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1327671#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 1328563#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1328193#L655 assume !(1 == ~t3_pc~0); 1328194#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1329013#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1327547#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1327548#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 1329196#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1329197#L674 assume !(1 == ~t4_pc~0); 1328991#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1328992#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1328708#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1327674#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 1327675#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1328187#L693 assume !(1 == ~t5_pc~0); 1328368#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1327993#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1327994#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1328912#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 1328078#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1328014#L712 assume !(1 == ~t6_pc~0); 1328015#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1328469#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1328470#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1328784#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 1328582#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1328578#L731 assume 1 == ~t7_pc~0; 1327521#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1327522#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1327713#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1328697#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 1328829#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1327629#L750 assume !(1 == ~t8_pc~0); 1327309#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1327308#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1327814#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1328926#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1327946#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1327947#L769 assume 1 == ~t9_pc~0; 1328523#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1327475#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1327476#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1328262#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 1328757#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1328855#L788 assume !(1 == ~t10_pc~0); 1328383#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1328384#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1328642#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1328643#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 1327627#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1327628#L807 assume 1 == ~t11_pc~0; 1328864#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1328398#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1328565#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1329061#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 1329260#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1328990#L826 assume !(1 == ~t12_pc~0); 1328018#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1328019#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1328589#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1329122#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 1328180#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1328087#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 1328088#L1344-2 assume !(1 == ~T1_E~0); 1328236#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1328426#L1354-1 assume !(1 == ~T3_E~0); 1328427#L1359-1 assume !(1 == ~T4_E~0); 1328842#L1364-1 assume !(1 == ~T5_E~0); 1327730#L1369-1 assume !(1 == ~T6_E~0); 1327731#L1374-1 assume !(1 == ~T7_E~0); 1328433#L1379-1 assume !(1 == ~T8_E~0); 1328434#L1384-1 assume !(1 == ~T9_E~0); 1328506#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1329037#L1394-1 assume !(1 == ~T11_E~0); 1329038#L1399-1 assume !(1 == ~T12_E~0); 1329156#L1404-1 assume !(1 == ~E_M~0); 1327848#L1409-1 assume !(1 == ~E_1~0); 1327849#L1414-1 assume !(1 == ~E_2~0); 1328736#L1419-1 assume !(1 == ~E_3~0); 1327488#L1424-1 assume !(1 == ~E_4~0); 1327489#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1328444#L1434-1 assume !(1 == ~E_6~0); 1329059#L1439-1 assume !(1 == ~E_7~0); 1327543#L1444-1 assume !(1 == ~E_8~0); 1327544#L1449-1 assume !(1 == ~E_9~0); 1327952#L1454-1 assume !(1 == ~E_10~0); 1327953#L1459-1 assume !(1 == ~E_11~0); 1328543#L1464-1 assume !(1 == ~E_12~0); 1328544#L1469-1 assume { :end_inline_reset_delta_events } true; 1611658#L1815-2 [2021-11-19 05:21:20,877 INFO L793 eck$LassoCheckResult]: Loop: 1611658#L1815-2 assume !false; 1611657#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1611652#L1181 assume !false; 1611651#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1611641#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1611629#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1611626#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1611621#L1008 assume !(0 != eval_~tmp~0#1); 1611622#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1643104#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1643101#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1643099#L1206-5 assume !(0 == ~T1_E~0); 1643097#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1643095#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1643093#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1643091#L1226-3 assume !(0 == ~T5_E~0); 1643088#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1327984#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1327985#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1329119#L1246-3 assume !(0 == ~T9_E~0); 1328971#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1328659#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1327637#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1327638#L1266-3 assume !(0 == ~E_M~0); 1327672#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1327673#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1328148#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1328149#L1286-3 assume !(0 == ~E_4~0); 1328733#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1328734#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1329204#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1329153#L1306-3 assume !(0 == ~E_8~0); 1328281#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1328282#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1641897#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1641894#L1326-3 assume !(0 == ~E_12~0); 1641891#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1641888#L598-42 assume !(1 == ~m_pc~0); 1641885#L598-44 is_master_triggered_~__retres1~0#1 := 0; 1641884#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1641883#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1641881#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 1641880#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1641879#L617-42 assume 1 == ~t1_pc~0; 1641877#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1641878#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1641882#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1641869#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1641867#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1611918#L636-42 assume !(1 == ~t2_pc~0); 1611916#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1611914#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1611911#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1611909#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1611907#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1611905#L655-42 assume 1 == ~t3_pc~0; 1611902#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1611900#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1611897#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1611895#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1611893#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1611891#L674-42 assume !(1 == ~t4_pc~0); 1611889#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1611887#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1611884#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1611882#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1611880#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1611878#L693-42 assume 1 == ~t5_pc~0; 1611875#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1611873#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1611870#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1611868#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1611866#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1611864#L712-42 assume !(1 == ~t6_pc~0); 1445244#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1611861#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1611858#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1611856#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1611854#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1611852#L731-42 assume 1 == ~t7_pc~0; 1611849#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1611847#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1611846#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1611845#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1611844#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1611843#L750-42 assume !(1 == ~t8_pc~0); 1611841#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1611840#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1611839#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1611838#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1611837#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1611836#L769-42 assume 1 == ~t9_pc~0; 1611833#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1611831#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1611829#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1611827#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 1611825#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1611823#L788-42 assume 1 == ~t10_pc~0; 1611819#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1611817#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1611815#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1611813#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1611811#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1611809#L807-42 assume !(1 == ~t11_pc~0); 1611806#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1611804#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1611802#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1611800#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1611798#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1611796#L826-42 assume 1 == ~t12_pc~0; 1611792#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1611790#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1611788#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1611786#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1611784#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1611782#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1556657#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1611776#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1611774#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1611772#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1611770#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1611768#L1369-3 assume !(1 == ~T6_E~0); 1611765#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1611763#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1611761#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1611757#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1611755#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1611753#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1611750#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1611748#L1409-3 assume !(1 == ~E_1~0); 1611746#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1611744#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1611742#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1611738#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1611735#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1611733#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1611731#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1611729#L1449-3 assume !(1 == ~E_9~0); 1611727#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1611725#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1611722#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1604680#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1611716#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1611703#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1611700#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1611698#L1834 assume !(0 == start_simulation_~tmp~3#1); 1611695#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1611682#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1611672#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1611671#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1611668#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1611666#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1611664#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1611663#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 1611658#L1815-2 [2021-11-19 05:21:20,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:21:20,878 INFO L85 PathProgramCache]: Analyzing trace with hash 1989947900, now seen corresponding path program 1 times [2021-11-19 05:21:20,878 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:21:20,878 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [361444388] [2021-11-19 05:21:20,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:21:20,878 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:21:20,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:21:20,922 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:21:20,922 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:21:20,922 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [361444388] [2021-11-19 05:21:20,922 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [361444388] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:21:20,922 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:21:20,923 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:21:20,923 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [662861126] [2021-11-19 05:21:20,923 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:21:20,923 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:21:20,924 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:21:20,924 INFO L85 PathProgramCache]: Analyzing trace with hash 992567325, now seen corresponding path program 1 times [2021-11-19 05:21:20,924 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:21:20,924 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122628670] [2021-11-19 05:21:20,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:21:20,925 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:21:20,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:21:20,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:21:20,960 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:21:20,960 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [122628670] [2021-11-19 05:21:20,960 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [122628670] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:21:20,960 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:21:20,960 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:21:20,961 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1454136146] [2021-11-19 05:21:20,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:21:20,961 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:21:20,961 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:21:20,962 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-19 05:21:20,962 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-19 05:21:20,962 INFO L87 Difference]: Start difference. First operand 317986 states and 454211 transitions. cyclomatic complexity: 136289 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:21:24,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:21:24,628 INFO L93 Difference]: Finished difference Result 769285 states and 1092412 transitions. [2021-11-19 05:21:24,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-19 05:21:24,629 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 769285 states and 1092412 transitions.