./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0f8a17c6 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/bin/uautomizer-ZXIjhQolGL/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/bin/uautomizer-ZXIjhQolGL/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/bin/uautomizer-ZXIjhQolGL/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/bin/uautomizer-ZXIjhQolGL/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.15.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/bin/uautomizer-ZXIjhQolGL/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/bin/uautomizer-ZXIjhQolGL --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d827a13f264a8106bf76fcdb72d7bd8ed8c070aef2487e4bd9a858009359b9d5 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-0f8a17c [2021-11-19 04:23:34,824 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-19 04:23:34,828 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-19 04:23:34,899 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-19 04:23:34,900 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-19 04:23:34,905 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-19 04:23:34,908 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-19 04:23:34,913 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-19 04:23:34,916 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-19 04:23:34,923 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-19 04:23:34,925 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-19 04:23:34,927 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-19 04:23:34,928 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-19 04:23:34,931 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-19 04:23:34,935 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-19 04:23:34,944 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-19 04:23:34,947 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-19 04:23:34,948 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-19 04:23:34,951 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-19 04:23:34,961 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-19 04:23:34,964 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-19 04:23:34,966 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-19 04:23:34,970 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-19 04:23:34,971 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-19 04:23:34,981 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-19 04:23:34,982 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-19 04:23:34,983 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-19 04:23:34,985 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-19 04:23:34,986 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-19 04:23:34,988 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-19 04:23:34,989 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-19 04:23:34,990 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-19 04:23:34,992 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-19 04:23:34,994 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-19 04:23:34,995 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-19 04:23:34,996 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-19 04:23:34,997 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-19 04:23:34,997 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-19 04:23:34,997 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-19 04:23:34,998 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-19 04:23:34,999 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-19 04:23:35,000 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/bin/uautomizer-ZXIjhQolGL/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-19 04:23:35,035 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-19 04:23:35,038 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-19 04:23:35,039 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-19 04:23:35,039 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-19 04:23:35,041 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-19 04:23:35,042 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-19 04:23:35,042 INFO L138 SettingsManager]: * Use SBE=true [2021-11-19 04:23:35,042 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-19 04:23:35,043 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-19 04:23:35,043 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-19 04:23:35,044 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-19 04:23:35,045 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-19 04:23:35,045 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-19 04:23:35,046 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-19 04:23:35,046 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-19 04:23:35,046 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-19 04:23:35,046 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-19 04:23:35,047 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-19 04:23:35,047 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-19 04:23:35,047 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-19 04:23:35,048 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-19 04:23:35,048 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-19 04:23:35,048 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-19 04:23:35,048 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-19 04:23:35,049 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-19 04:23:35,049 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-19 04:23:35,049 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-19 04:23:35,050 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-19 04:23:35,050 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-19 04:23:35,050 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-19 04:23:35,050 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-19 04:23:35,051 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-19 04:23:35,052 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-19 04:23:35,053 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/bin/uautomizer-ZXIjhQolGL/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/bin/uautomizer-ZXIjhQolGL Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d827a13f264a8106bf76fcdb72d7bd8ed8c070aef2487e4bd9a858009359b9d5 [2021-11-19 04:23:35,389 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-19 04:23:35,418 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-19 04:23:35,421 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-19 04:23:35,423 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-19 04:23:35,424 INFO L275 PluginConnector]: CDTParser initialized [2021-11-19 04:23:35,426 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/bin/uautomizer-ZXIjhQolGL/../../sv-benchmarks/c/systemc/token_ring.15.cil.c [2021-11-19 04:23:35,529 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/bin/uautomizer-ZXIjhQolGL/data/35c1027bd/9b13fd9d09604c71b888bbd3a9810ce2/FLAG7b24b1055 [2021-11-19 04:23:36,153 INFO L306 CDTParser]: Found 1 translation units. [2021-11-19 04:23:36,154 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/sv-benchmarks/c/systemc/token_ring.15.cil.c [2021-11-19 04:23:36,193 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/bin/uautomizer-ZXIjhQolGL/data/35c1027bd/9b13fd9d09604c71b888bbd3a9810ce2/FLAG7b24b1055 [2021-11-19 04:23:36,420 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/bin/uautomizer-ZXIjhQolGL/data/35c1027bd/9b13fd9d09604c71b888bbd3a9810ce2 [2021-11-19 04:23:36,424 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-19 04:23:36,425 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-19 04:23:36,431 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-19 04:23:36,432 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-19 04:23:36,436 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-19 04:23:36,437 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 04:23:36" (1/1) ... [2021-11-19 04:23:36,440 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@13624787 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 04:23:36, skipping insertion in model container [2021-11-19 04:23:36,441 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 04:23:36" (1/1) ... [2021-11-19 04:23:36,451 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-19 04:23:36,534 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-19 04:23:36,754 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/sv-benchmarks/c/systemc/token_ring.15.cil.c[669,682] [2021-11-19 04:23:36,979 INFO L207 PostProcessor]: Analyzing one entry point: main [2021-11-19 04:23:36,994 INFO L203 MainTranslator]: Completed pre-run [2021-11-19 04:23:37,008 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/sv-benchmarks/c/systemc/token_ring.15.cil.c[669,682] [2021-11-19 04:23:37,098 INFO L207 PostProcessor]: Analyzing one entry point: main [2021-11-19 04:23:37,129 INFO L208 MainTranslator]: Completed translation [2021-11-19 04:23:37,130 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 04:23:37 WrapperNode [2021-11-19 04:23:37,130 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-19 04:23:37,132 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-19 04:23:37,132 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-19 04:23:37,132 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-19 04:23:37,143 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 04:23:37" (1/1) ... [2021-11-19 04:23:37,174 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 04:23:37" (1/1) ... [2021-11-19 04:23:37,358 INFO L137 Inliner]: procedures = 54, calls = 71, calls flagged for inlining = 66, calls inlined = 303, statements flattened = 4663 [2021-11-19 04:23:37,359 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-19 04:23:37,360 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-19 04:23:37,360 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-19 04:23:37,360 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-19 04:23:37,371 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 04:23:37" (1/1) ... [2021-11-19 04:23:37,372 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 04:23:37" (1/1) ... [2021-11-19 04:23:37,390 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 04:23:37" (1/1) ... [2021-11-19 04:23:37,391 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 04:23:37" (1/1) ... [2021-11-19 04:23:37,471 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 04:23:37" (1/1) ... [2021-11-19 04:23:37,571 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 04:23:37" (1/1) ... [2021-11-19 04:23:37,580 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 04:23:37" (1/1) ... [2021-11-19 04:23:37,625 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-19 04:23:37,628 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-19 04:23:37,629 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-19 04:23:37,629 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-19 04:23:37,632 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 04:23:37" (1/1) ... [2021-11-19 04:23:37,647 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-19 04:23:37,664 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/bin/uautomizer-ZXIjhQolGL/z3 [2021-11-19 04:23:37,686 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/bin/uautomizer-ZXIjhQolGL/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-19 04:23:37,707 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_95bb4eae-afb3-41e8-91fe-72c6b60674cc/bin/uautomizer-ZXIjhQolGL/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-19 04:23:37,748 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-11-19 04:23:37,749 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-19 04:23:37,749 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-19 04:23:37,749 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-19 04:23:37,973 INFO L236 CfgBuilder]: Building ICFG [2021-11-19 04:23:37,974 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-11-19 04:23:40,716 INFO L277 CfgBuilder]: Performing block encoding [2021-11-19 04:23:40,762 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-19 04:23:40,762 INFO L301 CfgBuilder]: Removed 16 assume(true) statements. [2021-11-19 04:23:40,770 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 04:23:40 BoogieIcfgContainer [2021-11-19 04:23:40,770 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-19 04:23:40,775 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-19 04:23:40,776 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-19 04:23:40,779 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-19 04:23:40,780 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-19 04:23:40,780 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 04:23:36" (1/3) ... [2021-11-19 04:23:40,781 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@74e1b357 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 04:23:40, skipping insertion in model container [2021-11-19 04:23:40,781 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-19 04:23:40,782 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 04:23:37" (2/3) ... [2021-11-19 04:23:40,782 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@74e1b357 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 04:23:40, skipping insertion in model container [2021-11-19 04:23:40,782 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-19 04:23:40,782 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 04:23:40" (3/3) ... [2021-11-19 04:23:40,784 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.15.cil.c [2021-11-19 04:23:40,837 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-19 04:23:40,837 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-19 04:23:40,838 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-19 04:23:40,838 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-19 04:23:40,838 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-19 04:23:40,838 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-19 04:23:40,838 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-19 04:23:40,838 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-19 04:23:40,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2029 states, 2028 states have (on average 1.4960552268244576) internal successors, (3034), 2028 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:41,005 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1850 [2021-11-19 04:23:41,005 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:41,006 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:41,027 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:41,027 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:41,027 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-19 04:23:41,033 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2029 states, 2028 states have (on average 1.4960552268244576) internal successors, (3034), 2028 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:41,068 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1850 [2021-11-19 04:23:41,068 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:41,068 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:41,075 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:41,075 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:41,087 INFO L791 eck$LassoCheckResult]: Stem: 462#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1953#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 302#L1898true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1870#L902true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1830#L909true assume !(1 == ~m_i~0);~m_st~0 := 2; 1941#L909-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 410#L914-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 434#L919-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1230#L924-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1102#L929-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1858#L934-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1268#L939-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1672#L944-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 305#L949-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1321#L954-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1962#L959-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 631#L964-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1172#L969-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 1763#L974-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1911#L1286true assume 0 == ~M_E~0;~M_E~0 := 1; 1445#L1286-2true assume !(0 == ~T1_E~0); 257#L1291-1true assume !(0 == ~T2_E~0); 1845#L1296-1true assume !(0 == ~T3_E~0); 691#L1301-1true assume !(0 == ~T4_E~0); 1217#L1306-1true assume !(0 == ~T5_E~0); 1185#L1311-1true assume !(0 == ~T6_E~0); 235#L1316-1true assume !(0 == ~T7_E~0); 1681#L1321-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 706#L1326-1true assume !(0 == ~T9_E~0); 141#L1331-1true assume !(0 == ~T10_E~0); 5#L1336-1true assume !(0 == ~T11_E~0); 1065#L1341-1true assume !(0 == ~T12_E~0); 29#L1346-1true assume !(0 == ~T13_E~0); 1489#L1351-1true assume !(0 == ~E_M~0); 205#L1356-1true assume !(0 == ~E_1~0); 1970#L1361-1true assume 0 == ~E_2~0;~E_2~0 := 1; 1648#L1366-1true assume !(0 == ~E_3~0); 230#L1371-1true assume !(0 == ~E_4~0); 1452#L1376-1true assume !(0 == ~E_5~0); 743#L1381-1true assume !(0 == ~E_6~0); 1738#L1386-1true assume !(0 == ~E_7~0); 1882#L1391-1true assume !(0 == ~E_8~0); 1794#L1396-1true assume !(0 == ~E_9~0); 654#L1401-1true assume 0 == ~E_10~0;~E_10~0 := 1; 1280#L1406-1true assume !(0 == ~E_11~0); 901#L1411-1true assume !(0 == ~E_12~0); 1704#L1416-1true assume !(0 == ~E_13~0); 606#L1421-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 499#L635true assume !(1 == ~m_pc~0); 38#L635-2true is_master_triggered_~__retres1~0#1 := 0; 201#L646true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 584#L647true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1305#L1598true assume !(0 != activate_threads_~tmp~1#1); 121#L1598-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 569#L654true assume 1 == ~t1_pc~0; 510#L655true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1728#L665true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1924#L666true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 568#L1606true assume !(0 != activate_threads_~tmp___0~0#1); 818#L1606-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 143#L673true assume 1 == ~t2_pc~0; 1785#L674true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 871#L684true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1857#L685true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1885#L1614true assume !(0 != activate_threads_~tmp___1~0#1); 1985#L1614-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 621#L692true assume !(1 == ~t3_pc~0); 500#L692-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1777#L703true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 412#L704true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 390#L1622true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1710#L1622-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 154#L711true assume 1 == ~t4_pc~0; 421#L712true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1316#L722true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 723#L723true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16#L1630true assume !(0 != activate_threads_~tmp___3~0#1); 1831#L1630-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1828#L730true assume !(1 == ~t5_pc~0); 1966#L730-2true is_transmit5_triggered_~__retres1~5#1 := 0; 101#L741true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 276#L742true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 158#L1638true assume !(0 != activate_threads_~tmp___4~0#1); 342#L1638-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 869#L749true assume 1 == ~t6_pc~0; 218#L750true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 411#L760true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 325#L761true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1448#L1646true assume !(0 != activate_threads_~tmp___5~0#1); 458#L1646-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7#L768true assume !(1 == ~t7_pc~0); 1661#L768-2true is_transmit7_triggered_~__retres1~7#1 := 0; 1384#L779true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 118#L780true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1360#L1654true assume !(0 != activate_threads_~tmp___6~0#1); 780#L1654-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 236#L787true assume 1 == ~t8_pc~0; 1118#L788true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1690#L798true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1373#L799true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1900#L1662true assume !(0 != activate_threads_~tmp___7~0#1); 28#L1662-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1186#L806true assume 1 == ~t9_pc~0; 1131#L807true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45#L817true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 806#L818true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 159#L1670true assume !(0 != activate_threads_~tmp___8~0#1); 1593#L1670-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1110#L825true assume !(1 == ~t10_pc~0); 1378#L825-2true is_transmit10_triggered_~__retres1~10#1 := 0; 736#L836true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 845#L837true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 202#L1678true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2017#L1678-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 541#L844true assume 1 == ~t11_pc~0; 353#L845true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1259#L855true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 588#L856true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1168#L1686true assume !(0 != activate_threads_~tmp___10~0#1); 1097#L1686-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1400#L863true assume !(1 == ~t12_pc~0); 1460#L863-2true is_transmit12_triggered_~__retres1~12#1 := 0; 195#L874true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1526#L875true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1224#L1694true assume !(0 != activate_threads_~tmp___11~0#1); 1617#L1694-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 629#L882true assume 1 == ~t13_pc~0; 900#L883true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1852#L893true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1548#L894true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1175#L1702true assume !(0 != activate_threads_~tmp___12~0#1); 842#L1702-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1574#L1434true assume !(1 == ~M_E~0); 1940#L1434-2true assume !(1 == ~T1_E~0); 1850#L1439-1true assume !(1 == ~T2_E~0); 151#L1444-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 905#L1449-1true assume !(1 == ~T4_E~0); 388#L1454-1true assume !(1 == ~T5_E~0); 1484#L1459-1true assume !(1 == ~T6_E~0); 781#L1464-1true assume !(1 == ~T7_E~0); 851#L1469-1true assume !(1 == ~T8_E~0); 1725#L1474-1true assume !(1 == ~T9_E~0); 607#L1479-1true assume !(1 == ~T10_E~0); 789#L1484-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1248#L1489-1true assume !(1 == ~T12_E~0); 520#L1494-1true assume !(1 == ~T13_E~0); 1836#L1499-1true assume !(1 == ~E_M~0); 645#L1504-1true assume !(1 == ~E_1~0); 1534#L1509-1true assume !(1 == ~E_2~0); 1247#L1514-1true assume !(1 == ~E_3~0); 880#L1519-1true assume !(1 == ~E_4~0); 1954#L1524-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1692#L1529-1true assume !(1 == ~E_6~0); 1767#L1534-1true assume !(1 == ~E_7~0); 53#L1539-1true assume !(1 == ~E_8~0); 267#L1544-1true assume !(1 == ~E_9~0); 1609#L1549-1true assume !(1 == ~E_10~0); 1633#L1554-1true assume !(1 == ~E_11~0); 1606#L1559-1true assume !(1 == ~E_12~0); 1306#L1564-1true assume 1 == ~E_13~0;~E_13~0 := 2; 1673#L1569-1true assume { :end_inline_reset_delta_events } true; 1981#L1935-2true [2021-11-19 04:23:41,092 INFO L793 eck$LassoCheckResult]: Loop: 1981#L1935-2true assume !false; 57#L1936true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1722#L1261true assume false; 814#L1276true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1261#L902-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1349#L1286-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1483#L1286-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 965#L1291-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1861#L1296-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1772#L1301-3true assume !(0 == ~T4_E~0); 1632#L1306-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 579#L1311-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 165#L1316-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 222#L1321-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 667#L1326-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1597#L1331-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 883#L1336-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1519#L1341-3true assume !(0 == ~T12_E~0); 384#L1346-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 376#L1351-3true assume 0 == ~E_M~0;~E_M~0 := 1; 348#L1356-3true assume 0 == ~E_1~0;~E_1~0 := 1; 728#L1361-3true assume 0 == ~E_2~0;~E_2~0 := 1; 757#L1366-3true assume 0 == ~E_3~0;~E_3~0 := 1; 23#L1371-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1276#L1376-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1563#L1381-3true assume !(0 == ~E_6~0); 1068#L1386-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1696#L1391-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1325#L1396-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1977#L1401-3true assume 0 == ~E_10~0;~E_10~0 := 1; 200#L1406-3true assume 0 == ~E_11~0;~E_11~0 := 1; 122#L1411-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1771#L1416-3true assume 0 == ~E_13~0;~E_13~0 := 1; 466#L1421-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66#L635-45true assume !(1 == ~m_pc~0); 758#L635-47true is_master_triggered_~__retres1~0#1 := 0; 843#L646-15true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1406#L647-15true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1096#L1598-45true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 211#L1598-47true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 720#L654-45true assume 1 == ~t1_pc~0; 1750#L655-15true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1038#L665-15true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48#L666-15true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59#L1606-45true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1446#L1606-47true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 505#L673-45true assume !(1 == ~t2_pc~0); 1343#L673-47true is_transmit2_triggered_~__retres1~2#1 := 0; 732#L684-15true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1561#L685-15true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1497#L1614-45true assume !(0 != activate_threads_~tmp___1~0#1); 1171#L1614-47true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 282#L692-45true assume !(1 == ~t3_pc~0); 139#L692-47true is_transmit3_triggered_~__retres1~3#1 := 0; 1201#L703-15true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 786#L704-15true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 309#L1622-45true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 498#L1622-47true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2013#L711-45true assume !(1 == ~t4_pc~0); 627#L711-47true is_transmit4_triggered_~__retres1~4#1 := 0; 1971#L722-15true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 484#L723-15true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1695#L1630-45true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 765#L1630-47true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 224#L730-45true assume 1 == ~t5_pc~0; 144#L731-15true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2031#L741-15true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 359#L742-15true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 888#L1638-45true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 991#L1638-47true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 132#L749-45true assume !(1 == ~t6_pc~0); 1542#L749-47true is_transmit6_triggered_~__retres1~6#1 := 0; 1205#L760-15true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 866#L761-15true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1413#L1646-45true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1014#L1646-47true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 295#L768-45true assume 1 == ~t7_pc~0; 368#L769-15true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1173#L779-15true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 954#L780-15true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1841#L1654-45true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 993#L1654-47true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1898#L787-45true assume !(1 == ~t8_pc~0); 2020#L787-47true is_transmit8_triggered_~__retres1~8#1 := 0; 373#L798-15true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1683#L799-15true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 644#L1662-45true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 887#L1662-47true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1765#L806-45true assume !(1 == ~t9_pc~0); 74#L806-47true is_transmit9_triggered_~__retres1~9#1 := 0; 521#L817-15true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1136#L818-15true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 418#L1670-45true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 361#L1670-47true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1817#L825-45true assume 1 == ~t10_pc~0; 777#L826-15true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1837#L836-15true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 793#L837-15true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 922#L1678-45true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1015#L1678-47true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 171#L844-45true assume !(1 == ~t11_pc~0); 1536#L844-47true is_transmit11_triggered_~__retres1~11#1 := 0; 467#L855-15true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 477#L856-15true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 762#L1686-45true assume !(0 != activate_threads_~tmp___10~0#1); 1330#L1686-47true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 189#L863-45true assume !(1 == ~t12_pc~0); 648#L863-47true is_transmit12_triggered_~__retres1~12#1 := 0; 4#L874-15true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1423#L875-15true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 255#L1694-45true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 769#L1694-47true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1107#L882-45true assume 1 == ~t13_pc~0; 1367#L883-15true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12#L893-15true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 316#L894-15true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1315#L1702-45true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1369#L1702-47true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 855#L1434-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1071#L1434-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1036#L1439-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 149#L1444-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 231#L1449-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1631#L1454-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 848#L1459-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 2008#L1464-3true assume !(1 == ~T7_E~0); 1407#L1469-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1279#L1474-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1639#L1479-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1415#L1484-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 582#L1489-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1167#L1494-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1791#L1499-3true assume 1 == ~E_M~0;~E_M~0 := 2; 795#L1504-3true assume !(1 == ~E_1~0); 1294#L1509-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1358#L1514-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1892#L1519-3true assume 1 == ~E_4~0;~E_4~0 := 2; 522#L1524-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1470#L1529-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1691#L1534-3true assume 1 == ~E_7~0;~E_7~0 := 2; 735#L1539-3true assume 1 == ~E_8~0;~E_8~0 := 2; 369#L1544-3true assume !(1 == ~E_9~0); 1422#L1549-3true assume 1 == ~E_10~0;~E_10~0 := 2; 707#L1554-3true assume 1 == ~E_11~0;~E_11~0 := 2; 173#L1559-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1192#L1564-3true assume 1 == ~E_13~0;~E_13~0 := 2; 933#L1569-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1111#L987-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 427#L1059-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1099#L1060-1true start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 914#L1954true assume !(0 == start_simulation_~tmp~3#1); 1674#L1954-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1194#L987-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 990#L1059-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1381#L1060-2true stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1150#L1909true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1288#L1916true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1398#L1917true start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1793#L1967true assume !(0 != start_simulation_~tmp___0~1#1); 1981#L1935-2true [2021-11-19 04:23:41,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:41,100 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 1 times [2021-11-19 04:23:41,110 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:41,111 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1861317365] [2021-11-19 04:23:41,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:41,112 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:41,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:41,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:41,507 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:41,508 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1861317365] [2021-11-19 04:23:41,509 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1861317365] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:41,509 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:41,509 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:41,511 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1582866945] [2021-11-19 04:23:41,513 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:41,533 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:41,534 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:41,535 INFO L85 PathProgramCache]: Analyzing trace with hash -855363910, now seen corresponding path program 1 times [2021-11-19 04:23:41,535 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:41,535 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [39649766] [2021-11-19 04:23:41,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:41,536 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:41,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:41,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:41,662 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:41,663 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [39649766] [2021-11-19 04:23:41,663 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [39649766] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:41,663 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:41,664 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-19 04:23:41,664 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1879371038] [2021-11-19 04:23:41,664 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:41,666 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:41,668 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:41,709 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-11-19 04:23:41,710 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-11-19 04:23:41,720 INFO L87 Difference]: Start difference. First operand has 2029 states, 2028 states have (on average 1.4960552268244576) internal successors, (3034), 2028 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:41,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:41,891 INFO L93 Difference]: Finished difference Result 2027 states and 2998 transitions. [2021-11-19 04:23:41,896 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-11-19 04:23:41,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2027 states and 2998 transitions. [2021-11-19 04:23:41,937 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:41,988 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2027 states to 2021 states and 2992 transitions. [2021-11-19 04:23:41,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-11-19 04:23:41,995 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-11-19 04:23:41,997 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2992 transitions. [2021-11-19 04:23:42,015 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:42,016 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2992 transitions. [2021-11-19 04:23:42,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2992 transitions. [2021-11-19 04:23:42,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-11-19 04:23:42,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4804552201880257) internal successors, (2992), 2020 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:42,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2992 transitions. [2021-11-19 04:23:42,172 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2992 transitions. [2021-11-19 04:23:42,173 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2992 transitions. [2021-11-19 04:23:42,173 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-19 04:23:42,174 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2992 transitions. [2021-11-19 04:23:42,194 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:42,195 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:42,195 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:42,207 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:42,207 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:42,209 INFO L791 eck$LassoCheckResult]: Stem: 4941#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4942#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 4673#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4674#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6064#L909 assume !(1 == ~m_i~0);~m_st~0 := 2; 6065#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4860#L914-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4861#L919-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4895#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5732#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5733#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5845#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5846#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4679#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4680#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5882#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5204#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5205#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5786#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6052#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 5942#L1286-2 assume !(0 == ~T1_E~0); 4588#L1291-1 assume !(0 == ~T2_E~0); 4589#L1296-1 assume !(0 == ~T3_E~0); 5294#L1301-1 assume !(0 == ~T4_E~0); 5295#L1306-1 assume !(0 == ~T5_E~0); 5795#L1311-1 assume !(0 == ~T6_E~0); 4548#L1316-1 assume !(0 == ~T7_E~0); 4549#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5314#L1326-1 assume !(0 == ~T9_E~0); 4363#L1331-1 assume !(0 == ~T10_E~0); 4069#L1336-1 assume !(0 == ~T11_E~0); 4070#L1341-1 assume !(0 == ~T12_E~0); 4121#L1346-1 assume !(0 == ~T13_E~0); 4122#L1351-1 assume !(0 == ~E_M~0); 4495#L1356-1 assume !(0 == ~E_1~0); 4496#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 6015#L1366-1 assume !(0 == ~E_3~0); 4541#L1371-1 assume !(0 == ~E_4~0); 4542#L1376-1 assume !(0 == ~E_5~0); 5355#L1381-1 assume !(0 == ~E_6~0); 5356#L1386-1 assume !(0 == ~E_7~0); 6043#L1391-1 assume !(0 == ~E_8~0); 6056#L1396-1 assume !(0 == ~E_9~0); 5238#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5239#L1406-1 assume !(0 == ~E_11~0); 5541#L1411-1 assume !(0 == ~E_12~0); 5542#L1416-1 assume !(0 == ~E_13~0); 5162#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5000#L635 assume !(1 == ~m_pc~0); 4139#L635-2 is_master_triggered_~__retres1~0#1 := 0; 4140#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4490#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5126#L1598 assume !(0 != activate_threads_~tmp~1#1); 4318#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4319#L654 assume 1 == ~t1_pc~0; 5024#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5025#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6040#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5106#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 5107#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4366#L673 assume 1 == ~t2_pc~0; 4367#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5511#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5512#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6070#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 6077#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5185#L692 assume !(1 == ~t3_pc~0); 5002#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5003#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4862#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4830#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4831#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4391#L711 assume 1 == ~t4_pc~0; 4392#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4875#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5332#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4094#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 4095#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6063#L730 assume !(1 == ~t5_pc~0); 5445#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4273#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4274#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4401#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 4402#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4744#L749 assume 1 == ~t6_pc~0; 4518#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4278#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4710#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4711#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 4933#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4074#L768 assume !(1 == ~t7_pc~0); 4075#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5379#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4311#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4312#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 5398#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4550#L787 assume 1 == ~t8_pc~0; 4551#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5746#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5910#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5911#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 4119#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4120#L806 assume 1 == ~t9_pc~0; 5757#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4154#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4155#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4403#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 4404#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5740#L825 assume !(1 == ~t10_pc~0); 5741#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 5346#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5347#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4491#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4492#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5075#L844 assume 1 == ~t11_pc~0; 4765#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4766#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5132#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5133#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 5728#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5729#L863 assume !(1 == ~t12_pc~0); 4254#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4253#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4481#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5820#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 5821#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5199#L882 assume 1 == ~t13_pc~0; 5200#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5484#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5985#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5788#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 5471#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5472#L1434 assume !(1 == ~M_E~0); 5993#L1434-2 assume !(1 == ~T1_E~0); 6069#L1439-1 assume !(1 == ~T2_E~0); 4384#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4385#L1449-1 assume !(1 == ~T4_E~0); 4827#L1454-1 assume !(1 == ~T5_E~0); 4828#L1459-1 assume !(1 == ~T6_E~0); 5399#L1464-1 assume !(1 == ~T7_E~0); 5400#L1469-1 assume !(1 == ~T8_E~0); 5485#L1474-1 assume !(1 == ~T9_E~0); 5163#L1479-1 assume !(1 == ~T10_E~0); 5164#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5407#L1489-1 assume !(1 == ~T12_E~0); 5041#L1494-1 assume !(1 == ~T13_E~0); 5042#L1499-1 assume !(1 == ~E_M~0); 5223#L1504-1 assume !(1 == ~E_1~0); 5224#L1509-1 assume !(1 == ~E_2~0); 5837#L1514-1 assume !(1 == ~E_3~0); 5522#L1519-1 assume !(1 == ~E_4~0); 5523#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 6027#L1529-1 assume !(1 == ~E_6~0); 6028#L1534-1 assume !(1 == ~E_7~0); 4174#L1539-1 assume !(1 == ~E_8~0); 4175#L1544-1 assume !(1 == ~E_9~0); 4605#L1549-1 assume !(1 == ~E_10~0); 6005#L1554-1 assume !(1 == ~E_11~0); 6003#L1559-1 assume !(1 == ~E_12~0); 5865#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 5866#L1569-1 assume { :end_inline_reset_delta_events } true; 6021#L1935-2 [2021-11-19 04:23:42,218 INFO L793 eck$LassoCheckResult]: Loop: 6021#L1935-2 assume !false; 4183#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4184#L1261 assume !false; 5411#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5412#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4314#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4484#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4485#L1074 assume !(0 != eval_~tmp~0#1); 4842#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5440#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5841#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5897#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5616#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5617#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6053#L1301-3 assume !(0 == ~T4_E~0); 6011#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5119#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4418#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4419#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4524#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5260#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5525#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5526#L1341-3 assume !(0 == ~T12_E~0); 4820#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4811#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4755#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4756#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5336#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4109#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4110#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5852#L1381-3 assume !(0 == ~E_6~0); 5701#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5702#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5883#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5884#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4489#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4320#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4321#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 4948#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4198#L635-45 assume 1 == ~m_pc~0; 4199#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4993#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5473#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5727#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4507#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4508#L654-45 assume 1 == ~t1_pc~0; 5328#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5676#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4161#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4162#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4187#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5014#L673-45 assume !(1 == ~t2_pc~0); 5015#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 5339#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5340#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5965#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 5785#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4632#L692-45 assume !(1 == ~t3_pc~0); 4358#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 4359#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5403#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4686#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4687#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4999#L711-45 assume 1 == ~t4_pc~0; 5123#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5124#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4976#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4977#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5380#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4531#L730-45 assume 1 == ~t5_pc~0; 4369#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4370#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4779#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4780#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5531#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4342#L749-45 assume !(1 == ~t6_pc~0); 4343#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 5743#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5506#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5507#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5658#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4658#L768-45 assume 1 == ~t7_pc~0; 4659#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4798#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5602#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5603#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5642#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5643#L787-45 assume 1 == ~t8_pc~0; 5811#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4804#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4805#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5221#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5222#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5530#L806-45 assume 1 == ~t9_pc~0; 6006#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4218#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5043#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4871#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4783#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4784#L825-45 assume 1 == ~t10_pc~0; 5395#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5308#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5413#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5414#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5566#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4426#L844-45 assume !(1 == ~t11_pc~0); 4427#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 4949#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4950#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4966#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 5377#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4466#L863-45 assume 1 == ~t12_pc~0; 4467#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4067#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4068#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4583#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4584#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5383#L882-45 assume !(1 == ~t13_pc~0); 4913#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 4086#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4087#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 4695#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 5874#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5490#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5491#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5675#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4380#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4381#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4543#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5480#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5481#L1464-3 assume !(1 == ~T7_E~0); 5927#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5854#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5855#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5929#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5121#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5122#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 5782#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5417#L1504-3 assume !(1 == ~E_1~0); 5418#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5863#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5903#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5044#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5045#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5950#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5345#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4799#L1544-3 assume !(1 == ~E_9~0); 4800#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5315#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4431#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4432#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5581#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5582#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4316#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4881#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 5552#L1954 assume !(0 == start_simulation_~tmp~3#1); 5554#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5804#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4599#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5640#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 5770#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5771#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5861#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 5923#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 6021#L1935-2 [2021-11-19 04:23:42,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:42,221 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 2 times [2021-11-19 04:23:42,221 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:42,223 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240930357] [2021-11-19 04:23:42,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:42,223 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:42,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:42,364 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:42,365 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:42,365 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [240930357] [2021-11-19 04:23:42,365 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [240930357] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:42,366 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:42,366 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:42,366 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1949753175] [2021-11-19 04:23:42,366 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:42,367 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:42,368 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:42,368 INFO L85 PathProgramCache]: Analyzing trace with hash 766080739, now seen corresponding path program 1 times [2021-11-19 04:23:42,369 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:42,369 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533646162] [2021-11-19 04:23:42,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:42,370 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:42,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:42,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:42,604 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:42,604 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1533646162] [2021-11-19 04:23:42,605 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1533646162] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:42,605 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:42,605 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:42,606 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703547600] [2021-11-19 04:23:42,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:42,607 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:42,607 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:42,608 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 04:23:42,608 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 04:23:42,609 INFO L87 Difference]: Start difference. First operand 2021 states and 2992 transitions. cyclomatic complexity: 972 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:42,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:42,766 INFO L93 Difference]: Finished difference Result 2021 states and 2991 transitions. [2021-11-19 04:23:42,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 04:23:42,769 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2991 transitions. [2021-11-19 04:23:42,794 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:42,817 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2991 transitions. [2021-11-19 04:23:42,818 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-11-19 04:23:42,821 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-11-19 04:23:42,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2991 transitions. [2021-11-19 04:23:42,826 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:42,827 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2991 transitions. [2021-11-19 04:23:42,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2991 transitions. [2021-11-19 04:23:42,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-11-19 04:23:42,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.479960415635824) internal successors, (2991), 2020 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:42,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2991 transitions. [2021-11-19 04:23:42,889 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2991 transitions. [2021-11-19 04:23:42,890 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2991 transitions. [2021-11-19 04:23:42,890 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-19 04:23:42,890 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2991 transitions. [2021-11-19 04:23:42,908 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:42,908 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:42,908 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:42,918 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:42,919 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:42,919 INFO L791 eck$LassoCheckResult]: Stem: 8990#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 8991#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8722#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8723#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10113#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 10114#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8909#L914-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8910#L919-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8944#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9781#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9782#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9894#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9895#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8728#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8729#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9931#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9253#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9254#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 9835#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10101#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 9991#L1286-2 assume !(0 == ~T1_E~0); 8637#L1291-1 assume !(0 == ~T2_E~0); 8638#L1296-1 assume !(0 == ~T3_E~0); 9343#L1301-1 assume !(0 == ~T4_E~0); 9344#L1306-1 assume !(0 == ~T5_E~0); 9844#L1311-1 assume !(0 == ~T6_E~0); 8597#L1316-1 assume !(0 == ~T7_E~0); 8598#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9363#L1326-1 assume !(0 == ~T9_E~0); 8412#L1331-1 assume !(0 == ~T10_E~0); 8118#L1336-1 assume !(0 == ~T11_E~0); 8119#L1341-1 assume !(0 == ~T12_E~0); 8170#L1346-1 assume !(0 == ~T13_E~0); 8171#L1351-1 assume !(0 == ~E_M~0); 8544#L1356-1 assume !(0 == ~E_1~0); 8545#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 10064#L1366-1 assume !(0 == ~E_3~0); 8590#L1371-1 assume !(0 == ~E_4~0); 8591#L1376-1 assume !(0 == ~E_5~0); 9404#L1381-1 assume !(0 == ~E_6~0); 9405#L1386-1 assume !(0 == ~E_7~0); 10092#L1391-1 assume !(0 == ~E_8~0); 10105#L1396-1 assume !(0 == ~E_9~0); 9287#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 9288#L1406-1 assume !(0 == ~E_11~0); 9590#L1411-1 assume !(0 == ~E_12~0); 9591#L1416-1 assume !(0 == ~E_13~0); 9211#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9049#L635 assume !(1 == ~m_pc~0); 8188#L635-2 is_master_triggered_~__retres1~0#1 := 0; 8189#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8539#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9175#L1598 assume !(0 != activate_threads_~tmp~1#1); 8367#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8368#L654 assume 1 == ~t1_pc~0; 9073#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9074#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10089#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9155#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 9156#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8415#L673 assume 1 == ~t2_pc~0; 8416#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9560#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9561#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10119#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 10126#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9234#L692 assume !(1 == ~t3_pc~0); 9051#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9052#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8911#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8879#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8880#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8440#L711 assume 1 == ~t4_pc~0; 8441#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8924#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9381#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8143#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 8144#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10112#L730 assume !(1 == ~t5_pc~0); 9494#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8322#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8323#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8450#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 8451#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8793#L749 assume 1 == ~t6_pc~0; 8567#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8327#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8759#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8760#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 8982#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8123#L768 assume !(1 == ~t7_pc~0); 8124#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 9428#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8360#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8361#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 9447#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8599#L787 assume 1 == ~t8_pc~0; 8600#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9795#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9959#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9960#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 8168#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8169#L806 assume 1 == ~t9_pc~0; 9806#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8203#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8204#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8452#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 8453#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9789#L825 assume !(1 == ~t10_pc~0); 9790#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9395#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9396#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8540#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8541#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9124#L844 assume 1 == ~t11_pc~0; 8814#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8815#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9181#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9182#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 9777#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9778#L863 assume !(1 == ~t12_pc~0); 8303#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8302#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8530#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9869#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 9870#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9248#L882 assume 1 == ~t13_pc~0; 9249#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9533#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 10034#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9837#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 9520#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9521#L1434 assume !(1 == ~M_E~0); 10042#L1434-2 assume !(1 == ~T1_E~0); 10118#L1439-1 assume !(1 == ~T2_E~0); 8433#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8434#L1449-1 assume !(1 == ~T4_E~0); 8876#L1454-1 assume !(1 == ~T5_E~0); 8877#L1459-1 assume !(1 == ~T6_E~0); 9448#L1464-1 assume !(1 == ~T7_E~0); 9449#L1469-1 assume !(1 == ~T8_E~0); 9534#L1474-1 assume !(1 == ~T9_E~0); 9212#L1479-1 assume !(1 == ~T10_E~0); 9213#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9456#L1489-1 assume !(1 == ~T12_E~0); 9090#L1494-1 assume !(1 == ~T13_E~0); 9091#L1499-1 assume !(1 == ~E_M~0); 9272#L1504-1 assume !(1 == ~E_1~0); 9273#L1509-1 assume !(1 == ~E_2~0); 9886#L1514-1 assume !(1 == ~E_3~0); 9571#L1519-1 assume !(1 == ~E_4~0); 9572#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 10076#L1529-1 assume !(1 == ~E_6~0); 10077#L1534-1 assume !(1 == ~E_7~0); 8223#L1539-1 assume !(1 == ~E_8~0); 8224#L1544-1 assume !(1 == ~E_9~0); 8654#L1549-1 assume !(1 == ~E_10~0); 10054#L1554-1 assume !(1 == ~E_11~0); 10052#L1559-1 assume !(1 == ~E_12~0); 9914#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 9915#L1569-1 assume { :end_inline_reset_delta_events } true; 10070#L1935-2 [2021-11-19 04:23:42,920 INFO L793 eck$LassoCheckResult]: Loop: 10070#L1935-2 assume !false; 8232#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8233#L1261 assume !false; 9460#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9461#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8363#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8533#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8534#L1074 assume !(0 != eval_~tmp~0#1); 8891#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9489#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9890#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9946#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9665#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9666#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10102#L1301-3 assume !(0 == ~T4_E~0); 10060#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9168#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8467#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8468#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8573#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9309#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9574#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9575#L1341-3 assume !(0 == ~T12_E~0); 8869#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 8860#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8804#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8805#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9385#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8158#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8159#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9901#L1381-3 assume !(0 == ~E_6~0); 9750#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9751#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9932#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9933#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8538#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 8369#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 8370#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 8997#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8247#L635-45 assume 1 == ~m_pc~0; 8248#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9042#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9522#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9776#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8556#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8557#L654-45 assume 1 == ~t1_pc~0; 9377#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9725#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8210#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8211#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8236#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9063#L673-45 assume !(1 == ~t2_pc~0); 9064#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 9388#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9389#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10014#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 9834#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8681#L692-45 assume !(1 == ~t3_pc~0); 8407#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 8408#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9452#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8735#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8736#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9048#L711-45 assume 1 == ~t4_pc~0; 9172#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9173#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9025#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9026#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9429#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8580#L730-45 assume 1 == ~t5_pc~0; 8418#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8419#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8828#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8829#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9580#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8391#L749-45 assume !(1 == ~t6_pc~0); 8392#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 9792#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9555#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9556#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9707#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8707#L768-45 assume 1 == ~t7_pc~0; 8708#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8847#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9651#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9652#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9691#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9692#L787-45 assume 1 == ~t8_pc~0; 9860#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8853#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8854#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9270#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9271#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9579#L806-45 assume 1 == ~t9_pc~0; 10055#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8267#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9092#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8920#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8832#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8833#L825-45 assume 1 == ~t10_pc~0; 9444#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 9357#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9462#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9463#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9615#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8475#L844-45 assume !(1 == ~t11_pc~0); 8476#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 8998#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8999#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9015#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 9426#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8515#L863-45 assume 1 == ~t12_pc~0; 8516#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8116#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8117#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8632#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8633#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9432#L882-45 assume !(1 == ~t13_pc~0); 8962#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 8135#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8136#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 8744#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 9923#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9539#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9540#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9724#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8429#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8430#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8592#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9529#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9530#L1464-3 assume !(1 == ~T7_E~0); 9976#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9903#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9904#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9978#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9170#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 9171#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 9831#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9466#L1504-3 assume !(1 == ~E_1~0); 9467#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9912#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9952#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9093#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9094#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9999#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9394#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8848#L1544-3 assume !(1 == ~E_9~0); 8849#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9364#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8480#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8481#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 9630#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9631#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8365#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8930#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 9601#L1954 assume !(0 == start_simulation_~tmp~3#1); 9603#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9853#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8648#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9689#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 9819#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9820#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9910#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 9972#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 10070#L1935-2 [2021-11-19 04:23:42,924 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:42,925 INFO L85 PathProgramCache]: Analyzing trace with hash 1533490443, now seen corresponding path program 1 times [2021-11-19 04:23:42,925 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:42,925 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [287754728] [2021-11-19 04:23:42,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:42,926 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:42,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:43,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:43,039 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:43,039 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [287754728] [2021-11-19 04:23:43,039 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [287754728] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:43,040 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:43,049 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:43,050 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1118104645] [2021-11-19 04:23:43,050 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:43,050 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:43,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:43,051 INFO L85 PathProgramCache]: Analyzing trace with hash 766080739, now seen corresponding path program 2 times [2021-11-19 04:23:43,052 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:43,052 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315940954] [2021-11-19 04:23:43,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:43,053 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:43,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:43,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:43,134 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:43,135 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [315940954] [2021-11-19 04:23:43,135 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [315940954] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:43,136 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:43,136 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:43,136 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1760435835] [2021-11-19 04:23:43,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:43,137 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:43,138 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:43,138 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 04:23:43,138 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 04:23:43,139 INFO L87 Difference]: Start difference. First operand 2021 states and 2991 transitions. cyclomatic complexity: 971 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:43,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:43,208 INFO L93 Difference]: Finished difference Result 2021 states and 2990 transitions. [2021-11-19 04:23:43,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 04:23:43,210 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2990 transitions. [2021-11-19 04:23:43,234 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:43,256 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2990 transitions. [2021-11-19 04:23:43,256 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-11-19 04:23:43,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-11-19 04:23:43,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2990 transitions. [2021-11-19 04:23:43,264 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:43,265 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2990 transitions. [2021-11-19 04:23:43,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2990 transitions. [2021-11-19 04:23:43,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-11-19 04:23:43,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.479465611083622) internal successors, (2990), 2020 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:43,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2990 transitions. [2021-11-19 04:23:43,410 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2990 transitions. [2021-11-19 04:23:43,410 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2990 transitions. [2021-11-19 04:23:43,410 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-19 04:23:43,411 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2990 transitions. [2021-11-19 04:23:43,427 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:43,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:43,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:43,431 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:43,431 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:43,432 INFO L791 eck$LassoCheckResult]: Stem: 13039#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 13040#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12771#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12772#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14162#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 14163#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12958#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12959#L919-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12993#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13830#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13831#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13943#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13944#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12777#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12778#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13980#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13302#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13303#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13884#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14150#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 14040#L1286-2 assume !(0 == ~T1_E~0); 12686#L1291-1 assume !(0 == ~T2_E~0); 12687#L1296-1 assume !(0 == ~T3_E~0); 13392#L1301-1 assume !(0 == ~T4_E~0); 13393#L1306-1 assume !(0 == ~T5_E~0); 13893#L1311-1 assume !(0 == ~T6_E~0); 12646#L1316-1 assume !(0 == ~T7_E~0); 12647#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13412#L1326-1 assume !(0 == ~T9_E~0); 12461#L1331-1 assume !(0 == ~T10_E~0); 12167#L1336-1 assume !(0 == ~T11_E~0); 12168#L1341-1 assume !(0 == ~T12_E~0); 12219#L1346-1 assume !(0 == ~T13_E~0); 12220#L1351-1 assume !(0 == ~E_M~0); 12593#L1356-1 assume !(0 == ~E_1~0); 12594#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 14113#L1366-1 assume !(0 == ~E_3~0); 12639#L1371-1 assume !(0 == ~E_4~0); 12640#L1376-1 assume !(0 == ~E_5~0); 13453#L1381-1 assume !(0 == ~E_6~0); 13454#L1386-1 assume !(0 == ~E_7~0); 14141#L1391-1 assume !(0 == ~E_8~0); 14154#L1396-1 assume !(0 == ~E_9~0); 13336#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 13337#L1406-1 assume !(0 == ~E_11~0); 13639#L1411-1 assume !(0 == ~E_12~0); 13640#L1416-1 assume !(0 == ~E_13~0); 13260#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13098#L635 assume !(1 == ~m_pc~0); 12237#L635-2 is_master_triggered_~__retres1~0#1 := 0; 12238#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12588#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13224#L1598 assume !(0 != activate_threads_~tmp~1#1); 12416#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12417#L654 assume 1 == ~t1_pc~0; 13122#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13123#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14138#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13204#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 13205#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12464#L673 assume 1 == ~t2_pc~0; 12465#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13609#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13610#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14168#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 14175#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13283#L692 assume !(1 == ~t3_pc~0); 13100#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13101#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12960#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12928#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12929#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12489#L711 assume 1 == ~t4_pc~0; 12490#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12973#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13430#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12192#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 12193#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14161#L730 assume !(1 == ~t5_pc~0); 13543#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12371#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12372#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12499#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 12500#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12842#L749 assume 1 == ~t6_pc~0; 12616#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12376#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12808#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12809#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 13031#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12172#L768 assume !(1 == ~t7_pc~0); 12173#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13477#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12409#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12410#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 13496#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12648#L787 assume 1 == ~t8_pc~0; 12649#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13844#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14008#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14009#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 12217#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12218#L806 assume 1 == ~t9_pc~0; 13855#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12252#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12253#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12501#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 12502#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13838#L825 assume !(1 == ~t10_pc~0); 13839#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 13444#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13445#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12589#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12590#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13173#L844 assume 1 == ~t11_pc~0; 12863#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12864#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13230#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13231#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 13826#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13827#L863 assume !(1 == ~t12_pc~0); 12352#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 12351#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12579#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13918#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 13919#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13297#L882 assume 1 == ~t13_pc~0; 13298#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13582#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 14083#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13886#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 13569#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13570#L1434 assume !(1 == ~M_E~0); 14091#L1434-2 assume !(1 == ~T1_E~0); 14167#L1439-1 assume !(1 == ~T2_E~0); 12482#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12483#L1449-1 assume !(1 == ~T4_E~0); 12925#L1454-1 assume !(1 == ~T5_E~0); 12926#L1459-1 assume !(1 == ~T6_E~0); 13497#L1464-1 assume !(1 == ~T7_E~0); 13498#L1469-1 assume !(1 == ~T8_E~0); 13583#L1474-1 assume !(1 == ~T9_E~0); 13261#L1479-1 assume !(1 == ~T10_E~0); 13262#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13505#L1489-1 assume !(1 == ~T12_E~0); 13139#L1494-1 assume !(1 == ~T13_E~0); 13140#L1499-1 assume !(1 == ~E_M~0); 13321#L1504-1 assume !(1 == ~E_1~0); 13322#L1509-1 assume !(1 == ~E_2~0); 13935#L1514-1 assume !(1 == ~E_3~0); 13620#L1519-1 assume !(1 == ~E_4~0); 13621#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14125#L1529-1 assume !(1 == ~E_6~0); 14126#L1534-1 assume !(1 == ~E_7~0); 12272#L1539-1 assume !(1 == ~E_8~0); 12273#L1544-1 assume !(1 == ~E_9~0); 12703#L1549-1 assume !(1 == ~E_10~0); 14103#L1554-1 assume !(1 == ~E_11~0); 14101#L1559-1 assume !(1 == ~E_12~0); 13963#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 13964#L1569-1 assume { :end_inline_reset_delta_events } true; 14119#L1935-2 [2021-11-19 04:23:43,432 INFO L793 eck$LassoCheckResult]: Loop: 14119#L1935-2 assume !false; 12281#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12282#L1261 assume !false; 13509#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13510#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12412#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12582#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12583#L1074 assume !(0 != eval_~tmp~0#1); 12940#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13538#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13939#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13995#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13714#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13715#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14151#L1301-3 assume !(0 == ~T4_E~0); 14109#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13217#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12516#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12517#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12622#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13358#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13623#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13624#L1341-3 assume !(0 == ~T12_E~0); 12918#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 12909#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12853#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12854#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13434#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12207#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12208#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13950#L1381-3 assume !(0 == ~E_6~0); 13799#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13800#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13981#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 13982#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12587#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12418#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 12419#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13046#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12296#L635-45 assume 1 == ~m_pc~0; 12297#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13091#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13571#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13825#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12605#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12606#L654-45 assume 1 == ~t1_pc~0; 13426#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13774#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12259#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12260#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12285#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13112#L673-45 assume !(1 == ~t2_pc~0); 13113#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 13437#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13438#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14063#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 13883#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12730#L692-45 assume !(1 == ~t3_pc~0); 12456#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 12457#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13501#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12784#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12785#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13097#L711-45 assume 1 == ~t4_pc~0; 13221#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13222#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13074#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13075#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13478#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12629#L730-45 assume 1 == ~t5_pc~0; 12467#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12468#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12877#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12878#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13629#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12440#L749-45 assume !(1 == ~t6_pc~0); 12441#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 13841#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13604#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13605#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13756#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12756#L768-45 assume 1 == ~t7_pc~0; 12757#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12896#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13700#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13701#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13740#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13741#L787-45 assume 1 == ~t8_pc~0; 13909#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12902#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12903#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13319#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13320#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13628#L806-45 assume 1 == ~t9_pc~0; 14104#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12316#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13141#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12969#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12881#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12882#L825-45 assume 1 == ~t10_pc~0; 13493#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13406#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13511#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13512#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13664#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12524#L844-45 assume !(1 == ~t11_pc~0); 12525#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 13047#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13048#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13064#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 13475#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12564#L863-45 assume 1 == ~t12_pc~0; 12565#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12165#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12166#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12681#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 12682#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13481#L882-45 assume !(1 == ~t13_pc~0); 13011#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 12184#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12185#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 12793#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 13972#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13588#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13589#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13773#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12478#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12479#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12641#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13578#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13579#L1464-3 assume !(1 == ~T7_E~0); 14025#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13952#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13953#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14027#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13219#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 13220#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 13880#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13515#L1504-3 assume !(1 == ~E_1~0); 13516#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13961#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14001#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13142#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13143#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14048#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13443#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12897#L1544-3 assume !(1 == ~E_9~0); 12898#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13413#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12529#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12530#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13679#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13680#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12414#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12979#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 13650#L1954 assume !(0 == start_simulation_~tmp~3#1); 13652#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13902#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12697#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 13738#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 13868#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13869#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13959#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14021#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 14119#L1935-2 [2021-11-19 04:23:43,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:43,436 INFO L85 PathProgramCache]: Analyzing trace with hash -992005239, now seen corresponding path program 1 times [2021-11-19 04:23:43,437 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:43,438 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1782851128] [2021-11-19 04:23:43,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:43,439 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:43,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:43,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:43,508 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:43,508 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1782851128] [2021-11-19 04:23:43,509 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1782851128] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:43,510 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:43,511 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:43,515 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1070899794] [2021-11-19 04:23:43,515 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:43,516 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:43,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:43,516 INFO L85 PathProgramCache]: Analyzing trace with hash 766080739, now seen corresponding path program 3 times [2021-11-19 04:23:43,517 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:43,522 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [568394837] [2021-11-19 04:23:43,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:43,524 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:43,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:43,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:43,631 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:43,632 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [568394837] [2021-11-19 04:23:43,632 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [568394837] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:43,632 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:43,633 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:43,633 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [466391356] [2021-11-19 04:23:43,634 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:43,634 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:43,635 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:43,636 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 04:23:43,637 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 04:23:43,637 INFO L87 Difference]: Start difference. First operand 2021 states and 2990 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:43,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:43,698 INFO L93 Difference]: Finished difference Result 2021 states and 2989 transitions. [2021-11-19 04:23:43,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 04:23:43,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2989 transitions. [2021-11-19 04:23:43,723 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:43,741 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2989 transitions. [2021-11-19 04:23:43,741 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-11-19 04:23:43,744 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-11-19 04:23:43,744 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2989 transitions. [2021-11-19 04:23:43,748 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:43,749 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2989 transitions. [2021-11-19 04:23:43,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2989 transitions. [2021-11-19 04:23:43,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-11-19 04:23:43,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.47897080653142) internal successors, (2989), 2020 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:43,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2989 transitions. [2021-11-19 04:23:43,804 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2989 transitions. [2021-11-19 04:23:43,804 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2989 transitions. [2021-11-19 04:23:43,804 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-19 04:23:43,804 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2989 transitions. [2021-11-19 04:23:43,818 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:43,818 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:43,818 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:43,822 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:43,822 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:43,822 INFO L791 eck$LassoCheckResult]: Stem: 17088#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 17089#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 16820#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16821#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18211#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 18212#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17007#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17008#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17042#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 17879#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17880#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17992#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17993#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16826#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16827#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18029#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17351#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17352#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17933#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18199#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 18089#L1286-2 assume !(0 == ~T1_E~0); 16735#L1291-1 assume !(0 == ~T2_E~0); 16736#L1296-1 assume !(0 == ~T3_E~0); 17441#L1301-1 assume !(0 == ~T4_E~0); 17442#L1306-1 assume !(0 == ~T5_E~0); 17942#L1311-1 assume !(0 == ~T6_E~0); 16695#L1316-1 assume !(0 == ~T7_E~0); 16696#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17461#L1326-1 assume !(0 == ~T9_E~0); 16510#L1331-1 assume !(0 == ~T10_E~0); 16216#L1336-1 assume !(0 == ~T11_E~0); 16217#L1341-1 assume !(0 == ~T12_E~0); 16268#L1346-1 assume !(0 == ~T13_E~0); 16269#L1351-1 assume !(0 == ~E_M~0); 16642#L1356-1 assume !(0 == ~E_1~0); 16643#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 18162#L1366-1 assume !(0 == ~E_3~0); 16688#L1371-1 assume !(0 == ~E_4~0); 16689#L1376-1 assume !(0 == ~E_5~0); 17502#L1381-1 assume !(0 == ~E_6~0); 17503#L1386-1 assume !(0 == ~E_7~0); 18190#L1391-1 assume !(0 == ~E_8~0); 18203#L1396-1 assume !(0 == ~E_9~0); 17385#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 17386#L1406-1 assume !(0 == ~E_11~0); 17688#L1411-1 assume !(0 == ~E_12~0); 17689#L1416-1 assume !(0 == ~E_13~0); 17309#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17147#L635 assume !(1 == ~m_pc~0); 16286#L635-2 is_master_triggered_~__retres1~0#1 := 0; 16287#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16637#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17273#L1598 assume !(0 != activate_threads_~tmp~1#1); 16465#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16466#L654 assume 1 == ~t1_pc~0; 17171#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17172#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18187#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17253#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 17254#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16513#L673 assume 1 == ~t2_pc~0; 16514#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17658#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17659#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18217#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 18224#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17332#L692 assume !(1 == ~t3_pc~0); 17149#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17150#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17009#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16977#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16978#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16538#L711 assume 1 == ~t4_pc~0; 16539#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17022#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17479#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16241#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 16242#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18210#L730 assume !(1 == ~t5_pc~0); 17592#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16420#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16421#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16548#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 16549#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16891#L749 assume 1 == ~t6_pc~0; 16665#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16425#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16857#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16858#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 17080#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16221#L768 assume !(1 == ~t7_pc~0); 16222#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 17526#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16458#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16459#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 17545#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16697#L787 assume 1 == ~t8_pc~0; 16698#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17893#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18057#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18058#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 16266#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16267#L806 assume 1 == ~t9_pc~0; 17904#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16301#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16302#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16550#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 16551#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17887#L825 assume !(1 == ~t10_pc~0); 17888#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17493#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17494#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16638#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16639#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17222#L844 assume 1 == ~t11_pc~0; 16912#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16913#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17279#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17280#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 17875#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17876#L863 assume !(1 == ~t12_pc~0); 16401#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 16400#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16628#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17967#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 17968#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 17346#L882 assume 1 == ~t13_pc~0; 17347#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17631#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 18132#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 17935#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 17618#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17619#L1434 assume !(1 == ~M_E~0); 18140#L1434-2 assume !(1 == ~T1_E~0); 18216#L1439-1 assume !(1 == ~T2_E~0); 16531#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16532#L1449-1 assume !(1 == ~T4_E~0); 16974#L1454-1 assume !(1 == ~T5_E~0); 16975#L1459-1 assume !(1 == ~T6_E~0); 17546#L1464-1 assume !(1 == ~T7_E~0); 17547#L1469-1 assume !(1 == ~T8_E~0); 17632#L1474-1 assume !(1 == ~T9_E~0); 17310#L1479-1 assume !(1 == ~T10_E~0); 17311#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17554#L1489-1 assume !(1 == ~T12_E~0); 17188#L1494-1 assume !(1 == ~T13_E~0); 17189#L1499-1 assume !(1 == ~E_M~0); 17370#L1504-1 assume !(1 == ~E_1~0); 17371#L1509-1 assume !(1 == ~E_2~0); 17984#L1514-1 assume !(1 == ~E_3~0); 17669#L1519-1 assume !(1 == ~E_4~0); 17670#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18174#L1529-1 assume !(1 == ~E_6~0); 18175#L1534-1 assume !(1 == ~E_7~0); 16321#L1539-1 assume !(1 == ~E_8~0); 16322#L1544-1 assume !(1 == ~E_9~0); 16752#L1549-1 assume !(1 == ~E_10~0); 18152#L1554-1 assume !(1 == ~E_11~0); 18150#L1559-1 assume !(1 == ~E_12~0); 18012#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 18013#L1569-1 assume { :end_inline_reset_delta_events } true; 18168#L1935-2 [2021-11-19 04:23:43,823 INFO L793 eck$LassoCheckResult]: Loop: 18168#L1935-2 assume !false; 16330#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16331#L1261 assume !false; 17558#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17559#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16461#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16631#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16632#L1074 assume !(0 != eval_~tmp~0#1); 16989#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17587#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17988#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18044#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17763#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17764#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18200#L1301-3 assume !(0 == ~T4_E~0); 18158#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17266#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16565#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16566#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16671#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17407#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17672#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17673#L1341-3 assume !(0 == ~T12_E~0); 16967#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 16958#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16902#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16903#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17483#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16256#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16257#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17999#L1381-3 assume !(0 == ~E_6~0); 17848#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17849#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18030#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18031#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16636#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16467#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 16468#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 17095#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16345#L635-45 assume 1 == ~m_pc~0; 16346#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17140#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17620#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17874#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16654#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16655#L654-45 assume 1 == ~t1_pc~0; 17475#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17823#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16308#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16309#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16334#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17161#L673-45 assume !(1 == ~t2_pc~0); 17162#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 17486#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17487#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18112#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 17932#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16779#L692-45 assume !(1 == ~t3_pc~0); 16505#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 16506#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17550#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16833#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16834#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17146#L711-45 assume 1 == ~t4_pc~0; 17270#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17271#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17123#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17124#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17527#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16678#L730-45 assume 1 == ~t5_pc~0; 16516#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16517#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16926#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16927#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17678#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16489#L749-45 assume !(1 == ~t6_pc~0); 16490#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 17890#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17653#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17654#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17805#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16805#L768-45 assume 1 == ~t7_pc~0; 16806#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16945#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17749#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17750#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17789#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17790#L787-45 assume 1 == ~t8_pc~0; 17958#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16951#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16952#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17368#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17369#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17677#L806-45 assume 1 == ~t9_pc~0; 18153#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16365#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17190#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17018#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16930#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16931#L825-45 assume 1 == ~t10_pc~0; 17542#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17455#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17560#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17561#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17713#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16573#L844-45 assume !(1 == ~t11_pc~0); 16574#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 17096#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17097#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17113#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 17524#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16613#L863-45 assume 1 == ~t12_pc~0; 16614#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 16214#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16215#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 16730#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 16731#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 17530#L882-45 assume !(1 == ~t13_pc~0); 17060#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 16233#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16234#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 16842#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 18021#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17637#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17638#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17822#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16527#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16528#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16690#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17627#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17628#L1464-3 assume !(1 == ~T7_E~0); 18074#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18001#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18002#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18076#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17268#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 17269#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 17929#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17564#L1504-3 assume !(1 == ~E_1~0); 17565#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18010#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18050#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17191#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17192#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18097#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17492#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16946#L1544-3 assume !(1 == ~E_9~0); 16947#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17462#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16578#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16579#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 17728#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17729#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16463#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17028#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 17699#L1954 assume !(0 == start_simulation_~tmp~3#1); 17701#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17951#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16746#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17787#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 17917#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17918#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18008#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 18070#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 18168#L1935-2 [2021-11-19 04:23:43,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:43,824 INFO L85 PathProgramCache]: Analyzing trace with hash -380736181, now seen corresponding path program 1 times [2021-11-19 04:23:43,825 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:43,825 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [457554921] [2021-11-19 04:23:43,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:43,825 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:43,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:43,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:43,889 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:43,889 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [457554921] [2021-11-19 04:23:43,890 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [457554921] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:43,890 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:43,891 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:43,891 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [415207417] [2021-11-19 04:23:43,891 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:43,892 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:43,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:43,892 INFO L85 PathProgramCache]: Analyzing trace with hash 766080739, now seen corresponding path program 4 times [2021-11-19 04:23:43,893 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:43,893 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1512633483] [2021-11-19 04:23:43,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:43,894 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:43,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:43,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:43,963 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:43,964 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1512633483] [2021-11-19 04:23:43,965 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1512633483] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:43,965 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:43,965 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:43,965 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [856925496] [2021-11-19 04:23:43,966 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:43,966 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:43,966 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:43,967 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 04:23:43,967 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 04:23:43,968 INFO L87 Difference]: Start difference. First operand 2021 states and 2989 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:44,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:44,027 INFO L93 Difference]: Finished difference Result 2021 states and 2988 transitions. [2021-11-19 04:23:44,028 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 04:23:44,031 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2988 transitions. [2021-11-19 04:23:44,050 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:44,069 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2988 transitions. [2021-11-19 04:23:44,069 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-11-19 04:23:44,072 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-11-19 04:23:44,072 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2988 transitions. [2021-11-19 04:23:44,076 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:44,077 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2988 transitions. [2021-11-19 04:23:44,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2988 transitions. [2021-11-19 04:23:44,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-11-19 04:23:44,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4784760019792182) internal successors, (2988), 2020 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:44,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2988 transitions. [2021-11-19 04:23:44,136 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2988 transitions. [2021-11-19 04:23:44,136 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2988 transitions. [2021-11-19 04:23:44,136 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-19 04:23:44,136 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2988 transitions. [2021-11-19 04:23:44,148 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:44,148 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:44,149 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:44,154 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:44,154 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:44,155 INFO L791 eck$LassoCheckResult]: Stem: 21137#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 21138#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 20869#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20870#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22260#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 22261#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21056#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21057#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21091#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21928#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21929#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22041#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22042#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20875#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20876#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22078#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21400#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21401#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21982#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22248#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 22138#L1286-2 assume !(0 == ~T1_E~0); 20784#L1291-1 assume !(0 == ~T2_E~0); 20785#L1296-1 assume !(0 == ~T3_E~0); 21490#L1301-1 assume !(0 == ~T4_E~0); 21491#L1306-1 assume !(0 == ~T5_E~0); 21991#L1311-1 assume !(0 == ~T6_E~0); 20744#L1316-1 assume !(0 == ~T7_E~0); 20745#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21510#L1326-1 assume !(0 == ~T9_E~0); 20559#L1331-1 assume !(0 == ~T10_E~0); 20265#L1336-1 assume !(0 == ~T11_E~0); 20266#L1341-1 assume !(0 == ~T12_E~0); 20317#L1346-1 assume !(0 == ~T13_E~0); 20318#L1351-1 assume !(0 == ~E_M~0); 20691#L1356-1 assume !(0 == ~E_1~0); 20692#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 22211#L1366-1 assume !(0 == ~E_3~0); 20737#L1371-1 assume !(0 == ~E_4~0); 20738#L1376-1 assume !(0 == ~E_5~0); 21551#L1381-1 assume !(0 == ~E_6~0); 21552#L1386-1 assume !(0 == ~E_7~0); 22239#L1391-1 assume !(0 == ~E_8~0); 22252#L1396-1 assume !(0 == ~E_9~0); 21434#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 21435#L1406-1 assume !(0 == ~E_11~0); 21737#L1411-1 assume !(0 == ~E_12~0); 21738#L1416-1 assume !(0 == ~E_13~0); 21358#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21196#L635 assume !(1 == ~m_pc~0); 20335#L635-2 is_master_triggered_~__retres1~0#1 := 0; 20336#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20686#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21322#L1598 assume !(0 != activate_threads_~tmp~1#1); 20514#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20515#L654 assume 1 == ~t1_pc~0; 21220#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21221#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22236#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21302#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 21303#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20562#L673 assume 1 == ~t2_pc~0; 20563#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21707#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21708#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22266#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 22273#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21381#L692 assume !(1 == ~t3_pc~0); 21198#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21199#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21058#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21026#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21027#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20587#L711 assume 1 == ~t4_pc~0; 20588#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21071#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21528#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20290#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 20291#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22259#L730 assume !(1 == ~t5_pc~0); 21641#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20469#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20470#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20597#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 20598#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20940#L749 assume 1 == ~t6_pc~0; 20714#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20474#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20906#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20907#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 21129#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20270#L768 assume !(1 == ~t7_pc~0); 20271#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 21575#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20507#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20508#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 21594#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20746#L787 assume 1 == ~t8_pc~0; 20747#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21942#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22106#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22107#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 20315#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20316#L806 assume 1 == ~t9_pc~0; 21953#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20350#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20351#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20599#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 20600#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21936#L825 assume !(1 == ~t10_pc~0); 21937#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21542#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21543#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20687#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20688#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21271#L844 assume 1 == ~t11_pc~0; 20961#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20962#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21328#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21329#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 21924#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21925#L863 assume !(1 == ~t12_pc~0); 20450#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 20449#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20677#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22016#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 22017#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21395#L882 assume 1 == ~t13_pc~0; 21396#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21680#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 22181#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 21984#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 21667#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21668#L1434 assume !(1 == ~M_E~0); 22189#L1434-2 assume !(1 == ~T1_E~0); 22265#L1439-1 assume !(1 == ~T2_E~0); 20580#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20581#L1449-1 assume !(1 == ~T4_E~0); 21023#L1454-1 assume !(1 == ~T5_E~0); 21024#L1459-1 assume !(1 == ~T6_E~0); 21595#L1464-1 assume !(1 == ~T7_E~0); 21596#L1469-1 assume !(1 == ~T8_E~0); 21681#L1474-1 assume !(1 == ~T9_E~0); 21359#L1479-1 assume !(1 == ~T10_E~0); 21360#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21603#L1489-1 assume !(1 == ~T12_E~0); 21237#L1494-1 assume !(1 == ~T13_E~0); 21238#L1499-1 assume !(1 == ~E_M~0); 21419#L1504-1 assume !(1 == ~E_1~0); 21420#L1509-1 assume !(1 == ~E_2~0); 22033#L1514-1 assume !(1 == ~E_3~0); 21718#L1519-1 assume !(1 == ~E_4~0); 21719#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22223#L1529-1 assume !(1 == ~E_6~0); 22224#L1534-1 assume !(1 == ~E_7~0); 20370#L1539-1 assume !(1 == ~E_8~0); 20371#L1544-1 assume !(1 == ~E_9~0); 20801#L1549-1 assume !(1 == ~E_10~0); 22201#L1554-1 assume !(1 == ~E_11~0); 22199#L1559-1 assume !(1 == ~E_12~0); 22061#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 22062#L1569-1 assume { :end_inline_reset_delta_events } true; 22217#L1935-2 [2021-11-19 04:23:44,156 INFO L793 eck$LassoCheckResult]: Loop: 22217#L1935-2 assume !false; 20379#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20380#L1261 assume !false; 21607#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21608#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20510#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20680#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 20681#L1074 assume !(0 != eval_~tmp~0#1); 21038#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21636#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22037#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22093#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21812#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21813#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22249#L1301-3 assume !(0 == ~T4_E~0); 22207#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21315#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20614#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20615#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20720#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21456#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21721#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21722#L1341-3 assume !(0 == ~T12_E~0); 21016#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21007#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20951#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20952#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21532#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20305#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20306#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22048#L1381-3 assume !(0 == ~E_6~0); 21897#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21898#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22079#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22080#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20685#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20516#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 20517#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 21144#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20394#L635-45 assume 1 == ~m_pc~0; 20395#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21189#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21669#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21923#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20703#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20704#L654-45 assume 1 == ~t1_pc~0; 21524#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21872#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20357#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20358#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20383#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21210#L673-45 assume !(1 == ~t2_pc~0); 21211#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 21535#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21536#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22161#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 21981#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20828#L692-45 assume !(1 == ~t3_pc~0); 20554#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 20555#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21599#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20882#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20883#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21195#L711-45 assume 1 == ~t4_pc~0; 21319#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21320#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21172#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21173#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21576#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20727#L730-45 assume 1 == ~t5_pc~0; 20565#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20566#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20975#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20976#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21727#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20538#L749-45 assume !(1 == ~t6_pc~0); 20539#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 21939#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21702#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21703#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21854#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20854#L768-45 assume 1 == ~t7_pc~0; 20855#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20994#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21798#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21799#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21838#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21839#L787-45 assume 1 == ~t8_pc~0; 22007#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21000#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21001#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21417#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21418#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21726#L806-45 assume 1 == ~t9_pc~0; 22202#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20414#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21239#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21067#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20979#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20980#L825-45 assume 1 == ~t10_pc~0; 21591#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21504#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21609#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21610#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21762#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20622#L844-45 assume 1 == ~t11_pc~0; 20624#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21145#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21146#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21162#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 21573#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20662#L863-45 assume 1 == ~t12_pc~0; 20663#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20263#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20264#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 20779#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20780#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21579#L882-45 assume !(1 == ~t13_pc~0); 21109#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 20282#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 20283#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 20891#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 22070#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21686#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21687#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21871#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20576#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20577#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20739#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21676#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21677#L1464-3 assume !(1 == ~T7_E~0); 22123#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22050#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22051#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22125#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21317#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 21318#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 21978#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21613#L1504-3 assume !(1 == ~E_1~0); 21614#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22059#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22099#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21240#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21241#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22146#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21541#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20995#L1544-3 assume !(1 == ~E_9~0); 20996#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 21511#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20627#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20628#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 21777#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21778#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20512#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21077#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 21748#L1954 assume !(0 == start_simulation_~tmp~3#1); 21750#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 22000#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20795#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21836#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 21966#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21967#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22057#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22119#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 22217#L1935-2 [2021-11-19 04:23:44,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:44,157 INFO L85 PathProgramCache]: Analyzing trace with hash 1024455497, now seen corresponding path program 1 times [2021-11-19 04:23:44,157 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:44,158 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640452467] [2021-11-19 04:23:44,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:44,158 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:44,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:44,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:44,197 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:44,197 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [640452467] [2021-11-19 04:23:44,197 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [640452467] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:44,197 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:44,198 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:44,198 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [744279254] [2021-11-19 04:23:44,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:44,199 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:44,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:44,202 INFO L85 PathProgramCache]: Analyzing trace with hash 1797411554, now seen corresponding path program 1 times [2021-11-19 04:23:44,202 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:44,207 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1757009629] [2021-11-19 04:23:44,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:44,208 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:44,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:44,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:44,267 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:44,267 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1757009629] [2021-11-19 04:23:44,270 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1757009629] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:44,270 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:44,270 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:44,270 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [639567579] [2021-11-19 04:23:44,271 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:44,272 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:44,272 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:44,273 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 04:23:44,273 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 04:23:44,273 INFO L87 Difference]: Start difference. First operand 2021 states and 2988 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:44,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:44,331 INFO L93 Difference]: Finished difference Result 2021 states and 2987 transitions. [2021-11-19 04:23:44,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 04:23:44,333 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2987 transitions. [2021-11-19 04:23:44,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:44,366 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2987 transitions. [2021-11-19 04:23:44,366 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-11-19 04:23:44,369 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-11-19 04:23:44,369 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2987 transitions. [2021-11-19 04:23:44,373 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:44,373 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2987 transitions. [2021-11-19 04:23:44,378 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2987 transitions. [2021-11-19 04:23:44,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-11-19 04:23:44,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4779811974270163) internal successors, (2987), 2020 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:44,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2987 transitions. [2021-11-19 04:23:44,428 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2987 transitions. [2021-11-19 04:23:44,428 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2987 transitions. [2021-11-19 04:23:44,428 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-19 04:23:44,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2987 transitions. [2021-11-19 04:23:44,439 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:44,440 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:44,440 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:44,443 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:44,444 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:44,444 INFO L791 eck$LassoCheckResult]: Stem: 25186#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 25187#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 24918#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24919#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26309#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 26310#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25105#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25106#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25140#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25977#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25978#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 26090#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26091#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24924#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24925#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26127#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25449#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25450#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 26031#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26297#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 26187#L1286-2 assume !(0 == ~T1_E~0); 24833#L1291-1 assume !(0 == ~T2_E~0); 24834#L1296-1 assume !(0 == ~T3_E~0); 25539#L1301-1 assume !(0 == ~T4_E~0); 25540#L1306-1 assume !(0 == ~T5_E~0); 26040#L1311-1 assume !(0 == ~T6_E~0); 24793#L1316-1 assume !(0 == ~T7_E~0); 24794#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25559#L1326-1 assume !(0 == ~T9_E~0); 24608#L1331-1 assume !(0 == ~T10_E~0); 24314#L1336-1 assume !(0 == ~T11_E~0); 24315#L1341-1 assume !(0 == ~T12_E~0); 24366#L1346-1 assume !(0 == ~T13_E~0); 24367#L1351-1 assume !(0 == ~E_M~0); 24740#L1356-1 assume !(0 == ~E_1~0); 24741#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 26260#L1366-1 assume !(0 == ~E_3~0); 24786#L1371-1 assume !(0 == ~E_4~0); 24787#L1376-1 assume !(0 == ~E_5~0); 25600#L1381-1 assume !(0 == ~E_6~0); 25601#L1386-1 assume !(0 == ~E_7~0); 26288#L1391-1 assume !(0 == ~E_8~0); 26301#L1396-1 assume !(0 == ~E_9~0); 25483#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 25484#L1406-1 assume !(0 == ~E_11~0); 25786#L1411-1 assume !(0 == ~E_12~0); 25787#L1416-1 assume !(0 == ~E_13~0); 25407#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25245#L635 assume !(1 == ~m_pc~0); 24384#L635-2 is_master_triggered_~__retres1~0#1 := 0; 24385#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24735#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25371#L1598 assume !(0 != activate_threads_~tmp~1#1); 24563#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24564#L654 assume 1 == ~t1_pc~0; 25269#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25270#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26285#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25351#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 25352#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24611#L673 assume 1 == ~t2_pc~0; 24612#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25756#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25757#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26315#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 26322#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25430#L692 assume !(1 == ~t3_pc~0); 25247#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25248#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25107#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25075#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25076#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24636#L711 assume 1 == ~t4_pc~0; 24637#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25120#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25577#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24339#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 24340#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26308#L730 assume !(1 == ~t5_pc~0); 25690#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 24518#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24519#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24646#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 24647#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24989#L749 assume 1 == ~t6_pc~0; 24763#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24523#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24955#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24956#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 25178#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24319#L768 assume !(1 == ~t7_pc~0); 24320#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 25624#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24556#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24557#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 25643#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24795#L787 assume 1 == ~t8_pc~0; 24796#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25991#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26155#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26156#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 24364#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24365#L806 assume 1 == ~t9_pc~0; 26002#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24399#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24400#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24648#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 24649#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25985#L825 assume !(1 == ~t10_pc~0); 25986#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25591#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25592#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24736#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24737#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25320#L844 assume 1 == ~t11_pc~0; 25010#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25011#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25377#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25378#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 25973#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25974#L863 assume !(1 == ~t12_pc~0); 24499#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 24498#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24726#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26065#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 26066#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 25444#L882 assume 1 == ~t13_pc~0; 25445#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25729#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 26230#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 26033#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 25716#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25717#L1434 assume !(1 == ~M_E~0); 26238#L1434-2 assume !(1 == ~T1_E~0); 26314#L1439-1 assume !(1 == ~T2_E~0); 24629#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24630#L1449-1 assume !(1 == ~T4_E~0); 25072#L1454-1 assume !(1 == ~T5_E~0); 25073#L1459-1 assume !(1 == ~T6_E~0); 25644#L1464-1 assume !(1 == ~T7_E~0); 25645#L1469-1 assume !(1 == ~T8_E~0); 25730#L1474-1 assume !(1 == ~T9_E~0); 25408#L1479-1 assume !(1 == ~T10_E~0); 25409#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25652#L1489-1 assume !(1 == ~T12_E~0); 25286#L1494-1 assume !(1 == ~T13_E~0); 25287#L1499-1 assume !(1 == ~E_M~0); 25468#L1504-1 assume !(1 == ~E_1~0); 25469#L1509-1 assume !(1 == ~E_2~0); 26082#L1514-1 assume !(1 == ~E_3~0); 25767#L1519-1 assume !(1 == ~E_4~0); 25768#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26272#L1529-1 assume !(1 == ~E_6~0); 26273#L1534-1 assume !(1 == ~E_7~0); 24419#L1539-1 assume !(1 == ~E_8~0); 24420#L1544-1 assume !(1 == ~E_9~0); 24850#L1549-1 assume !(1 == ~E_10~0); 26250#L1554-1 assume !(1 == ~E_11~0); 26248#L1559-1 assume !(1 == ~E_12~0); 26110#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 26111#L1569-1 assume { :end_inline_reset_delta_events } true; 26266#L1935-2 [2021-11-19 04:23:44,445 INFO L793 eck$LassoCheckResult]: Loop: 26266#L1935-2 assume !false; 24428#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24429#L1261 assume !false; 25656#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25657#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24559#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24729#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 24730#L1074 assume !(0 != eval_~tmp~0#1); 25087#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25685#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26086#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26142#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25861#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25862#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26298#L1301-3 assume !(0 == ~T4_E~0); 26256#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25364#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24663#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24664#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24769#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25505#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25770#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25771#L1341-3 assume !(0 == ~T12_E~0); 25065#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25056#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25000#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25001#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25581#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24354#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24355#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26097#L1381-3 assume !(0 == ~E_6~0); 25946#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25947#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26128#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26129#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24734#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24565#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 24566#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 25193#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24443#L635-45 assume 1 == ~m_pc~0; 24444#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25238#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25718#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25972#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24752#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24753#L654-45 assume 1 == ~t1_pc~0; 25573#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25921#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24406#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24407#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24432#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25259#L673-45 assume !(1 == ~t2_pc~0); 25260#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 25584#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25585#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26210#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 26030#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24877#L692-45 assume !(1 == ~t3_pc~0); 24603#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 24604#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25648#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24931#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24932#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25244#L711-45 assume 1 == ~t4_pc~0; 25368#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25369#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25221#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25222#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25625#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24776#L730-45 assume 1 == ~t5_pc~0; 24614#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24615#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25024#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25025#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25776#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24587#L749-45 assume !(1 == ~t6_pc~0); 24588#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 25988#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25751#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25752#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25903#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24903#L768-45 assume 1 == ~t7_pc~0; 24904#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25043#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25847#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25848#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25887#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25888#L787-45 assume 1 == ~t8_pc~0; 26056#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25049#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25050#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25466#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25467#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25775#L806-45 assume 1 == ~t9_pc~0; 26251#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24463#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25288#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25116#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25028#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25029#L825-45 assume !(1 == ~t10_pc~0); 25552#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 25553#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25658#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25659#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25811#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24671#L844-45 assume !(1 == ~t11_pc~0); 24672#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 25194#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25195#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25211#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 25622#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24711#L863-45 assume 1 == ~t12_pc~0; 24712#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24312#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24313#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 24828#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24829#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 25628#L882-45 assume !(1 == ~t13_pc~0); 25158#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 24331#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 24332#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 24940#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 26119#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25735#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25736#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25920#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24625#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24626#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24788#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25725#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25726#L1464-3 assume !(1 == ~T7_E~0); 26172#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26099#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26100#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26174#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25366#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25367#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 26027#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25662#L1504-3 assume !(1 == ~E_1~0); 25663#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26108#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26148#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25289#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25290#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26195#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25590#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25044#L1544-3 assume !(1 == ~E_9~0); 25045#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25560#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24676#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24677#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 25826#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25827#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24561#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 25126#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 25797#L1954 assume !(0 == start_simulation_~tmp~3#1); 25799#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 26049#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24844#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 25885#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 26015#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26016#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26106#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 26168#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 26266#L1935-2 [2021-11-19 04:23:44,446 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:44,446 INFO L85 PathProgramCache]: Analyzing trace with hash -869878389, now seen corresponding path program 1 times [2021-11-19 04:23:44,446 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:44,446 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175018889] [2021-11-19 04:23:44,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:44,447 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:44,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:44,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:44,487 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:44,487 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1175018889] [2021-11-19 04:23:44,487 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1175018889] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:44,488 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:44,488 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:44,488 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1081202659] [2021-11-19 04:23:44,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:44,489 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:44,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:44,490 INFO L85 PathProgramCache]: Analyzing trace with hash 1143723556, now seen corresponding path program 1 times [2021-11-19 04:23:44,490 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:44,490 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430058262] [2021-11-19 04:23:44,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:44,490 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:44,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:44,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:44,572 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:44,572 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [430058262] [2021-11-19 04:23:44,572 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [430058262] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:44,572 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:44,573 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:44,573 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1076677185] [2021-11-19 04:23:44,573 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:44,573 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:44,574 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:44,574 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 04:23:44,574 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 04:23:44,575 INFO L87 Difference]: Start difference. First operand 2021 states and 2987 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:44,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:44,631 INFO L93 Difference]: Finished difference Result 2021 states and 2986 transitions. [2021-11-19 04:23:44,631 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 04:23:44,633 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2986 transitions. [2021-11-19 04:23:44,647 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:44,664 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2986 transitions. [2021-11-19 04:23:44,665 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-11-19 04:23:44,667 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-11-19 04:23:44,667 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2986 transitions. [2021-11-19 04:23:44,671 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:44,672 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2986 transitions. [2021-11-19 04:23:44,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2986 transitions. [2021-11-19 04:23:44,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-11-19 04:23:44,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4774863928748145) internal successors, (2986), 2020 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:44,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2986 transitions. [2021-11-19 04:23:44,765 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2986 transitions. [2021-11-19 04:23:44,765 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2986 transitions. [2021-11-19 04:23:44,765 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-19 04:23:44,765 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2986 transitions. [2021-11-19 04:23:44,775 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:44,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:44,775 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:44,778 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:44,778 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:44,779 INFO L791 eck$LassoCheckResult]: Stem: 29235#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 29236#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 28967#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28968#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30358#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 30359#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29154#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29155#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29189#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30026#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30027#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30139#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 30140#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 28973#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28974#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 30176#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29498#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29499#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 30080#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30346#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 30236#L1286-2 assume !(0 == ~T1_E~0); 28882#L1291-1 assume !(0 == ~T2_E~0); 28883#L1296-1 assume !(0 == ~T3_E~0); 29588#L1301-1 assume !(0 == ~T4_E~0); 29589#L1306-1 assume !(0 == ~T5_E~0); 30089#L1311-1 assume !(0 == ~T6_E~0); 28842#L1316-1 assume !(0 == ~T7_E~0); 28843#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29608#L1326-1 assume !(0 == ~T9_E~0); 28657#L1331-1 assume !(0 == ~T10_E~0); 28363#L1336-1 assume !(0 == ~T11_E~0); 28364#L1341-1 assume !(0 == ~T12_E~0); 28415#L1346-1 assume !(0 == ~T13_E~0); 28416#L1351-1 assume !(0 == ~E_M~0); 28789#L1356-1 assume !(0 == ~E_1~0); 28790#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 30309#L1366-1 assume !(0 == ~E_3~0); 28835#L1371-1 assume !(0 == ~E_4~0); 28836#L1376-1 assume !(0 == ~E_5~0); 29649#L1381-1 assume !(0 == ~E_6~0); 29650#L1386-1 assume !(0 == ~E_7~0); 30337#L1391-1 assume !(0 == ~E_8~0); 30350#L1396-1 assume !(0 == ~E_9~0); 29532#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 29533#L1406-1 assume !(0 == ~E_11~0); 29835#L1411-1 assume !(0 == ~E_12~0); 29836#L1416-1 assume !(0 == ~E_13~0); 29456#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29294#L635 assume !(1 == ~m_pc~0); 28433#L635-2 is_master_triggered_~__retres1~0#1 := 0; 28434#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28784#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29420#L1598 assume !(0 != activate_threads_~tmp~1#1); 28612#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28613#L654 assume 1 == ~t1_pc~0; 29318#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29319#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30334#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29400#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 29401#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28660#L673 assume 1 == ~t2_pc~0; 28661#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29805#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29806#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30364#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 30371#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29479#L692 assume !(1 == ~t3_pc~0); 29296#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29297#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29156#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29124#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29125#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28685#L711 assume 1 == ~t4_pc~0; 28686#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29169#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29626#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28388#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 28389#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30357#L730 assume !(1 == ~t5_pc~0); 29739#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28567#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28568#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28695#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 28696#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29038#L749 assume 1 == ~t6_pc~0; 28812#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28572#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29004#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29005#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 29227#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28368#L768 assume !(1 == ~t7_pc~0); 28369#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 29673#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28605#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28606#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 29692#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28844#L787 assume 1 == ~t8_pc~0; 28845#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30040#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30204#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30205#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 28413#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28414#L806 assume 1 == ~t9_pc~0; 30051#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28448#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28449#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28697#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 28698#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30034#L825 assume !(1 == ~t10_pc~0); 30035#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29640#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29641#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28785#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28786#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29369#L844 assume 1 == ~t11_pc~0; 29059#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29060#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29426#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29427#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 30022#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30023#L863 assume !(1 == ~t12_pc~0); 28548#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 28547#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28775#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30114#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 30115#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29493#L882 assume 1 == ~t13_pc~0; 29494#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29778#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30279#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30082#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 29765#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29766#L1434 assume !(1 == ~M_E~0); 30287#L1434-2 assume !(1 == ~T1_E~0); 30363#L1439-1 assume !(1 == ~T2_E~0); 28678#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28679#L1449-1 assume !(1 == ~T4_E~0); 29121#L1454-1 assume !(1 == ~T5_E~0); 29122#L1459-1 assume !(1 == ~T6_E~0); 29693#L1464-1 assume !(1 == ~T7_E~0); 29694#L1469-1 assume !(1 == ~T8_E~0); 29779#L1474-1 assume !(1 == ~T9_E~0); 29457#L1479-1 assume !(1 == ~T10_E~0); 29458#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29701#L1489-1 assume !(1 == ~T12_E~0); 29335#L1494-1 assume !(1 == ~T13_E~0); 29336#L1499-1 assume !(1 == ~E_M~0); 29517#L1504-1 assume !(1 == ~E_1~0); 29518#L1509-1 assume !(1 == ~E_2~0); 30131#L1514-1 assume !(1 == ~E_3~0); 29816#L1519-1 assume !(1 == ~E_4~0); 29817#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30321#L1529-1 assume !(1 == ~E_6~0); 30322#L1534-1 assume !(1 == ~E_7~0); 28468#L1539-1 assume !(1 == ~E_8~0); 28469#L1544-1 assume !(1 == ~E_9~0); 28899#L1549-1 assume !(1 == ~E_10~0); 30299#L1554-1 assume !(1 == ~E_11~0); 30297#L1559-1 assume !(1 == ~E_12~0); 30159#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 30160#L1569-1 assume { :end_inline_reset_delta_events } true; 30315#L1935-2 [2021-11-19 04:23:44,780 INFO L793 eck$LassoCheckResult]: Loop: 30315#L1935-2 assume !false; 28477#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28478#L1261 assume !false; 29705#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29706#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28608#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28778#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 28779#L1074 assume !(0 != eval_~tmp~0#1); 29136#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29734#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30135#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30191#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29910#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29911#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30347#L1301-3 assume !(0 == ~T4_E~0); 30305#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29413#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28712#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28713#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28818#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29554#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29819#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29820#L1341-3 assume !(0 == ~T12_E~0); 29114#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29105#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29049#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29050#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29630#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28403#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28404#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30146#L1381-3 assume !(0 == ~E_6~0); 29995#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29996#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30177#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 30178#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28783#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28614#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 28615#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 29242#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28492#L635-45 assume 1 == ~m_pc~0; 28493#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29287#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29767#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30021#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28801#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28802#L654-45 assume 1 == ~t1_pc~0; 29622#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29970#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28455#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28456#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28481#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29308#L673-45 assume !(1 == ~t2_pc~0); 29309#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 29633#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29634#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30259#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 30079#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28926#L692-45 assume !(1 == ~t3_pc~0); 28652#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 28653#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29697#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28980#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28981#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29293#L711-45 assume 1 == ~t4_pc~0; 29417#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29418#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29270#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29271#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29674#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28825#L730-45 assume 1 == ~t5_pc~0; 28663#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28664#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29073#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29074#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29825#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28636#L749-45 assume !(1 == ~t6_pc~0); 28637#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 30037#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29800#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29801#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29952#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28952#L768-45 assume 1 == ~t7_pc~0; 28953#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29092#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29896#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29897#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29936#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29937#L787-45 assume 1 == ~t8_pc~0; 30105#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29098#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29099#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29515#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29516#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29824#L806-45 assume 1 == ~t9_pc~0; 30300#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28512#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29337#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29165#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29077#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29078#L825-45 assume !(1 == ~t10_pc~0); 29601#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 29602#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29707#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29708#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29860#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28720#L844-45 assume !(1 == ~t11_pc~0); 28721#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 29243#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29244#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29260#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 29671#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28760#L863-45 assume 1 == ~t12_pc~0; 28761#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28361#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28362#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 28877#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28878#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29677#L882-45 assume !(1 == ~t13_pc~0); 29207#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 28380#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 28381#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 28989#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 30168#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29784#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29785#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29969#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28674#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28675#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28837#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29774#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29775#L1464-3 assume !(1 == ~T7_E~0); 30221#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30148#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30149#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30223#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29415#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29416#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 30076#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29711#L1504-3 assume !(1 == ~E_1~0); 29712#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30157#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30197#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29338#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29339#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30244#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29639#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29093#L1544-3 assume !(1 == ~E_9~0); 29094#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29609#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28725#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28726#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 29875#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29876#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28610#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29175#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 29846#L1954 assume !(0 == start_simulation_~tmp~3#1); 29848#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 30098#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28893#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29934#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 30064#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30065#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30155#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 30217#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 30315#L1935-2 [2021-11-19 04:23:44,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:44,780 INFO L85 PathProgramCache]: Analyzing trace with hash 1978508041, now seen corresponding path program 1 times [2021-11-19 04:23:44,781 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:44,781 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [187813264] [2021-11-19 04:23:44,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:44,781 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:44,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:44,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:44,818 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:44,818 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [187813264] [2021-11-19 04:23:44,818 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [187813264] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:44,820 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:44,820 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:44,820 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1643598468] [2021-11-19 04:23:44,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:44,821 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:44,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:44,821 INFO L85 PathProgramCache]: Analyzing trace with hash 1143723556, now seen corresponding path program 2 times [2021-11-19 04:23:44,822 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:44,822 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23453071] [2021-11-19 04:23:44,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:44,822 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:44,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:44,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:44,870 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:44,872 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [23453071] [2021-11-19 04:23:44,874 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [23453071] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:44,874 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:44,875 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:44,876 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1113308180] [2021-11-19 04:23:44,876 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:44,876 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:44,877 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:44,877 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 04:23:44,877 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 04:23:44,878 INFO L87 Difference]: Start difference. First operand 2021 states and 2986 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:44,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:44,922 INFO L93 Difference]: Finished difference Result 2021 states and 2985 transitions. [2021-11-19 04:23:44,923 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 04:23:44,925 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2985 transitions. [2021-11-19 04:23:44,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:44,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2985 transitions. [2021-11-19 04:23:44,952 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-11-19 04:23:44,954 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-11-19 04:23:44,954 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2985 transitions. [2021-11-19 04:23:44,958 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:44,958 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2985 transitions. [2021-11-19 04:23:44,963 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2985 transitions. [2021-11-19 04:23:44,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-11-19 04:23:44,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4769915883226126) internal successors, (2985), 2020 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:45,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2985 transitions. [2021-11-19 04:23:45,003 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2985 transitions. [2021-11-19 04:23:45,003 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2985 transitions. [2021-11-19 04:23:45,003 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-19 04:23:45,003 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2985 transitions. [2021-11-19 04:23:45,012 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:45,013 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:45,013 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:45,016 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:45,016 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:45,017 INFO L791 eck$LassoCheckResult]: Stem: 33284#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 33285#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 33016#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33017#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34407#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 34408#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33203#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33204#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33238#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34075#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34076#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34188#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34189#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33022#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33023#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 34225#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33547#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33548#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 34129#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34395#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 34285#L1286-2 assume !(0 == ~T1_E~0); 32931#L1291-1 assume !(0 == ~T2_E~0); 32932#L1296-1 assume !(0 == ~T3_E~0); 33637#L1301-1 assume !(0 == ~T4_E~0); 33638#L1306-1 assume !(0 == ~T5_E~0); 34138#L1311-1 assume !(0 == ~T6_E~0); 32891#L1316-1 assume !(0 == ~T7_E~0); 32892#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33657#L1326-1 assume !(0 == ~T9_E~0); 32706#L1331-1 assume !(0 == ~T10_E~0); 32412#L1336-1 assume !(0 == ~T11_E~0); 32413#L1341-1 assume !(0 == ~T12_E~0); 32464#L1346-1 assume !(0 == ~T13_E~0); 32465#L1351-1 assume !(0 == ~E_M~0); 32838#L1356-1 assume !(0 == ~E_1~0); 32839#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 34358#L1366-1 assume !(0 == ~E_3~0); 32884#L1371-1 assume !(0 == ~E_4~0); 32885#L1376-1 assume !(0 == ~E_5~0); 33698#L1381-1 assume !(0 == ~E_6~0); 33699#L1386-1 assume !(0 == ~E_7~0); 34386#L1391-1 assume !(0 == ~E_8~0); 34399#L1396-1 assume !(0 == ~E_9~0); 33581#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 33582#L1406-1 assume !(0 == ~E_11~0); 33884#L1411-1 assume !(0 == ~E_12~0); 33885#L1416-1 assume !(0 == ~E_13~0); 33505#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33343#L635 assume !(1 == ~m_pc~0); 32482#L635-2 is_master_triggered_~__retres1~0#1 := 0; 32483#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32833#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33469#L1598 assume !(0 != activate_threads_~tmp~1#1); 32661#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32662#L654 assume 1 == ~t1_pc~0; 33367#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33368#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34383#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33449#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 33450#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32709#L673 assume 1 == ~t2_pc~0; 32710#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33854#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33855#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34413#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 34420#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33528#L692 assume !(1 == ~t3_pc~0); 33345#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33346#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33205#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33173#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33174#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32734#L711 assume 1 == ~t4_pc~0; 32735#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33218#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33675#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32437#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 32438#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34406#L730 assume !(1 == ~t5_pc~0); 33788#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32616#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32617#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32744#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 32745#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33087#L749 assume 1 == ~t6_pc~0; 32861#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32621#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33053#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33054#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 33276#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32417#L768 assume !(1 == ~t7_pc~0); 32418#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 33722#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32654#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32655#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 33741#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32893#L787 assume 1 == ~t8_pc~0; 32894#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34089#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34253#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34254#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 32462#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32463#L806 assume 1 == ~t9_pc~0; 34100#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32497#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32498#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32746#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 32747#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34083#L825 assume !(1 == ~t10_pc~0); 34084#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 33689#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33690#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32834#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32835#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33418#L844 assume 1 == ~t11_pc~0; 33108#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33109#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33475#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33476#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 34071#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34072#L863 assume !(1 == ~t12_pc~0); 32597#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 32596#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32824#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34163#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 34164#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33542#L882 assume 1 == ~t13_pc~0; 33543#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33827#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34328#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 34131#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 33814#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33815#L1434 assume !(1 == ~M_E~0); 34336#L1434-2 assume !(1 == ~T1_E~0); 34412#L1439-1 assume !(1 == ~T2_E~0); 32727#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32728#L1449-1 assume !(1 == ~T4_E~0); 33170#L1454-1 assume !(1 == ~T5_E~0); 33171#L1459-1 assume !(1 == ~T6_E~0); 33742#L1464-1 assume !(1 == ~T7_E~0); 33743#L1469-1 assume !(1 == ~T8_E~0); 33828#L1474-1 assume !(1 == ~T9_E~0); 33506#L1479-1 assume !(1 == ~T10_E~0); 33507#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33750#L1489-1 assume !(1 == ~T12_E~0); 33384#L1494-1 assume !(1 == ~T13_E~0); 33385#L1499-1 assume !(1 == ~E_M~0); 33566#L1504-1 assume !(1 == ~E_1~0); 33567#L1509-1 assume !(1 == ~E_2~0); 34180#L1514-1 assume !(1 == ~E_3~0); 33865#L1519-1 assume !(1 == ~E_4~0); 33866#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 34370#L1529-1 assume !(1 == ~E_6~0); 34371#L1534-1 assume !(1 == ~E_7~0); 32517#L1539-1 assume !(1 == ~E_8~0); 32518#L1544-1 assume !(1 == ~E_9~0); 32948#L1549-1 assume !(1 == ~E_10~0); 34348#L1554-1 assume !(1 == ~E_11~0); 34346#L1559-1 assume !(1 == ~E_12~0); 34208#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 34209#L1569-1 assume { :end_inline_reset_delta_events } true; 34364#L1935-2 [2021-11-19 04:23:45,017 INFO L793 eck$LassoCheckResult]: Loop: 34364#L1935-2 assume !false; 32526#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32527#L1261 assume !false; 33754#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33755#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32657#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32827#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 32828#L1074 assume !(0 != eval_~tmp~0#1); 33185#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33783#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34184#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34240#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33959#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33960#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34396#L1301-3 assume !(0 == ~T4_E~0); 34354#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33462#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32761#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32762#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32867#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33603#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33868#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33869#L1341-3 assume !(0 == ~T12_E~0); 33163#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 33154#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33098#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33099#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33679#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32452#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32453#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34195#L1381-3 assume !(0 == ~E_6~0); 34044#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34045#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34226#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 34227#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32832#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32663#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 32664#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 33291#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32541#L635-45 assume 1 == ~m_pc~0; 32542#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33336#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33816#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34070#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32850#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32851#L654-45 assume 1 == ~t1_pc~0; 33671#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34019#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32504#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32505#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32530#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33357#L673-45 assume !(1 == ~t2_pc~0); 33358#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 33682#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33683#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34308#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 34128#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32975#L692-45 assume 1 == ~t3_pc~0; 32976#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32702#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33746#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33029#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33030#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33342#L711-45 assume 1 == ~t4_pc~0; 33466#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33467#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33319#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33320#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33723#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32874#L730-45 assume 1 == ~t5_pc~0; 32712#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32713#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33122#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33123#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33874#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32685#L749-45 assume !(1 == ~t6_pc~0); 32686#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 34086#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33849#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33850#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34001#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33001#L768-45 assume 1 == ~t7_pc~0; 33002#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33141#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33945#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33946#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33985#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33986#L787-45 assume 1 == ~t8_pc~0; 34154#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33147#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33148#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33564#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33565#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33873#L806-45 assume !(1 == ~t9_pc~0); 32560#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 32561#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33386#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33214#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33126#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33127#L825-45 assume !(1 == ~t10_pc~0); 33650#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 33651#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33756#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33757#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 33909#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32769#L844-45 assume !(1 == ~t11_pc~0); 32770#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 33292#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33293#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33309#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 33720#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32809#L863-45 assume 1 == ~t12_pc~0; 32810#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 32410#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32411#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 32926#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32927#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33726#L882-45 assume 1 == ~t13_pc~0; 34080#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 32429#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 32430#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 33038#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34217#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33833#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33834#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34018#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32723#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32724#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32886#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33823#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33824#L1464-3 assume !(1 == ~T7_E~0); 34270#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34197#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34198#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 34272#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33464#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33465#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 34125#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33760#L1504-3 assume !(1 == ~E_1~0); 33761#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34206#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34246#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33387#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33388#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 34293#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33688#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33142#L1544-3 assume !(1 == ~E_9~0); 33143#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33658#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32774#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 32775#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 33924#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33925#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32659#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33224#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 33895#L1954 assume !(0 == start_simulation_~tmp~3#1); 33897#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 34147#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32942#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33983#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 34113#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34114#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34204#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 34266#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 34364#L1935-2 [2021-11-19 04:23:45,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:45,018 INFO L85 PathProgramCache]: Analyzing trace with hash -1393291829, now seen corresponding path program 1 times [2021-11-19 04:23:45,018 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:45,019 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1696140781] [2021-11-19 04:23:45,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:45,019 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:45,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:45,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:45,053 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:45,053 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1696140781] [2021-11-19 04:23:45,053 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1696140781] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:45,053 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:45,053 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:45,053 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [903855505] [2021-11-19 04:23:45,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:45,054 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:45,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:45,055 INFO L85 PathProgramCache]: Analyzing trace with hash -289217245, now seen corresponding path program 1 times [2021-11-19 04:23:45,055 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:45,055 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983279821] [2021-11-19 04:23:45,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:45,056 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:45,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:45,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:45,103 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:45,104 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [983279821] [2021-11-19 04:23:45,104 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [983279821] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:45,104 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:45,104 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:45,104 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [453926415] [2021-11-19 04:23:45,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:45,105 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:45,105 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:45,106 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 04:23:45,106 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 04:23:45,106 INFO L87 Difference]: Start difference. First operand 2021 states and 2985 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:45,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:45,150 INFO L93 Difference]: Finished difference Result 2021 states and 2984 transitions. [2021-11-19 04:23:45,151 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 04:23:45,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2984 transitions. [2021-11-19 04:23:45,163 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:45,188 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2984 transitions. [2021-11-19 04:23:45,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-11-19 04:23:45,191 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-11-19 04:23:45,191 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2984 transitions. [2021-11-19 04:23:45,195 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:45,195 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2984 transitions. [2021-11-19 04:23:45,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2984 transitions. [2021-11-19 04:23:45,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-11-19 04:23:45,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4764967837704106) internal successors, (2984), 2020 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:45,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2984 transitions. [2021-11-19 04:23:45,257 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2984 transitions. [2021-11-19 04:23:45,258 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2984 transitions. [2021-11-19 04:23:45,258 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-19 04:23:45,258 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2984 transitions. [2021-11-19 04:23:45,267 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:45,268 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:45,268 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:45,271 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:45,271 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:45,272 INFO L791 eck$LassoCheckResult]: Stem: 37333#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 37334#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 37065#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37066#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38456#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 38457#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37252#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37253#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37287#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38124#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38125#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38237#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38238#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37071#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37072#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 38274#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37596#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37597#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 38178#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38444#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 38334#L1286-2 assume !(0 == ~T1_E~0); 36980#L1291-1 assume !(0 == ~T2_E~0); 36981#L1296-1 assume !(0 == ~T3_E~0); 37686#L1301-1 assume !(0 == ~T4_E~0); 37687#L1306-1 assume !(0 == ~T5_E~0); 38187#L1311-1 assume !(0 == ~T6_E~0); 36940#L1316-1 assume !(0 == ~T7_E~0); 36941#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37706#L1326-1 assume !(0 == ~T9_E~0); 36755#L1331-1 assume !(0 == ~T10_E~0); 36461#L1336-1 assume !(0 == ~T11_E~0); 36462#L1341-1 assume !(0 == ~T12_E~0); 36513#L1346-1 assume !(0 == ~T13_E~0); 36514#L1351-1 assume !(0 == ~E_M~0); 36887#L1356-1 assume !(0 == ~E_1~0); 36888#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 38407#L1366-1 assume !(0 == ~E_3~0); 36933#L1371-1 assume !(0 == ~E_4~0); 36934#L1376-1 assume !(0 == ~E_5~0); 37747#L1381-1 assume !(0 == ~E_6~0); 37748#L1386-1 assume !(0 == ~E_7~0); 38435#L1391-1 assume !(0 == ~E_8~0); 38448#L1396-1 assume !(0 == ~E_9~0); 37630#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 37631#L1406-1 assume !(0 == ~E_11~0); 37933#L1411-1 assume !(0 == ~E_12~0); 37934#L1416-1 assume !(0 == ~E_13~0); 37554#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37392#L635 assume !(1 == ~m_pc~0); 36531#L635-2 is_master_triggered_~__retres1~0#1 := 0; 36532#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36882#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37518#L1598 assume !(0 != activate_threads_~tmp~1#1); 36710#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36711#L654 assume 1 == ~t1_pc~0; 37416#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37417#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38432#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37498#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 37499#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36758#L673 assume 1 == ~t2_pc~0; 36759#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37903#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37904#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38462#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 38469#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37577#L692 assume !(1 == ~t3_pc~0); 37394#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37395#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37254#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37222#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37223#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36783#L711 assume 1 == ~t4_pc~0; 36784#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37267#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37724#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36486#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 36487#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38455#L730 assume !(1 == ~t5_pc~0); 37837#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36665#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36666#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36793#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 36794#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37136#L749 assume 1 == ~t6_pc~0; 36910#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36670#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37102#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37103#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 37325#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36466#L768 assume !(1 == ~t7_pc~0); 36467#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 37771#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36703#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36704#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 37790#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36942#L787 assume 1 == ~t8_pc~0; 36943#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38138#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38302#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38303#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 36511#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36512#L806 assume 1 == ~t9_pc~0; 38149#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36546#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36547#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36795#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 36796#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38132#L825 assume !(1 == ~t10_pc~0); 38133#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 37738#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37739#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36883#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36884#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37467#L844 assume 1 == ~t11_pc~0; 37157#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37158#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37524#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37525#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 38120#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38121#L863 assume !(1 == ~t12_pc~0); 36646#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 36645#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36873#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38212#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 38213#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37591#L882 assume 1 == ~t13_pc~0; 37592#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37876#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38377#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38180#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 37863#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37864#L1434 assume !(1 == ~M_E~0); 38385#L1434-2 assume !(1 == ~T1_E~0); 38461#L1439-1 assume !(1 == ~T2_E~0); 36776#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36777#L1449-1 assume !(1 == ~T4_E~0); 37219#L1454-1 assume !(1 == ~T5_E~0); 37220#L1459-1 assume !(1 == ~T6_E~0); 37791#L1464-1 assume !(1 == ~T7_E~0); 37792#L1469-1 assume !(1 == ~T8_E~0); 37877#L1474-1 assume !(1 == ~T9_E~0); 37555#L1479-1 assume !(1 == ~T10_E~0); 37556#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37799#L1489-1 assume !(1 == ~T12_E~0); 37433#L1494-1 assume !(1 == ~T13_E~0); 37434#L1499-1 assume !(1 == ~E_M~0); 37615#L1504-1 assume !(1 == ~E_1~0); 37616#L1509-1 assume !(1 == ~E_2~0); 38229#L1514-1 assume !(1 == ~E_3~0); 37914#L1519-1 assume !(1 == ~E_4~0); 37915#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38419#L1529-1 assume !(1 == ~E_6~0); 38420#L1534-1 assume !(1 == ~E_7~0); 36566#L1539-1 assume !(1 == ~E_8~0); 36567#L1544-1 assume !(1 == ~E_9~0); 36997#L1549-1 assume !(1 == ~E_10~0); 38397#L1554-1 assume !(1 == ~E_11~0); 38395#L1559-1 assume !(1 == ~E_12~0); 38257#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 38258#L1569-1 assume { :end_inline_reset_delta_events } true; 38413#L1935-2 [2021-11-19 04:23:45,272 INFO L793 eck$LassoCheckResult]: Loop: 38413#L1935-2 assume !false; 36575#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36576#L1261 assume !false; 37803#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37804#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36706#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36876#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 36877#L1074 assume !(0 != eval_~tmp~0#1); 37234#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37832#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38233#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38289#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38008#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38009#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38445#L1301-3 assume !(0 == ~T4_E~0); 38403#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37511#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36810#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36811#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36916#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37652#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37917#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37918#L1341-3 assume !(0 == ~T12_E~0); 37212#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37203#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37147#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37148#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37728#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36501#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36502#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38244#L1381-3 assume !(0 == ~E_6~0); 38093#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38094#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38275#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38276#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36881#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36712#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36713#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 37340#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36590#L635-45 assume !(1 == ~m_pc~0); 36592#L635-47 is_master_triggered_~__retres1~0#1 := 0; 37385#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37865#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38119#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36899#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36900#L654-45 assume 1 == ~t1_pc~0; 37720#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38068#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36553#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36554#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36579#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37406#L673-45 assume 1 == ~t2_pc~0; 37408#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37731#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37732#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38357#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 38177#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37024#L692-45 assume 1 == ~t3_pc~0; 37025#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36751#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37795#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37078#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37079#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37391#L711-45 assume 1 == ~t4_pc~0; 37515#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37516#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37368#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37369#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37772#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36923#L730-45 assume 1 == ~t5_pc~0; 36761#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36762#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37171#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37172#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37923#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36734#L749-45 assume 1 == ~t6_pc~0; 36736#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38135#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37898#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37899#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38050#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37050#L768-45 assume 1 == ~t7_pc~0; 37051#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37190#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37994#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37995#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38034#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38035#L787-45 assume 1 == ~t8_pc~0; 38203#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37196#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37197#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37613#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37614#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37922#L806-45 assume !(1 == ~t9_pc~0); 36609#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 36610#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37435#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37263#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37175#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37176#L825-45 assume !(1 == ~t10_pc~0); 37699#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 37700#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37805#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37806#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37958#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36818#L844-45 assume !(1 == ~t11_pc~0); 36819#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 37341#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37342#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37358#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 37769#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36858#L863-45 assume 1 == ~t12_pc~0; 36859#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36459#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36460#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 36975#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36976#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37775#L882-45 assume 1 == ~t13_pc~0; 38129#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 36478#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 36479#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 37087#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38266#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37882#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37883#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38067#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36772#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36773#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36935#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37872#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37873#L1464-3 assume !(1 == ~T7_E~0); 38319#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38246#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38247#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38321#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37513#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 37514#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 38174#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37809#L1504-3 assume !(1 == ~E_1~0); 37810#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38255#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38295#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37436#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37437#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38342#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37737#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37191#L1544-3 assume !(1 == ~E_9~0); 37192#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37707#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 36823#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 36824#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 37973#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37974#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36708#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37273#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 37944#L1954 assume !(0 == start_simulation_~tmp~3#1); 37946#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 38196#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36991#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38032#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 38162#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38163#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38253#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 38315#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 38413#L1935-2 [2021-11-19 04:23:45,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:45,273 INFO L85 PathProgramCache]: Analyzing trace with hash -1779154231, now seen corresponding path program 1 times [2021-11-19 04:23:45,274 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:45,274 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [84788388] [2021-11-19 04:23:45,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:45,274 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:45,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:45,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:45,311 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:45,311 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [84788388] [2021-11-19 04:23:45,311 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [84788388] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:45,311 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:45,311 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:45,312 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1797277356] [2021-11-19 04:23:45,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:45,313 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:45,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:45,314 INFO L85 PathProgramCache]: Analyzing trace with hash -1698619550, now seen corresponding path program 1 times [2021-11-19 04:23:45,314 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:45,314 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803797199] [2021-11-19 04:23:45,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:45,315 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:45,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:45,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:45,367 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:45,367 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [803797199] [2021-11-19 04:23:45,367 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [803797199] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:45,368 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:45,368 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:45,368 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96371464] [2021-11-19 04:23:45,368 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:45,369 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:45,369 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:45,369 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 04:23:45,369 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 04:23:45,370 INFO L87 Difference]: Start difference. First operand 2021 states and 2984 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:45,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:45,414 INFO L93 Difference]: Finished difference Result 2021 states and 2983 transitions. [2021-11-19 04:23:45,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 04:23:45,415 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2983 transitions. [2021-11-19 04:23:45,426 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:45,437 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2983 transitions. [2021-11-19 04:23:45,437 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-11-19 04:23:45,440 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-11-19 04:23:45,440 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2983 transitions. [2021-11-19 04:23:45,444 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:45,444 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2983 transitions. [2021-11-19 04:23:45,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2983 transitions. [2021-11-19 04:23:45,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-11-19 04:23:45,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4760019792182089) internal successors, (2983), 2020 states have internal predecessors, (2983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:45,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2983 transitions. [2021-11-19 04:23:45,487 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2983 transitions. [2021-11-19 04:23:45,488 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2983 transitions. [2021-11-19 04:23:45,488 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-19 04:23:45,488 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2983 transitions. [2021-11-19 04:23:45,496 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:45,496 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:45,496 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:45,499 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:45,500 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:45,500 INFO L791 eck$LassoCheckResult]: Stem: 41382#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 41383#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 41114#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41115#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42505#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 42506#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41301#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41302#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41336#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42173#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42174#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42286#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42287#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41120#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41121#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 42323#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41645#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 41646#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42227#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42493#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 42383#L1286-2 assume !(0 == ~T1_E~0); 41029#L1291-1 assume !(0 == ~T2_E~0); 41030#L1296-1 assume !(0 == ~T3_E~0); 41735#L1301-1 assume !(0 == ~T4_E~0); 41736#L1306-1 assume !(0 == ~T5_E~0); 42236#L1311-1 assume !(0 == ~T6_E~0); 40989#L1316-1 assume !(0 == ~T7_E~0); 40990#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41755#L1326-1 assume !(0 == ~T9_E~0); 40804#L1331-1 assume !(0 == ~T10_E~0); 40510#L1336-1 assume !(0 == ~T11_E~0); 40511#L1341-1 assume !(0 == ~T12_E~0); 40562#L1346-1 assume !(0 == ~T13_E~0); 40563#L1351-1 assume !(0 == ~E_M~0); 40936#L1356-1 assume !(0 == ~E_1~0); 40937#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 42456#L1366-1 assume !(0 == ~E_3~0); 40982#L1371-1 assume !(0 == ~E_4~0); 40983#L1376-1 assume !(0 == ~E_5~0); 41796#L1381-1 assume !(0 == ~E_6~0); 41797#L1386-1 assume !(0 == ~E_7~0); 42484#L1391-1 assume !(0 == ~E_8~0); 42497#L1396-1 assume !(0 == ~E_9~0); 41679#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 41680#L1406-1 assume !(0 == ~E_11~0); 41982#L1411-1 assume !(0 == ~E_12~0); 41983#L1416-1 assume !(0 == ~E_13~0); 41603#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41441#L635 assume !(1 == ~m_pc~0); 40580#L635-2 is_master_triggered_~__retres1~0#1 := 0; 40581#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40931#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41567#L1598 assume !(0 != activate_threads_~tmp~1#1); 40759#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40760#L654 assume 1 == ~t1_pc~0; 41465#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41466#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42481#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41547#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 41548#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40807#L673 assume 1 == ~t2_pc~0; 40808#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41952#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41953#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42511#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 42518#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41626#L692 assume !(1 == ~t3_pc~0); 41443#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41444#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41303#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41271#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41272#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40832#L711 assume 1 == ~t4_pc~0; 40833#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41316#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41773#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40535#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 40536#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42504#L730 assume !(1 == ~t5_pc~0); 41886#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 40714#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40715#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40842#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 40843#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41185#L749 assume 1 == ~t6_pc~0; 40959#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40719#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41151#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41152#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 41374#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40515#L768 assume !(1 == ~t7_pc~0); 40516#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 41820#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40752#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40753#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 41839#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40991#L787 assume 1 == ~t8_pc~0; 40992#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42187#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42351#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42352#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 40560#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40561#L806 assume 1 == ~t9_pc~0; 42198#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40595#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40596#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40844#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 40845#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42181#L825 assume !(1 == ~t10_pc~0); 42182#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 41787#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41788#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40932#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40933#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41516#L844 assume 1 == ~t11_pc~0; 41206#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41207#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41573#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41574#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 42169#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42170#L863 assume !(1 == ~t12_pc~0); 40695#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40694#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40922#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42261#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 42262#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41640#L882 assume 1 == ~t13_pc~0; 41641#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41925#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42426#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42229#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 41912#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41913#L1434 assume !(1 == ~M_E~0); 42434#L1434-2 assume !(1 == ~T1_E~0); 42510#L1439-1 assume !(1 == ~T2_E~0); 40825#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40826#L1449-1 assume !(1 == ~T4_E~0); 41268#L1454-1 assume !(1 == ~T5_E~0); 41269#L1459-1 assume !(1 == ~T6_E~0); 41840#L1464-1 assume !(1 == ~T7_E~0); 41841#L1469-1 assume !(1 == ~T8_E~0); 41926#L1474-1 assume !(1 == ~T9_E~0); 41604#L1479-1 assume !(1 == ~T10_E~0); 41605#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41848#L1489-1 assume !(1 == ~T12_E~0); 41482#L1494-1 assume !(1 == ~T13_E~0); 41483#L1499-1 assume !(1 == ~E_M~0); 41664#L1504-1 assume !(1 == ~E_1~0); 41665#L1509-1 assume !(1 == ~E_2~0); 42278#L1514-1 assume !(1 == ~E_3~0); 41963#L1519-1 assume !(1 == ~E_4~0); 41964#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 42468#L1529-1 assume !(1 == ~E_6~0); 42469#L1534-1 assume !(1 == ~E_7~0); 40615#L1539-1 assume !(1 == ~E_8~0); 40616#L1544-1 assume !(1 == ~E_9~0); 41046#L1549-1 assume !(1 == ~E_10~0); 42446#L1554-1 assume !(1 == ~E_11~0); 42444#L1559-1 assume !(1 == ~E_12~0); 42306#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 42307#L1569-1 assume { :end_inline_reset_delta_events } true; 42462#L1935-2 [2021-11-19 04:23:45,501 INFO L793 eck$LassoCheckResult]: Loop: 42462#L1935-2 assume !false; 40624#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40625#L1261 assume !false; 41852#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41853#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40755#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40925#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40926#L1074 assume !(0 != eval_~tmp~0#1); 41283#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41881#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42282#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42338#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42057#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42058#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42494#L1301-3 assume !(0 == ~T4_E~0); 42452#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41560#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40859#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40860#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40965#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41701#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41966#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41967#L1341-3 assume !(0 == ~T12_E~0); 41261#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 41252#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41196#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41197#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41777#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40550#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40551#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42293#L1381-3 assume !(0 == ~E_6~0); 42142#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42143#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 42324#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42325#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40930#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40761#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40762#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 41389#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40639#L635-45 assume 1 == ~m_pc~0; 40640#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41434#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41914#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42168#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40948#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40949#L654-45 assume 1 == ~t1_pc~0; 41769#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42117#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40602#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40603#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40628#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41455#L673-45 assume !(1 == ~t2_pc~0); 41456#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 41780#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41781#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42406#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 42226#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41073#L692-45 assume 1 == ~t3_pc~0; 41074#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40800#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41844#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41127#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41128#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41440#L711-45 assume 1 == ~t4_pc~0; 41564#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41565#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41417#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41418#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41821#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40972#L730-45 assume 1 == ~t5_pc~0; 40810#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40811#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41220#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41221#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41972#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40783#L749-45 assume !(1 == ~t6_pc~0); 40784#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 42184#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41947#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41948#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42099#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41099#L768-45 assume 1 == ~t7_pc~0; 41100#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41239#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42043#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42044#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42083#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42084#L787-45 assume 1 == ~t8_pc~0; 42252#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41245#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41246#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41662#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41663#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41971#L806-45 assume !(1 == ~t9_pc~0); 40658#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 40659#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41484#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41312#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41224#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41225#L825-45 assume !(1 == ~t10_pc~0); 41748#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 41749#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41854#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41855#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 42007#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40867#L844-45 assume !(1 == ~t11_pc~0); 40868#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 41390#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41391#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41407#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 41818#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40907#L863-45 assume 1 == ~t12_pc~0; 40908#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40508#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40509#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 41024#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 41025#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41824#L882-45 assume 1 == ~t13_pc~0; 42178#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 40527#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 40528#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 41136#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42315#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41931#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 41932#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42116#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40821#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40822#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40984#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41921#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41922#L1464-3 assume !(1 == ~T7_E~0); 42368#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42295#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42296#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42370#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41562#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 41563#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 42223#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41858#L1504-3 assume !(1 == ~E_1~0); 41859#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42304#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42344#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41485#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41486#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42391#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41786#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41240#L1544-3 assume !(1 == ~E_9~0); 41241#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41756#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40872#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 40873#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 42022#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 42023#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40757#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41322#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 41993#L1954 assume !(0 == start_simulation_~tmp~3#1); 41995#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 42245#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41040#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42081#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 42211#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42212#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42302#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 42364#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 42462#L1935-2 [2021-11-19 04:23:45,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:45,501 INFO L85 PathProgramCache]: Analyzing trace with hash 584687431, now seen corresponding path program 1 times [2021-11-19 04:23:45,502 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:45,502 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [924909330] [2021-11-19 04:23:45,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:45,502 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:45,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:45,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:45,541 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:45,541 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [924909330] [2021-11-19 04:23:45,541 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [924909330] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:45,541 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:45,542 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:45,542 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1667554011] [2021-11-19 04:23:45,542 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:45,542 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:45,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:45,543 INFO L85 PathProgramCache]: Analyzing trace with hash -289217245, now seen corresponding path program 2 times [2021-11-19 04:23:45,543 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:45,543 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1565589872] [2021-11-19 04:23:45,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:45,544 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:45,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:45,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:45,616 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:45,616 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1565589872] [2021-11-19 04:23:45,616 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1565589872] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:45,616 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:45,617 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:45,617 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1349483761] [2021-11-19 04:23:45,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:45,617 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:45,618 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:45,618 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 04:23:45,619 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 04:23:45,619 INFO L87 Difference]: Start difference. First operand 2021 states and 2983 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:45,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:45,655 INFO L93 Difference]: Finished difference Result 2021 states and 2982 transitions. [2021-11-19 04:23:45,656 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 04:23:45,656 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2982 transitions. [2021-11-19 04:23:45,667 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:45,678 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2982 transitions. [2021-11-19 04:23:45,678 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-11-19 04:23:45,680 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-11-19 04:23:45,680 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2982 transitions. [2021-11-19 04:23:45,684 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:45,684 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2982 transitions. [2021-11-19 04:23:45,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2982 transitions. [2021-11-19 04:23:45,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-11-19 04:23:45,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.475507174666007) internal successors, (2982), 2020 states have internal predecessors, (2982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:45,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2982 transitions. [2021-11-19 04:23:45,727 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2982 transitions. [2021-11-19 04:23:45,727 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2982 transitions. [2021-11-19 04:23:45,727 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-19 04:23:45,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2982 transitions. [2021-11-19 04:23:45,735 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:45,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:45,736 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:45,739 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:45,739 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:45,739 INFO L791 eck$LassoCheckResult]: Stem: 45431#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 45432#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 45163#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45164#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46554#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 46555#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45350#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45351#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45385#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46222#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46223#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46335#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46336#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45169#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 45170#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 46372#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45694#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 45695#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46276#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46542#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 46432#L1286-2 assume !(0 == ~T1_E~0); 45078#L1291-1 assume !(0 == ~T2_E~0); 45079#L1296-1 assume !(0 == ~T3_E~0); 45784#L1301-1 assume !(0 == ~T4_E~0); 45785#L1306-1 assume !(0 == ~T5_E~0); 46285#L1311-1 assume !(0 == ~T6_E~0); 45038#L1316-1 assume !(0 == ~T7_E~0); 45039#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45804#L1326-1 assume !(0 == ~T9_E~0); 44853#L1331-1 assume !(0 == ~T10_E~0); 44559#L1336-1 assume !(0 == ~T11_E~0); 44560#L1341-1 assume !(0 == ~T12_E~0); 44611#L1346-1 assume !(0 == ~T13_E~0); 44612#L1351-1 assume !(0 == ~E_M~0); 44985#L1356-1 assume !(0 == ~E_1~0); 44986#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 46505#L1366-1 assume !(0 == ~E_3~0); 45031#L1371-1 assume !(0 == ~E_4~0); 45032#L1376-1 assume !(0 == ~E_5~0); 45845#L1381-1 assume !(0 == ~E_6~0); 45846#L1386-1 assume !(0 == ~E_7~0); 46533#L1391-1 assume !(0 == ~E_8~0); 46546#L1396-1 assume !(0 == ~E_9~0); 45728#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 45729#L1406-1 assume !(0 == ~E_11~0); 46031#L1411-1 assume !(0 == ~E_12~0); 46032#L1416-1 assume !(0 == ~E_13~0); 45652#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45490#L635 assume !(1 == ~m_pc~0); 44629#L635-2 is_master_triggered_~__retres1~0#1 := 0; 44630#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44980#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45616#L1598 assume !(0 != activate_threads_~tmp~1#1); 44808#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44809#L654 assume 1 == ~t1_pc~0; 45514#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45515#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46530#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45596#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 45597#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44856#L673 assume 1 == ~t2_pc~0; 44857#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46001#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46002#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46560#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 46567#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45675#L692 assume !(1 == ~t3_pc~0); 45492#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45493#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45352#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45320#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45321#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44881#L711 assume 1 == ~t4_pc~0; 44882#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45365#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45822#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44584#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 44585#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46553#L730 assume !(1 == ~t5_pc~0); 45935#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 44763#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44764#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44891#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 44892#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45234#L749 assume 1 == ~t6_pc~0; 45008#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44768#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45200#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45201#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 45423#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44564#L768 assume !(1 == ~t7_pc~0); 44565#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 45869#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44801#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44802#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 45888#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45040#L787 assume 1 == ~t8_pc~0; 45041#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46236#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46400#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46401#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 44609#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44610#L806 assume 1 == ~t9_pc~0; 46247#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44644#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44645#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44893#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 44894#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46230#L825 assume !(1 == ~t10_pc~0); 46231#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 45836#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45837#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44981#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44982#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 45565#L844 assume 1 == ~t11_pc~0; 45255#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45256#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45622#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45623#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 46218#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46219#L863 assume !(1 == ~t12_pc~0); 44744#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 44743#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44971#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46310#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 46311#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45689#L882 assume 1 == ~t13_pc~0; 45690#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45974#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46475#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46278#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 45961#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45962#L1434 assume !(1 == ~M_E~0); 46483#L1434-2 assume !(1 == ~T1_E~0); 46559#L1439-1 assume !(1 == ~T2_E~0); 44874#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44875#L1449-1 assume !(1 == ~T4_E~0); 45317#L1454-1 assume !(1 == ~T5_E~0); 45318#L1459-1 assume !(1 == ~T6_E~0); 45889#L1464-1 assume !(1 == ~T7_E~0); 45890#L1469-1 assume !(1 == ~T8_E~0); 45975#L1474-1 assume !(1 == ~T9_E~0); 45653#L1479-1 assume !(1 == ~T10_E~0); 45654#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45897#L1489-1 assume !(1 == ~T12_E~0); 45531#L1494-1 assume !(1 == ~T13_E~0); 45532#L1499-1 assume !(1 == ~E_M~0); 45713#L1504-1 assume !(1 == ~E_1~0); 45714#L1509-1 assume !(1 == ~E_2~0); 46327#L1514-1 assume !(1 == ~E_3~0); 46012#L1519-1 assume !(1 == ~E_4~0); 46013#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46517#L1529-1 assume !(1 == ~E_6~0); 46518#L1534-1 assume !(1 == ~E_7~0); 44664#L1539-1 assume !(1 == ~E_8~0); 44665#L1544-1 assume !(1 == ~E_9~0); 45095#L1549-1 assume !(1 == ~E_10~0); 46495#L1554-1 assume !(1 == ~E_11~0); 46493#L1559-1 assume !(1 == ~E_12~0); 46355#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 46356#L1569-1 assume { :end_inline_reset_delta_events } true; 46511#L1935-2 [2021-11-19 04:23:45,740 INFO L793 eck$LassoCheckResult]: Loop: 46511#L1935-2 assume !false; 44673#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44674#L1261 assume !false; 45901#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45902#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44804#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44974#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44975#L1074 assume !(0 != eval_~tmp~0#1); 45332#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45930#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46331#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46387#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46106#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46107#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46543#L1301-3 assume !(0 == ~T4_E~0); 46501#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45609#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44908#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44909#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45014#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45750#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 46015#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 46016#L1341-3 assume !(0 == ~T12_E~0); 45310#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45301#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45245#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45246#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45826#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44599#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44600#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46342#L1381-3 assume !(0 == ~E_6~0); 46191#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46192#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 46373#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46374#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44979#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44810#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 44811#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 45438#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44688#L635-45 assume 1 == ~m_pc~0; 44689#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 45483#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45963#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46217#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44997#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44998#L654-45 assume 1 == ~t1_pc~0; 45818#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46166#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44651#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44652#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44677#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45504#L673-45 assume !(1 == ~t2_pc~0); 45505#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 45829#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45830#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46455#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 46275#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45122#L692-45 assume !(1 == ~t3_pc~0); 44848#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 44849#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45893#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45176#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45177#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45489#L711-45 assume 1 == ~t4_pc~0; 45613#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45614#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45466#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45467#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45870#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45021#L730-45 assume 1 == ~t5_pc~0; 44859#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44860#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45269#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45270#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46021#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44832#L749-45 assume !(1 == ~t6_pc~0); 44833#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 46233#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45996#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45997#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46148#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45148#L768-45 assume 1 == ~t7_pc~0; 45149#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45288#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46092#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46093#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46132#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46133#L787-45 assume 1 == ~t8_pc~0; 46301#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45294#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45295#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45711#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45712#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46020#L806-45 assume 1 == ~t9_pc~0; 46496#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44708#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45533#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45361#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45273#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45274#L825-45 assume !(1 == ~t10_pc~0); 45797#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 45798#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45903#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45904#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 46056#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44916#L844-45 assume !(1 == ~t11_pc~0); 44917#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 45439#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45440#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45456#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 45867#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44956#L863-45 assume 1 == ~t12_pc~0; 44957#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44557#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44558#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45073#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 45074#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45873#L882-45 assume 1 == ~t13_pc~0; 46227#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 44576#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 44577#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 45185#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46364#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45980#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 45981#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46165#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44870#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44871#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45033#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45970#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 45971#L1464-3 assume !(1 == ~T7_E~0); 46417#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46344#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46345#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46419#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45611#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 45612#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46272#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45907#L1504-3 assume !(1 == ~E_1~0); 45908#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46353#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46393#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45534#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 45535#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46440#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 45835#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45289#L1544-3 assume !(1 == ~E_9~0); 45290#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 45805#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44921#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44922#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46071#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46072#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44806#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45371#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 46042#L1954 assume !(0 == start_simulation_~tmp~3#1); 46044#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46294#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45089#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46130#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 46260#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46261#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46351#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 46413#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 46511#L1935-2 [2021-11-19 04:23:45,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:45,741 INFO L85 PathProgramCache]: Analyzing trace with hash 1907866377, now seen corresponding path program 1 times [2021-11-19 04:23:45,741 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:45,741 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1878278819] [2021-11-19 04:23:45,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:45,742 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:45,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:45,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:45,786 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:45,787 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1878278819] [2021-11-19 04:23:45,787 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1878278819] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:45,789 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:45,789 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:45,791 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1633208052] [2021-11-19 04:23:45,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:45,791 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:45,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:45,792 INFO L85 PathProgramCache]: Analyzing trace with hash -1257801565, now seen corresponding path program 1 times [2021-11-19 04:23:45,792 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:45,792 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081362672] [2021-11-19 04:23:45,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:45,793 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:45,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:45,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:45,836 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:45,836 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1081362672] [2021-11-19 04:23:45,837 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1081362672] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:45,837 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:45,837 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:45,837 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259618922] [2021-11-19 04:23:45,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:45,838 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:45,838 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:45,838 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 04:23:45,838 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 04:23:45,839 INFO L87 Difference]: Start difference. First operand 2021 states and 2982 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:45,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:45,877 INFO L93 Difference]: Finished difference Result 2021 states and 2981 transitions. [2021-11-19 04:23:45,877 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 04:23:45,878 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2981 transitions. [2021-11-19 04:23:45,888 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:45,899 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2981 transitions. [2021-11-19 04:23:45,900 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-11-19 04:23:45,902 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-11-19 04:23:45,902 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2981 transitions. [2021-11-19 04:23:45,906 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:45,906 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2981 transitions. [2021-11-19 04:23:45,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2981 transitions. [2021-11-19 04:23:45,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-11-19 04:23:45,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4750123701138051) internal successors, (2981), 2020 states have internal predecessors, (2981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:45,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2981 transitions. [2021-11-19 04:23:45,949 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2981 transitions. [2021-11-19 04:23:45,949 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2981 transitions. [2021-11-19 04:23:45,949 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-19 04:23:45,949 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2981 transitions. [2021-11-19 04:23:45,957 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:45,957 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:45,957 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:45,960 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:45,960 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:45,961 INFO L791 eck$LassoCheckResult]: Stem: 49480#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 49481#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 49212#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49213#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50603#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 50604#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49399#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49400#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49434#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50271#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50272#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50384#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50385#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49218#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49219#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50421#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49743#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 49744#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 50325#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50591#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 50481#L1286-2 assume !(0 == ~T1_E~0); 49127#L1291-1 assume !(0 == ~T2_E~0); 49128#L1296-1 assume !(0 == ~T3_E~0); 49833#L1301-1 assume !(0 == ~T4_E~0); 49834#L1306-1 assume !(0 == ~T5_E~0); 50334#L1311-1 assume !(0 == ~T6_E~0); 49087#L1316-1 assume !(0 == ~T7_E~0); 49088#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49853#L1326-1 assume !(0 == ~T9_E~0); 48902#L1331-1 assume !(0 == ~T10_E~0); 48608#L1336-1 assume !(0 == ~T11_E~0); 48609#L1341-1 assume !(0 == ~T12_E~0); 48660#L1346-1 assume !(0 == ~T13_E~0); 48661#L1351-1 assume !(0 == ~E_M~0); 49034#L1356-1 assume !(0 == ~E_1~0); 49035#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 50554#L1366-1 assume !(0 == ~E_3~0); 49080#L1371-1 assume !(0 == ~E_4~0); 49081#L1376-1 assume !(0 == ~E_5~0); 49894#L1381-1 assume !(0 == ~E_6~0); 49895#L1386-1 assume !(0 == ~E_7~0); 50582#L1391-1 assume !(0 == ~E_8~0); 50595#L1396-1 assume !(0 == ~E_9~0); 49777#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 49778#L1406-1 assume !(0 == ~E_11~0); 50080#L1411-1 assume !(0 == ~E_12~0); 50081#L1416-1 assume !(0 == ~E_13~0); 49701#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49539#L635 assume !(1 == ~m_pc~0); 48678#L635-2 is_master_triggered_~__retres1~0#1 := 0; 48679#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49029#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49665#L1598 assume !(0 != activate_threads_~tmp~1#1); 48857#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48858#L654 assume 1 == ~t1_pc~0; 49563#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49564#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50579#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49645#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 49646#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48905#L673 assume 1 == ~t2_pc~0; 48906#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50050#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50051#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50609#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 50616#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49724#L692 assume !(1 == ~t3_pc~0); 49541#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49542#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49401#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49369#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49370#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48930#L711 assume 1 == ~t4_pc~0; 48931#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49414#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49871#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48633#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 48634#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50602#L730 assume !(1 == ~t5_pc~0); 49984#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 48812#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48813#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48940#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 48941#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49283#L749 assume 1 == ~t6_pc~0; 49057#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48817#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49249#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49250#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 49472#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48613#L768 assume !(1 == ~t7_pc~0); 48614#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49918#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48850#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48851#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 49937#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49089#L787 assume 1 == ~t8_pc~0; 49090#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50285#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50449#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50450#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 48658#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48659#L806 assume 1 == ~t9_pc~0; 50296#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48693#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48694#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48942#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 48943#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50279#L825 assume !(1 == ~t10_pc~0); 50280#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49885#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49886#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49030#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49031#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49614#L844 assume 1 == ~t11_pc~0; 49304#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49305#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49671#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49672#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 50267#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50268#L863 assume !(1 == ~t12_pc~0); 48793#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 48792#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49020#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50359#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 50360#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49738#L882 assume 1 == ~t13_pc~0; 49739#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50023#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50524#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50327#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 50010#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50011#L1434 assume !(1 == ~M_E~0); 50532#L1434-2 assume !(1 == ~T1_E~0); 50608#L1439-1 assume !(1 == ~T2_E~0); 48923#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48924#L1449-1 assume !(1 == ~T4_E~0); 49366#L1454-1 assume !(1 == ~T5_E~0); 49367#L1459-1 assume !(1 == ~T6_E~0); 49938#L1464-1 assume !(1 == ~T7_E~0); 49939#L1469-1 assume !(1 == ~T8_E~0); 50024#L1474-1 assume !(1 == ~T9_E~0); 49702#L1479-1 assume !(1 == ~T10_E~0); 49703#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49946#L1489-1 assume !(1 == ~T12_E~0); 49580#L1494-1 assume !(1 == ~T13_E~0); 49581#L1499-1 assume !(1 == ~E_M~0); 49762#L1504-1 assume !(1 == ~E_1~0); 49763#L1509-1 assume !(1 == ~E_2~0); 50376#L1514-1 assume !(1 == ~E_3~0); 50061#L1519-1 assume !(1 == ~E_4~0); 50062#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 50566#L1529-1 assume !(1 == ~E_6~0); 50567#L1534-1 assume !(1 == ~E_7~0); 48713#L1539-1 assume !(1 == ~E_8~0); 48714#L1544-1 assume !(1 == ~E_9~0); 49144#L1549-1 assume !(1 == ~E_10~0); 50544#L1554-1 assume !(1 == ~E_11~0); 50542#L1559-1 assume !(1 == ~E_12~0); 50404#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 50405#L1569-1 assume { :end_inline_reset_delta_events } true; 50560#L1935-2 [2021-11-19 04:23:45,961 INFO L793 eck$LassoCheckResult]: Loop: 50560#L1935-2 assume !false; 48722#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48723#L1261 assume !false; 49950#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49951#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48853#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49023#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49024#L1074 assume !(0 != eval_~tmp~0#1); 49381#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49979#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50380#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50436#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50155#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50156#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50592#L1301-3 assume !(0 == ~T4_E~0); 50550#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49658#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 48957#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 48958#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49063#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 49799#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 50064#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 50065#L1341-3 assume !(0 == ~T12_E~0); 49359#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 49350#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 49294#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49295#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49875#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48648#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48649#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50391#L1381-3 assume !(0 == ~E_6~0); 50240#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50241#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50422#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50423#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49028#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 48859#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 48860#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 49487#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48737#L635-45 assume 1 == ~m_pc~0; 48738#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49532#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50012#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50266#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49046#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49047#L654-45 assume 1 == ~t1_pc~0; 49867#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50215#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48700#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48701#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48726#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49553#L673-45 assume !(1 == ~t2_pc~0); 49554#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 49878#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49879#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50504#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 50324#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49171#L692-45 assume !(1 == ~t3_pc~0); 48897#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 48898#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49942#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49225#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49226#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49538#L711-45 assume !(1 == ~t4_pc~0); 49664#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 49663#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49515#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49516#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49919#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49070#L730-45 assume 1 == ~t5_pc~0; 48908#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48909#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49318#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49319#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50070#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48881#L749-45 assume !(1 == ~t6_pc~0); 48882#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 50282#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50045#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50046#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50197#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49197#L768-45 assume 1 == ~t7_pc~0; 49198#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49337#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50141#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50142#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50181#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50182#L787-45 assume 1 == ~t8_pc~0; 50350#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49343#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49344#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49760#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49761#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50069#L806-45 assume 1 == ~t9_pc~0; 50545#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48757#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49582#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49410#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49322#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49323#L825-45 assume !(1 == ~t10_pc~0); 49846#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 49847#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49952#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49953#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50105#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48965#L844-45 assume !(1 == ~t11_pc~0); 48966#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 49488#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49489#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49505#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 49916#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49005#L863-45 assume 1 == ~t12_pc~0; 49006#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 48606#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48607#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 49122#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49123#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49922#L882-45 assume 1 == ~t13_pc~0; 50276#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 48625#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 48626#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 49234#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50413#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50029#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50030#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50214#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48919#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48920#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49082#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50019#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50020#L1464-3 assume !(1 == ~T7_E~0); 50466#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50393#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50394#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50468#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49660#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 49661#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50321#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49956#L1504-3 assume !(1 == ~E_1~0); 49957#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50402#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50442#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49583#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49584#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50489#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49884#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49338#L1544-3 assume !(1 == ~E_9~0); 49339#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49854#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 48970#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 48971#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50120#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50121#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48855#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49420#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 50091#L1954 assume !(0 == start_simulation_~tmp~3#1); 50093#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50343#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49138#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50179#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 50309#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50310#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50400#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 50462#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 50560#L1935-2 [2021-11-19 04:23:45,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:45,962 INFO L85 PathProgramCache]: Analyzing trace with hash 10886919, now seen corresponding path program 1 times [2021-11-19 04:23:45,963 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:45,963 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1878821952] [2021-11-19 04:23:45,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:45,963 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:45,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:45,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:45,997 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:45,997 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1878821952] [2021-11-19 04:23:45,997 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1878821952] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:45,997 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:45,997 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:45,998 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [588682417] [2021-11-19 04:23:45,998 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:45,999 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:45,999 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:45,999 INFO L85 PathProgramCache]: Analyzing trace with hash 2007173988, now seen corresponding path program 1 times [2021-11-19 04:23:46,000 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:46,000 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1429327779] [2021-11-19 04:23:46,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:46,000 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:46,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:46,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:46,047 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:46,048 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1429327779] [2021-11-19 04:23:46,048 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1429327779] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:46,048 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:46,048 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:46,048 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [800853742] [2021-11-19 04:23:46,049 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:46,049 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:46,050 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:46,050 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 04:23:46,050 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 04:23:46,050 INFO L87 Difference]: Start difference. First operand 2021 states and 2981 transitions. cyclomatic complexity: 961 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:46,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:46,084 INFO L93 Difference]: Finished difference Result 2021 states and 2980 transitions. [2021-11-19 04:23:46,084 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 04:23:46,086 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2980 transitions. [2021-11-19 04:23:46,098 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:46,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2980 transitions. [2021-11-19 04:23:46,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-11-19 04:23:46,120 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-11-19 04:23:46,120 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2980 transitions. [2021-11-19 04:23:46,123 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:46,124 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2980 transitions. [2021-11-19 04:23:46,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2980 transitions. [2021-11-19 04:23:46,157 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-11-19 04:23:46,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4745175655616032) internal successors, (2980), 2020 states have internal predecessors, (2980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:46,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2980 transitions. [2021-11-19 04:23:46,167 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2980 transitions. [2021-11-19 04:23:46,167 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2980 transitions. [2021-11-19 04:23:46,168 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-19 04:23:46,168 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2980 transitions. [2021-11-19 04:23:46,175 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-11-19 04:23:46,176 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:46,176 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:46,179 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:46,179 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:46,180 INFO L791 eck$LassoCheckResult]: Stem: 53529#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 53530#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 53261#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53262#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54652#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 54653#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53448#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53449#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53483#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54320#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54321#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54433#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 54434#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53267#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 53268#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 54470#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53792#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 53793#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 54374#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54640#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 54530#L1286-2 assume !(0 == ~T1_E~0); 53176#L1291-1 assume !(0 == ~T2_E~0); 53177#L1296-1 assume !(0 == ~T3_E~0); 53882#L1301-1 assume !(0 == ~T4_E~0); 53883#L1306-1 assume !(0 == ~T5_E~0); 54383#L1311-1 assume !(0 == ~T6_E~0); 53136#L1316-1 assume !(0 == ~T7_E~0); 53137#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53902#L1326-1 assume !(0 == ~T9_E~0); 52951#L1331-1 assume !(0 == ~T10_E~0); 52657#L1336-1 assume !(0 == ~T11_E~0); 52658#L1341-1 assume !(0 == ~T12_E~0); 52709#L1346-1 assume !(0 == ~T13_E~0); 52710#L1351-1 assume !(0 == ~E_M~0); 53083#L1356-1 assume !(0 == ~E_1~0); 53084#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 54603#L1366-1 assume !(0 == ~E_3~0); 53129#L1371-1 assume !(0 == ~E_4~0); 53130#L1376-1 assume !(0 == ~E_5~0); 53943#L1381-1 assume !(0 == ~E_6~0); 53944#L1386-1 assume !(0 == ~E_7~0); 54631#L1391-1 assume !(0 == ~E_8~0); 54644#L1396-1 assume !(0 == ~E_9~0); 53826#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 53827#L1406-1 assume !(0 == ~E_11~0); 54129#L1411-1 assume !(0 == ~E_12~0); 54130#L1416-1 assume !(0 == ~E_13~0); 53750#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53588#L635 assume !(1 == ~m_pc~0); 52727#L635-2 is_master_triggered_~__retres1~0#1 := 0; 52728#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53078#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53714#L1598 assume !(0 != activate_threads_~tmp~1#1); 52906#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52907#L654 assume 1 == ~t1_pc~0; 53612#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53613#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54628#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53694#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 53695#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52954#L673 assume 1 == ~t2_pc~0; 52955#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54099#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54100#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54658#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 54665#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53773#L692 assume !(1 == ~t3_pc~0); 53590#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53591#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53450#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53418#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53419#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52979#L711 assume 1 == ~t4_pc~0; 52980#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53463#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53920#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52682#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 52683#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54651#L730 assume !(1 == ~t5_pc~0); 54033#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52861#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52862#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52989#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 52990#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53332#L749 assume 1 == ~t6_pc~0; 53106#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52866#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53298#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53299#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 53521#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52662#L768 assume !(1 == ~t7_pc~0); 52663#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53967#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52899#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52900#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 53986#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53138#L787 assume 1 == ~t8_pc~0; 53139#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54334#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54498#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54499#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 52707#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52708#L806 assume 1 == ~t9_pc~0; 54345#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52742#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52743#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52991#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 52992#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54328#L825 assume !(1 == ~t10_pc~0); 54329#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53934#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53935#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53079#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53080#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53663#L844 assume 1 == ~t11_pc~0; 53353#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53354#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53720#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53721#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 54316#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54317#L863 assume !(1 == ~t12_pc~0); 52842#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 52841#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53069#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54408#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 54409#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53787#L882 assume 1 == ~t13_pc~0; 53788#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 54072#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54573#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54376#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 54059#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54060#L1434 assume !(1 == ~M_E~0); 54581#L1434-2 assume !(1 == ~T1_E~0); 54657#L1439-1 assume !(1 == ~T2_E~0); 52972#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52973#L1449-1 assume !(1 == ~T4_E~0); 53415#L1454-1 assume !(1 == ~T5_E~0); 53416#L1459-1 assume !(1 == ~T6_E~0); 53987#L1464-1 assume !(1 == ~T7_E~0); 53988#L1469-1 assume !(1 == ~T8_E~0); 54073#L1474-1 assume !(1 == ~T9_E~0); 53751#L1479-1 assume !(1 == ~T10_E~0); 53752#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53995#L1489-1 assume !(1 == ~T12_E~0); 53629#L1494-1 assume !(1 == ~T13_E~0); 53630#L1499-1 assume !(1 == ~E_M~0); 53811#L1504-1 assume !(1 == ~E_1~0); 53812#L1509-1 assume !(1 == ~E_2~0); 54425#L1514-1 assume !(1 == ~E_3~0); 54110#L1519-1 assume !(1 == ~E_4~0); 54111#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54615#L1529-1 assume !(1 == ~E_6~0); 54616#L1534-1 assume !(1 == ~E_7~0); 52762#L1539-1 assume !(1 == ~E_8~0); 52763#L1544-1 assume !(1 == ~E_9~0); 53193#L1549-1 assume !(1 == ~E_10~0); 54593#L1554-1 assume !(1 == ~E_11~0); 54591#L1559-1 assume !(1 == ~E_12~0); 54453#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 54454#L1569-1 assume { :end_inline_reset_delta_events } true; 54609#L1935-2 [2021-11-19 04:23:46,180 INFO L793 eck$LassoCheckResult]: Loop: 54609#L1935-2 assume !false; 52771#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52772#L1261 assume !false; 53999#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54000#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52902#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53072#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53073#L1074 assume !(0 != eval_~tmp~0#1); 53430#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54028#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54429#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54485#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54204#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54205#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54641#L1301-3 assume !(0 == ~T4_E~0); 54599#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53707#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53006#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53007#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53112#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 53848#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 54113#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 54114#L1341-3 assume !(0 == ~T12_E~0); 53408#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 53399#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53343#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53344#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53924#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52697#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 52698#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54440#L1381-3 assume !(0 == ~E_6~0); 54289#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54290#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 54471#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 54472#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53077#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52908#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 52909#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 53536#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52786#L635-45 assume 1 == ~m_pc~0; 52787#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53581#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54061#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54315#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53095#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53096#L654-45 assume 1 == ~t1_pc~0; 53916#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 54264#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52749#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52750#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52775#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53602#L673-45 assume !(1 == ~t2_pc~0); 53603#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 53927#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53928#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54553#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 54373#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53220#L692-45 assume !(1 == ~t3_pc~0); 52946#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 52947#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53991#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53274#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53275#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53587#L711-45 assume !(1 == ~t4_pc~0); 53713#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 53712#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53564#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53565#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53968#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53119#L730-45 assume 1 == ~t5_pc~0; 52957#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 52958#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53367#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53368#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54119#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52930#L749-45 assume !(1 == ~t6_pc~0); 52931#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 54331#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54094#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54095#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54246#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53246#L768-45 assume !(1 == ~t7_pc~0); 53248#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 53386#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54190#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54191#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54230#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54231#L787-45 assume !(1 == ~t8_pc~0); 54400#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 53392#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53393#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53809#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53810#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54118#L806-45 assume 1 == ~t9_pc~0; 54594#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52806#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53631#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53459#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53371#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53372#L825-45 assume !(1 == ~t10_pc~0); 53895#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 53896#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54001#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54002#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 54154#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53014#L844-45 assume !(1 == ~t11_pc~0); 53015#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 53537#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53538#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53554#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 53965#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53054#L863-45 assume !(1 == ~t12_pc~0); 53056#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 52655#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52656#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 53171#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 53172#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53971#L882-45 assume 1 == ~t13_pc~0; 54325#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 52674#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 52675#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 53283#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 54462#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54078#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54079#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54263#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52968#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52969#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53131#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54068#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54069#L1464-3 assume !(1 == ~T7_E~0); 54515#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54442#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54443#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54517#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53709#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 53710#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 54370#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54005#L1504-3 assume !(1 == ~E_1~0); 54006#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54451#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54491#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53632#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53633#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 54538#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53933#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53387#L1544-3 assume !(1 == ~E_9~0); 53388#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 53903#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53019#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 53020#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 54169#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54170#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52904#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53469#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 54140#L1954 assume !(0 == start_simulation_~tmp~3#1); 54142#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54392#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53187#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 54228#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 54358#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54359#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54449#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 54511#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 54609#L1935-2 [2021-11-19 04:23:46,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:46,183 INFO L85 PathProgramCache]: Analyzing trace with hash -327400631, now seen corresponding path program 1 times [2021-11-19 04:23:46,183 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:46,183 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [773488314] [2021-11-19 04:23:46,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:46,184 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:46,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:46,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:46,229 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:46,229 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [773488314] [2021-11-19 04:23:46,229 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [773488314] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:46,229 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:46,229 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-19 04:23:46,230 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1093417552] [2021-11-19 04:23:46,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:46,232 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:46,233 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:46,233 INFO L85 PathProgramCache]: Analyzing trace with hash -1509066009, now seen corresponding path program 1 times [2021-11-19 04:23:46,233 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:46,233 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1522827979] [2021-11-19 04:23:46,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:46,234 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:46,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:46,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:46,277 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:46,277 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1522827979] [2021-11-19 04:23:46,278 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1522827979] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:46,278 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:46,278 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:46,278 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1184127066] [2021-11-19 04:23:46,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:46,279 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:46,279 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:46,279 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 04:23:46,280 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 04:23:46,280 INFO L87 Difference]: Start difference. First operand 2021 states and 2980 transitions. cyclomatic complexity: 960 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:46,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:46,363 INFO L93 Difference]: Finished difference Result 3767 states and 5538 transitions. [2021-11-19 04:23:46,364 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 04:23:46,365 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3767 states and 5538 transitions. [2021-11-19 04:23:46,384 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3592 [2021-11-19 04:23:46,400 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3767 states to 3767 states and 5538 transitions. [2021-11-19 04:23:46,400 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3767 [2021-11-19 04:23:46,404 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3767 [2021-11-19 04:23:46,405 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3767 states and 5538 transitions. [2021-11-19 04:23:46,412 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:46,412 INFO L681 BuchiCegarLoop]: Abstraction has 3767 states and 5538 transitions. [2021-11-19 04:23:46,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3767 states and 5538 transitions. [2021-11-19 04:23:46,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3767 to 3767. [2021-11-19 04:23:46,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3767 states, 3767 states have (on average 1.4701353862490045) internal successors, (5538), 3766 states have internal predecessors, (5538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:46,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3767 states to 3767 states and 5538 transitions. [2021-11-19 04:23:46,548 INFO L704 BuchiCegarLoop]: Abstraction has 3767 states and 5538 transitions. [2021-11-19 04:23:46,548 INFO L587 BuchiCegarLoop]: Abstraction has 3767 states and 5538 transitions. [2021-11-19 04:23:46,549 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-19 04:23:46,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3767 states and 5538 transitions. [2021-11-19 04:23:46,566 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3592 [2021-11-19 04:23:46,566 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:46,566 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:46,570 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:46,570 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:46,571 INFO L791 eck$LassoCheckResult]: Stem: 59327#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 59328#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 59056#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59057#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60502#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 60503#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59244#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59245#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59279#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60128#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60129#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60246#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 60247#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59062#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59063#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 60286#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59590#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 59591#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 60185#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60487#L1286 assume !(0 == ~M_E~0); 60350#L1286-2 assume !(0 == ~T1_E~0); 58971#L1291-1 assume !(0 == ~T2_E~0); 58972#L1296-1 assume !(0 == ~T3_E~0); 59682#L1301-1 assume !(0 == ~T4_E~0); 59683#L1306-1 assume !(0 == ~T5_E~0); 60194#L1311-1 assume !(0 == ~T6_E~0); 58931#L1316-1 assume !(0 == ~T7_E~0); 58932#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59702#L1326-1 assume !(0 == ~T9_E~0); 58746#L1331-1 assume !(0 == ~T10_E~0); 58452#L1336-1 assume !(0 == ~T11_E~0); 58453#L1341-1 assume !(0 == ~T12_E~0); 58504#L1346-1 assume !(0 == ~T13_E~0); 58505#L1351-1 assume !(0 == ~E_M~0); 58878#L1356-1 assume !(0 == ~E_1~0); 58879#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 60437#L1366-1 assume !(0 == ~E_3~0); 58924#L1371-1 assume !(0 == ~E_4~0); 58925#L1376-1 assume !(0 == ~E_5~0); 59745#L1381-1 assume !(0 == ~E_6~0); 59746#L1386-1 assume !(0 == ~E_7~0); 60475#L1391-1 assume !(0 == ~E_8~0); 60493#L1396-1 assume !(0 == ~E_9~0); 59624#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 59625#L1406-1 assume !(0 == ~E_11~0); 59933#L1411-1 assume !(0 == ~E_12~0); 59934#L1416-1 assume !(0 == ~E_13~0); 59548#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59386#L635 assume !(1 == ~m_pc~0); 58522#L635-2 is_master_triggered_~__retres1~0#1 := 0; 58523#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58875#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59512#L1598 assume !(0 != activate_threads_~tmp~1#1); 58701#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58702#L654 assume 1 == ~t1_pc~0; 59410#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59411#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60471#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59492#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 59493#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58752#L673 assume 1 == ~t2_pc~0; 58753#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59902#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59903#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60508#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 60516#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59571#L692 assume !(1 == ~t3_pc~0); 59388#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59389#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59248#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59213#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59214#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58774#L711 assume 1 == ~t4_pc~0; 58775#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59259#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59720#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58477#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 58478#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60501#L730 assume !(1 == ~t5_pc~0); 59836#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 58656#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58657#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58784#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 58785#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59127#L749 assume 1 == ~t6_pc~0; 58901#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 58664#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59093#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59094#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 59319#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58459#L768 assume !(1 == ~t7_pc~0); 58460#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 59769#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58694#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58695#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 59788#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58933#L787 assume 1 == ~t8_pc~0; 58934#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60145#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60315#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 60316#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 58502#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58503#L806 assume 1 == ~t9_pc~0; 60156#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58537#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58538#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58786#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 58787#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60139#L825 assume !(1 == ~t10_pc~0); 60140#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 59735#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59736#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58876#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 58877#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59461#L844 assume 1 == ~t11_pc~0; 59150#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 59151#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59518#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 59519#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 60124#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 60125#L863 assume !(1 == ~t12_pc~0); 58639#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 58638#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58864#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 60221#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 60222#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 59585#L882 assume 1 == ~t13_pc~0; 59586#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59875#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 60397#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 60187#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 59862#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59863#L1434 assume !(1 == ~M_E~0); 60410#L1434-2 assume !(1 == ~T1_E~0); 60507#L1439-1 assume !(1 == ~T2_E~0); 58767#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58768#L1449-1 assume !(1 == ~T4_E~0); 59211#L1454-1 assume !(1 == ~T5_E~0); 59212#L1459-1 assume !(1 == ~T6_E~0); 59789#L1464-1 assume !(1 == ~T7_E~0); 59790#L1469-1 assume !(1 == ~T8_E~0); 59876#L1474-1 assume !(1 == ~T9_E~0); 59549#L1479-1 assume !(1 == ~T10_E~0); 59550#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59797#L1489-1 assume !(1 == ~T12_E~0); 59427#L1494-1 assume !(1 == ~T13_E~0); 59428#L1499-1 assume !(1 == ~E_M~0); 59609#L1504-1 assume !(1 == ~E_1~0); 59610#L1509-1 assume !(1 == ~E_2~0); 60238#L1514-1 assume !(1 == ~E_3~0); 59913#L1519-1 assume !(1 == ~E_4~0); 59914#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 60456#L1529-1 assume !(1 == ~E_6~0); 60457#L1534-1 assume !(1 == ~E_7~0); 58557#L1539-1 assume !(1 == ~E_8~0); 58558#L1544-1 assume !(1 == ~E_9~0); 58988#L1549-1 assume !(1 == ~E_10~0); 60425#L1554-1 assume !(1 == ~E_11~0); 60423#L1559-1 assume !(1 == ~E_12~0); 60269#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 60270#L1569-1 assume { :end_inline_reset_delta_events } true; 60449#L1935-2 [2021-11-19 04:23:46,571 INFO L793 eck$LassoCheckResult]: Loop: 60449#L1935-2 assume !false; 60556#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60469#L1261 assume !false; 59804#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59805#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58697#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58868#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 58869#L1074 assume !(0 != eval_~tmp~0#1); 59225#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59831#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60242#L1286-3 assume !(0 == ~M_E~0); 60303#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62201#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 62200#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62199#L1301-3 assume !(0 == ~T4_E~0); 62198#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 62197#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 62196#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 62195#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 62194#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 62193#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 62192#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 62191#L1341-3 assume !(0 == ~T12_E~0); 62190#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 62189#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 62188#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62187#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62186#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62185#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 62184#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62183#L1381-3 assume !(0 == ~E_6~0); 62182#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62181#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 62180#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 62179#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 62178#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 62177#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 62176#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 62175#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62174#L635-45 assume 1 == ~m_pc~0; 62172#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 62171#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62170#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62169#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 62168#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62167#L654-45 assume !(1 == ~t1_pc~0); 62165#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 62164#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62163#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62162#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62161#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62160#L673-45 assume 1 == ~t2_pc~0; 62158#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62157#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62156#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62155#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 62154#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62153#L692-45 assume 1 == ~t3_pc~0; 62151#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 62150#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62149#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62148#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62147#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62146#L711-45 assume 1 == ~t4_pc~0; 62144#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 62143#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62142#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62141#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62140#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62139#L730-45 assume 1 == ~t5_pc~0; 62137#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 62136#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62135#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62134#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62133#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62132#L749-45 assume !(1 == ~t6_pc~0); 62130#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 62129#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62128#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62127#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62126#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62125#L768-45 assume 1 == ~t7_pc~0; 62123#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62122#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62121#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62120#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 62119#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62118#L787-45 assume !(1 == ~t8_pc~0); 62116#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 62115#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62114#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62113#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 62112#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62111#L806-45 assume 1 == ~t9_pc~0; 62109#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62108#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62107#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62106#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 61679#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 61678#L825-45 assume !(1 == ~t10_pc~0); 61676#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 61675#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61674#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 61673#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 61672#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61671#L844-45 assume 1 == ~t11_pc~0; 61669#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 61668#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61667#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 61666#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 61665#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 61664#L863-45 assume 1 == ~t12_pc~0; 61662#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 61661#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61660#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 61659#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 61658#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 61657#L882-45 assume !(1 == ~t13_pc~0); 61655#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 61654#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 61653#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 61652#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 61651#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59881#L1434-3 assume !(1 == ~M_E~0); 59882#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 60069#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58763#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58764#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58926#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 59871#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 59872#L1464-3 assume !(1 == ~T7_E~0); 60335#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 60255#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60256#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 60337#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59507#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 59508#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 60181#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59808#L1504-3 assume !(1 == ~E_1~0); 59809#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 60265#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 60307#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59430#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 59431#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 60358#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 59731#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 59182#L1544-3 assume !(1 == ~E_9~0); 59183#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 59703#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 58814#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 58815#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 60201#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 61482#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 61472#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 61471#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 61470#L1954 assume !(0 == start_simulation_~tmp~3#1); 61467#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 60853#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 60843#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 60626#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 60587#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60579#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60573#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 60565#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 60449#L1935-2 [2021-11-19 04:23:46,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:46,572 INFO L85 PathProgramCache]: Analyzing trace with hash -867830137, now seen corresponding path program 1 times [2021-11-19 04:23:46,572 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:46,573 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [317471950] [2021-11-19 04:23:46,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:46,573 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:46,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:46,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:46,621 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:46,621 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [317471950] [2021-11-19 04:23:46,621 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [317471950] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:46,621 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:46,621 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:46,622 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1714574026] [2021-11-19 04:23:46,622 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:46,622 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:46,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:46,623 INFO L85 PathProgramCache]: Analyzing trace with hash 627302755, now seen corresponding path program 1 times [2021-11-19 04:23:46,623 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:46,623 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2144648420] [2021-11-19 04:23:46,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:46,624 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:46,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:46,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:46,670 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:46,671 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2144648420] [2021-11-19 04:23:46,671 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2144648420] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:46,672 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:46,672 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:46,673 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205654831] [2021-11-19 04:23:46,673 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:46,673 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:46,674 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:46,674 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-19 04:23:46,674 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-19 04:23:46,675 INFO L87 Difference]: Start difference. First operand 3767 states and 5538 transitions. cyclomatic complexity: 1772 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:46,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:46,877 INFO L93 Difference]: Finished difference Result 7386 states and 10848 transitions. [2021-11-19 04:23:46,877 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-19 04:23:46,878 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7386 states and 10848 transitions. [2021-11-19 04:23:46,914 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7184 [2021-11-19 04:23:46,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7386 states to 7386 states and 10848 transitions. [2021-11-19 04:23:46,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7386 [2021-11-19 04:23:46,952 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7386 [2021-11-19 04:23:46,952 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7386 states and 10848 transitions. [2021-11-19 04:23:46,963 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:46,963 INFO L681 BuchiCegarLoop]: Abstraction has 7386 states and 10848 transitions. [2021-11-19 04:23:46,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7386 states and 10848 transitions. [2021-11-19 04:23:47,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7386 to 7386. [2021-11-19 04:23:47,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7386 states, 7386 states have (on average 1.4687246141348498) internal successors, (10848), 7385 states have internal predecessors, (10848), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:47,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7386 states to 7386 states and 10848 transitions. [2021-11-19 04:23:47,127 INFO L704 BuchiCegarLoop]: Abstraction has 7386 states and 10848 transitions. [2021-11-19 04:23:47,127 INFO L587 BuchiCegarLoop]: Abstraction has 7386 states and 10848 transitions. [2021-11-19 04:23:47,127 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-19 04:23:47,128 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7386 states and 10848 transitions. [2021-11-19 04:23:47,159 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7184 [2021-11-19 04:23:47,159 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:47,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:47,163 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:47,163 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:47,164 INFO L791 eck$LassoCheckResult]: Stem: 70491#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 70492#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 70223#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 70224#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 71768#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 71769#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 70410#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 70411#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 70445#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 71317#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 71318#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 71462#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 71463#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 70229#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 70230#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 71506#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 70759#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 70760#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 71382#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 71751#L1286 assume !(0 == ~M_E~0); 71585#L1286-2 assume !(0 == ~T1_E~0); 70137#L1291-1 assume !(0 == ~T2_E~0); 70138#L1296-1 assume !(0 == ~T3_E~0); 70852#L1301-1 assume !(0 == ~T4_E~0); 70853#L1306-1 assume !(0 == ~T5_E~0); 71392#L1311-1 assume !(0 == ~T6_E~0); 70095#L1316-1 assume !(0 == ~T7_E~0); 70096#L1321-1 assume !(0 == ~T8_E~0); 70871#L1326-1 assume !(0 == ~T9_E~0); 69909#L1331-1 assume !(0 == ~T10_E~0); 69615#L1336-1 assume !(0 == ~T11_E~0); 69616#L1341-1 assume !(0 == ~T12_E~0); 69667#L1346-1 assume !(0 == ~T13_E~0); 69668#L1351-1 assume !(0 == ~E_M~0); 70042#L1356-1 assume !(0 == ~E_1~0); 70043#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 71690#L1366-1 assume !(0 == ~E_3~0); 70088#L1371-1 assume !(0 == ~E_4~0); 70089#L1376-1 assume !(0 == ~E_5~0); 70915#L1381-1 assume !(0 == ~E_6~0); 70916#L1386-1 assume !(0 == ~E_7~0); 71734#L1391-1 assume !(0 == ~E_8~0); 71757#L1396-1 assume !(0 == ~E_9~0); 70793#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 70794#L1406-1 assume !(0 == ~E_11~0); 71107#L1411-1 assume !(0 == ~E_12~0); 71108#L1416-1 assume !(0 == ~E_13~0); 70716#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70554#L635 assume !(1 == ~m_pc~0); 69687#L635-2 is_master_triggered_~__retres1~0#1 := 0; 69688#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70039#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 70680#L1598 assume !(0 != activate_threads_~tmp~1#1); 69864#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69865#L654 assume 1 == ~t1_pc~0; 70578#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 70579#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 71727#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70660#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 70661#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69915#L673 assume 1 == ~t2_pc~0; 69916#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 71076#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 71077#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 71776#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 71784#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70740#L692 assume !(1 == ~t3_pc~0); 70556#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 70557#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70414#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 70380#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 70381#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69937#L711 assume 1 == ~t4_pc~0; 69938#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 70425#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70889#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69640#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 69641#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 71766#L730 assume !(1 == ~t5_pc~0); 71008#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 69819#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69820#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69947#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 69948#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70294#L749 assume 1 == ~t6_pc~0; 70065#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69829#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70260#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 70261#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 70483#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69622#L768 assume !(1 == ~t7_pc~0); 69623#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 70938#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69857#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69858#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 70958#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70097#L787 assume 1 == ~t8_pc~0; 70098#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 71336#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 71543#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 71544#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 69665#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69666#L806 assume 1 == ~t9_pc~0; 71348#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 69700#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69701#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69949#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 69950#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 71328#L825 assume !(1 == ~t10_pc~0); 71329#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 70903#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 70904#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 70040#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 70041#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 70629#L844 assume 1 == ~t11_pc~0; 70317#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 70318#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 70686#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 70687#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 71312#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 71313#L863 assume !(1 == ~t12_pc~0); 69804#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 69803#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 70030#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 71425#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 71426#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 70754#L882 assume 1 == ~t13_pc~0; 70755#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 71049#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 71638#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 71384#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 71036#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71037#L1434 assume !(1 == ~M_E~0); 71654#L1434-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 71773#L1439-1 assume !(1 == ~T2_E~0); 69930#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69931#L1449-1 assume !(1 == ~T4_E~0); 70378#L1454-1 assume !(1 == ~T5_E~0); 70379#L1459-1 assume !(1 == ~T6_E~0); 70959#L1464-1 assume !(1 == ~T7_E~0); 70960#L1469-1 assume !(1 == ~T8_E~0); 71052#L1474-1 assume !(1 == ~T9_E~0); 70717#L1479-1 assume !(1 == ~T10_E~0); 70718#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 70968#L1489-1 assume !(1 == ~T12_E~0); 70595#L1494-1 assume !(1 == ~T13_E~0); 70596#L1499-1 assume !(1 == ~E_M~0); 70778#L1504-1 assume !(1 == ~E_1~0); 70779#L1509-1 assume !(1 == ~E_2~0); 71447#L1514-1 assume !(1 == ~E_3~0); 71087#L1519-1 assume !(1 == ~E_4~0); 71088#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 71707#L1529-1 assume !(1 == ~E_6~0); 71708#L1534-1 assume !(1 == ~E_7~0); 69722#L1539-1 assume !(1 == ~E_8~0); 69723#L1544-1 assume !(1 == ~E_9~0); 70155#L1549-1 assume !(1 == ~E_10~0); 71673#L1554-1 assume !(1 == ~E_11~0); 71670#L1559-1 assume !(1 == ~E_12~0); 71671#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 71698#L1569-1 assume { :end_inline_reset_delta_events } true; 71699#L1935-2 [2021-11-19 04:23:47,165 INFO L793 eck$LassoCheckResult]: Loop: 71699#L1935-2 assume !false; 71855#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 71725#L1261 assume !false; 70975#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 70976#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 69860#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 72932#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 72930#L1074 assume !(0 != eval_~tmp~0#1); 72928#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 71456#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 71457#L1286-3 assume !(0 == ~M_E~0); 72925#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 72926#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 76579#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 76578#L1301-3 assume !(0 == ~T4_E~0); 76577#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 76576#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 76575#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 76574#L1321-3 assume !(0 == ~T8_E~0); 76573#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 76572#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 76571#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 76570#L1341-3 assume !(0 == ~T12_E~0); 76569#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 76568#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 76567#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 76566#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 76565#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76564#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 76563#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 76562#L1381-3 assume !(0 == ~E_6~0); 76561#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 76560#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 76559#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 76558#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 76557#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 76556#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 76555#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 76554#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76553#L635-45 assume 1 == ~m_pc~0; 76551#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 76550#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76549#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76548#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 76547#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76546#L654-45 assume 1 == ~t1_pc~0; 74873#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 74871#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74870#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 74869#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 71584#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70568#L673-45 assume !(1 == ~t2_pc~0); 70569#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 70896#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70897#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 71611#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 71381#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70182#L692-45 assume !(1 == ~t3_pc~0); 69907#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 69908#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70963#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 70236#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 70237#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70553#L711-45 assume 1 == ~t4_pc~0; 70677#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 70678#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70527#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 70528#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70940#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70078#L730-45 assume 1 == ~t5_pc~0; 69912#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 69913#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70329#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 70330#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 71096#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69888#L749-45 assume !(1 == ~t6_pc~0); 69889#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 71332#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 71071#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 71072#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 71229#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 70208#L768-45 assume 1 == ~t7_pc~0; 70209#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 70352#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 71168#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 71169#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 71209#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 71210#L787-45 assume !(1 == ~t8_pc~0); 71413#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 70354#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 70355#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 70776#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 70777#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 71095#L806-45 assume !(1 == ~t9_pc~0); 69766#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 69767#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 70597#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 70421#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 70333#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 70334#L825-45 assume !(1 == ~t10_pc~0); 70864#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 70865#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 70973#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 70974#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 71130#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69968#L844-45 assume !(1 == ~t11_pc~0); 69969#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 70499#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 70500#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 70516#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 70935#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 70009#L863-45 assume !(1 == ~t12_pc~0); 70011#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 69613#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 69614#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 70129#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 70130#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 70941#L882-45 assume 1 == ~t13_pc~0; 71323#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 69632#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 69633#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 70245#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 71497#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71055#L1434-3 assume !(1 == ~M_E~0); 71056#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 71247#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69926#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69927#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 70090#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 71045#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 71046#L1464-3 assume !(1 == ~T7_E~0); 71566#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 71472#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 71473#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 71568#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 70675#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 70676#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 71378#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 70977#L1504-3 assume !(1 == ~E_1~0); 70978#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 72632#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 72631#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 72630#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 72629#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 72628#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 72627#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 72626#L1544-3 assume !(1 == ~E_9~0); 72625#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 72624#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 72623#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 72622#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 72620#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 72621#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 74317#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 74316#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 72026#L1954 assume !(0 == start_simulation_~tmp~3#1); 72022#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 72023#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 72991#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 72990#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 72989#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 72988#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 72987#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 71863#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 71699#L1935-2 [2021-11-19 04:23:47,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:47,166 INFO L85 PathProgramCache]: Analyzing trace with hash -1975797497, now seen corresponding path program 1 times [2021-11-19 04:23:47,166 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:47,166 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1968392611] [2021-11-19 04:23:47,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:47,167 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:47,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:47,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:47,209 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:47,209 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1968392611] [2021-11-19 04:23:47,209 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1968392611] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:47,209 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:47,209 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-19 04:23:47,210 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2083504317] [2021-11-19 04:23:47,210 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:47,210 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:47,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:47,211 INFO L85 PathProgramCache]: Analyzing trace with hash 1749918244, now seen corresponding path program 1 times [2021-11-19 04:23:47,211 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:47,211 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973271857] [2021-11-19 04:23:47,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:47,212 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:47,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:47,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:47,263 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:47,263 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [973271857] [2021-11-19 04:23:47,264 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [973271857] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:47,264 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:47,264 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:47,264 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [721213940] [2021-11-19 04:23:47,264 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:47,265 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:47,265 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:47,265 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 04:23:47,266 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 04:23:47,266 INFO L87 Difference]: Start difference. First operand 7386 states and 10848 transitions. cyclomatic complexity: 3464 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:47,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:47,437 INFO L93 Difference]: Finished difference Result 7386 states and 10774 transitions. [2021-11-19 04:23:47,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 04:23:47,438 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7386 states and 10774 transitions. [2021-11-19 04:23:47,479 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7184 [2021-11-19 04:23:47,512 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7386 states to 7386 states and 10774 transitions. [2021-11-19 04:23:47,512 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7386 [2021-11-19 04:23:47,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7386 [2021-11-19 04:23:47,520 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7386 states and 10774 transitions. [2021-11-19 04:23:47,531 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:47,531 INFO L681 BuchiCegarLoop]: Abstraction has 7386 states and 10774 transitions. [2021-11-19 04:23:47,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7386 states and 10774 transitions. [2021-11-19 04:23:47,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7386 to 7386. [2021-11-19 04:23:47,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7386 states, 7386 states have (on average 1.4587056593555374) internal successors, (10774), 7385 states have internal predecessors, (10774), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:47,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7386 states to 7386 states and 10774 transitions. [2021-11-19 04:23:47,710 INFO L704 BuchiCegarLoop]: Abstraction has 7386 states and 10774 transitions. [2021-11-19 04:23:47,710 INFO L587 BuchiCegarLoop]: Abstraction has 7386 states and 10774 transitions. [2021-11-19 04:23:47,710 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-19 04:23:47,711 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7386 states and 10774 transitions. [2021-11-19 04:23:47,740 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7184 [2021-11-19 04:23:47,741 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:47,741 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:47,745 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:47,745 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:47,746 INFO L791 eck$LassoCheckResult]: Stem: 85270#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 85271#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 85000#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 85001#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86558#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 86559#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85187#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 85188#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 85224#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86106#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86107#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 86230#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 86231#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85006#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 85007#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 86274#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 85539#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 85540#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 86163#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86535#L1286 assume !(0 == ~M_E~0); 86353#L1286-2 assume !(0 == ~T1_E~0); 84915#L1291-1 assume !(0 == ~T2_E~0); 84916#L1296-1 assume !(0 == ~T3_E~0); 85632#L1301-1 assume !(0 == ~T4_E~0); 85633#L1306-1 assume !(0 == ~T5_E~0); 86175#L1311-1 assume !(0 == ~T6_E~0); 84875#L1316-1 assume !(0 == ~T7_E~0); 84876#L1321-1 assume !(0 == ~T8_E~0); 85653#L1326-1 assume !(0 == ~T9_E~0); 84688#L1331-1 assume !(0 == ~T10_E~0); 84394#L1336-1 assume !(0 == ~T11_E~0); 84395#L1341-1 assume !(0 == ~T12_E~0); 84446#L1346-1 assume !(0 == ~T13_E~0); 84447#L1351-1 assume !(0 == ~E_M~0); 84822#L1356-1 assume !(0 == ~E_1~0); 84823#L1361-1 assume !(0 == ~E_2~0); 86475#L1366-1 assume !(0 == ~E_3~0); 84868#L1371-1 assume !(0 == ~E_4~0); 84869#L1376-1 assume !(0 == ~E_5~0); 85696#L1381-1 assume !(0 == ~E_6~0); 85697#L1386-1 assume !(0 == ~E_7~0); 86520#L1391-1 assume !(0 == ~E_8~0); 86543#L1396-1 assume !(0 == ~E_9~0); 85573#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 85574#L1406-1 assume !(0 == ~E_11~0); 85894#L1411-1 assume !(0 == ~E_12~0); 85895#L1416-1 assume !(0 == ~E_13~0); 85497#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85330#L635 assume !(1 == ~m_pc~0); 84464#L635-2 is_master_triggered_~__retres1~0#1 := 0; 84465#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84819#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85460#L1598 assume !(0 != activate_threads_~tmp~1#1); 84643#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84644#L654 assume 1 == ~t1_pc~0; 85353#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85354#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86515#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 85438#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 85439#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84694#L673 assume !(1 == ~t2_pc~0); 84696#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 85860#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85861#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86565#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 86573#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85520#L692 assume !(1 == ~t3_pc~0); 85332#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 85333#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85193#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85156#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 85157#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84716#L711 assume 1 == ~t4_pc~0; 84717#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 85204#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85672#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 84419#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 84420#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86557#L730 assume !(1 == ~t5_pc~0); 85791#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 84598#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 84599#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 84726#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 84727#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85070#L749 assume 1 == ~t6_pc~0; 84845#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 84606#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85036#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85037#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 85262#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 84401#L768 assume !(1 == ~t7_pc~0); 84402#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 85719#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84636#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 84637#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 85738#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 84877#L787 assume 1 == ~t8_pc~0; 84878#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 86122#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 86311#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 86312#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 84444#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 84445#L806 assume 1 == ~t9_pc~0; 86133#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 84479#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 84480#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 84728#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 84729#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86116#L825 assume !(1 == ~t10_pc~0); 86117#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 85686#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85687#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 84820#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 84821#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 85406#L844 assume 1 == ~t11_pc~0; 85093#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85094#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85466#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 85467#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 86100#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86101#L863 assume !(1 == ~t12_pc~0); 84581#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 84580#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 84807#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 86203#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 86204#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 85534#L882 assume 1 == ~t13_pc~0; 85535#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 85832#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86416#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 86166#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 85819#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85820#L1434 assume !(1 == ~M_E~0); 86433#L1434-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86582#L1439-1 assume !(1 == ~T2_E~0); 88290#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 88289#L1449-1 assume !(1 == ~T4_E~0); 88288#L1454-1 assume !(1 == ~T5_E~0); 88287#L1459-1 assume !(1 == ~T6_E~0); 88286#L1464-1 assume !(1 == ~T7_E~0); 88285#L1469-1 assume !(1 == ~T8_E~0); 85835#L1474-1 assume !(1 == ~T9_E~0); 88284#L1479-1 assume !(1 == ~T10_E~0); 88283#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 88282#L1489-1 assume !(1 == ~T12_E~0); 88281#L1494-1 assume !(1 == ~T13_E~0); 88280#L1499-1 assume !(1 == ~E_M~0); 88279#L1504-1 assume !(1 == ~E_1~0); 88278#L1509-1 assume !(1 == ~E_2~0); 88277#L1514-1 assume !(1 == ~E_3~0); 88276#L1519-1 assume !(1 == ~E_4~0); 88275#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 88274#L1529-1 assume !(1 == ~E_6~0); 88273#L1534-1 assume !(1 == ~E_7~0); 88272#L1539-1 assume !(1 == ~E_8~0); 88271#L1544-1 assume !(1 == ~E_9~0); 88270#L1549-1 assume !(1 == ~E_10~0); 88269#L1554-1 assume !(1 == ~E_11~0); 88268#L1559-1 assume !(1 == ~E_12~0); 86255#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 86256#L1569-1 assume { :end_inline_reset_delta_events } true; 88258#L1935-2 [2021-11-19 04:23:47,746 INFO L793 eck$LassoCheckResult]: Loop: 88258#L1935-2 assume !false; 86623#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 86619#L1261 assume !false; 85755#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85756#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 86104#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 86105#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 85167#L1074 assume !(0 != eval_~tmp~0#1); 85169#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 86225#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 86226#L1286-3 assume !(0 == ~M_E~0); 88241#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 88240#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 88239#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 88238#L1301-3 assume !(0 == ~T4_E~0); 88237#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 88236#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 88235#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 88234#L1321-3 assume !(0 == ~T8_E~0); 88233#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 88232#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 88231#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 88230#L1341-3 assume !(0 == ~T12_E~0); 88229#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 88228#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 88227#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 88226#L1361-3 assume !(0 == ~E_2~0); 88225#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 88224#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 88223#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 88222#L1381-3 assume !(0 == ~E_6~0); 88221#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 88220#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 88219#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 88218#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 88217#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 88216#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 88215#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 88214#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88213#L635-45 assume 1 == ~m_pc~0; 88211#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 88210#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88209#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 88208#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 88207#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88206#L654-45 assume 1 == ~t1_pc~0; 88205#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 88203#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88202#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 88201#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 88200#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88199#L673-45 assume !(1 == ~t2_pc~0); 88197#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 88196#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88195#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 88194#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 88193#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88192#L692-45 assume !(1 == ~t3_pc~0); 88191#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 88075#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88074#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 88073#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 88072#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88071#L711-45 assume 1 == ~t4_pc~0; 88069#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 88068#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88067#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 88066#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 88062#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88056#L730-45 assume 1 == ~t5_pc~0; 88053#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 88051#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88050#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 88049#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 88048#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88047#L749-45 assume !(1 == ~t6_pc~0); 88045#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 88044#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88043#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 88042#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 88041#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 88040#L768-45 assume !(1 == ~t7_pc~0); 88039#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 88037#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85960#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 85961#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 86004#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86005#L787-45 assume 1 == ~t8_pc~0; 86193#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 85130#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85131#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 85556#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 85557#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85881#L806-45 assume !(1 == ~t9_pc~0); 86537#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 90174#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 90173#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 90172#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 90171#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 90170#L825-45 assume 1 == ~t10_pc~0; 90169#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 90167#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 90166#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 90165#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 90164#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 90163#L844-45 assume 1 == ~t11_pc~0; 90161#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 90160#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 90159#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 90158#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 90157#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 90156#L863-45 assume !(1 == ~t12_pc~0); 90155#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 90153#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 90152#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 90151#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 90150#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 90149#L882-45 assume 1 == ~t13_pc~0; 86308#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 84411#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 84412#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 85021#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 86266#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85839#L1434-3 assume !(1 == ~M_E~0); 85840#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 87792#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87790#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 87788#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 87786#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 87784#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 87782#L1464-3 assume !(1 == ~T7_E~0); 87780#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 87778#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 87776#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 87774#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 87772#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 87770#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 87768#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 87766#L1504-3 assume !(1 == ~E_1~0); 87764#L1509-3 assume !(1 == ~E_2~0); 87761#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 87762#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 90126#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 90124#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 90122#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 90120#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 90118#L1544-3 assume !(1 == ~E_9~0); 90115#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 90113#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 87751#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 87750#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 87748#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 87749#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 88617#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 88615#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 88612#L1954 assume !(0 == start_simulation_~tmp~3#1); 88609#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 86667#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 86657#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 86655#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 86653#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86652#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86647#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 86648#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 88258#L1935-2 [2021-11-19 04:23:47,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:47,747 INFO L85 PathProgramCache]: Analyzing trace with hash 859519750, now seen corresponding path program 1 times [2021-11-19 04:23:47,748 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:47,748 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [18277789] [2021-11-19 04:23:47,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:47,748 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:47,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:47,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:47,799 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:47,799 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [18277789] [2021-11-19 04:23:47,799 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [18277789] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:47,799 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:47,800 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:47,800 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2017263135] [2021-11-19 04:23:47,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:47,801 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:47,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:47,801 INFO L85 PathProgramCache]: Analyzing trace with hash 850437730, now seen corresponding path program 1 times [2021-11-19 04:23:47,802 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:47,802 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748956123] [2021-11-19 04:23:47,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:47,802 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:47,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:47,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:47,852 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:47,852 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [748956123] [2021-11-19 04:23:47,852 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [748956123] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:47,853 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:47,853 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:47,853 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1233592396] [2021-11-19 04:23:47,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:47,854 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:47,854 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:47,854 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-19 04:23:47,855 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-19 04:23:47,855 INFO L87 Difference]: Start difference. First operand 7386 states and 10774 transitions. cyclomatic complexity: 3390 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:48,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:48,156 INFO L93 Difference]: Finished difference Result 14198 states and 20702 transitions. [2021-11-19 04:23:48,157 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-19 04:23:48,157 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14198 states and 20702 transitions. [2021-11-19 04:23:48,230 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13968 [2021-11-19 04:23:48,291 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14198 states to 14198 states and 20702 transitions. [2021-11-19 04:23:48,291 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14198 [2021-11-19 04:23:48,307 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14198 [2021-11-19 04:23:48,307 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14198 states and 20702 transitions. [2021-11-19 04:23:48,327 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:48,327 INFO L681 BuchiCegarLoop]: Abstraction has 14198 states and 20702 transitions. [2021-11-19 04:23:48,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14198 states and 20702 transitions. [2021-11-19 04:23:48,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14198 to 14194. [2021-11-19 04:23:48,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14194 states, 14194 states have (on average 1.458221783852332) internal successors, (20698), 14193 states have internal predecessors, (20698), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:48,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14194 states to 14194 states and 20698 transitions. [2021-11-19 04:23:48,728 INFO L704 BuchiCegarLoop]: Abstraction has 14194 states and 20698 transitions. [2021-11-19 04:23:48,729 INFO L587 BuchiCegarLoop]: Abstraction has 14194 states and 20698 transitions. [2021-11-19 04:23:48,729 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-19 04:23:48,729 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14194 states and 20698 transitions. [2021-11-19 04:23:48,789 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13968 [2021-11-19 04:23:48,789 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:48,789 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:48,793 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:48,793 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:48,793 INFO L791 eck$LassoCheckResult]: Stem: 106864#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 106865#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 106593#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 106594#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 108149#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 108150#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 106781#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 106782#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 106816#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 107694#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 107695#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 107837#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 107838#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 106599#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 106600#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 107880#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 107137#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 107138#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 107759#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 108131#L1286 assume !(0 == ~M_E~0); 107958#L1286-2 assume !(0 == ~T1_E~0); 106507#L1291-1 assume !(0 == ~T2_E~0); 106508#L1296-1 assume !(0 == ~T3_E~0); 107231#L1301-1 assume !(0 == ~T4_E~0); 107232#L1306-1 assume !(0 == ~T5_E~0); 107772#L1311-1 assume !(0 == ~T6_E~0); 106467#L1316-1 assume !(0 == ~T7_E~0); 106468#L1321-1 assume !(0 == ~T8_E~0); 107250#L1326-1 assume !(0 == ~T9_E~0); 106282#L1331-1 assume !(0 == ~T10_E~0); 105988#L1336-1 assume !(0 == ~T11_E~0); 105989#L1341-1 assume !(0 == ~T12_E~0); 106040#L1346-1 assume !(0 == ~T13_E~0); 106041#L1351-1 assume !(0 == ~E_M~0); 106414#L1356-1 assume !(0 == ~E_1~0); 106415#L1361-1 assume !(0 == ~E_2~0); 108074#L1366-1 assume !(0 == ~E_3~0); 106460#L1371-1 assume !(0 == ~E_4~0); 106461#L1376-1 assume !(0 == ~E_5~0); 107293#L1381-1 assume !(0 == ~E_6~0); 107294#L1386-1 assume !(0 == ~E_7~0); 108117#L1391-1 assume !(0 == ~E_8~0); 108138#L1396-1 assume !(0 == ~E_9~0); 107171#L1401-1 assume !(0 == ~E_10~0); 107172#L1406-1 assume !(0 == ~E_11~0); 107487#L1411-1 assume !(0 == ~E_12~0); 107488#L1416-1 assume !(0 == ~E_13~0); 107094#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106923#L635 assume !(1 == ~m_pc~0); 106060#L635-2 is_master_triggered_~__retres1~0#1 := 0; 106061#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106411#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 107055#L1598 assume !(0 != activate_threads_~tmp~1#1); 106237#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 106238#L654 assume 1 == ~t1_pc~0; 106947#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 106948#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 108113#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 107035#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 107036#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 106288#L673 assume !(1 == ~t2_pc~0); 106290#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 107457#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 107458#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 108158#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 108169#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 107117#L692 assume !(1 == ~t3_pc~0); 106925#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 106926#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 106785#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 106751#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 106752#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 106310#L711 assume 1 == ~t4_pc~0; 106311#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 106796#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 107268#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 106013#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 106014#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 108148#L730 assume !(1 == ~t5_pc~0); 107388#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 106192#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 106193#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 106320#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 106321#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 106664#L749 assume 1 == ~t6_pc~0; 106437#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 106202#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 106630#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 106631#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 106856#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 105995#L768 assume !(1 == ~t7_pc~0); 105996#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 107316#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 106230#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 106231#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 107337#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 106469#L787 assume 1 == ~t8_pc~0; 106470#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 107710#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 107918#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 107919#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 106038#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 106039#L806 assume 1 == ~t9_pc~0; 107721#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 106073#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 106074#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 106322#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 106323#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 107703#L825 assume !(1 == ~t10_pc~0); 107704#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 107282#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 107283#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 106412#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 106413#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 107002#L844 assume 1 == ~t11_pc~0; 106687#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 106688#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 107062#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 107063#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 107690#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 107691#L863 assume !(1 == ~t12_pc~0); 106177#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 106176#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 106402#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 107805#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 107806#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 107132#L882 assume 1 == ~t13_pc~0; 107133#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 107430#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 108021#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 107761#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 107417#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 107418#L1434 assume !(1 == ~M_E~0); 108032#L1434-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 108155#L1439-1 assume !(1 == ~T2_E~0); 108156#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 111608#L1449-1 assume !(1 == ~T4_E~0); 106749#L1454-1 assume !(1 == ~T5_E~0); 106750#L1459-1 assume !(1 == ~T6_E~0); 107338#L1464-1 assume !(1 == ~T7_E~0); 107339#L1469-1 assume !(1 == ~T8_E~0); 107433#L1474-1 assume !(1 == ~T9_E~0); 107095#L1479-1 assume !(1 == ~T10_E~0); 107096#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 107347#L1489-1 assume !(1 == ~T12_E~0); 111371#L1494-1 assume !(1 == ~T13_E~0); 111369#L1499-1 assume !(1 == ~E_M~0); 111366#L1504-1 assume !(1 == ~E_1~0); 108015#L1509-1 assume !(1 == ~E_2~0); 108016#L1514-1 assume !(1 == ~E_3~0); 111234#L1519-1 assume !(1 == ~E_4~0); 111232#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 111230#L1529-1 assume !(1 == ~E_6~0); 111228#L1534-1 assume !(1 == ~E_7~0); 106095#L1539-1 assume !(1 == ~E_8~0); 106096#L1544-1 assume !(1 == ~E_9~0); 111218#L1549-1 assume !(1 == ~E_10~0); 109609#L1554-1 assume !(1 == ~E_11~0); 109575#L1559-1 assume !(1 == ~E_12~0); 109550#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 109532#L1569-1 assume { :end_inline_reset_delta_events } true; 109518#L1935-2 [2021-11-19 04:23:48,794 INFO L793 eck$LassoCheckResult]: Loop: 109518#L1935-2 assume !false; 109507#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 109501#L1261 assume !false; 109500#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 109492#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 109470#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 109468#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 109465#L1074 assume !(0 != eval_~tmp~0#1); 109462#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 109460#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 109457#L1286-3 assume !(0 == ~M_E~0); 109458#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 117328#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 117326#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 117323#L1301-3 assume !(0 == ~T4_E~0); 117321#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 117319#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 117317#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 117315#L1321-3 assume !(0 == ~T8_E~0); 117314#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 117313#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 117309#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 117307#L1341-3 assume !(0 == ~T12_E~0); 117305#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 117304#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 117303#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 117302#L1361-3 assume !(0 == ~E_2~0); 117301#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 117300#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 117299#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 117296#L1381-3 assume !(0 == ~E_6~0); 117294#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 117292#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 117290#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 117288#L1401-3 assume !(0 == ~E_10~0); 117286#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 117284#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 117281#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 117279#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117277#L635-45 assume !(1 == ~m_pc~0); 117275#L635-47 is_master_triggered_~__retres1~0#1 := 0; 117272#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117270#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 114219#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 113546#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 113543#L654-45 assume 1 == ~t1_pc~0; 113541#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 113538#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 113536#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 113534#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 113532#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 113529#L673-45 assume !(1 == ~t2_pc~0); 113526#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 113524#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 113522#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 113520#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 113516#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 113514#L692-45 assume 1 == ~t3_pc~0; 113511#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 113510#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 113509#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 113508#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 113507#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 113506#L711-45 assume !(1 == ~t4_pc~0); 113504#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 113501#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 113499#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 113496#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 113494#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 113492#L730-45 assume 1 == ~t5_pc~0; 113489#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 113487#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 113485#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 113482#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 113480#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 113478#L749-45 assume !(1 == ~t6_pc~0); 113475#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 113473#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 113471#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 113470#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 113469#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 112808#L768-45 assume !(1 == ~t7_pc~0); 112805#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 112802#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 112800#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 112798#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 112796#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 112793#L787-45 assume !(1 == ~t8_pc~0); 112789#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 112787#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 112785#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 112783#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 112781#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 112778#L806-45 assume 1 == ~t9_pc~0; 112775#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 112773#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 112771#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 112769#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 112767#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 112764#L825-45 assume !(1 == ~t10_pc~0); 112761#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 112759#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 112757#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 112755#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 112753#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 112752#L844-45 assume 1 == ~t11_pc~0; 112749#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 112747#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 112744#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 112742#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 112740#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 112737#L863-45 assume !(1 == ~t12_pc~0); 112735#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 112732#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 112730#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 112728#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 112726#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 112724#L882-45 assume 1 == ~t13_pc~0; 112720#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 112717#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 112715#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 112713#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 112712#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112711#L1434-3 assume !(1 == ~M_E~0); 109416#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 112291#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 112289#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 112287#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 112285#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 112283#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 112280#L1464-3 assume !(1 == ~T7_E~0); 112278#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 109302#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 112275#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 112273#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 112030#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 112028#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 112026#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 112024#L1504-3 assume !(1 == ~E_1~0); 112021#L1509-3 assume !(1 == ~E_2~0); 112019#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 112017#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 112015#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 111808#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 111806#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 111804#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 111802#L1544-3 assume !(1 == ~E_9~0); 111801#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 111799#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 111798#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 111797#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 111795#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 111592#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 111582#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 111580#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 111434#L1954 assume !(0 == start_simulation_~tmp~3#1); 111430#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 111347#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 111275#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 111221#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 109610#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 109576#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 109551#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 109533#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 109518#L1935-2 [2021-11-19 04:23:48,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:48,795 INFO L85 PathProgramCache]: Analyzing trace with hash -982955964, now seen corresponding path program 1 times [2021-11-19 04:23:48,795 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:48,796 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [107606031] [2021-11-19 04:23:48,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:48,796 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:48,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:48,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:48,839 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:48,839 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [107606031] [2021-11-19 04:23:48,839 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [107606031] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:48,839 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:48,839 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:48,840 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017485403] [2021-11-19 04:23:48,840 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:48,840 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:48,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:48,841 INFO L85 PathProgramCache]: Analyzing trace with hash 2130703778, now seen corresponding path program 1 times [2021-11-19 04:23:48,841 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:48,841 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [908588651] [2021-11-19 04:23:48,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:48,842 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:48,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:48,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:48,884 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:48,884 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [908588651] [2021-11-19 04:23:48,885 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [908588651] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:48,885 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:48,885 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:48,885 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1596196341] [2021-11-19 04:23:48,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:48,886 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:48,886 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:48,886 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-19 04:23:48,886 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-19 04:23:48,887 INFO L87 Difference]: Start difference. First operand 14194 states and 20698 transitions. cyclomatic complexity: 6508 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:49,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:49,546 INFO L93 Difference]: Finished difference Result 40856 states and 59000 transitions. [2021-11-19 04:23:49,564 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-19 04:23:49,564 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40856 states and 59000 transitions. [2021-11-19 04:23:49,778 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 39792 [2021-11-19 04:23:50,116 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40856 states to 40856 states and 59000 transitions. [2021-11-19 04:23:50,116 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40856 [2021-11-19 04:23:50,157 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40856 [2021-11-19 04:23:50,157 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40856 states and 59000 transitions. [2021-11-19 04:23:50,187 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:50,188 INFO L681 BuchiCegarLoop]: Abstraction has 40856 states and 59000 transitions. [2021-11-19 04:23:50,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40856 states and 59000 transitions. [2021-11-19 04:23:50,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40856 to 39320. [2021-11-19 04:23:50,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39320 states, 39320 states have (on average 1.4461851475076297) internal successors, (56864), 39319 states have internal predecessors, (56864), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:51,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39320 states to 39320 states and 56864 transitions. [2021-11-19 04:23:51,005 INFO L704 BuchiCegarLoop]: Abstraction has 39320 states and 56864 transitions. [2021-11-19 04:23:51,006 INFO L587 BuchiCegarLoop]: Abstraction has 39320 states and 56864 transitions. [2021-11-19 04:23:51,006 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-19 04:23:51,006 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39320 states and 56864 transitions. [2021-11-19 04:23:51,388 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 39056 [2021-11-19 04:23:51,388 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:51,389 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:51,392 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:51,393 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:51,393 INFO L791 eck$LassoCheckResult]: Stem: 161928#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 161929#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 161654#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 161655#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 163261#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 163262#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 161846#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 161847#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 161881#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 162801#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 162802#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 162940#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 162941#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 161660#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 161661#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 162982#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 162192#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 162193#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 162871#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 163236#L1286 assume !(0 == ~M_E~0); 163074#L1286-2 assume !(0 == ~T1_E~0); 161565#L1291-1 assume !(0 == ~T2_E~0); 161566#L1296-1 assume !(0 == ~T3_E~0); 162291#L1301-1 assume !(0 == ~T4_E~0); 162292#L1306-1 assume !(0 == ~T5_E~0); 162881#L1311-1 assume !(0 == ~T6_E~0); 161524#L1316-1 assume !(0 == ~T7_E~0); 161525#L1321-1 assume !(0 == ~T8_E~0); 162311#L1326-1 assume !(0 == ~T9_E~0); 161343#L1331-1 assume !(0 == ~T10_E~0); 161048#L1336-1 assume !(0 == ~T11_E~0); 161049#L1341-1 assume !(0 == ~T12_E~0); 161100#L1346-1 assume !(0 == ~T13_E~0); 161101#L1351-1 assume !(0 == ~E_M~0); 161471#L1356-1 assume !(0 == ~E_1~0); 161472#L1361-1 assume !(0 == ~E_2~0); 163174#L1366-1 assume !(0 == ~E_3~0); 161517#L1371-1 assume !(0 == ~E_4~0); 161518#L1376-1 assume !(0 == ~E_5~0); 162357#L1381-1 assume !(0 == ~E_6~0); 162358#L1386-1 assume !(0 == ~E_7~0); 163219#L1391-1 assume !(0 == ~E_8~0); 163243#L1396-1 assume !(0 == ~E_9~0); 162227#L1401-1 assume !(0 == ~E_10~0); 162228#L1406-1 assume !(0 == ~E_11~0); 162567#L1411-1 assume !(0 == ~E_12~0); 162568#L1416-1 assume !(0 == ~E_13~0); 162148#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 161989#L635 assume !(1 == ~m_pc~0); 161120#L635-2 is_master_triggered_~__retres1~0#1 := 0; 161121#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 161468#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 162111#L1598 assume !(0 != activate_threads_~tmp~1#1); 161298#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 161299#L654 assume !(1 == ~t1_pc~0); 162095#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 162984#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 163213#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 162091#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 162092#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 161349#L673 assume !(1 == ~t2_pc~0); 161351#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 162524#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 162525#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 163275#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 163285#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 162173#L692 assume !(1 == ~t3_pc~0); 161990#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 161991#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 161850#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 161817#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 161818#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 161371#L711 assume 1 == ~t4_pc~0; 161372#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 161861#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 162333#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 161073#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 161074#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 163260#L730 assume !(1 == ~t5_pc~0); 162451#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 161254#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 161255#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 161381#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 161382#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 161726#L749 assume 1 == ~t6_pc~0; 161494#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 161264#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 161691#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 161692#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 161920#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 161055#L768 assume !(1 == ~t7_pc~0); 161056#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 162381#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 161291#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 161292#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 162402#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 161526#L787 assume 1 == ~t8_pc~0; 161527#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 162818#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 163017#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 163018#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 161098#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 161099#L806 assume 1 == ~t9_pc~0; 162832#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 161133#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 161134#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 161383#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 161384#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 162809#L825 assume !(1 == ~t10_pc~0); 162810#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 162347#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 162348#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 161469#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 161470#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 162060#L844 assume 1 == ~t11_pc~0; 161749#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 161750#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 162117#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 162118#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 162796#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 162797#L863 assume !(1 == ~t12_pc~0); 161238#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 161237#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 161459#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 162914#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 162915#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 162187#L882 assume 1 == ~t13_pc~0; 162188#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 162493#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 163128#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 162873#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 162480#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 162481#L1434 assume !(1 == ~M_E~0); 163142#L1434-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 163296#L1439-1 assume !(1 == ~T2_E~0); 178109#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 162571#L1449-1 assume !(1 == ~T4_E~0); 161815#L1454-1 assume !(1 == ~T5_E~0); 161816#L1459-1 assume !(1 == ~T6_E~0); 163092#L1464-1 assume !(1 == ~T7_E~0); 178098#L1469-1 assume !(1 == ~T8_E~0); 178095#L1474-1 assume !(1 == ~T9_E~0); 178093#L1479-1 assume !(1 == ~T10_E~0); 178091#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 178088#L1489-1 assume !(1 == ~T12_E~0); 178085#L1494-1 assume !(1 == ~T13_E~0); 178082#L1499-1 assume !(1 == ~E_M~0); 162212#L1504-1 assume !(1 == ~E_1~0); 162213#L1509-1 assume !(1 == ~E_2~0); 162932#L1514-1 assume !(1 == ~E_3~0); 162539#L1519-1 assume !(1 == ~E_4~0); 162540#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 163194#L1529-1 assume !(1 == ~E_6~0); 163195#L1534-1 assume !(1 == ~E_7~0); 161155#L1539-1 assume !(1 == ~E_8~0); 161156#L1544-1 assume !(1 == ~E_9~0); 161585#L1549-1 assume !(1 == ~E_10~0); 163157#L1554-1 assume !(1 == ~E_11~0); 163169#L1559-1 assume !(1 == ~E_12~0); 162966#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 162967#L1569-1 assume { :end_inline_reset_delta_events } true; 177082#L1935-2 [2021-11-19 04:23:51,394 INFO L793 eck$LassoCheckResult]: Loop: 177082#L1935-2 assume !false; 177081#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 177076#L1261 assume !false; 177075#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 177065#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 177056#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 177055#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 177052#L1074 assume !(0 != eval_~tmp~0#1); 177053#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 177472#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 177470#L1286-3 assume !(0 == ~M_E~0); 177468#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 177465#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 177463#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 177461#L1301-3 assume !(0 == ~T4_E~0); 177459#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 177457#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 177455#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 177452#L1321-3 assume !(0 == ~T8_E~0); 177450#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 177448#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 177446#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 177444#L1341-3 assume !(0 == ~T12_E~0); 177442#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 177439#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 177437#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 177435#L1361-3 assume !(0 == ~E_2~0); 177433#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 177431#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 177429#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 177426#L1381-3 assume !(0 == ~E_6~0); 177424#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 177422#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 177420#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 177418#L1401-3 assume !(0 == ~E_10~0); 177416#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 177413#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 177411#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 177409#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 177407#L635-45 assume !(1 == ~m_pc~0); 177405#L635-47 is_master_triggered_~__retres1~0#1 := 0; 177403#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 177400#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 177398#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 177396#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 177394#L654-45 assume !(1 == ~t1_pc~0); 177392#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 177390#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 177387#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 177385#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 177383#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 177381#L673-45 assume !(1 == ~t2_pc~0); 177378#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 177376#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 177373#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 177371#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 177369#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 177367#L692-45 assume 1 == ~t3_pc~0; 177364#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 177362#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 177359#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 177357#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 177355#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 177353#L711-45 assume 1 == ~t4_pc~0; 177350#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 177348#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 177345#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 177343#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 177341#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 177339#L730-45 assume 1 == ~t5_pc~0; 177336#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 177334#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 177331#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 177329#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 177327#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 177325#L749-45 assume !(1 == ~t6_pc~0); 177322#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 177321#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 177320#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 177319#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 177318#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 177317#L768-45 assume 1 == ~t7_pc~0; 177315#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 177314#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 177313#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 177312#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 177311#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 177310#L787-45 assume !(1 == ~t8_pc~0); 177308#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 177307#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 177305#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 177303#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 177301#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 177299#L806-45 assume 1 == ~t9_pc~0; 177296#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 177294#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 177292#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 177290#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 177288#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 177286#L825-45 assume !(1 == ~t10_pc~0); 177283#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 177281#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 177278#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 177276#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 177274#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 177272#L844-45 assume !(1 == ~t11_pc~0); 177270#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 177267#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 177265#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 177262#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 177260#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 177258#L863-45 assume 1 == ~t12_pc~0; 177255#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 177253#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 177251#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 177248#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 177246#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 177244#L882-45 assume 1 == ~t13_pc~0; 177242#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 177239#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 177237#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 177234#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 177232#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 177230#L1434-3 assume !(1 == ~M_E~0); 177226#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 177222#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 177220#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 177217#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 177215#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 177213#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 177211#L1464-3 assume !(1 == ~T7_E~0); 177209#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 177205#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 177202#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 177200#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 177198#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 177196#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 177194#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 177192#L1504-3 assume !(1 == ~E_1~0); 177189#L1509-3 assume !(1 == ~E_2~0); 177187#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 177185#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 177183#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 177181#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 177179#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 177176#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 177174#L1544-3 assume !(1 == ~E_9~0); 177172#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 177168#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 177166#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 177164#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 177161#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 177145#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 177135#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 177133#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 177129#L1954 assume !(0 == start_simulation_~tmp~3#1); 177126#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 177110#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 177101#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 177097#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 177095#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 177093#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 177092#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 177087#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 177082#L1935-2 [2021-11-19 04:23:51,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:51,395 INFO L85 PathProgramCache]: Analyzing trace with hash 388105797, now seen corresponding path program 1 times [2021-11-19 04:23:51,395 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:51,395 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [699807101] [2021-11-19 04:23:51,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:51,396 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:51,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:51,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:51,454 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:51,454 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [699807101] [2021-11-19 04:23:51,455 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [699807101] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:51,455 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:51,455 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-19 04:23:51,455 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [865122620] [2021-11-19 04:23:51,455 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:51,457 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:51,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:51,460 INFO L85 PathProgramCache]: Analyzing trace with hash -1916771935, now seen corresponding path program 1 times [2021-11-19 04:23:51,460 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:51,460 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175684197] [2021-11-19 04:23:51,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:51,461 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:51,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:51,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:51,627 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:51,628 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1175684197] [2021-11-19 04:23:51,628 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1175684197] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:51,628 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:51,628 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:51,628 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1072915094] [2021-11-19 04:23:51,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:51,630 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:51,630 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:51,631 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-19 04:23:51,631 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-19 04:23:51,631 INFO L87 Difference]: Start difference. First operand 39320 states and 56864 transitions. cyclomatic complexity: 17552 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:52,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:52,530 INFO L93 Difference]: Finished difference Result 108049 states and 156545 transitions. [2021-11-19 04:23:52,530 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-19 04:23:52,531 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108049 states and 156545 transitions. [2021-11-19 04:23:53,525 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 107408 [2021-11-19 04:23:54,055 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108049 states to 108049 states and 156545 transitions. [2021-11-19 04:23:54,055 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 108049 [2021-11-19 04:23:54,107 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 108049 [2021-11-19 04:23:54,107 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108049 states and 156545 transitions. [2021-11-19 04:23:54,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:54,166 INFO L681 BuchiCegarLoop]: Abstraction has 108049 states and 156545 transitions. [2021-11-19 04:23:54,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108049 states and 156545 transitions. [2021-11-19 04:23:54,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108049 to 40331. [2021-11-19 04:23:55,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40331 states, 40331 states have (on average 1.4350003719223425) internal successors, (57875), 40330 states have internal predecessors, (57875), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:55,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40331 states to 40331 states and 57875 transitions. [2021-11-19 04:23:55,117 INFO L704 BuchiCegarLoop]: Abstraction has 40331 states and 57875 transitions. [2021-11-19 04:23:55,117 INFO L587 BuchiCegarLoop]: Abstraction has 40331 states and 57875 transitions. [2021-11-19 04:23:55,117 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-19 04:23:55,117 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40331 states and 57875 transitions. [2021-11-19 04:23:55,272 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 40064 [2021-11-19 04:23:55,273 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:55,273 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:55,278 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:55,279 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:55,279 INFO L791 eck$LassoCheckResult]: Stem: 309307#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 309308#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 309035#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 309036#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 310645#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 310646#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 309224#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 309225#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 309261#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 310168#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 310169#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 310310#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 310311#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 309041#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 309042#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 310355#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 309574#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 309575#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 310235#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 310617#L1286 assume !(0 == ~M_E~0); 310436#L1286-2 assume !(0 == ~T1_E~0); 308950#L1291-1 assume !(0 == ~T2_E~0); 308951#L1296-1 assume !(0 == ~T3_E~0); 309676#L1301-1 assume !(0 == ~T4_E~0); 309677#L1306-1 assume !(0 == ~T5_E~0); 310245#L1311-1 assume !(0 == ~T6_E~0); 308910#L1316-1 assume !(0 == ~T7_E~0); 308911#L1321-1 assume !(0 == ~T8_E~0); 309695#L1326-1 assume !(0 == ~T9_E~0); 308725#L1331-1 assume !(0 == ~T10_E~0); 308430#L1336-1 assume !(0 == ~T11_E~0); 308431#L1341-1 assume !(0 == ~T12_E~0); 308482#L1346-1 assume !(0 == ~T13_E~0); 308483#L1351-1 assume !(0 == ~E_M~0); 308854#L1356-1 assume !(0 == ~E_1~0); 308855#L1361-1 assume !(0 == ~E_2~0); 310551#L1366-1 assume !(0 == ~E_3~0); 308901#L1371-1 assume !(0 == ~E_4~0); 308902#L1376-1 assume !(0 == ~E_5~0); 309741#L1381-1 assume !(0 == ~E_6~0); 309742#L1386-1 assume !(0 == ~E_7~0); 310599#L1391-1 assume !(0 == ~E_8~0); 310628#L1396-1 assume !(0 == ~E_9~0); 309614#L1401-1 assume !(0 == ~E_10~0); 309615#L1406-1 assume !(0 == ~E_11~0); 309953#L1411-1 assume !(0 == ~E_12~0); 309954#L1416-1 assume !(0 == ~E_13~0); 309532#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 309368#L635 assume !(1 == ~m_pc~0); 308502#L635-2 is_master_triggered_~__retres1~0#1 := 0; 308503#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 308851#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 309494#L1598 assume !(0 != activate_threads_~tmp~1#1); 308679#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 308680#L654 assume !(1 == ~t1_pc~0); 309476#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 310358#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 310593#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 309472#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 309473#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 308731#L673 assume !(1 == ~t2_pc~0); 308733#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 309914#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 309915#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 310655#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 310667#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 309555#L692 assume !(1 == ~t3_pc~0); 309369#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 309370#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 310623#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 309194#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 309195#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 308753#L711 assume 1 == ~t4_pc~0; 308754#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 309241#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 309712#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 308455#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 308456#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 310644#L730 assume !(1 == ~t5_pc~0); 309842#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 308634#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 308635#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 308763#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 308764#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 309106#L749 assume 1 == ~t6_pc~0; 308877#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 308644#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 309072#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 309073#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 309299#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 308437#L768 assume !(1 == ~t7_pc~0); 308438#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 309768#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 308672#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 308673#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 309789#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 308912#L787 assume 1 == ~t8_pc~0; 308913#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 310187#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 310391#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 310392#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 308480#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 308481#L806 assume 1 == ~t9_pc~0; 310198#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 308515#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 308516#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 308765#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 308766#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 310177#L825 assume !(1 == ~t10_pc~0); 310178#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 309729#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 309730#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 308852#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 308853#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 309439#L844 assume 1 == ~t11_pc~0; 309129#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 309130#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 309500#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 309501#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 310161#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 310162#L863 assume !(1 == ~t12_pc~0); 308618#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 308617#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 308842#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 310279#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 310280#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 309569#L882 assume 1 == ~t13_pc~0; 309570#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 309885#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 310495#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 310237#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 309871#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 309872#L1434 assume !(1 == ~M_E~0); 310509#L1434-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 310654#L1439-1 assume !(1 == ~T2_E~0); 308746#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 308747#L1449-1 assume !(1 == ~T4_E~0); 309957#L1454-1 assume !(1 == ~T5_E~0); 314070#L1459-1 assume !(1 == ~T6_E~0); 314068#L1464-1 assume !(1 == ~T7_E~0); 309888#L1469-1 assume !(1 == ~T8_E~0); 309889#L1474-1 assume !(1 == ~T9_E~0); 309533#L1479-1 assume !(1 == ~T10_E~0); 309534#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 309802#L1489-1 assume !(1 == ~T12_E~0); 310300#L1494-1 assume !(1 == ~T13_E~0); 313333#L1499-1 assume !(1 == ~E_M~0); 313331#L1504-1 assume !(1 == ~E_1~0); 313330#L1509-1 assume !(1 == ~E_2~0); 313329#L1514-1 assume !(1 == ~E_3~0); 313328#L1519-1 assume !(1 == ~E_4~0); 313327#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 310568#L1529-1 assume !(1 == ~E_6~0); 310569#L1534-1 assume !(1 == ~E_7~0); 308537#L1539-1 assume !(1 == ~E_8~0); 308538#L1544-1 assume !(1 == ~E_9~0); 308967#L1549-1 assume !(1 == ~E_10~0); 313318#L1554-1 assume !(1 == ~E_11~0); 313317#L1559-1 assume !(1 == ~E_12~0); 313316#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 312876#L1569-1 assume { :end_inline_reset_delta_events } true; 312874#L1935-2 [2021-11-19 04:23:55,280 INFO L793 eck$LassoCheckResult]: Loop: 312874#L1935-2 assume !false; 312872#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 312866#L1261 assume !false; 312863#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 312767#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 312759#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 312758#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 312756#L1074 assume !(0 != eval_~tmp~0#1); 312757#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 348756#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 348755#L1286-3 assume !(0 == ~M_E~0); 348754#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 348753#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 348752#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 348751#L1301-3 assume !(0 == ~T4_E~0); 310542#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 310543#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 348750#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 348749#L1321-3 assume !(0 == ~T8_E~0); 348748#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 348747#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 348746#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 348745#L1341-3 assume !(0 == ~T12_E~0); 348744#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 348742#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 348740#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 348738#L1361-3 assume !(0 == ~E_2~0); 348736#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 348734#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 348732#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 348730#L1381-3 assume !(0 == ~E_6~0); 348728#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 348726#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 310359#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 310360#L1401-3 assume !(0 == ~E_10~0); 308848#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 308681#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 308682#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 309314#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 308559#L635-45 assume !(1 == ~m_pc~0); 308560#L635-47 is_master_triggered_~__retres1~0#1 := 0; 309763#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 309873#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 310160#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 308866#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 308867#L654-45 assume !(1 == ~t1_pc~0); 309709#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 310103#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 310104#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 348703#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 310435#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 309380#L673-45 assume !(1 == ~t2_pc~0); 309381#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 309722#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 309723#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 310465#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 310233#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 310234#L692-45 assume 1 == ~t3_pc~0; 310615#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 310262#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 310263#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 348720#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 309049#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 309367#L711-45 assume !(1 == ~t4_pc~0); 309493#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 309492#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 309342#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 309343#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 309769#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 308890#L730-45 assume 1 == ~t5_pc~0; 308728#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 308729#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 309141#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 309142#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 309938#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 308703#L749-45 assume !(1 == ~t6_pc~0); 308704#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 310181#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 309909#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 309910#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 310084#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 309021#L768-45 assume 1 == ~t7_pc~0; 309022#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 309160#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 310022#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 310023#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 310064#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 310065#L787-45 assume 1 == ~t8_pc~0; 310672#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 309168#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 309169#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 309592#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 309593#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 348563#L806-45 assume 1 == ~t9_pc~0; 348561#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 348502#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 310202#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 309236#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 309237#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 348431#L825-45 assume 1 == ~t10_pc~0; 348429#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 348426#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 348424#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 348422#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 348420#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 348417#L844-45 assume !(1 == ~t11_pc~0); 348415#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 309315#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 309316#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 309332#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 309766#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 308826#L863-45 assume !(1 == ~t12_pc~0); 308828#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 309602#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 310424#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 308945#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 308946#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 309774#L882-45 assume !(1 == ~t13_pc~0); 309280#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 308447#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 308448#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 310346#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 310347#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 309892#L1434-3 assume !(1 == ~M_E~0); 309893#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 310102#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 308742#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 308743#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 308903#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 309880#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 309881#L1464-3 assume !(1 == ~T7_E~0); 310417#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 310321#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 310322#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 310419#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 309489#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 309490#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 310230#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 309812#L1504-3 assume !(1 == ~E_1~0); 309813#L1509-3 assume !(1 == ~E_2~0); 310332#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 310384#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 309408#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 309409#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 310448#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 309728#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 309161#L1544-3 assume !(1 == ~E_9~0); 309162#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 346891#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 346689#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 345055#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 345054#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 314647#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 313421#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 313406#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 313403#L1954 assume !(0 == start_simulation_~tmp~3#1); 313400#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 312898#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 312888#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 312886#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 312884#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 312881#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 312879#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 312877#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 312874#L1935-2 [2021-11-19 04:23:55,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:55,281 INFO L85 PathProgramCache]: Analyzing trace with hash -1552476217, now seen corresponding path program 1 times [2021-11-19 04:23:55,281 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:55,282 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1437611048] [2021-11-19 04:23:55,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:55,282 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:55,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:55,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:55,345 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:55,345 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1437611048] [2021-11-19 04:23:55,346 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1437611048] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:55,346 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:55,346 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-19 04:23:55,346 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [796758444] [2021-11-19 04:23:55,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:55,349 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:55,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:55,350 INFO L85 PathProgramCache]: Analyzing trace with hash 645653922, now seen corresponding path program 1 times [2021-11-19 04:23:55,350 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:55,350 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [947455065] [2021-11-19 04:23:55,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:55,351 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:55,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:55,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:55,400 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:55,401 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [947455065] [2021-11-19 04:23:55,401 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [947455065] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:55,401 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:55,401 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:55,401 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2125493662] [2021-11-19 04:23:55,402 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:55,402 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:55,402 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:55,403 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 04:23:55,403 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 04:23:55,403 INFO L87 Difference]: Start difference. First operand 40331 states and 57875 transitions. cyclomatic complexity: 17552 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:56,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:23:56,015 INFO L93 Difference]: Finished difference Result 77650 states and 111018 transitions. [2021-11-19 04:23:56,016 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 04:23:56,016 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77650 states and 111018 transitions. [2021-11-19 04:23:56,387 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 77296 [2021-11-19 04:23:56,936 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77650 states to 77650 states and 111018 transitions. [2021-11-19 04:23:56,936 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77650 [2021-11-19 04:23:56,986 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77650 [2021-11-19 04:23:56,986 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77650 states and 111018 transitions. [2021-11-19 04:23:57,075 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:23:57,076 INFO L681 BuchiCegarLoop]: Abstraction has 77650 states and 111018 transitions. [2021-11-19 04:23:57,123 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77650 states and 111018 transitions. [2021-11-19 04:23:58,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77650 to 77602. [2021-11-19 04:23:58,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77602 states, 77602 states have (on average 1.4299889178113967) internal successors, (110970), 77601 states have internal predecessors, (110970), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:23:58,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77602 states to 77602 states and 110970 transitions. [2021-11-19 04:23:58,748 INFO L704 BuchiCegarLoop]: Abstraction has 77602 states and 110970 transitions. [2021-11-19 04:23:58,748 INFO L587 BuchiCegarLoop]: Abstraction has 77602 states and 110970 transitions. [2021-11-19 04:23:58,748 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-19 04:23:58,748 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77602 states and 110970 transitions. [2021-11-19 04:23:59,070 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 77248 [2021-11-19 04:23:59,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:23:59,070 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:23:59,074 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:59,074 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:23:59,075 INFO L791 eck$LassoCheckResult]: Stem: 427293#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 427294#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 427024#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 427025#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 428661#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 428662#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 427212#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 427213#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 427247#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 428177#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 428178#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 428318#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 428319#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 427030#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 427031#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 428365#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 427570#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 427571#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 428243#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 428636#L1286 assume !(0 == ~M_E~0); 428446#L1286-2 assume !(0 == ~T1_E~0); 426935#L1291-1 assume !(0 == ~T2_E~0); 426936#L1296-1 assume !(0 == ~T3_E~0); 427668#L1301-1 assume !(0 == ~T4_E~0); 427669#L1306-1 assume !(0 == ~T5_E~0); 428253#L1311-1 assume !(0 == ~T6_E~0); 426894#L1316-1 assume !(0 == ~T7_E~0); 426895#L1321-1 assume !(0 == ~T8_E~0); 427688#L1326-1 assume !(0 == ~T9_E~0); 426713#L1331-1 assume !(0 == ~T10_E~0); 426418#L1336-1 assume !(0 == ~T11_E~0); 426419#L1341-1 assume !(0 == ~T12_E~0); 426470#L1346-1 assume !(0 == ~T13_E~0); 426471#L1351-1 assume !(0 == ~E_M~0); 426841#L1356-1 assume !(0 == ~E_1~0); 426842#L1361-1 assume !(0 == ~E_2~0); 428565#L1366-1 assume !(0 == ~E_3~0); 426887#L1371-1 assume !(0 == ~E_4~0); 426888#L1376-1 assume !(0 == ~E_5~0); 427742#L1381-1 assume !(0 == ~E_6~0); 427743#L1386-1 assume !(0 == ~E_7~0); 428614#L1391-1 assume !(0 == ~E_8~0); 428646#L1396-1 assume !(0 == ~E_9~0); 427607#L1401-1 assume !(0 == ~E_10~0); 427608#L1406-1 assume !(0 == ~E_11~0); 427948#L1411-1 assume !(0 == ~E_12~0); 427949#L1416-1 assume !(0 == ~E_13~0); 427523#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 427356#L635 assume !(1 == ~m_pc~0); 426491#L635-2 is_master_triggered_~__retres1~0#1 := 0; 426492#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 426838#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 427484#L1598 assume !(0 != activate_threads_~tmp~1#1); 426668#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 426669#L654 assume !(1 == ~t1_pc~0); 427465#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 428367#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 428610#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 427461#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 427462#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 426719#L673 assume !(1 == ~t2_pc~0); 426721#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 427911#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 427912#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 428674#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 428688#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 427551#L692 assume !(1 == ~t3_pc~0); 427357#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 427358#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 427216#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 427181#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 427182#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 426741#L711 assume !(1 == ~t4_pc~0); 426742#L711-2 is_transmit4_triggered_~__retres1~4#1 := 0; 428357#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 427712#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 426443#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 426444#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 428660#L730 assume !(1 == ~t5_pc~0); 427838#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 426623#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 426624#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 426750#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 426751#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 427095#L749 assume 1 == ~t6_pc~0; 426864#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 426633#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 427061#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 427062#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 427285#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 426425#L768 assume !(1 == ~t7_pc~0); 426426#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 427766#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 426661#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 426662#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 427787#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 426896#L787 assume 1 == ~t8_pc~0; 426897#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 428194#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 428402#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 428403#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 426468#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 426469#L806 assume 1 == ~t9_pc~0; 428207#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 426504#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 426505#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 426752#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 426753#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 428185#L825 assume !(1 == ~t10_pc~0); 428186#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 427730#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 427731#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 426839#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 426840#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 427427#L844 assume 1 == ~t11_pc~0; 427118#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 427119#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 427490#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 427491#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 428171#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 428172#L863 assume !(1 == ~t12_pc~0); 426608#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 426607#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 426829#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 428284#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 428285#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 427565#L882 assume 1 == ~t13_pc~0; 427566#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 427881#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 428506#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 428245#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 427868#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 427869#L1434 assume !(1 == ~M_E~0); 428524#L1434-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 428703#L1439-1 assume !(1 == ~T2_E~0); 441718#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 441716#L1449-1 assume !(1 == ~T4_E~0); 441714#L1454-1 assume !(1 == ~T5_E~0); 441711#L1459-1 assume !(1 == ~T6_E~0); 441709#L1464-1 assume !(1 == ~T7_E~0); 441707#L1469-1 assume !(1 == ~T8_E~0); 441705#L1474-1 assume !(1 == ~T9_E~0); 441703#L1479-1 assume !(1 == ~T10_E~0); 441701#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 441698#L1489-1 assume !(1 == ~T12_E~0); 441696#L1494-1 assume !(1 == ~T13_E~0); 441694#L1499-1 assume !(1 == ~E_M~0); 441692#L1504-1 assume !(1 == ~E_1~0); 441690#L1509-1 assume !(1 == ~E_2~0); 441688#L1514-1 assume !(1 == ~E_3~0); 441685#L1519-1 assume !(1 == ~E_4~0); 441683#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 441681#L1529-1 assume !(1 == ~E_6~0); 441679#L1534-1 assume !(1 == ~E_7~0); 441677#L1539-1 assume !(1 == ~E_8~0); 441675#L1544-1 assume !(1 == ~E_9~0); 441672#L1549-1 assume !(1 == ~E_10~0); 428548#L1554-1 assume !(1 == ~E_11~0); 441669#L1559-1 assume !(1 == ~E_12~0); 441667#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 439192#L1569-1 assume { :end_inline_reset_delta_events } true; 439190#L1935-2 [2021-11-19 04:23:59,076 INFO L793 eck$LassoCheckResult]: Loop: 439190#L1935-2 assume !false; 439187#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 439181#L1261 assume !false; 439179#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 439159#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 439150#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 439148#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 439145#L1074 assume !(0 != eval_~tmp~0#1); 439146#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 449432#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 449430#L1286-3 assume !(0 == ~M_E~0); 449428#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 449425#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 449423#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 449421#L1301-3 assume !(0 == ~T4_E~0); 449419#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 449417#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 449415#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 449413#L1321-3 assume !(0 == ~T8_E~0); 449411#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 449409#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 449407#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 449405#L1341-3 assume !(0 == ~T12_E~0); 449403#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 449401#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 449399#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 449397#L1361-3 assume !(0 == ~E_2~0); 449395#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 449393#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 449391#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 449389#L1381-3 assume !(0 == ~E_6~0); 449387#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 449385#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 449383#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 449381#L1401-3 assume !(0 == ~E_10~0); 449379#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 449377#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 449375#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 449373#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 449371#L635-45 assume !(1 == ~m_pc~0); 449369#L635-47 is_master_triggered_~__retres1~0#1 := 0; 449367#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 449365#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 449363#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 449361#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 449359#L654-45 assume !(1 == ~t1_pc~0); 449357#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 449355#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 449353#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 449351#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 449349#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 449230#L673-45 assume !(1 == ~t2_pc~0); 449218#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 449208#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 449199#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 449194#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 449189#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 449184#L692-45 assume !(1 == ~t3_pc~0); 449180#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 449176#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 449173#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 449078#L1622-45 assume !(0 != activate_threads_~tmp___2~0#1); 449075#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 449073#L711-45 assume !(1 == ~t4_pc~0); 449071#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 449069#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 449067#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 449065#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 449063#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 449061#L730-45 assume 1 == ~t5_pc~0; 449058#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 449056#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 449053#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 449051#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 449049#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 449047#L749-45 assume 1 == ~t6_pc~0; 449044#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 449040#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 449038#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 449036#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 449034#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 449016#L768-45 assume 1 == ~t7_pc~0; 449010#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 449002#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 448994#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 448988#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 448981#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 448976#L787-45 assume 1 == ~t8_pc~0; 448970#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 448961#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 448954#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 448947#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 448940#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 448933#L806-45 assume 1 == ~t9_pc~0; 448924#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 448915#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 448909#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 448903#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 448896#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 448890#L825-45 assume 1 == ~t10_pc~0; 448884#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 448874#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 448868#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 448862#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 448856#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 448849#L844-45 assume !(1 == ~t11_pc~0); 448842#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 448831#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 448824#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 448818#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 448812#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 448807#L863-45 assume 1 == ~t12_pc~0; 448800#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 448791#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 448785#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 448780#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 448775#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 448769#L882-45 assume !(1 == ~t13_pc~0); 448762#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 448753#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 448748#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 448743#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 448738#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 448731#L1434-3 assume !(1 == ~M_E~0); 448723#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 439725#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 448710#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 448704#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 448698#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 448691#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 448685#L1464-3 assume !(1 == ~T7_E~0); 448677#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 448549#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 448666#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 448660#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 448652#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 448647#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 448639#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 448634#L1504-3 assume !(1 == ~E_1~0); 448629#L1509-3 assume !(1 == ~E_2~0); 448624#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 448618#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 448611#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 448602#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 448594#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 448586#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 448579#L1544-3 assume !(1 == ~E_9~0); 448572#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 442679#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 448564#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 448560#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 448558#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 448253#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 448228#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 446856#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 446854#L1954 assume !(0 == start_simulation_~tmp~3#1); 446852#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 439214#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 439204#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 439201#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 439199#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 439197#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 439195#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 439193#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 439190#L1935-2 [2021-11-19 04:23:59,076 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:59,077 INFO L85 PathProgramCache]: Analyzing trace with hash 1355809800, now seen corresponding path program 1 times [2021-11-19 04:23:59,077 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:59,077 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1693108561] [2021-11-19 04:23:59,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:59,078 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:59,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:59,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:59,129 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:59,129 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1693108561] [2021-11-19 04:23:59,129 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1693108561] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:59,129 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:59,129 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:59,130 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1878566935] [2021-11-19 04:23:59,130 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:59,130 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:23:59,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:23:59,131 INFO L85 PathProgramCache]: Analyzing trace with hash 1643781411, now seen corresponding path program 1 times [2021-11-19 04:23:59,131 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:23:59,131 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [921455438] [2021-11-19 04:23:59,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:23:59,132 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:23:59,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:23:59,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:23:59,186 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:23:59,186 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [921455438] [2021-11-19 04:23:59,187 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [921455438] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:23:59,187 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:23:59,187 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:23:59,187 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [291792150] [2021-11-19 04:23:59,187 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:23:59,188 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:23:59,188 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:23:59,189 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-19 04:23:59,189 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-19 04:23:59,189 INFO L87 Difference]: Start difference. First operand 77602 states and 110970 transitions. cyclomatic complexity: 33384 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:24:00,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:24:00,749 INFO L93 Difference]: Finished difference Result 223377 states and 317199 transitions. [2021-11-19 04:24:00,749 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-19 04:24:00,751 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 223377 states and 317199 transitions. [2021-11-19 04:24:02,213 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 219280 [2021-11-19 04:24:02,842 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 223377 states to 223377 states and 317199 transitions. [2021-11-19 04:24:02,843 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 223377 [2021-11-19 04:24:02,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 223377 [2021-11-19 04:24:02,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 223377 states and 317199 transitions. [2021-11-19 04:24:03,020 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:24:03,020 INFO L681 BuchiCegarLoop]: Abstraction has 223377 states and 317199 transitions. [2021-11-19 04:24:03,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223377 states and 317199 transitions. [2021-11-19 04:24:05,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223377 to 217153. [2021-11-19 04:24:05,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 217153 states, 217153 states have (on average 1.421665830082937) internal successors, (308719), 217152 states have internal predecessors, (308719), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:24:07,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217153 states to 217153 states and 308719 transitions. [2021-11-19 04:24:07,220 INFO L704 BuchiCegarLoop]: Abstraction has 217153 states and 308719 transitions. [2021-11-19 04:24:07,220 INFO L587 BuchiCegarLoop]: Abstraction has 217153 states and 308719 transitions. [2021-11-19 04:24:07,220 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-19 04:24:07,221 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 217153 states and 308719 transitions. [2021-11-19 04:24:07,809 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 216544 [2021-11-19 04:24:07,813 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:24:07,813 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:24:07,819 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:24:07,820 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:24:07,820 INFO L791 eck$LassoCheckResult]: Stem: 728280#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 728281#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 728013#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 728014#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 729735#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 729736#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 728201#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 728202#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 728235#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 729185#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 729186#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 729348#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 729349#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 728019#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 728020#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 729395#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 728553#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 728554#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 729259#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 729698#L1286 assume !(0 == ~M_E~0); 729485#L1286-2 assume !(0 == ~T1_E~0); 727926#L1291-1 assume !(0 == ~T2_E~0); 727927#L1296-1 assume !(0 == ~T3_E~0); 728661#L1301-1 assume !(0 == ~T4_E~0); 728662#L1306-1 assume !(0 == ~T5_E~0); 729272#L1311-1 assume !(0 == ~T6_E~0); 727884#L1316-1 assume !(0 == ~T7_E~0); 727885#L1321-1 assume !(0 == ~T8_E~0); 728680#L1326-1 assume !(0 == ~T9_E~0); 727700#L1331-1 assume !(0 == ~T10_E~0); 727407#L1336-1 assume !(0 == ~T11_E~0); 727408#L1341-1 assume !(0 == ~T12_E~0); 727459#L1346-1 assume !(0 == ~T13_E~0); 727460#L1351-1 assume !(0 == ~E_M~0); 727828#L1356-1 assume !(0 == ~E_1~0); 727829#L1361-1 assume !(0 == ~E_2~0); 729613#L1366-1 assume !(0 == ~E_3~0); 727877#L1371-1 assume !(0 == ~E_4~0); 727878#L1376-1 assume !(0 == ~E_5~0); 728725#L1381-1 assume !(0 == ~E_6~0); 728726#L1386-1 assume !(0 == ~E_7~0); 729676#L1391-1 assume !(0 == ~E_8~0); 729717#L1396-1 assume !(0 == ~E_9~0); 728593#L1401-1 assume !(0 == ~E_10~0); 728594#L1406-1 assume !(0 == ~E_11~0); 728948#L1411-1 assume !(0 == ~E_12~0); 728949#L1416-1 assume !(0 == ~E_13~0); 728509#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 728343#L635 assume !(1 == ~m_pc~0); 727479#L635-2 is_master_triggered_~__retres1~0#1 := 0; 727480#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 727825#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 728473#L1598 assume !(0 != activate_threads_~tmp~1#1); 727656#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 727657#L654 assume !(1 == ~t1_pc~0); 728456#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 729397#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 729669#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 728452#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 728453#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 727706#L673 assume !(1 == ~t2_pc~0); 727708#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 728908#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 728909#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 729753#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 729768#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 728534#L692 assume !(1 == ~t3_pc~0); 728344#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 728345#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 728205#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 728169#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 728170#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 727728#L711 assume !(1 == ~t4_pc~0); 727729#L711-2 is_transmit4_triggered_~__retres1~4#1 := 0; 729387#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 728700#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 727432#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 727433#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 729734#L730 assume !(1 == ~t5_pc~0); 728834#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 727613#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 727614#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 727737#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 727738#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 728082#L749 assume !(1 == ~t6_pc~0); 727622#L749-2 is_transmit6_triggered_~__retres1~6#1 := 0; 727623#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 728050#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 728051#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 728272#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 727414#L768 assume !(1 == ~t7_pc~0); 727415#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 728753#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 727649#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 727650#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 728776#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 727886#L787 assume 1 == ~t8_pc~0; 727887#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 729202#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 729435#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 729436#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 727457#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 727458#L806 assume 1 == ~t9_pc~0; 729216#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 727492#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 727493#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 727739#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 727740#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 729193#L825 assume !(1 == ~t10_pc~0); 729194#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 728714#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 728715#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 727826#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 727827#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 728416#L844 assume 1 == ~t11_pc~0; 728105#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 728106#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 728479#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 728480#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 729181#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 729182#L863 assume !(1 == ~t12_pc~0); 727597#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 727596#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 727815#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 729308#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 729309#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 728548#L882 assume 1 == ~t13_pc~0; 728549#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 728880#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 729558#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 729262#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 728867#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 728868#L1434 assume !(1 == ~M_E~0); 729576#L1434-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 729752#L1439-1 assume !(1 == ~T2_E~0); 727721#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 727722#L1449-1 assume !(1 == ~T4_E~0); 728167#L1454-1 assume !(1 == ~T5_E~0); 728168#L1459-1 assume !(1 == ~T6_E~0); 728777#L1464-1 assume !(1 == ~T7_E~0); 728778#L1469-1 assume !(1 == ~T8_E~0); 728883#L1474-1 assume !(1 == ~T9_E~0); 728510#L1479-1 assume !(1 == ~T10_E~0); 728511#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 729332#L1489-1 assume !(1 == ~T12_E~0); 729333#L1494-1 assume !(1 == ~T13_E~0); 729740#L1499-1 assume !(1 == ~E_M~0); 729741#L1504-1 assume !(1 == ~E_1~0); 729547#L1509-1 assume !(1 == ~E_2~0); 729548#L1514-1 assume !(1 == ~E_3~0); 728922#L1519-1 assume !(1 == ~E_4~0); 728923#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 729641#L1529-1 assume !(1 == ~E_6~0); 729642#L1534-1 assume !(1 == ~E_7~0); 727514#L1539-1 assume !(1 == ~E_8~0); 727515#L1544-1 assume !(1 == ~E_9~0); 729594#L1549-1 assume !(1 == ~E_10~0); 729595#L1554-1 assume !(1 == ~E_11~0); 729591#L1559-1 assume !(1 == ~E_12~0); 729592#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 729627#L1569-1 assume { :end_inline_reset_delta_events } true; 729628#L1935-2 [2021-11-19 04:24:07,821 INFO L793 eck$LassoCheckResult]: Loop: 729628#L1935-2 assume !false; 888490#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 888485#L1261 assume !false; 888484#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 888477#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 888469#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 888468#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 888466#L1074 assume !(0 != eval_~tmp~0#1); 888465#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 888464#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 888463#L1286-3 assume !(0 == ~M_E~0); 888462#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 888461#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 888460#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 888459#L1301-3 assume !(0 == ~T4_E~0); 888458#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 888457#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 888456#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 888455#L1321-3 assume !(0 == ~T8_E~0); 888454#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 888453#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 888452#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 888451#L1341-3 assume !(0 == ~T12_E~0); 888450#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 888449#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 888448#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 888447#L1361-3 assume !(0 == ~E_2~0); 888446#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 888445#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 888444#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 888443#L1381-3 assume !(0 == ~E_6~0); 888442#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 888441#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 888440#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 888439#L1401-3 assume !(0 == ~E_10~0); 888438#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 888437#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 888436#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 888435#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 888434#L635-45 assume !(1 == ~m_pc~0); 888433#L635-47 is_master_triggered_~__retres1~0#1 := 0; 888432#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 888431#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 888430#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 888429#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 888428#L654-45 assume !(1 == ~t1_pc~0); 888427#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 888426#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 888425#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 888424#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 888423#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 888422#L673-45 assume !(1 == ~t2_pc~0); 888420#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 888419#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 888418#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 888417#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 888416#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 888415#L692-45 assume 1 == ~t3_pc~0; 888413#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 888414#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 889598#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 888408#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 888407#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 888406#L711-45 assume !(1 == ~t4_pc~0); 888405#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 888404#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 888403#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 888402#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 888401#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 888400#L730-45 assume !(1 == ~t5_pc~0); 888399#L730-47 is_transmit5_triggered_~__retres1~5#1 := 0; 888397#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 888396#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 888395#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 888394#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 888393#L749-45 assume !(1 == ~t6_pc~0); 888392#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 888391#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 888390#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 888389#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 888388#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 888387#L768-45 assume 1 == ~t7_pc~0; 888385#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 888384#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 888383#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 888382#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 888381#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 888380#L787-45 assume 1 == ~t8_pc~0; 888379#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 888377#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 888376#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 888375#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 888374#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 888373#L806-45 assume !(1 == ~t9_pc~0); 888372#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 888370#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 888369#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 888368#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 888367#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 888366#L825-45 assume 1 == ~t10_pc~0; 888365#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 888363#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 888362#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 888361#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 888360#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 888359#L844-45 assume 1 == ~t11_pc~0; 888357#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 888356#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 888355#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 888354#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 888353#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 888352#L863-45 assume !(1 == ~t12_pc~0); 888351#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 888349#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 888348#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 888347#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 888346#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 888345#L882-45 assume 1 == ~t13_pc~0; 888344#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 888342#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 888341#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 888340#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 888339#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 888338#L1434-3 assume !(1 == ~M_E~0); 883896#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 859142#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 888337#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 888336#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 888335#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 888334#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 888333#L1464-3 assume !(1 == ~T7_E~0); 888332#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 866336#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 888331#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 888330#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 888329#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 888328#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 888327#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 888326#L1504-3 assume !(1 == ~E_1~0); 888325#L1509-3 assume !(1 == ~E_2~0); 888324#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 888323#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 888322#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 888321#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 888320#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 888319#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 888318#L1544-3 assume !(1 == ~E_9~0); 888317#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 884512#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 888316#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 888315#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 888314#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 888308#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 888299#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 888298#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 888296#L1954 assume !(0 == start_simulation_~tmp~3#1); 888297#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 888505#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 888496#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 888495#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 888494#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 888493#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 888492#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 888491#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 729628#L1935-2 [2021-11-19 04:24:07,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:24:07,822 INFO L85 PathProgramCache]: Analyzing trace with hash -486503991, now seen corresponding path program 1 times [2021-11-19 04:24:07,822 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:24:07,822 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [62350964] [2021-11-19 04:24:07,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:24:07,823 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:24:07,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:24:07,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:24:07,874 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:24:07,875 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [62350964] [2021-11-19 04:24:07,876 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [62350964] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:24:07,878 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:24:07,878 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-19 04:24:07,878 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1531482366] [2021-11-19 04:24:07,878 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:24:07,879 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:24:07,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:24:07,880 INFO L85 PathProgramCache]: Analyzing trace with hash 1488029218, now seen corresponding path program 1 times [2021-11-19 04:24:07,880 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:24:07,880 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213130484] [2021-11-19 04:24:07,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:24:07,880 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:24:07,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:24:07,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:24:07,921 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:24:07,921 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [213130484] [2021-11-19 04:24:07,921 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [213130484] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:24:07,921 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:24:07,921 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:24:07,922 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [55314326] [2021-11-19 04:24:07,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:24:07,922 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:24:07,922 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:24:07,923 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 04:24:07,923 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 04:24:07,923 INFO L87 Difference]: Start difference. First operand 217153 states and 308719 transitions. cyclomatic complexity: 91598 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:24:10,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 04:24:10,175 INFO L93 Difference]: Finished difference Result 417776 states and 592072 transitions. [2021-11-19 04:24:10,175 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 04:24:10,176 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 417776 states and 592072 transitions. [2021-11-19 04:24:12,717 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 416496 [2021-11-19 04:24:14,420 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 417776 states to 417776 states and 592072 transitions. [2021-11-19 04:24:14,421 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 417776 [2021-11-19 04:24:14,590 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 417776 [2021-11-19 04:24:14,590 INFO L73 IsDeterministic]: Start isDeterministic. Operand 417776 states and 592072 transitions. [2021-11-19 04:24:14,738 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 04:24:14,739 INFO L681 BuchiCegarLoop]: Abstraction has 417776 states and 592072 transitions. [2021-11-19 04:24:14,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 417776 states and 592072 transitions. [2021-11-19 04:24:18,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 417776 to 417488. [2021-11-19 04:24:19,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 417488 states, 417488 states have (on average 1.4174874487410416) internal successors, (591784), 417487 states have internal predecessors, (591784), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 04:24:21,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 417488 states to 417488 states and 591784 transitions. [2021-11-19 04:24:21,291 INFO L704 BuchiCegarLoop]: Abstraction has 417488 states and 591784 transitions. [2021-11-19 04:24:21,292 INFO L587 BuchiCegarLoop]: Abstraction has 417488 states and 591784 transitions. [2021-11-19 04:24:21,292 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-19 04:24:21,292 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 417488 states and 591784 transitions. [2021-11-19 04:24:22,409 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 416208 [2021-11-19 04:24:22,409 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 04:24:22,409 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 04:24:22,413 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:24:22,414 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 04:24:22,414 INFO L791 eck$LassoCheckResult]: Stem: 1363205#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1363206#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1362939#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1362940#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1364585#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 1364586#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1363126#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1363127#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1363160#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1364082#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1364083#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1364226#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1364227#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1362945#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1362946#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1364275#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1363479#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1363480#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1364149#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1364555#L1286 assume !(0 == ~M_E~0); 1364363#L1286-2 assume !(0 == ~T1_E~0); 1362854#L1291-1 assume !(0 == ~T2_E~0); 1362855#L1296-1 assume !(0 == ~T3_E~0); 1363582#L1301-1 assume !(0 == ~T4_E~0); 1363583#L1306-1 assume !(0 == ~T5_E~0); 1364162#L1311-1 assume !(0 == ~T6_E~0); 1362814#L1316-1 assume !(0 == ~T7_E~0); 1362815#L1321-1 assume !(0 == ~T8_E~0); 1363601#L1326-1 assume !(0 == ~T9_E~0); 1362634#L1331-1 assume !(0 == ~T10_E~0); 1362343#L1336-1 assume !(0 == ~T11_E~0); 1362344#L1341-1 assume !(0 == ~T12_E~0); 1362395#L1346-1 assume !(0 == ~T13_E~0); 1362396#L1351-1 assume !(0 == ~E_M~0); 1362761#L1356-1 assume !(0 == ~E_1~0); 1362762#L1361-1 assume !(0 == ~E_2~0); 1364489#L1366-1 assume !(0 == ~E_3~0); 1362807#L1371-1 assume !(0 == ~E_4~0); 1362808#L1376-1 assume !(0 == ~E_5~0); 1363647#L1381-1 assume !(0 == ~E_6~0); 1363648#L1386-1 assume !(0 == ~E_7~0); 1364537#L1391-1 assume !(0 == ~E_8~0); 1364567#L1396-1 assume !(0 == ~E_9~0); 1363518#L1401-1 assume !(0 == ~E_10~0); 1363519#L1406-1 assume !(0 == ~E_11~0); 1363851#L1411-1 assume !(0 == ~E_12~0); 1363852#L1416-1 assume !(0 == ~E_13~0); 1363434#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1363268#L635 assume !(1 == ~m_pc~0); 1362415#L635-2 is_master_triggered_~__retres1~0#1 := 0; 1362416#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1362758#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1363396#L1598 assume !(0 != activate_threads_~tmp~1#1); 1362590#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1362591#L654 assume !(1 == ~t1_pc~0); 1363379#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1364277#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1364532#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1363375#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 1363376#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1362640#L673 assume !(1 == ~t2_pc~0); 1362642#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1363814#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1363815#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1364598#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 1364615#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1363458#L692 assume !(1 == ~t3_pc~0); 1363269#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1363270#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1363130#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1363095#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 1363096#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1362662#L711 assume !(1 == ~t4_pc~0); 1362663#L711-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1364267#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1363621#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1362368#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 1362369#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1364584#L730 assume !(1 == ~t5_pc~0); 1363745#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1362546#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1362547#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1362671#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 1362672#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1363007#L749 assume !(1 == ~t6_pc~0); 1362555#L749-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1362556#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1362974#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1362975#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 1363197#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1362350#L768 assume !(1 == ~t7_pc~0); 1362351#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1363670#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1362583#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1362584#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 1363691#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1362816#L787 assume !(1 == ~t8_pc~0); 1362817#L787-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1364382#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1364313#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1364314#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 1362393#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1362394#L806 assume 1 == ~t9_pc~0; 1364113#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1362428#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1362429#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1362673#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 1362674#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1364090#L825 assume !(1 == ~t10_pc~0); 1364091#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1363636#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1363637#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1362759#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1362760#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1363341#L844 assume 1 == ~t11_pc~0; 1363031#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1363032#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1363403#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1363404#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 1364076#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1364077#L863 assume !(1 == ~t12_pc~0); 1362531#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1362530#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1362749#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1364195#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 1364196#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1363474#L882 assume 1 == ~t13_pc~0; 1363475#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1363784#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1364437#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1364151#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 1363771#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1363772#L1434 assume !(1 == ~M_E~0); 1364449#L1434-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1364597#L1439-1 assume !(1 == ~T2_E~0); 1362655#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1362656#L1449-1 assume !(1 == ~T4_E~0); 1363855#L1454-1 assume !(1 == ~T5_E~0); 1364391#L1459-1 assume !(1 == ~T6_E~0); 1364392#L1464-1 assume !(1 == ~T7_E~0); 1363787#L1469-1 assume !(1 == ~T8_E~0); 1363788#L1474-1 assume !(1 == ~T9_E~0); 1363435#L1479-1 assume !(1 == ~T10_E~0); 1363436#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1363704#L1489-1 assume !(1 == ~T12_E~0); 1363304#L1494-1 assume !(1 == ~T13_E~0); 1363305#L1499-1 assume !(1 == ~E_M~0); 1364588#L1504-1 assume !(1 == ~E_1~0); 1582774#L1509-1 assume !(1 == ~E_2~0); 1582772#L1514-1 assume !(1 == ~E_3~0); 1582770#L1519-1 assume !(1 == ~E_4~0); 1582768#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1582766#L1529-1 assume !(1 == ~E_6~0); 1582730#L1534-1 assume !(1 == ~E_7~0); 1362450#L1539-1 assume !(1 == ~E_8~0); 1362451#L1544-1 assume !(1 == ~E_9~0); 1362872#L1549-1 assume !(1 == ~E_10~0); 1364469#L1554-1 assume !(1 == ~E_11~0); 1364467#L1559-1 assume !(1 == ~E_12~0); 1364255#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 1364256#L1569-1 assume { :end_inline_reset_delta_events } true; 1364502#L1935-2 [2021-11-19 04:24:22,415 INFO L793 eck$LassoCheckResult]: Loop: 1364502#L1935-2 assume !false; 1629877#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1629871#L1261 assume !false; 1629868#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1629789#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1629780#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1629757#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1629747#L1074 assume !(0 != eval_~tmp~0#1); 1629748#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1636916#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1636909#L1286-3 assume !(0 == ~M_E~0); 1636902#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1636895#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1636886#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1636878#L1301-3 assume !(0 == ~T4_E~0); 1636870#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1636862#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1636856#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1636850#L1321-3 assume !(0 == ~T8_E~0); 1636844#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1636835#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1636829#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1636824#L1341-3 assume !(0 == ~T12_E~0); 1636808#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1636801#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1636794#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1636784#L1361-3 assume !(0 == ~E_2~0); 1636776#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1636769#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1636761#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1636754#L1381-3 assume !(0 == ~E_6~0); 1636747#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1636737#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1636730#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1636722#L1401-3 assume !(0 == ~E_10~0); 1636714#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1636704#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1636695#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1636684#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1636676#L635-45 assume !(1 == ~m_pc~0); 1636669#L635-47 is_master_triggered_~__retres1~0#1 := 0; 1636662#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1636655#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1636649#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1636640#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1636634#L654-45 assume !(1 == ~t1_pc~0); 1636559#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 1636550#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1636544#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1636536#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1636526#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1630344#L673-45 assume !(1 == ~t2_pc~0); 1630341#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 1630339#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1630337#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1630335#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 1630333#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1630331#L692-45 assume 1 == ~t3_pc~0; 1630329#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1630330#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1630417#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1630319#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1630317#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1630315#L711-45 assume !(1 == ~t4_pc~0); 1630313#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 1630311#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1630309#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1630307#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1630305#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1630303#L730-45 assume 1 == ~t5_pc~0; 1630300#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1630298#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1630295#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1630293#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1630291#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1630289#L749-45 assume !(1 == ~t6_pc~0); 1630287#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 1630285#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1630282#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1630280#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1630278#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1630276#L768-45 assume 1 == ~t7_pc~0; 1630273#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1630271#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1630268#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1630266#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1630264#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1630262#L787-45 assume !(1 == ~t8_pc~0); 1630260#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 1630258#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1630255#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1630253#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1630251#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1630249#L806-45 assume 1 == ~t9_pc~0; 1630246#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1630244#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1630241#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1630239#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1630237#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1630235#L825-45 assume !(1 == ~t10_pc~0); 1630232#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 1630231#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1630230#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1630229#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1630228#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1630227#L844-45 assume 1 == ~t11_pc~0; 1630180#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1630178#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1630176#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1630174#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 1630172#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1630169#L863-45 assume 1 == ~t12_pc~0; 1630166#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1630164#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1630162#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1630160#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1630158#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1630155#L882-45 assume !(1 == ~t13_pc~0); 1630152#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 1630150#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1630148#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1630146#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1630144#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1630141#L1434-3 assume !(1 == ~M_E~0); 1630137#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1542433#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1630134#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1630132#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1630130#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1630127#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1630125#L1464-3 assume !(1 == ~T7_E~0); 1630123#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1591719#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1630120#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1630117#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1630115#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1630114#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1630112#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1630110#L1504-3 assume !(1 == ~E_1~0); 1630108#L1509-3 assume !(1 == ~E_2~0); 1630106#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1630104#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1630102#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1630101#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1630099#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1630097#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1630095#L1544-3 assume !(1 == ~E_9~0); 1630093#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1581808#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1630090#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1630088#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1630086#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1630073#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1630063#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1630061#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1630059#L1954 assume !(0 == start_simulation_~tmp~3#1); 1630057#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1629901#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1629891#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1629889#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1629887#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1629884#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1629882#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1629880#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 1364502#L1935-2 [2021-11-19 04:24:22,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:24:22,416 INFO L85 PathProgramCache]: Analyzing trace with hash -108861174, now seen corresponding path program 1 times [2021-11-19 04:24:22,416 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:24:22,416 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [146369326] [2021-11-19 04:24:22,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:24:22,417 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:24:22,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:24:22,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:24:22,463 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:24:22,463 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [146369326] [2021-11-19 04:24:22,463 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [146369326] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:24:22,463 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:24:22,464 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:24:22,464 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [23912722] [2021-11-19 04:24:22,464 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:24:22,464 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 04:24:22,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 04:24:22,465 INFO L85 PathProgramCache]: Analyzing trace with hash 486092258, now seen corresponding path program 1 times [2021-11-19 04:24:22,465 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 04:24:22,465 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1310085726] [2021-11-19 04:24:22,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 04:24:22,466 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 04:24:22,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 04:24:22,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 04:24:22,507 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 04:24:22,507 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1310085726] [2021-11-19 04:24:22,507 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1310085726] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 04:24:22,507 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 04:24:22,508 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 04:24:22,508 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [858526916] [2021-11-19 04:24:22,508 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 04:24:22,508 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 04:24:22,509 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 04:24:22,509 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-19 04:24:22,509 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-19 04:24:22,509 INFO L87 Difference]: Start difference. First operand 417488 states and 591784 transitions. cyclomatic complexity: 174360 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)