./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.16.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0f8a17c6 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/bin/uautomizer-ZXIjhQolGL/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/bin/uautomizer-ZXIjhQolGL/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/bin/uautomizer-ZXIjhQolGL/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/bin/uautomizer-ZXIjhQolGL/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.16.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/bin/uautomizer-ZXIjhQolGL/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/bin/uautomizer-ZXIjhQolGL --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-0f8a17c [2021-11-19 05:31:48,322 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-19 05:31:48,324 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-19 05:31:48,373 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-19 05:31:48,374 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-19 05:31:48,378 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-19 05:31:48,381 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-19 05:31:48,385 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-19 05:31:48,388 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-19 05:31:48,396 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-19 05:31:48,397 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-19 05:31:48,399 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-19 05:31:48,399 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-19 05:31:48,403 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-19 05:31:48,406 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-19 05:31:48,411 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-19 05:31:48,414 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-19 05:31:48,415 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-19 05:31:48,417 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-19 05:31:48,420 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-19 05:31:48,422 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-19 05:31:48,426 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-19 05:31:48,429 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-19 05:31:48,430 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-19 05:31:48,442 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-19 05:31:48,442 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-19 05:31:48,442 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-19 05:31:48,445 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-19 05:31:48,445 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-19 05:31:48,446 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-19 05:31:48,447 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-19 05:31:48,448 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-19 05:31:48,450 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-19 05:31:48,451 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-19 05:31:48,452 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-19 05:31:48,452 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-19 05:31:48,453 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-19 05:31:48,453 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-19 05:31:48,453 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-19 05:31:48,454 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-19 05:31:48,455 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-19 05:31:48,456 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/bin/uautomizer-ZXIjhQolGL/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-19 05:31:48,487 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-19 05:31:48,488 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-19 05:31:48,489 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-19 05:31:48,489 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-19 05:31:48,490 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-19 05:31:48,491 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-19 05:31:48,491 INFO L138 SettingsManager]: * Use SBE=true [2021-11-19 05:31:48,492 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-19 05:31:48,492 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-19 05:31:48,492 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-19 05:31:48,493 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-19 05:31:48,493 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-19 05:31:48,494 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-19 05:31:48,494 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-19 05:31:48,494 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-19 05:31:48,494 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-19 05:31:48,495 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-19 05:31:48,495 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-19 05:31:48,495 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-19 05:31:48,495 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-19 05:31:48,496 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-19 05:31:48,496 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-19 05:31:48,496 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-19 05:31:48,496 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-19 05:31:48,496 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-19 05:31:48,497 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-19 05:31:48,499 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-19 05:31:48,499 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-19 05:31:48,499 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-19 05:31:48,499 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-19 05:31:48,500 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-19 05:31:48,500 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-19 05:31:48,501 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-19 05:31:48,502 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/bin/uautomizer-ZXIjhQolGL/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/bin/uautomizer-ZXIjhQolGL Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 [2021-11-19 05:31:48,766 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-19 05:31:48,794 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-19 05:31:48,798 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-19 05:31:48,799 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-19 05:31:48,800 INFO L275 PluginConnector]: CDTParser initialized [2021-11-19 05:31:48,802 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/bin/uautomizer-ZXIjhQolGL/../../sv-benchmarks/c/systemc/transmitter.16.cil.c [2021-11-19 05:31:48,906 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/bin/uautomizer-ZXIjhQolGL/data/42e50c1d2/920d5c16208e4542b06a78bd48added2/FLAG038bc415e [2021-11-19 05:31:49,418 INFO L306 CDTParser]: Found 1 translation units. [2021-11-19 05:31:49,428 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/sv-benchmarks/c/systemc/transmitter.16.cil.c [2021-11-19 05:31:49,443 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/bin/uautomizer-ZXIjhQolGL/data/42e50c1d2/920d5c16208e4542b06a78bd48added2/FLAG038bc415e [2021-11-19 05:31:49,727 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/bin/uautomizer-ZXIjhQolGL/data/42e50c1d2/920d5c16208e4542b06a78bd48added2 [2021-11-19 05:31:49,730 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-19 05:31:49,731 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-19 05:31:49,738 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-19 05:31:49,738 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-19 05:31:49,756 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-19 05:31:49,757 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 05:31:49" (1/1) ... [2021-11-19 05:31:49,758 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@72bd06f4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:31:49, skipping insertion in model container [2021-11-19 05:31:49,758 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 05:31:49" (1/1) ... [2021-11-19 05:31:49,766 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-19 05:31:49,844 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-19 05:31:50,007 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2021-11-19 05:31:50,155 INFO L207 PostProcessor]: Analyzing one entry point: main [2021-11-19 05:31:50,168 INFO L203 MainTranslator]: Completed pre-run [2021-11-19 05:31:50,180 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2021-11-19 05:31:50,258 INFO L207 PostProcessor]: Analyzing one entry point: main [2021-11-19 05:31:50,287 INFO L208 MainTranslator]: Completed translation [2021-11-19 05:31:50,287 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:31:50 WrapperNode [2021-11-19 05:31:50,287 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-19 05:31:50,289 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-19 05:31:50,289 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-19 05:31:50,289 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-19 05:31:50,297 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:31:50" (1/1) ... [2021-11-19 05:31:50,314 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:31:50" (1/1) ... [2021-11-19 05:31:50,469 INFO L137 Inliner]: procedures = 56, calls = 71, calls flagged for inlining = 66, calls inlined = 303, statements flattened = 4715 [2021-11-19 05:31:50,470 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-19 05:31:50,471 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-19 05:31:50,471 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-19 05:31:50,471 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-19 05:31:50,480 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:31:50" (1/1) ... [2021-11-19 05:31:50,480 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:31:50" (1/1) ... [2021-11-19 05:31:50,490 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:31:50" (1/1) ... [2021-11-19 05:31:50,490 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:31:50" (1/1) ... [2021-11-19 05:31:50,557 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:31:50" (1/1) ... [2021-11-19 05:31:50,593 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:31:50" (1/1) ... [2021-11-19 05:31:50,599 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:31:50" (1/1) ... [2021-11-19 05:31:50,655 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-19 05:31:50,656 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-19 05:31:50,656 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-19 05:31:50,656 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-19 05:31:50,683 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:31:50" (1/1) ... [2021-11-19 05:31:50,694 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-19 05:31:50,706 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/bin/uautomizer-ZXIjhQolGL/z3 [2021-11-19 05:31:50,722 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/bin/uautomizer-ZXIjhQolGL/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-19 05:31:50,740 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46dc7f5b-8d51-4b79-b72a-5c45e035068c/bin/uautomizer-ZXIjhQolGL/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-19 05:31:50,776 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-11-19 05:31:50,777 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-19 05:31:50,777 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-19 05:31:50,777 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-19 05:31:50,970 INFO L236 CfgBuilder]: Building ICFG [2021-11-19 05:31:50,972 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-11-19 05:31:53,302 INFO L277 CfgBuilder]: Performing block encoding [2021-11-19 05:31:53,326 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-19 05:31:53,327 INFO L301 CfgBuilder]: Removed 18 assume(true) statements. [2021-11-19 05:31:53,332 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 05:31:53 BoogieIcfgContainer [2021-11-19 05:31:53,332 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-19 05:31:53,333 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-19 05:31:53,334 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-19 05:31:53,337 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-19 05:31:53,338 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-19 05:31:53,338 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 05:31:49" (1/3) ... [2021-11-19 05:31:53,340 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2da54346 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 05:31:53, skipping insertion in model container [2021-11-19 05:31:53,340 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-19 05:31:53,340 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 05:31:50" (2/3) ... [2021-11-19 05:31:53,341 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2da54346 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 05:31:53, skipping insertion in model container [2021-11-19 05:31:53,341 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-19 05:31:53,341 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 05:31:53" (3/3) ... [2021-11-19 05:31:53,342 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.16.cil.c [2021-11-19 05:31:53,404 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-19 05:31:53,404 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-19 05:31:53,404 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-19 05:31:53,404 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-19 05:31:53,404 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-19 05:31:53,404 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-19 05:31:53,405 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-19 05:31:53,405 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-19 05:31:53,471 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2053 states, 2052 states have (on average 1.4995126705653021) internal successors, (3077), 2052 states have internal predecessors, (3077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:53,571 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1864 [2021-11-19 05:31:53,571 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:53,571 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:53,594 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:53,594 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:53,594 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-19 05:31:53,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2053 states, 2052 states have (on average 1.4995126705653021) internal successors, (3077), 2052 states have internal predecessors, (3077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:53,629 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1864 [2021-11-19 05:31:53,629 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:53,630 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:53,638 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:53,638 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:53,649 INFO L791 eck$LassoCheckResult]: Stem: 490#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 1963#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 967#L1980true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 327#L932true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1919#L939true assume !(1 == ~m_i~0);~m_st~0 := 2; 471#L939-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1669#L944-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 311#L949-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1324#L954-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1969#L959-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 680#L964-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1176#L969-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1779#L974-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 615#L979-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 952#L984-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 257#L989-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 449#L994-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1206#L999-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 580#L1004-1true assume !(1 == ~t14_i~0);~t14_st~0 := 2; 48#L1009-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 127#L1342true assume !(0 == ~M_E~0); 429#L1342-2true assume !(0 == ~T1_E~0); 1614#L1347-1true assume !(0 == ~T2_E~0); 1304#L1352-1true assume !(0 == ~T3_E~0); 1073#L1357-1true assume !(0 == ~T4_E~0); 445#L1362-1true assume !(0 == ~T5_E~0); 1387#L1367-1true assume !(0 == ~T6_E~0); 215#L1372-1true assume 0 == ~T7_E~0;~T7_E~0 := 1; 568#L1377-1true assume !(0 == ~T8_E~0); 401#L1382-1true assume !(0 == ~T9_E~0); 946#L1387-1true assume !(0 == ~T10_E~0); 1525#L1392-1true assume !(0 == ~T11_E~0); 420#L1397-1true assume !(0 == ~T12_E~0); 1682#L1402-1true assume !(0 == ~T13_E~0); 224#L1407-1true assume !(0 == ~T14_E~0); 1860#L1412-1true assume 0 == ~E_1~0;~E_1~0 := 1; 1201#L1417-1true assume !(0 == ~E_2~0); 2053#L1422-1true assume !(0 == ~E_3~0); 1681#L1427-1true assume !(0 == ~E_4~0); 331#L1432-1true assume !(0 == ~E_5~0); 1532#L1437-1true assume !(0 == ~E_6~0); 1118#L1442-1true assume !(0 == ~E_7~0); 1459#L1447-1true assume !(0 == ~E_8~0); 942#L1452-1true assume 0 == ~E_9~0;~E_9~0 := 1; 113#L1457-1true assume !(0 == ~E_10~0); 1154#L1462-1true assume !(0 == ~E_11~0); 1857#L1467-1true assume !(0 == ~E_12~0); 1172#L1472-1true assume !(0 == ~E_13~0); 1360#L1477-1true assume !(0 == ~E_14~0); 894#L1482-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 210#L646true assume 1 == ~m_pc~0; 624#L647true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 632#L657true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 663#L658true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 258#L1666true assume !(0 != activate_threads_~tmp~1#1); 1984#L1666-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1747#L665true assume !(1 == ~t1_pc~0); 541#L665-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1200#L676true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 262#L677true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1708#L1674true assume !(0 != activate_threads_~tmp___0~0#1); 779#L1674-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 890#L684true assume 1 == ~t2_pc~0; 1868#L685true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 881#L695true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1693#L696true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1308#L1682true assume !(0 != activate_threads_~tmp___1~0#1); 1813#L1682-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1789#L703true assume !(1 == ~t3_pc~0); 342#L703-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1403#L714true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 771#L715true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35#L1690true assume !(0 != activate_threads_~tmp___2~0#1); 274#L1690-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1322#L722true assume 1 == ~t4_pc~0; 752#L723true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 603#L733true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1105#L734true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1623#L1698true assume !(0 != activate_threads_~tmp___3~0#1); 649#L1698-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 128#L741true assume 1 == ~t5_pc~0; 288#L742true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 806#L752true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 374#L753true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 860#L1706true assume !(0 != activate_threads_~tmp___4~0#1); 1385#L1706-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 430#L760true assume !(1 == ~t6_pc~0); 739#L760-2true is_transmit6_triggered_~__retres1~6#1 := 0; 986#L771true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 259#L772true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1660#L1714true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 719#L1714-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1402#L779true assume 1 == ~t7_pc~0; 148#L780true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 76#L790true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 281#L791true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1377#L1722true assume !(0 != activate_threads_~tmp___6~0#1); 295#L1722-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1691#L798true assume !(1 == ~t8_pc~0); 1935#L798-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1262#L809true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 149#L810true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1749#L1730true assume !(0 != activate_threads_~tmp___7~0#1); 1907#L1730-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66#L817true assume 1 == ~t9_pc~0; 828#L818true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 495#L828true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 899#L829true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1862#L1738true assume !(0 != activate_threads_~tmp___8~0#1); 265#L1738-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 773#L836true assume !(1 == ~t10_pc~0); 276#L836-2true is_transmit10_triggered_~__retres1~10#1 := 0; 238#L847true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1563#L848true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 377#L1746true assume !(0 != activate_threads_~tmp___9~0#1); 1276#L1746-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1277#L855true assume 1 == ~t11_pc~0; 630#L856true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1147#L866true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1245#L867true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 939#L1754true assume !(0 != activate_threads_~tmp___10~0#1); 784#L1754-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 208#L874true assume !(1 == ~t12_pc~0); 1641#L874-2true is_transmit12_triggered_~__retres1~12#1 := 0; 300#L885true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 378#L886true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1987#L1762true assume !(0 != activate_threads_~tmp___11~0#1); 52#L1762-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1861#L893true assume 1 == ~t13_pc~0; 1545#L894true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 400#L904true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1386#L905true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1560#L1770true assume !(0 != activate_threads_~tmp___12~0#1); 1396#L1770-2true assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1767#L912true assume 1 == ~t14_pc~0; 1123#L913true assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 2023#L923true is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 209#L924true activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 174#L1778true assume !(0 != activate_threads_~tmp___13~0#1); 643#L1778-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1342#L1495true assume 1 == ~M_E~0;~M_E~0 := 2; 1001#L1495-2true assume !(1 == ~T1_E~0); 1674#L1500-1true assume !(1 == ~T2_E~0); 716#L1505-1true assume !(1 == ~T3_E~0); 1914#L1510-1true assume !(1 == ~T4_E~0); 759#L1515-1true assume !(1 == ~T5_E~0); 1727#L1520-1true assume !(1 == ~T6_E~0); 1394#L1525-1true assume !(1 == ~T7_E~0); 1031#L1530-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 263#L1535-1true assume !(1 == ~T9_E~0); 1837#L1540-1true assume !(1 == ~T10_E~0); 17#L1545-1true assume !(1 == ~T11_E~0); 1973#L1550-1true assume !(1 == ~T12_E~0); 132#L1555-1true assume !(1 == ~T13_E~0); 289#L1560-1true assume !(1 == ~T14_E~0); 1706#L1565-1true assume !(1 == ~E_1~0); 1928#L1570-1true assume 1 == ~E_2~0;~E_2~0 := 2; 913#L1575-1true assume !(1 == ~E_3~0); 446#L1580-1true assume !(1 == ~E_4~0); 774#L1585-1true assume !(1 == ~E_5~0); 1045#L1590-1true assume !(1 == ~E_6~0); 468#L1595-1true assume !(1 == ~E_7~0); 1895#L1600-1true assume !(1 == ~E_8~0); 723#L1605-1true assume !(1 == ~E_9~0); 1649#L1610-1true assume 1 == ~E_10~0;~E_10~0 := 2; 1240#L1615-1true assume !(1 == ~E_11~0); 365#L1620-1true assume !(1 == ~E_12~0); 1103#L1625-1true assume !(1 == ~E_13~0); 943#L1630-1true assume !(1 == ~E_14~0); 467#L1635-1true assume { :end_inline_reset_delta_events } true; 431#L2017-2true [2021-11-19 05:31:53,653 INFO L793 eck$LassoCheckResult]: Loop: 431#L2017-2true assume !false; 50#L2018true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 882#L1316true assume !true; 1267#L1332true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 502#L932-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 629#L1342-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1078#L1342-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1167#L1347-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 751#L1352-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1355#L1357-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 2038#L1362-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1880#L1367-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1847#L1372-3true assume !(0 == ~T7_E~0); 42#L1377-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 491#L1382-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 388#L1387-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1124#L1392-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1948#L1397-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 1666#L1402-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 708#L1407-3true assume 0 == ~T14_E~0;~T14_E~0 := 1; 188#L1412-3true assume !(0 == ~E_1~0); 1397#L1417-3true assume 0 == ~E_2~0;~E_2~0 := 1; 654#L1422-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1347#L1427-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1534#L1432-3true assume 0 == ~E_5~0;~E_5~0 := 1; 976#L1437-3true assume 0 == ~E_6~0;~E_6~0 := 1; 720#L1442-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1000#L1447-3true assume 0 == ~E_8~0;~E_8~0 := 1; 73#L1452-3true assume !(0 == ~E_9~0); 1999#L1457-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1258#L1462-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1689#L1467-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1048#L1472-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1714#L1477-3true assume 0 == ~E_14~0;~E_14~0 := 1; 187#L1482-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 523#L646-42true assume 1 == ~m_pc~0; 1978#L647-14true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1306#L657-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1676#L658-14true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1619#L1666-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1711#L1666-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1216#L665-42true assume !(1 == ~t1_pc~0); 1456#L665-44true is_transmit1_triggered_~__retres1~1#1 := 0; 1538#L676-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1463#L677-14true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 277#L1674-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1883#L1674-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1879#L684-42true assume !(1 == ~t2_pc~0); 1793#L684-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1893#L695-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1808#L696-14true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 678#L1682-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 766#L1682-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1741#L703-42true assume 1 == ~t3_pc~0; 950#L704-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1851#L714-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 434#L715-14true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1630#L1690-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1052#L1690-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 698#L722-42true assume 1 == ~t4_pc~0; 1091#L723-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1719#L733-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 464#L734-14true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 357#L1698-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1920#L1698-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1730#L741-42true assume 1 == ~t5_pc~0; 1548#L742-14true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 606#L752-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1965#L753-14true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1898#L1706-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 536#L1706-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 636#L760-42true assume 1 == ~t6_pc~0; 1763#L761-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 730#L771-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1114#L772-14true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1638#L1714-42true assume !(0 != activate_threads_~tmp___5~0#1); 506#L1714-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1315#L779-42true assume 1 == ~t7_pc~0; 1242#L780-14true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1870#L790-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 319#L791-14true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1701#L1722-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 237#L1722-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 500#L798-42true assume 1 == ~t8_pc~0; 1924#L799-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1432#L809-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1330#L810-14true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 747#L1730-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 150#L1730-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1370#L817-42true assume !(1 == ~t9_pc~0); 1149#L817-44true is_transmit9_triggered_~__retres1~9#1 := 0; 303#L828-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 372#L829-14true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1186#L1738-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 974#L1738-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1515#L836-42true assume !(1 == ~t10_pc~0); 1817#L836-44true is_transmit10_triggered_~__retres1~10#1 := 0; 326#L847-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1842#L848-14true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1553#L1746-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1697#L1746-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2046#L855-42true assume 1 == ~t11_pc~0; 1722#L856-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 92#L866-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 503#L867-14true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1169#L1754-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2048#L1754-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 418#L874-42true assume 1 == ~t12_pc~0; 575#L875-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1487#L885-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51#L886-14true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 892#L1762-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 171#L1762-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1982#L893-42true assume 1 == ~t13_pc~0; 1007#L894-14true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1836#L904-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 808#L905-14true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 728#L1770-42true assume !(0 != activate_threads_~tmp___12~0#1); 375#L1770-44true assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1849#L912-42true assume !(1 == ~t14_pc~0); 981#L912-44true is_transmit14_triggered_~__retres1~14#1 := 0; 27#L923-14true is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1089#L924-14true activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1219#L1778-42true assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 233#L1778-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 611#L1495-3true assume !(1 == ~M_E~0); 966#L1495-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1574#L1500-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1070#L1505-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 360#L1510-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 343#L1515-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 783#L1520-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 997#L1525-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1580#L1530-3true assume !(1 == ~T8_E~0); 254#L1535-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 275#L1540-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1289#L1545-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1533#L1550-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1513#L1555-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 516#L1560-3true assume 1 == ~T14_E~0;~T14_E~0 := 2; 1025#L1565-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1874#L1570-3true assume !(1 == ~E_2~0); 970#L1575-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1421#L1580-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1522#L1585-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1759#L1590-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1663#L1595-3true assume 1 == ~E_7~0;~E_7~0 := 2; 803#L1600-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1309#L1605-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1398#L1610-3true assume !(1 == ~E_10~0); 366#L1615-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1912#L1620-3true assume 1 == ~E_12~0;~E_12~0 := 2; 776#L1625-3true assume 1 == ~E_13~0;~E_13~0 := 2; 2041#L1630-3true assume 1 == ~E_14~0;~E_14~0 := 2; 700#L1635-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 336#L1022-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 539#L1100-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1967#L1101-1true start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 999#L2036true assume !(0 == start_simulation_~tmp~3#1); 1175#L2036-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1631#L1022-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1422#L1100-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1927#L1101-2true stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 733#L1991true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1734#L1998true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1704#L1999true start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1807#L2049true assume !(0 != start_simulation_~tmp___0~1#1); 431#L2017-2true [2021-11-19 05:31:53,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:53,660 INFO L85 PathProgramCache]: Analyzing trace with hash -1440429276, now seen corresponding path program 1 times [2021-11-19 05:31:53,669 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:53,670 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1796572389] [2021-11-19 05:31:53,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:53,671 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:53,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:53,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:53,972 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:53,972 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1796572389] [2021-11-19 05:31:53,973 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1796572389] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:53,973 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:53,974 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:53,976 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1988719187] [2021-11-19 05:31:53,977 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:53,982 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:31:53,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:53,983 INFO L85 PathProgramCache]: Analyzing trace with hash 1941229649, now seen corresponding path program 1 times [2021-11-19 05:31:53,983 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:53,984 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [766719073] [2021-11-19 05:31:53,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:53,984 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:54,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:54,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:54,084 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:54,084 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [766719073] [2021-11-19 05:31:54,085 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [766719073] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:54,085 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:54,085 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-19 05:31:54,085 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984877110] [2021-11-19 05:31:54,086 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:54,087 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:31:54,088 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:31:54,120 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-11-19 05:31:54,121 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-11-19 05:31:54,128 INFO L87 Difference]: Start difference. First operand has 2053 states, 2052 states have (on average 1.4995126705653021) internal successors, (3077), 2052 states have internal predecessors, (3077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 83.5) internal successors, (167), 2 states have internal predecessors, (167), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:54,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:31:54,344 INFO L93 Difference]: Finished difference Result 2052 states and 3039 transitions. [2021-11-19 05:31:54,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-11-19 05:31:54,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2052 states and 3039 transitions. [2021-11-19 05:31:54,381 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:54,414 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2052 states to 2047 states and 3034 transitions. [2021-11-19 05:31:54,415 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-11-19 05:31:54,419 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-11-19 05:31:54,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3034 transitions. [2021-11-19 05:31:54,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:31:54,434 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3034 transitions. [2021-11-19 05:31:54,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3034 transitions. [2021-11-19 05:31:54,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-11-19 05:31:54,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4821690278456277) internal successors, (3034), 2046 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:54,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3034 transitions. [2021-11-19 05:31:54,545 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3034 transitions. [2021-11-19 05:31:54,545 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3034 transitions. [2021-11-19 05:31:54,545 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-19 05:31:54,546 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3034 transitions. [2021-11-19 05:31:54,562 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:54,563 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:54,563 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:54,570 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:54,570 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:54,572 INFO L791 eck$LassoCheckResult]: Stem: 5040#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 5041#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 5643#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4760#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4761#L939 assume !(1 == ~m_i~0);~m_st~0 := 2; 5006#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5007#L944-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4734#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4735#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5958#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5310#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5311#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5828#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5220#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5221#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4641#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4642#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4973#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5171#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 4218#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4219#L1342 assume !(0 == ~M_E~0); 4384#L1342-2 assume !(0 == ~T1_E~0); 4940#L1347-1 assume !(0 == ~T2_E~0); 5941#L1352-1 assume !(0 == ~T3_E~0); 5737#L1357-1 assume !(0 == ~T4_E~0); 4965#L1362-1 assume !(0 == ~T5_E~0); 4966#L1367-1 assume !(0 == ~T6_E~0); 4563#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4564#L1377-1 assume !(0 == ~T8_E~0); 4894#L1382-1 assume !(0 == ~T9_E~0); 4895#L1387-1 assume !(0 == ~T10_E~0); 5622#L1392-1 assume !(0 == ~T11_E~0); 4926#L1397-1 assume !(0 == ~T12_E~0); 4927#L1402-1 assume !(0 == ~T13_E~0); 4579#L1407-1 assume !(0 == ~T14_E~0); 4580#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 5858#L1417-1 assume !(0 == ~E_2~0); 5859#L1422-1 assume !(0 == ~E_3~0); 6100#L1427-1 assume !(0 == ~E_4~0); 4767#L1432-1 assume !(0 == ~E_5~0); 4768#L1437-1 assume !(0 == ~E_6~0); 5776#L1442-1 assume !(0 == ~E_7~0); 5777#L1447-1 assume !(0 == ~E_8~0); 5619#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 4354#L1457-1 assume !(0 == ~E_10~0); 4355#L1462-1 assume !(0 == ~E_11~0); 5811#L1467-1 assume !(0 == ~E_12~0); 5823#L1472-1 assume !(0 == ~E_13~0); 5824#L1477-1 assume !(0 == ~E_14~0); 5566#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4553#L646 assume 1 == ~m_pc~0; 4554#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5230#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5245#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4643#L1666 assume !(0 != activate_threads_~tmp~1#1); 4644#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6121#L665 assume !(1 == ~t1_pc~0); 5119#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5120#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4652#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4653#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 5443#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5444#L684 assume 1 == ~t2_pc~0; 5561#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5485#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5550#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5945#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 5946#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6134#L703 assume !(1 == ~t3_pc~0); 4789#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4790#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5436#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4188#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 4189#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4674#L722 assume 1 == ~t4_pc~0; 5412#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4855#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5200#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5760#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 5267#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4385#L741 assume 1 == ~t5_pc~0; 4386#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4696#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4850#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4851#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 5530#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4941#L760 assume !(1 == ~t6_pc~0); 4788#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4787#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4645#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4646#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5367#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5368#L779 assume 1 == ~t7_pc~0; 4430#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4276#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4277#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4685#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 4708#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4709#L798 assume !(1 == ~t8_pc~0); 5990#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5913#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4432#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4433#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 6123#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4253#L817 assume 1 == ~t9_pc~0; 4254#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5048#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5049#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5571#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 4659#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4660#L836 assume !(1 == ~t10_pc~0); 4676#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4607#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4608#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4856#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 4857#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5923#L855 assume 1 == ~t11_pc~0; 5241#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5242#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5806#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5615#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 5450#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4549#L874 assume !(1 == ~t12_pc~0); 4550#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4717#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4718#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4858#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 4226#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4227#L893 assume 1 == ~t13_pc~0; 6057#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4582#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4893#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5984#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 5992#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 5993#L912 assume 1 == ~t14_pc~0; 5783#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 5784#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 4552#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 4484#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 4485#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5260#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 5676#L1495-2 assume !(1 == ~T1_E~0); 5677#L1500-1 assume !(1 == ~T2_E~0); 5363#L1505-1 assume !(1 == ~T3_E~0); 5364#L1510-1 assume !(1 == ~T4_E~0); 5421#L1515-1 assume !(1 == ~T5_E~0); 5422#L1520-1 assume !(1 == ~T6_E~0); 5991#L1525-1 assume !(1 == ~T7_E~0); 5701#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4654#L1535-1 assume !(1 == ~T9_E~0); 4655#L1540-1 assume !(1 == ~T10_E~0); 4147#L1545-1 assume !(1 == ~T11_E~0); 4148#L1550-1 assume !(1 == ~T12_E~0); 4396#L1555-1 assume !(1 == ~T13_E~0); 4397#L1560-1 assume !(1 == ~T14_E~0); 4697#L1565-1 assume !(1 == ~E_1~0); 6110#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 5588#L1575-1 assume !(1 == ~E_3~0); 4967#L1580-1 assume !(1 == ~E_4~0); 4968#L1585-1 assume !(1 == ~E_5~0); 5438#L1590-1 assume !(1 == ~E_6~0); 5002#L1595-1 assume !(1 == ~E_7~0); 5003#L1600-1 assume !(1 == ~E_8~0); 5375#L1605-1 assume !(1 == ~E_9~0); 5376#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 5893#L1615-1 assume !(1 == ~E_11~0); 4832#L1620-1 assume !(1 == ~E_12~0); 4833#L1625-1 assume !(1 == ~E_13~0); 5620#L1630-1 assume !(1 == ~E_14~0); 5001#L1635-1 assume { :end_inline_reset_delta_events } true; 4942#L2017-2 [2021-11-19 05:31:54,575 INFO L793 eck$LassoCheckResult]: Loop: 4942#L2017-2 assume !false; 4222#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4223#L1316 assume !false; 5551#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 5613#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4160#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 4302#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4303#L1115 assume !(0 != eval_~tmp~0#1); 5636#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5057#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5058#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5240#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5741#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5410#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5411#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5973#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6148#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6143#L1372-3 assume !(0 == ~T7_E~0); 4204#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4205#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4874#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4875#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5786#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 6096#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 5354#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 4510#L1412-3 assume !(0 == ~E_1~0); 4511#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5275#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5276#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5970#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5657#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5369#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5370#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4270#L1452-3 assume !(0 == ~E_9~0); 4271#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 5909#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5910#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 5714#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5715#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 4508#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4509#L646-42 assume 1 == ~m_pc~0; 5094#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5942#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5943#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6081#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6082#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5874#L665-42 assume 1 == ~t1_pc~0; 5835#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5837#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6023#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4677#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4678#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6147#L684-42 assume 1 == ~t2_pc~0; 5526#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5527#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6137#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5306#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5307#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5429#L703-42 assume 1 == ~t3_pc~0; 5627#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5628#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4946#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4947#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5721#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5341#L722-42 assume 1 == ~t4_pc~0; 5342#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5752#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4995#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4822#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4823#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6117#L741-42 assume !(1 == ~t5_pc~0); 5734#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 5204#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5205#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6150#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5112#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5113#L760-42 assume 1 == ~t6_pc~0; 5248#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5382#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5383#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5771#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 5064#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5065#L779-42 assume !(1 == ~t7_pc~0); 5841#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 5842#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4749#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4750#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4605#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4606#L798-42 assume 1 == ~t8_pc~0; 5056#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4217#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5960#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5406#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4436#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4437#L817-42 assume 1 == ~t9_pc~0; 5210#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4720#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4721#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4847#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5652#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5653#L836-42 assume 1 == ~t10_pc~0; 5745#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4758#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4759#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 6060#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6061#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6102#L855-42 assume 1 == ~t11_pc~0; 6115#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4309#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4310#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5059#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5822#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4923#L874-42 assume 1 == ~t12_pc~0; 4924#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 5163#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4224#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4225#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4478#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4479#L893-42 assume 1 == ~t13_pc~0; 5681#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5463#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5478#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5380#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 4852#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 4853#L912-42 assume 1 == ~t14_pc~0; 6097#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 4170#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 4171#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5751#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 4598#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4599#L1495-3 assume !(1 == ~M_E~0); 5214#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5642#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5735#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4828#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4791#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4792#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5449#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5672#L1530-3 assume !(1 == ~T8_E~0); 4637#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4638#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4675#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5932#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 6041#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 5081#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 5082#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5697#L1570-3 assume !(1 == ~E_2~0); 5648#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5649#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6004#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6048#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6094#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5471#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5472#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5947#L1610-3 assume !(1 == ~E_10~0); 4834#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4835#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5439#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5440#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 5344#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 4775#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4380#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 5118#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 5674#L2036 assume !(0 == start_simulation_~tmp~3#1); 5675#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 5827#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4987#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 6005#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 5387#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5388#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6108#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 6109#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 4942#L2017-2 [2021-11-19 05:31:54,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:54,576 INFO L85 PathProgramCache]: Analyzing trace with hash -1440429276, now seen corresponding path program 2 times [2021-11-19 05:31:54,577 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:54,578 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1423726044] [2021-11-19 05:31:54,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:54,578 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:54,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:54,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:54,683 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:54,683 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1423726044] [2021-11-19 05:31:54,684 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1423726044] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:54,684 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:54,684 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:54,685 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [130296739] [2021-11-19 05:31:54,686 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:54,687 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:31:54,687 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:54,694 INFO L85 PathProgramCache]: Analyzing trace with hash 1105916303, now seen corresponding path program 1 times [2021-11-19 05:31:54,694 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:54,695 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1442520141] [2021-11-19 05:31:54,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:54,695 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:54,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:54,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:54,875 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:54,875 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1442520141] [2021-11-19 05:31:54,875 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1442520141] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:54,876 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:54,876 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:54,876 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1476200453] [2021-11-19 05:31:54,876 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:54,877 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:31:54,877 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:31:54,878 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:31:54,878 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:31:54,879 INFO L87 Difference]: Start difference. First operand 2047 states and 3034 transitions. cyclomatic complexity: 988 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:55,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:31:55,020 INFO L93 Difference]: Finished difference Result 2047 states and 3033 transitions. [2021-11-19 05:31:55,020 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:31:55,023 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3033 transitions. [2021-11-19 05:31:55,041 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:55,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3033 transitions. [2021-11-19 05:31:55,060 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-11-19 05:31:55,063 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-11-19 05:31:55,064 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3033 transitions. [2021-11-19 05:31:55,067 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:31:55,067 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3033 transitions. [2021-11-19 05:31:55,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3033 transitions. [2021-11-19 05:31:55,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-11-19 05:31:55,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4816805080605764) internal successors, (3033), 2046 states have internal predecessors, (3033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:55,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3033 transitions. [2021-11-19 05:31:55,114 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3033 transitions. [2021-11-19 05:31:55,114 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3033 transitions. [2021-11-19 05:31:55,115 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-19 05:31:55,115 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3033 transitions. [2021-11-19 05:31:55,127 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:55,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:55,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:55,137 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:55,137 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:55,138 INFO L791 eck$LassoCheckResult]: Stem: 9141#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 9142#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 9744#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8861#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8862#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 9107#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9108#L944-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8835#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8836#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10059#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9411#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9412#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9929#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9321#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9322#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8742#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8743#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9074#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 9272#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 8319#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8320#L1342 assume !(0 == ~M_E~0); 8485#L1342-2 assume !(0 == ~T1_E~0); 9041#L1347-1 assume !(0 == ~T2_E~0); 10042#L1352-1 assume !(0 == ~T3_E~0); 9838#L1357-1 assume !(0 == ~T4_E~0); 9066#L1362-1 assume !(0 == ~T5_E~0); 9067#L1367-1 assume !(0 == ~T6_E~0); 8664#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8665#L1377-1 assume !(0 == ~T8_E~0); 8995#L1382-1 assume !(0 == ~T9_E~0); 8996#L1387-1 assume !(0 == ~T10_E~0); 9723#L1392-1 assume !(0 == ~T11_E~0); 9027#L1397-1 assume !(0 == ~T12_E~0); 9028#L1402-1 assume !(0 == ~T13_E~0); 8680#L1407-1 assume !(0 == ~T14_E~0); 8681#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 9959#L1417-1 assume !(0 == ~E_2~0); 9960#L1422-1 assume !(0 == ~E_3~0); 10201#L1427-1 assume !(0 == ~E_4~0); 8868#L1432-1 assume !(0 == ~E_5~0); 8869#L1437-1 assume !(0 == ~E_6~0); 9877#L1442-1 assume !(0 == ~E_7~0); 9878#L1447-1 assume !(0 == ~E_8~0); 9720#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 8455#L1457-1 assume !(0 == ~E_10~0); 8456#L1462-1 assume !(0 == ~E_11~0); 9912#L1467-1 assume !(0 == ~E_12~0); 9924#L1472-1 assume !(0 == ~E_13~0); 9925#L1477-1 assume !(0 == ~E_14~0); 9667#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8654#L646 assume 1 == ~m_pc~0; 8655#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9331#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9346#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8744#L1666 assume !(0 != activate_threads_~tmp~1#1); 8745#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10222#L665 assume !(1 == ~t1_pc~0); 9220#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9221#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8753#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8754#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 9544#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9545#L684 assume 1 == ~t2_pc~0; 9662#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9586#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9651#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10046#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 10047#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10235#L703 assume !(1 == ~t3_pc~0); 8890#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8891#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9537#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8289#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 8290#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8775#L722 assume 1 == ~t4_pc~0; 9513#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8956#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9301#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9861#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 9368#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8486#L741 assume 1 == ~t5_pc~0; 8487#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8797#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8951#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8952#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 9631#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9042#L760 assume !(1 == ~t6_pc~0); 8889#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8888#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8746#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8747#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9468#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9469#L779 assume 1 == ~t7_pc~0; 8531#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8377#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8378#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8786#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 8809#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8810#L798 assume !(1 == ~t8_pc~0); 10091#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10014#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8533#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8534#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 10224#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8354#L817 assume 1 == ~t9_pc~0; 8355#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9149#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9150#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9672#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 8760#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8761#L836 assume !(1 == ~t10_pc~0); 8777#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8708#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8709#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8957#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 8958#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10024#L855 assume 1 == ~t11_pc~0; 9342#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9343#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9907#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9716#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 9551#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8650#L874 assume !(1 == ~t12_pc~0); 8651#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8818#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8819#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8959#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 8327#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8328#L893 assume 1 == ~t13_pc~0; 10158#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8683#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8994#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 10085#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 10093#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 10094#L912 assume 1 == ~t14_pc~0; 9884#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 9885#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 8653#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 8585#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 8586#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9361#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 9777#L1495-2 assume !(1 == ~T1_E~0); 9778#L1500-1 assume !(1 == ~T2_E~0); 9464#L1505-1 assume !(1 == ~T3_E~0); 9465#L1510-1 assume !(1 == ~T4_E~0); 9522#L1515-1 assume !(1 == ~T5_E~0); 9523#L1520-1 assume !(1 == ~T6_E~0); 10092#L1525-1 assume !(1 == ~T7_E~0); 9802#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8755#L1535-1 assume !(1 == ~T9_E~0); 8756#L1540-1 assume !(1 == ~T10_E~0); 8248#L1545-1 assume !(1 == ~T11_E~0); 8249#L1550-1 assume !(1 == ~T12_E~0); 8497#L1555-1 assume !(1 == ~T13_E~0); 8498#L1560-1 assume !(1 == ~T14_E~0); 8798#L1565-1 assume !(1 == ~E_1~0); 10211#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9689#L1575-1 assume !(1 == ~E_3~0); 9068#L1580-1 assume !(1 == ~E_4~0); 9069#L1585-1 assume !(1 == ~E_5~0); 9539#L1590-1 assume !(1 == ~E_6~0); 9103#L1595-1 assume !(1 == ~E_7~0); 9104#L1600-1 assume !(1 == ~E_8~0); 9476#L1605-1 assume !(1 == ~E_9~0); 9477#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 9994#L1615-1 assume !(1 == ~E_11~0); 8933#L1620-1 assume !(1 == ~E_12~0); 8934#L1625-1 assume !(1 == ~E_13~0); 9721#L1630-1 assume !(1 == ~E_14~0); 9102#L1635-1 assume { :end_inline_reset_delta_events } true; 9043#L2017-2 [2021-11-19 05:31:55,138 INFO L793 eck$LassoCheckResult]: Loop: 9043#L2017-2 assume !false; 8323#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8324#L1316 assume !false; 9652#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 9714#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 8261#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 8403#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8404#L1115 assume !(0 != eval_~tmp~0#1); 9737#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9158#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9159#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9341#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9842#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9511#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9512#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10074#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10249#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10244#L1372-3 assume !(0 == ~T7_E~0); 8305#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8306#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8975#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8976#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9887#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 10197#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 9455#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 8611#L1412-3 assume !(0 == ~E_1~0); 8612#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9376#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9377#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10071#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9758#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9470#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9471#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8371#L1452-3 assume !(0 == ~E_9~0); 8372#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 10010#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10011#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 9815#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9816#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 8609#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8610#L646-42 assume 1 == ~m_pc~0; 9195#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10043#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10044#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10182#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10183#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9975#L665-42 assume 1 == ~t1_pc~0; 9936#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9938#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10124#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8778#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8779#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10248#L684-42 assume 1 == ~t2_pc~0; 9627#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9628#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10238#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9407#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9408#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9530#L703-42 assume 1 == ~t3_pc~0; 9728#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9729#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9047#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9048#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9822#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9442#L722-42 assume 1 == ~t4_pc~0; 9443#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9853#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9096#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8923#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8924#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10218#L741-42 assume 1 == ~t5_pc~0; 10160#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9305#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9306#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10251#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9213#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9214#L760-42 assume !(1 == ~t6_pc~0); 9348#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 9483#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9484#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9872#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 9165#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9166#L779-42 assume !(1 == ~t7_pc~0); 9942#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 9943#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8850#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8851#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8706#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8707#L798-42 assume 1 == ~t8_pc~0; 9157#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8318#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10061#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9507#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8537#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8538#L817-42 assume !(1 == ~t9_pc~0); 9312#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 8821#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8822#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8948#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9753#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9754#L836-42 assume 1 == ~t10_pc~0; 9846#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8859#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8860#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10161#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 10162#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10203#L855-42 assume 1 == ~t11_pc~0; 10216#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8410#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8411#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9160#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 9923#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9024#L874-42 assume 1 == ~t12_pc~0; 9025#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 9264#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8325#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8326#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8579#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8580#L893-42 assume 1 == ~t13_pc~0; 9782#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9564#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9579#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9481#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 8953#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 8954#L912-42 assume !(1 == ~t14_pc~0); 9763#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 8271#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 8272#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9852#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 8699#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8700#L1495-3 assume !(1 == ~M_E~0); 9315#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9743#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9836#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8929#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8892#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8893#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9550#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9773#L1530-3 assume !(1 == ~T8_E~0); 8738#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8739#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8776#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10033#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 10142#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 9182#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 9183#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9798#L1570-3 assume !(1 == ~E_2~0); 9749#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9750#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10105#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10149#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10195#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9572#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9573#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10048#L1610-3 assume !(1 == ~E_10~0); 8935#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8936#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 9540#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 9541#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 9445#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 8876#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 8481#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 9219#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 9775#L2036 assume !(0 == start_simulation_~tmp~3#1); 9776#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 9928#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 9088#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 10106#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 9488#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 9489#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10209#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 10210#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 9043#L2017-2 [2021-11-19 05:31:55,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:55,142 INFO L85 PathProgramCache]: Analyzing trace with hash -1949208090, now seen corresponding path program 1 times [2021-11-19 05:31:55,143 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:55,143 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1584272917] [2021-11-19 05:31:55,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:55,144 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:55,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:55,240 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:55,245 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:55,246 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1584272917] [2021-11-19 05:31:55,246 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1584272917] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:55,246 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:55,247 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:55,247 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1936658757] [2021-11-19 05:31:55,247 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:55,248 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:31:55,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:55,250 INFO L85 PathProgramCache]: Analyzing trace with hash -812799539, now seen corresponding path program 1 times [2021-11-19 05:31:55,250 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:55,251 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396020851] [2021-11-19 05:31:55,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:55,252 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:55,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:55,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:55,358 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:55,358 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1396020851] [2021-11-19 05:31:55,359 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1396020851] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:55,359 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:55,359 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:55,360 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1230403829] [2021-11-19 05:31:55,361 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:55,361 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:31:55,361 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:31:55,362 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:31:55,362 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:31:55,363 INFO L87 Difference]: Start difference. First operand 2047 states and 3033 transitions. cyclomatic complexity: 987 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:55,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:31:55,420 INFO L93 Difference]: Finished difference Result 2047 states and 3032 transitions. [2021-11-19 05:31:55,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:31:55,422 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3032 transitions. [2021-11-19 05:31:55,441 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:55,459 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3032 transitions. [2021-11-19 05:31:55,459 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-11-19 05:31:55,461 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-11-19 05:31:55,462 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3032 transitions. [2021-11-19 05:31:55,466 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:31:55,466 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3032 transitions. [2021-11-19 05:31:55,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3032 transitions. [2021-11-19 05:31:55,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-11-19 05:31:55,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4811919882755251) internal successors, (3032), 2046 states have internal predecessors, (3032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:55,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3032 transitions. [2021-11-19 05:31:55,574 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3032 transitions. [2021-11-19 05:31:55,574 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3032 transitions. [2021-11-19 05:31:55,574 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-19 05:31:55,574 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3032 transitions. [2021-11-19 05:31:55,587 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:55,587 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:55,587 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:55,590 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:55,590 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:55,591 INFO L791 eck$LassoCheckResult]: Stem: 13242#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 13243#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 13845#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12962#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12963#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 13208#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13209#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12936#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12937#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 14160#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13512#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13513#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14030#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13422#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13423#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12843#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12844#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13175#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13373#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 12420#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12421#L1342 assume !(0 == ~M_E~0); 12586#L1342-2 assume !(0 == ~T1_E~0); 13142#L1347-1 assume !(0 == ~T2_E~0); 14143#L1352-1 assume !(0 == ~T3_E~0); 13939#L1357-1 assume !(0 == ~T4_E~0); 13167#L1362-1 assume !(0 == ~T5_E~0); 13168#L1367-1 assume !(0 == ~T6_E~0); 12765#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12766#L1377-1 assume !(0 == ~T8_E~0); 13096#L1382-1 assume !(0 == ~T9_E~0); 13097#L1387-1 assume !(0 == ~T10_E~0); 13824#L1392-1 assume !(0 == ~T11_E~0); 13128#L1397-1 assume !(0 == ~T12_E~0); 13129#L1402-1 assume !(0 == ~T13_E~0); 12781#L1407-1 assume !(0 == ~T14_E~0); 12782#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 14060#L1417-1 assume !(0 == ~E_2~0); 14061#L1422-1 assume !(0 == ~E_3~0); 14302#L1427-1 assume !(0 == ~E_4~0); 12969#L1432-1 assume !(0 == ~E_5~0); 12970#L1437-1 assume !(0 == ~E_6~0); 13978#L1442-1 assume !(0 == ~E_7~0); 13979#L1447-1 assume !(0 == ~E_8~0); 13821#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 12556#L1457-1 assume !(0 == ~E_10~0); 12557#L1462-1 assume !(0 == ~E_11~0); 14013#L1467-1 assume !(0 == ~E_12~0); 14025#L1472-1 assume !(0 == ~E_13~0); 14026#L1477-1 assume !(0 == ~E_14~0); 13768#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12755#L646 assume 1 == ~m_pc~0; 12756#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13432#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13447#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12845#L1666 assume !(0 != activate_threads_~tmp~1#1); 12846#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14323#L665 assume !(1 == ~t1_pc~0); 13321#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13322#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12854#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12855#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 13645#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13646#L684 assume 1 == ~t2_pc~0; 13763#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13687#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13752#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14147#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 14148#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14336#L703 assume !(1 == ~t3_pc~0); 12991#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12992#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13638#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12390#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 12391#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12876#L722 assume 1 == ~t4_pc~0; 13614#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13057#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13402#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13962#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 13469#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12587#L741 assume 1 == ~t5_pc~0; 12588#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12898#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13052#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13053#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 13732#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13143#L760 assume !(1 == ~t6_pc~0); 12990#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12989#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12847#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12848#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13569#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13570#L779 assume 1 == ~t7_pc~0; 12632#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12478#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12479#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12887#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 12910#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12911#L798 assume !(1 == ~t8_pc~0); 14192#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14115#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12634#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12635#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 14325#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12455#L817 assume 1 == ~t9_pc~0; 12456#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13250#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13251#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13773#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 12861#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12862#L836 assume !(1 == ~t10_pc~0); 12878#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12809#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12810#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13058#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 13059#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14125#L855 assume 1 == ~t11_pc~0; 13443#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13444#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14008#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13817#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 13652#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12751#L874 assume !(1 == ~t12_pc~0); 12752#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 12919#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12920#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13060#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 12428#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12429#L893 assume 1 == ~t13_pc~0; 14259#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12784#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13095#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 14186#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 14194#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 14195#L912 assume 1 == ~t14_pc~0; 13985#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 13986#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 12754#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 12686#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 12687#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13462#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 13878#L1495-2 assume !(1 == ~T1_E~0); 13879#L1500-1 assume !(1 == ~T2_E~0); 13565#L1505-1 assume !(1 == ~T3_E~0); 13566#L1510-1 assume !(1 == ~T4_E~0); 13623#L1515-1 assume !(1 == ~T5_E~0); 13624#L1520-1 assume !(1 == ~T6_E~0); 14193#L1525-1 assume !(1 == ~T7_E~0); 13903#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12856#L1535-1 assume !(1 == ~T9_E~0); 12857#L1540-1 assume !(1 == ~T10_E~0); 12349#L1545-1 assume !(1 == ~T11_E~0); 12350#L1550-1 assume !(1 == ~T12_E~0); 12598#L1555-1 assume !(1 == ~T13_E~0); 12599#L1560-1 assume !(1 == ~T14_E~0); 12899#L1565-1 assume !(1 == ~E_1~0); 14312#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13790#L1575-1 assume !(1 == ~E_3~0); 13169#L1580-1 assume !(1 == ~E_4~0); 13170#L1585-1 assume !(1 == ~E_5~0); 13640#L1590-1 assume !(1 == ~E_6~0); 13204#L1595-1 assume !(1 == ~E_7~0); 13205#L1600-1 assume !(1 == ~E_8~0); 13577#L1605-1 assume !(1 == ~E_9~0); 13578#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 14095#L1615-1 assume !(1 == ~E_11~0); 13034#L1620-1 assume !(1 == ~E_12~0); 13035#L1625-1 assume !(1 == ~E_13~0); 13822#L1630-1 assume !(1 == ~E_14~0); 13203#L1635-1 assume { :end_inline_reset_delta_events } true; 13144#L2017-2 [2021-11-19 05:31:55,592 INFO L793 eck$LassoCheckResult]: Loop: 13144#L2017-2 assume !false; 12424#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12425#L1316 assume !false; 13753#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 13815#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 12362#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 12504#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12505#L1115 assume !(0 != eval_~tmp~0#1); 13838#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13259#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13260#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13442#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13943#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13612#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13613#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14175#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14350#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14345#L1372-3 assume !(0 == ~T7_E~0); 12406#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12407#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13076#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13077#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13988#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14298#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 13556#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 12712#L1412-3 assume !(0 == ~E_1~0); 12713#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13477#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13478#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14172#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13859#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13571#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13572#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12472#L1452-3 assume !(0 == ~E_9~0); 12473#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14111#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14112#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 13916#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13917#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 12710#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12711#L646-42 assume 1 == ~m_pc~0; 13296#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14144#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14145#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14283#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14284#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14076#L665-42 assume 1 == ~t1_pc~0; 14037#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14039#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14225#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12879#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12880#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14349#L684-42 assume 1 == ~t2_pc~0; 13728#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13729#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14339#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13508#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13509#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13631#L703-42 assume 1 == ~t3_pc~0; 13829#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13830#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13148#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13149#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13923#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13543#L722-42 assume 1 == ~t4_pc~0; 13544#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13954#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13197#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13024#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13025#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14319#L741-42 assume !(1 == ~t5_pc~0); 13936#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 13406#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13407#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14352#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13314#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13315#L760-42 assume !(1 == ~t6_pc~0); 13449#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 13584#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13585#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13973#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 13266#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13267#L779-42 assume 1 == ~t7_pc~0; 14096#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14044#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12951#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12952#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12807#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12808#L798-42 assume !(1 == ~t8_pc~0); 12418#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 12419#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14162#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13608#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12638#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12639#L817-42 assume 1 == ~t9_pc~0; 13412#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12922#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12923#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13049#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13854#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13855#L836-42 assume 1 == ~t10_pc~0; 13947#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12960#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12961#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14262#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14263#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14304#L855-42 assume 1 == ~t11_pc~0; 14317#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12511#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12512#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13261#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14024#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13125#L874-42 assume 1 == ~t12_pc~0; 13126#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 13365#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12426#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12427#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 12680#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12681#L893-42 assume !(1 == ~t13_pc~0); 13664#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 13665#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13680#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13582#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 13054#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 13055#L912-42 assume !(1 == ~t14_pc~0); 13864#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 12372#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 12373#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13953#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 12800#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12801#L1495-3 assume !(1 == ~M_E~0); 13416#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13844#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13937#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13030#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12993#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12994#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13651#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13874#L1530-3 assume !(1 == ~T8_E~0); 12839#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12840#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12877#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14134#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 14243#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 13283#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 13284#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13899#L1570-3 assume !(1 == ~E_2~0); 13850#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13851#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14206#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14250#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14296#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13673#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13674#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14149#L1610-3 assume !(1 == ~E_10~0); 13036#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13037#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13641#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13642#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 13546#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 12977#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 12582#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 13320#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 13876#L2036 assume !(0 == start_simulation_~tmp~3#1); 13877#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 14029#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 13189#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 14207#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 13589#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 13590#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14310#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14311#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 13144#L2017-2 [2021-11-19 05:31:55,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:55,594 INFO L85 PathProgramCache]: Analyzing trace with hash -224599768, now seen corresponding path program 1 times [2021-11-19 05:31:55,595 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:55,595 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416504927] [2021-11-19 05:31:55,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:55,595 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:55,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:55,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:55,657 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:55,657 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [416504927] [2021-11-19 05:31:55,658 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [416504927] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:55,658 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:55,659 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:55,662 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1015223786] [2021-11-19 05:31:55,662 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:55,663 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:31:55,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:55,663 INFO L85 PathProgramCache]: Analyzing trace with hash -1715277972, now seen corresponding path program 1 times [2021-11-19 05:31:55,664 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:55,668 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [910656913] [2021-11-19 05:31:55,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:55,670 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:55,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:55,740 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:55,740 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:55,740 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [910656913] [2021-11-19 05:31:55,741 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [910656913] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:55,741 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:55,741 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:55,741 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [301606504] [2021-11-19 05:31:55,741 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:55,742 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:31:55,742 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:31:55,744 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:31:55,744 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:31:55,744 INFO L87 Difference]: Start difference. First operand 2047 states and 3032 transitions. cyclomatic complexity: 986 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:55,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:31:55,795 INFO L93 Difference]: Finished difference Result 2047 states and 3031 transitions. [2021-11-19 05:31:55,795 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:31:55,796 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3031 transitions. [2021-11-19 05:31:55,815 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:55,832 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3031 transitions. [2021-11-19 05:31:55,832 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-11-19 05:31:55,835 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-11-19 05:31:55,835 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3031 transitions. [2021-11-19 05:31:55,838 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:31:55,839 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3031 transitions. [2021-11-19 05:31:55,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3031 transitions. [2021-11-19 05:31:55,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-11-19 05:31:55,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4807034684904739) internal successors, (3031), 2046 states have internal predecessors, (3031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:55,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3031 transitions. [2021-11-19 05:31:55,884 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3031 transitions. [2021-11-19 05:31:55,884 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3031 transitions. [2021-11-19 05:31:55,884 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-19 05:31:55,884 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3031 transitions. [2021-11-19 05:31:55,893 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:55,894 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:55,894 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:55,897 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:55,897 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:55,933 INFO L791 eck$LassoCheckResult]: Stem: 17343#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 17344#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 17946#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17063#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17064#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 17309#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17310#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17037#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17038#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 18261#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17613#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17614#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18131#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17523#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17524#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16944#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16945#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17276#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17474#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 16521#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16522#L1342 assume !(0 == ~M_E~0); 16687#L1342-2 assume !(0 == ~T1_E~0); 17243#L1347-1 assume !(0 == ~T2_E~0); 18244#L1352-1 assume !(0 == ~T3_E~0); 18040#L1357-1 assume !(0 == ~T4_E~0); 17268#L1362-1 assume !(0 == ~T5_E~0); 17269#L1367-1 assume !(0 == ~T6_E~0); 16866#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16867#L1377-1 assume !(0 == ~T8_E~0); 17197#L1382-1 assume !(0 == ~T9_E~0); 17198#L1387-1 assume !(0 == ~T10_E~0); 17925#L1392-1 assume !(0 == ~T11_E~0); 17229#L1397-1 assume !(0 == ~T12_E~0); 17230#L1402-1 assume !(0 == ~T13_E~0); 16882#L1407-1 assume !(0 == ~T14_E~0); 16883#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 18161#L1417-1 assume !(0 == ~E_2~0); 18162#L1422-1 assume !(0 == ~E_3~0); 18403#L1427-1 assume !(0 == ~E_4~0); 17070#L1432-1 assume !(0 == ~E_5~0); 17071#L1437-1 assume !(0 == ~E_6~0); 18079#L1442-1 assume !(0 == ~E_7~0); 18080#L1447-1 assume !(0 == ~E_8~0); 17922#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 16657#L1457-1 assume !(0 == ~E_10~0); 16658#L1462-1 assume !(0 == ~E_11~0); 18114#L1467-1 assume !(0 == ~E_12~0); 18126#L1472-1 assume !(0 == ~E_13~0); 18127#L1477-1 assume !(0 == ~E_14~0); 17869#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16856#L646 assume 1 == ~m_pc~0; 16857#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17533#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17548#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16946#L1666 assume !(0 != activate_threads_~tmp~1#1); 16947#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18424#L665 assume !(1 == ~t1_pc~0); 17422#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17423#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16955#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16956#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 17746#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17747#L684 assume 1 == ~t2_pc~0; 17864#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17788#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17853#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18248#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 18249#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18437#L703 assume !(1 == ~t3_pc~0); 17092#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17093#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17739#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16491#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 16492#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16977#L722 assume 1 == ~t4_pc~0; 17715#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17158#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17503#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18063#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 17570#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16688#L741 assume 1 == ~t5_pc~0; 16689#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16999#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17153#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17154#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 17833#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17244#L760 assume !(1 == ~t6_pc~0); 17091#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17090#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16948#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16949#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17670#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17671#L779 assume 1 == ~t7_pc~0; 16733#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16579#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16580#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16988#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 17011#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17012#L798 assume !(1 == ~t8_pc~0); 18293#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 18216#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16735#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16736#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 18426#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16556#L817 assume 1 == ~t9_pc~0; 16557#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17351#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17352#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17874#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 16962#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16963#L836 assume !(1 == ~t10_pc~0); 16979#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16910#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16911#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17159#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 17160#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18226#L855 assume 1 == ~t11_pc~0; 17544#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17545#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18109#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17918#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 17753#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16852#L874 assume !(1 == ~t12_pc~0); 16853#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 17020#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17021#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17161#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 16529#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16530#L893 assume 1 == ~t13_pc~0; 18360#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 16885#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17196#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 18287#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 18295#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 18296#L912 assume 1 == ~t14_pc~0; 18086#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 18087#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 16855#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 16787#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 16788#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17563#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 17979#L1495-2 assume !(1 == ~T1_E~0); 17980#L1500-1 assume !(1 == ~T2_E~0); 17666#L1505-1 assume !(1 == ~T3_E~0); 17667#L1510-1 assume !(1 == ~T4_E~0); 17724#L1515-1 assume !(1 == ~T5_E~0); 17725#L1520-1 assume !(1 == ~T6_E~0); 18294#L1525-1 assume !(1 == ~T7_E~0); 18004#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16957#L1535-1 assume !(1 == ~T9_E~0); 16958#L1540-1 assume !(1 == ~T10_E~0); 16450#L1545-1 assume !(1 == ~T11_E~0); 16451#L1550-1 assume !(1 == ~T12_E~0); 16699#L1555-1 assume !(1 == ~T13_E~0); 16700#L1560-1 assume !(1 == ~T14_E~0); 17000#L1565-1 assume !(1 == ~E_1~0); 18413#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17891#L1575-1 assume !(1 == ~E_3~0); 17270#L1580-1 assume !(1 == ~E_4~0); 17271#L1585-1 assume !(1 == ~E_5~0); 17741#L1590-1 assume !(1 == ~E_6~0); 17305#L1595-1 assume !(1 == ~E_7~0); 17306#L1600-1 assume !(1 == ~E_8~0); 17678#L1605-1 assume !(1 == ~E_9~0); 17679#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 18196#L1615-1 assume !(1 == ~E_11~0); 17135#L1620-1 assume !(1 == ~E_12~0); 17136#L1625-1 assume !(1 == ~E_13~0); 17923#L1630-1 assume !(1 == ~E_14~0); 17304#L1635-1 assume { :end_inline_reset_delta_events } true; 17245#L2017-2 [2021-11-19 05:31:55,933 INFO L793 eck$LassoCheckResult]: Loop: 17245#L2017-2 assume !false; 16525#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16526#L1316 assume !false; 17854#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 17916#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 16463#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 16605#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16606#L1115 assume !(0 != eval_~tmp~0#1); 17939#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17360#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17361#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17543#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18044#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17713#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17714#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18276#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18451#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18446#L1372-3 assume !(0 == ~T7_E~0); 16507#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16508#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17177#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17178#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18089#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18399#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 17657#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 16813#L1412-3 assume !(0 == ~E_1~0); 16814#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17578#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17579#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18273#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17960#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17672#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17673#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16573#L1452-3 assume !(0 == ~E_9~0); 16574#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18212#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18213#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18017#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 18018#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 16811#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16812#L646-42 assume 1 == ~m_pc~0; 17397#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 18245#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18246#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18384#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18385#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18177#L665-42 assume 1 == ~t1_pc~0; 18138#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18140#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18326#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16980#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16981#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18450#L684-42 assume 1 == ~t2_pc~0; 17829#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17830#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18440#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17609#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17610#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17732#L703-42 assume 1 == ~t3_pc~0; 17930#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17931#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17249#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17250#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18024#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17644#L722-42 assume 1 == ~t4_pc~0; 17645#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18055#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17298#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17125#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17126#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18420#L741-42 assume !(1 == ~t5_pc~0); 18037#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 17507#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17508#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18453#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17415#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17416#L760-42 assume !(1 == ~t6_pc~0); 17550#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 17685#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17686#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18074#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 17367#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17368#L779-42 assume !(1 == ~t7_pc~0); 18144#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 18145#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17052#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17053#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16908#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16909#L798-42 assume !(1 == ~t8_pc~0); 16519#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 16520#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18263#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17709#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16739#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16740#L817-42 assume 1 == ~t9_pc~0; 17513#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17023#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17024#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17150#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17955#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17956#L836-42 assume 1 == ~t10_pc~0; 18048#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17061#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17062#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18363#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 18364#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18405#L855-42 assume 1 == ~t11_pc~0; 18418#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16612#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16613#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17362#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18125#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17226#L874-42 assume 1 == ~t12_pc~0; 17227#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17466#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16527#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16528#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 16781#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16782#L893-42 assume 1 == ~t13_pc~0; 17984#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17766#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17781#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17683#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 17155#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 17156#L912-42 assume 1 == ~t14_pc~0; 18400#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 16473#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 16474#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 18054#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 16901#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16902#L1495-3 assume !(1 == ~M_E~0); 17517#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17945#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18038#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17131#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17094#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17095#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17752#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17975#L1530-3 assume !(1 == ~T8_E~0); 16940#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16941#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16978#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18235#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18344#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 17384#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 17385#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18000#L1570-3 assume !(1 == ~E_2~0); 17951#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17952#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18307#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18351#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18397#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17774#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17775#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18250#L1610-3 assume !(1 == ~E_10~0); 17137#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17138#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17742#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 17743#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 17647#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 17078#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 16683#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 17421#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 17977#L2036 assume !(0 == start_simulation_~tmp~3#1); 17978#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 18130#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 17290#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 18308#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 17690#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 17691#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18411#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 18412#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 17245#L2017-2 [2021-11-19 05:31:55,934 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:55,934 INFO L85 PathProgramCache]: Analyzing trace with hash -723156570, now seen corresponding path program 1 times [2021-11-19 05:31:55,934 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:55,935 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1482575965] [2021-11-19 05:31:55,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:55,935 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:55,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:55,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:55,992 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:55,992 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1482575965] [2021-11-19 05:31:55,992 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1482575965] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:55,992 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:55,993 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:55,993 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1378503400] [2021-11-19 05:31:55,993 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:55,994 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:31:55,994 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:55,994 INFO L85 PathProgramCache]: Analyzing trace with hash 1006606669, now seen corresponding path program 1 times [2021-11-19 05:31:55,995 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:55,995 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [810836635] [2021-11-19 05:31:55,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:55,995 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:56,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:56,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:56,056 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:56,057 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [810836635] [2021-11-19 05:31:56,057 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [810836635] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:56,057 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:56,057 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:56,058 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1119256949] [2021-11-19 05:31:56,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:56,058 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:31:56,058 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:31:56,059 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:31:56,059 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:31:56,059 INFO L87 Difference]: Start difference. First operand 2047 states and 3031 transitions. cyclomatic complexity: 985 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:56,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:31:56,116 INFO L93 Difference]: Finished difference Result 2047 states and 3030 transitions. [2021-11-19 05:31:56,116 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:31:56,119 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3030 transitions. [2021-11-19 05:31:56,133 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:56,150 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3030 transitions. [2021-11-19 05:31:56,150 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-11-19 05:31:56,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-11-19 05:31:56,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3030 transitions. [2021-11-19 05:31:56,157 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:31:56,157 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3030 transitions. [2021-11-19 05:31:56,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3030 transitions. [2021-11-19 05:31:56,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-11-19 05:31:56,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4802149487054226) internal successors, (3030), 2046 states have internal predecessors, (3030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:56,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3030 transitions. [2021-11-19 05:31:56,207 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3030 transitions. [2021-11-19 05:31:56,207 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3030 transitions. [2021-11-19 05:31:56,207 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-19 05:31:56,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3030 transitions. [2021-11-19 05:31:56,217 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:56,217 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:56,217 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:56,221 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:56,221 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:56,222 INFO L791 eck$LassoCheckResult]: Stem: 21444#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 21445#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 22047#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21164#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21165#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 21410#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21411#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21138#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21139#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22362#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21714#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21715#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22232#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21624#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21625#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21045#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21046#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21377#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21575#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 20622#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20623#L1342 assume !(0 == ~M_E~0); 20788#L1342-2 assume !(0 == ~T1_E~0); 21344#L1347-1 assume !(0 == ~T2_E~0); 22345#L1352-1 assume !(0 == ~T3_E~0); 22141#L1357-1 assume !(0 == ~T4_E~0); 21369#L1362-1 assume !(0 == ~T5_E~0); 21370#L1367-1 assume !(0 == ~T6_E~0); 20967#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20968#L1377-1 assume !(0 == ~T8_E~0); 21298#L1382-1 assume !(0 == ~T9_E~0); 21299#L1387-1 assume !(0 == ~T10_E~0); 22026#L1392-1 assume !(0 == ~T11_E~0); 21330#L1397-1 assume !(0 == ~T12_E~0); 21331#L1402-1 assume !(0 == ~T13_E~0); 20983#L1407-1 assume !(0 == ~T14_E~0); 20984#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 22262#L1417-1 assume !(0 == ~E_2~0); 22263#L1422-1 assume !(0 == ~E_3~0); 22504#L1427-1 assume !(0 == ~E_4~0); 21171#L1432-1 assume !(0 == ~E_5~0); 21172#L1437-1 assume !(0 == ~E_6~0); 22180#L1442-1 assume !(0 == ~E_7~0); 22181#L1447-1 assume !(0 == ~E_8~0); 22023#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 20758#L1457-1 assume !(0 == ~E_10~0); 20759#L1462-1 assume !(0 == ~E_11~0); 22215#L1467-1 assume !(0 == ~E_12~0); 22227#L1472-1 assume !(0 == ~E_13~0); 22228#L1477-1 assume !(0 == ~E_14~0); 21970#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20957#L646 assume 1 == ~m_pc~0; 20958#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21634#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21649#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21047#L1666 assume !(0 != activate_threads_~tmp~1#1); 21048#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22525#L665 assume !(1 == ~t1_pc~0); 21523#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21524#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21056#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21057#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 21847#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21848#L684 assume 1 == ~t2_pc~0; 21965#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21889#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21954#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22349#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 22350#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22538#L703 assume !(1 == ~t3_pc~0); 21193#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21194#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21840#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20592#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 20593#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21078#L722 assume 1 == ~t4_pc~0; 21816#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21259#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21604#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22164#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 21671#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20789#L741 assume 1 == ~t5_pc~0; 20790#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21100#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21254#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21255#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 21934#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21345#L760 assume !(1 == ~t6_pc~0); 21192#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21191#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21049#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21050#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21771#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21772#L779 assume 1 == ~t7_pc~0; 20834#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20680#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20681#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21089#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 21112#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21113#L798 assume !(1 == ~t8_pc~0); 22394#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22317#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20836#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20837#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 22527#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20657#L817 assume 1 == ~t9_pc~0; 20658#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21452#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21453#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21975#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 21063#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21064#L836 assume !(1 == ~t10_pc~0); 21080#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21011#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21012#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21260#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 21261#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22327#L855 assume 1 == ~t11_pc~0; 21645#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21646#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22210#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22019#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 21854#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20953#L874 assume !(1 == ~t12_pc~0); 20954#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 21121#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21122#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21262#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 20630#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20631#L893 assume 1 == ~t13_pc~0; 22461#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 20986#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21297#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22388#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 22396#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 22397#L912 assume 1 == ~t14_pc~0; 22187#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 22188#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 20956#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 20888#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 20889#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21664#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 22080#L1495-2 assume !(1 == ~T1_E~0); 22081#L1500-1 assume !(1 == ~T2_E~0); 21767#L1505-1 assume !(1 == ~T3_E~0); 21768#L1510-1 assume !(1 == ~T4_E~0); 21825#L1515-1 assume !(1 == ~T5_E~0); 21826#L1520-1 assume !(1 == ~T6_E~0); 22395#L1525-1 assume !(1 == ~T7_E~0); 22105#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21058#L1535-1 assume !(1 == ~T9_E~0); 21059#L1540-1 assume !(1 == ~T10_E~0); 20551#L1545-1 assume !(1 == ~T11_E~0); 20552#L1550-1 assume !(1 == ~T12_E~0); 20800#L1555-1 assume !(1 == ~T13_E~0); 20801#L1560-1 assume !(1 == ~T14_E~0); 21101#L1565-1 assume !(1 == ~E_1~0); 22514#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 21992#L1575-1 assume !(1 == ~E_3~0); 21371#L1580-1 assume !(1 == ~E_4~0); 21372#L1585-1 assume !(1 == ~E_5~0); 21842#L1590-1 assume !(1 == ~E_6~0); 21406#L1595-1 assume !(1 == ~E_7~0); 21407#L1600-1 assume !(1 == ~E_8~0); 21779#L1605-1 assume !(1 == ~E_9~0); 21780#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22297#L1615-1 assume !(1 == ~E_11~0); 21236#L1620-1 assume !(1 == ~E_12~0); 21237#L1625-1 assume !(1 == ~E_13~0); 22024#L1630-1 assume !(1 == ~E_14~0); 21405#L1635-1 assume { :end_inline_reset_delta_events } true; 21346#L2017-2 [2021-11-19 05:31:56,223 INFO L793 eck$LassoCheckResult]: Loop: 21346#L2017-2 assume !false; 20626#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20627#L1316 assume !false; 21955#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 22017#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 20564#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 20706#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20707#L1115 assume !(0 != eval_~tmp~0#1); 22040#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21461#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21462#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21644#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22145#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21814#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21815#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22377#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22552#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22547#L1372-3 assume !(0 == ~T7_E~0); 20608#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20609#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21278#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21279#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22190#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 22500#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21758#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 20914#L1412-3 assume !(0 == ~E_1~0); 20915#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21679#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21680#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22374#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22061#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21773#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21774#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20674#L1452-3 assume !(0 == ~E_9~0); 20675#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22313#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22314#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22118#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 22119#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 20912#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20913#L646-42 assume 1 == ~m_pc~0; 21498#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 22346#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22347#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22485#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22486#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22278#L665-42 assume !(1 == ~t1_pc~0); 22240#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 22241#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22427#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21081#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21082#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22551#L684-42 assume 1 == ~t2_pc~0; 21930#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21931#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22541#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21710#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21711#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21833#L703-42 assume !(1 == ~t3_pc~0); 22033#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 22032#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21350#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21351#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22125#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21745#L722-42 assume 1 == ~t4_pc~0; 21746#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22156#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21399#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21226#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21227#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22521#L741-42 assume !(1 == ~t5_pc~0); 22138#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 21608#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21609#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22554#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21516#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21517#L760-42 assume !(1 == ~t6_pc~0); 21651#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 21786#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21787#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22175#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 21468#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21469#L779-42 assume !(1 == ~t7_pc~0); 22245#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 22246#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21153#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21154#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21009#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21010#L798-42 assume 1 == ~t8_pc~0; 21460#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20621#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22364#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21810#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20840#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20841#L817-42 assume 1 == ~t9_pc~0; 21614#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21124#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21125#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21251#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22056#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22057#L836-42 assume 1 == ~t10_pc~0; 22149#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21162#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21163#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22464#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22465#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22506#L855-42 assume 1 == ~t11_pc~0; 22519#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20713#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20714#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21463#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22226#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21327#L874-42 assume 1 == ~t12_pc~0; 21328#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 21567#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20628#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20629#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20882#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20883#L893-42 assume 1 == ~t13_pc~0; 22085#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21867#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21882#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21784#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 21256#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 21257#L912-42 assume !(1 == ~t14_pc~0); 22066#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 20574#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 20575#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 22155#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 21002#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21003#L1495-3 assume !(1 == ~M_E~0); 21618#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22046#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22139#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21232#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21195#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21196#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21853#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22076#L1530-3 assume !(1 == ~T8_E~0); 21041#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21042#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21079#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22336#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22445#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 21485#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 21486#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22101#L1570-3 assume !(1 == ~E_2~0); 22052#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22053#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22408#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22452#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22498#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21875#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21876#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22351#L1610-3 assume !(1 == ~E_10~0); 21238#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21239#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21843#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 21844#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 21748#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 21179#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 20784#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 21522#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 22078#L2036 assume !(0 == start_simulation_~tmp~3#1); 22079#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 22231#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 21391#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 22409#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 21791#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 21792#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22512#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22513#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 21346#L2017-2 [2021-11-19 05:31:56,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:56,229 INFO L85 PathProgramCache]: Analyzing trace with hash -1293428376, now seen corresponding path program 1 times [2021-11-19 05:31:56,229 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:56,229 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2037028521] [2021-11-19 05:31:56,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:56,230 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:56,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:56,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:56,271 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:56,271 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2037028521] [2021-11-19 05:31:56,271 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2037028521] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:56,271 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:56,272 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:56,272 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1790303987] [2021-11-19 05:31:56,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:56,274 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:31:56,277 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:56,277 INFO L85 PathProgramCache]: Analyzing trace with hash 721372171, now seen corresponding path program 1 times [2021-11-19 05:31:56,277 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:56,282 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [519279368] [2021-11-19 05:31:56,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:56,283 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:56,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:56,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:56,343 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:56,343 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [519279368] [2021-11-19 05:31:56,346 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [519279368] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:56,346 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:56,346 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:56,347 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1552034153] [2021-11-19 05:31:56,347 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:56,348 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:31:56,348 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:31:56,349 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:31:56,349 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:31:56,350 INFO L87 Difference]: Start difference. First operand 2047 states and 3030 transitions. cyclomatic complexity: 984 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:56,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:31:56,405 INFO L93 Difference]: Finished difference Result 2047 states and 3029 transitions. [2021-11-19 05:31:56,406 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:31:56,408 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3029 transitions. [2021-11-19 05:31:56,421 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:56,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3029 transitions. [2021-11-19 05:31:56,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-11-19 05:31:56,443 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-11-19 05:31:56,443 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3029 transitions. [2021-11-19 05:31:56,480 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:31:56,480 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3029 transitions. [2021-11-19 05:31:56,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3029 transitions. [2021-11-19 05:31:56,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-11-19 05:31:56,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4797264289203713) internal successors, (3029), 2046 states have internal predecessors, (3029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:56,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3029 transitions. [2021-11-19 05:31:56,534 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3029 transitions. [2021-11-19 05:31:56,534 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3029 transitions. [2021-11-19 05:31:56,534 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-19 05:31:56,534 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3029 transitions. [2021-11-19 05:31:56,543 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:56,543 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:56,543 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:56,547 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:56,547 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:56,547 INFO L791 eck$LassoCheckResult]: Stem: 25545#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 25546#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 26148#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25265#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25266#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 25511#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25512#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25239#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25240#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26463#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25815#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 25816#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26333#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25725#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25726#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25146#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25147#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25478#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 25676#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 24723#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24724#L1342 assume !(0 == ~M_E~0); 24889#L1342-2 assume !(0 == ~T1_E~0); 25445#L1347-1 assume !(0 == ~T2_E~0); 26446#L1352-1 assume !(0 == ~T3_E~0); 26242#L1357-1 assume !(0 == ~T4_E~0); 25470#L1362-1 assume !(0 == ~T5_E~0); 25471#L1367-1 assume !(0 == ~T6_E~0); 25068#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25069#L1377-1 assume !(0 == ~T8_E~0); 25399#L1382-1 assume !(0 == ~T9_E~0); 25400#L1387-1 assume !(0 == ~T10_E~0); 26127#L1392-1 assume !(0 == ~T11_E~0); 25431#L1397-1 assume !(0 == ~T12_E~0); 25432#L1402-1 assume !(0 == ~T13_E~0); 25084#L1407-1 assume !(0 == ~T14_E~0); 25085#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 26363#L1417-1 assume !(0 == ~E_2~0); 26364#L1422-1 assume !(0 == ~E_3~0); 26605#L1427-1 assume !(0 == ~E_4~0); 25272#L1432-1 assume !(0 == ~E_5~0); 25273#L1437-1 assume !(0 == ~E_6~0); 26281#L1442-1 assume !(0 == ~E_7~0); 26282#L1447-1 assume !(0 == ~E_8~0); 26124#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 24859#L1457-1 assume !(0 == ~E_10~0); 24860#L1462-1 assume !(0 == ~E_11~0); 26316#L1467-1 assume !(0 == ~E_12~0); 26328#L1472-1 assume !(0 == ~E_13~0); 26329#L1477-1 assume !(0 == ~E_14~0); 26071#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25058#L646 assume 1 == ~m_pc~0; 25059#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 25735#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25750#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25148#L1666 assume !(0 != activate_threads_~tmp~1#1); 25149#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26626#L665 assume !(1 == ~t1_pc~0); 25624#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25625#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25157#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25158#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 25948#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25949#L684 assume 1 == ~t2_pc~0; 26066#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25990#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26055#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26450#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 26451#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26639#L703 assume !(1 == ~t3_pc~0); 25294#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25295#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25941#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24693#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 24694#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25179#L722 assume 1 == ~t4_pc~0; 25917#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25360#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25705#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26265#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 25772#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24890#L741 assume 1 == ~t5_pc~0; 24891#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25201#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25355#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25356#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 26035#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25446#L760 assume !(1 == ~t6_pc~0); 25293#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25292#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25150#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25151#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25872#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25873#L779 assume 1 == ~t7_pc~0; 24935#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24781#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24782#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25190#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 25213#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25214#L798 assume !(1 == ~t8_pc~0); 26495#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 26418#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24937#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24938#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 26628#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24758#L817 assume 1 == ~t9_pc~0; 24759#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25553#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25554#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26076#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 25164#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25165#L836 assume !(1 == ~t10_pc~0); 25181#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25112#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25113#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25361#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 25362#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26428#L855 assume 1 == ~t11_pc~0; 25746#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25747#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26311#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26120#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 25955#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25054#L874 assume !(1 == ~t12_pc~0); 25055#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 25222#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25223#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25363#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 24731#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24732#L893 assume 1 == ~t13_pc~0; 26562#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25087#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25398#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26489#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 26497#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 26498#L912 assume 1 == ~t14_pc~0; 26288#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 26289#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 25057#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 24989#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 24990#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25765#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 26181#L1495-2 assume !(1 == ~T1_E~0); 26182#L1500-1 assume !(1 == ~T2_E~0); 25868#L1505-1 assume !(1 == ~T3_E~0); 25869#L1510-1 assume !(1 == ~T4_E~0); 25926#L1515-1 assume !(1 == ~T5_E~0); 25927#L1520-1 assume !(1 == ~T6_E~0); 26496#L1525-1 assume !(1 == ~T7_E~0); 26206#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25159#L1535-1 assume !(1 == ~T9_E~0); 25160#L1540-1 assume !(1 == ~T10_E~0); 24652#L1545-1 assume !(1 == ~T11_E~0); 24653#L1550-1 assume !(1 == ~T12_E~0); 24901#L1555-1 assume !(1 == ~T13_E~0); 24902#L1560-1 assume !(1 == ~T14_E~0); 25202#L1565-1 assume !(1 == ~E_1~0); 26615#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 26093#L1575-1 assume !(1 == ~E_3~0); 25472#L1580-1 assume !(1 == ~E_4~0); 25473#L1585-1 assume !(1 == ~E_5~0); 25943#L1590-1 assume !(1 == ~E_6~0); 25507#L1595-1 assume !(1 == ~E_7~0); 25508#L1600-1 assume !(1 == ~E_8~0); 25880#L1605-1 assume !(1 == ~E_9~0); 25881#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26398#L1615-1 assume !(1 == ~E_11~0); 25337#L1620-1 assume !(1 == ~E_12~0); 25338#L1625-1 assume !(1 == ~E_13~0); 26125#L1630-1 assume !(1 == ~E_14~0); 25506#L1635-1 assume { :end_inline_reset_delta_events } true; 25447#L2017-2 [2021-11-19 05:31:56,548 INFO L793 eck$LassoCheckResult]: Loop: 25447#L2017-2 assume !false; 24727#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24728#L1316 assume !false; 26056#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 26118#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 24665#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 24807#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24808#L1115 assume !(0 != eval_~tmp~0#1); 26141#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25562#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25563#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25745#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26246#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25915#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25916#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26478#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26653#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26648#L1372-3 assume !(0 == ~T7_E~0); 24709#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24710#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25379#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25380#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26291#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 26601#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25859#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 25015#L1412-3 assume !(0 == ~E_1~0); 25016#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25780#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25781#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26475#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26162#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25874#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25875#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24775#L1452-3 assume !(0 == ~E_9~0); 24776#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26414#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 26415#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 26219#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 26220#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 25013#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25014#L646-42 assume !(1 == ~m_pc~0); 25600#L646-44 is_master_triggered_~__retres1~0#1 := 0; 26447#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26448#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26586#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26587#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26379#L665-42 assume 1 == ~t1_pc~0; 26340#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26342#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26528#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25182#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25183#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26652#L684-42 assume !(1 == ~t2_pc~0); 26033#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 26032#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26642#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25811#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25812#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25934#L703-42 assume 1 == ~t3_pc~0; 26132#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26133#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25451#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25452#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26226#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25846#L722-42 assume 1 == ~t4_pc~0; 25847#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26257#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25500#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25327#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25328#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26622#L741-42 assume 1 == ~t5_pc~0; 26564#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25709#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25710#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26655#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25617#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25618#L760-42 assume !(1 == ~t6_pc~0); 25752#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 25887#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25888#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26276#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 25569#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25570#L779-42 assume !(1 == ~t7_pc~0); 26346#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 26347#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25256#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25257#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25110#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25111#L798-42 assume !(1 == ~t8_pc~0); 24721#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 24722#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26465#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25911#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24941#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24942#L817-42 assume 1 == ~t9_pc~0; 25715#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25225#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25226#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25352#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26157#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26158#L836-42 assume 1 == ~t10_pc~0; 26250#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25263#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25264#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26565#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26566#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26607#L855-42 assume 1 == ~t11_pc~0; 26620#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24814#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24815#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25564#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26327#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25428#L874-42 assume 1 == ~t12_pc~0; 25429#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 25668#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24729#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24730#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24983#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24984#L893-42 assume 1 == ~t13_pc~0; 26186#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25968#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25983#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 25885#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 25357#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 25358#L912-42 assume !(1 == ~t14_pc~0); 26167#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 24675#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 24676#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 26256#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 25103#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25104#L1495-3 assume !(1 == ~M_E~0); 25719#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26147#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26240#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25333#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25296#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25297#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25954#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26177#L1530-3 assume !(1 == ~T8_E~0); 25142#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25143#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25180#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26437#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26546#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 25586#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 25587#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26202#L1570-3 assume !(1 == ~E_2~0); 26153#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26154#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26509#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26553#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26599#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25976#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25977#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 26452#L1610-3 assume !(1 == ~E_10~0); 25339#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25340#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25944#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 25945#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 25849#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 25280#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 24885#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 25623#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 26179#L2036 assume !(0 == start_simulation_~tmp~3#1); 26180#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 26332#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 25492#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 26510#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 25892#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 25893#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26613#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 26614#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 25447#L2017-2 [2021-11-19 05:31:56,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:56,548 INFO L85 PathProgramCache]: Analyzing trace with hash 1597669734, now seen corresponding path program 1 times [2021-11-19 05:31:56,549 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:56,549 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [837687209] [2021-11-19 05:31:56,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:56,549 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:56,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:56,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:56,584 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:56,584 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [837687209] [2021-11-19 05:31:56,585 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [837687209] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:56,585 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:56,585 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:56,585 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [124483275] [2021-11-19 05:31:56,585 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:56,586 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:31:56,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:56,586 INFO L85 PathProgramCache]: Analyzing trace with hash -1842591925, now seen corresponding path program 1 times [2021-11-19 05:31:56,586 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:56,587 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290275904] [2021-11-19 05:31:56,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:56,587 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:56,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:56,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:56,660 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:56,661 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1290275904] [2021-11-19 05:31:56,661 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1290275904] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:56,661 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:56,661 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:56,661 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [612982910] [2021-11-19 05:31:56,661 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:56,662 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:31:56,662 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:31:56,662 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:31:56,662 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:31:56,663 INFO L87 Difference]: Start difference. First operand 2047 states and 3029 transitions. cyclomatic complexity: 983 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:56,714 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:31:56,714 INFO L93 Difference]: Finished difference Result 2047 states and 3028 transitions. [2021-11-19 05:31:56,714 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:31:56,716 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3028 transitions. [2021-11-19 05:31:56,733 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:56,749 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3028 transitions. [2021-11-19 05:31:56,749 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-11-19 05:31:56,751 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-11-19 05:31:56,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3028 transitions. [2021-11-19 05:31:56,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:31:56,755 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3028 transitions. [2021-11-19 05:31:56,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3028 transitions. [2021-11-19 05:31:56,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-11-19 05:31:56,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.47923790913532) internal successors, (3028), 2046 states have internal predecessors, (3028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:56,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3028 transitions. [2021-11-19 05:31:56,805 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3028 transitions. [2021-11-19 05:31:56,806 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3028 transitions. [2021-11-19 05:31:56,806 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-19 05:31:56,806 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3028 transitions. [2021-11-19 05:31:56,815 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:56,815 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:56,815 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:56,818 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:56,818 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:56,819 INFO L791 eck$LassoCheckResult]: Stem: 29646#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 29647#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 30249#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29366#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29367#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 29612#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29613#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29340#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29341#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30564#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29916#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29917#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 30434#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29826#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29827#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29247#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29248#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29579#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29777#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 28824#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28825#L1342 assume !(0 == ~M_E~0); 28990#L1342-2 assume !(0 == ~T1_E~0); 29546#L1347-1 assume !(0 == ~T2_E~0); 30547#L1352-1 assume !(0 == ~T3_E~0); 30343#L1357-1 assume !(0 == ~T4_E~0); 29571#L1362-1 assume !(0 == ~T5_E~0); 29572#L1367-1 assume !(0 == ~T6_E~0); 29169#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29170#L1377-1 assume !(0 == ~T8_E~0); 29500#L1382-1 assume !(0 == ~T9_E~0); 29501#L1387-1 assume !(0 == ~T10_E~0); 30228#L1392-1 assume !(0 == ~T11_E~0); 29532#L1397-1 assume !(0 == ~T12_E~0); 29533#L1402-1 assume !(0 == ~T13_E~0); 29185#L1407-1 assume !(0 == ~T14_E~0); 29186#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 30464#L1417-1 assume !(0 == ~E_2~0); 30465#L1422-1 assume !(0 == ~E_3~0); 30706#L1427-1 assume !(0 == ~E_4~0); 29373#L1432-1 assume !(0 == ~E_5~0); 29374#L1437-1 assume !(0 == ~E_6~0); 30382#L1442-1 assume !(0 == ~E_7~0); 30383#L1447-1 assume !(0 == ~E_8~0); 30225#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 28960#L1457-1 assume !(0 == ~E_10~0); 28961#L1462-1 assume !(0 == ~E_11~0); 30417#L1467-1 assume !(0 == ~E_12~0); 30429#L1472-1 assume !(0 == ~E_13~0); 30430#L1477-1 assume !(0 == ~E_14~0); 30172#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29159#L646 assume 1 == ~m_pc~0; 29160#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 29836#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29851#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29249#L1666 assume !(0 != activate_threads_~tmp~1#1); 29250#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30727#L665 assume !(1 == ~t1_pc~0); 29725#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29726#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29258#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29259#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 30049#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30050#L684 assume 1 == ~t2_pc~0; 30167#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30091#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30156#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30551#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 30552#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30740#L703 assume !(1 == ~t3_pc~0); 29395#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29396#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30042#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28794#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 28795#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29280#L722 assume 1 == ~t4_pc~0; 30018#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29461#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29806#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30366#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 29873#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28991#L741 assume 1 == ~t5_pc~0; 28992#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29302#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29456#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29457#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 30136#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29547#L760 assume !(1 == ~t6_pc~0); 29394#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29393#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29251#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29252#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29973#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29974#L779 assume 1 == ~t7_pc~0; 29036#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28882#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28883#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29291#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 29314#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29315#L798 assume !(1 == ~t8_pc~0); 30596#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30519#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29038#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29039#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 30729#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28859#L817 assume 1 == ~t9_pc~0; 28860#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29654#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29655#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30177#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 29265#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29266#L836 assume !(1 == ~t10_pc~0); 29282#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29213#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29214#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29462#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 29463#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30529#L855 assume 1 == ~t11_pc~0; 29847#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29848#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30412#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30221#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 30056#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29155#L874 assume !(1 == ~t12_pc~0); 29156#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29323#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29324#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29464#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 28832#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28833#L893 assume 1 == ~t13_pc~0; 30663#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29188#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29499#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30590#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 30598#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 30599#L912 assume 1 == ~t14_pc~0; 30389#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 30390#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 29158#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 29090#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 29091#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29866#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 30282#L1495-2 assume !(1 == ~T1_E~0); 30283#L1500-1 assume !(1 == ~T2_E~0); 29969#L1505-1 assume !(1 == ~T3_E~0); 29970#L1510-1 assume !(1 == ~T4_E~0); 30027#L1515-1 assume !(1 == ~T5_E~0); 30028#L1520-1 assume !(1 == ~T6_E~0); 30597#L1525-1 assume !(1 == ~T7_E~0); 30307#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29260#L1535-1 assume !(1 == ~T9_E~0); 29261#L1540-1 assume !(1 == ~T10_E~0); 28753#L1545-1 assume !(1 == ~T11_E~0); 28754#L1550-1 assume !(1 == ~T12_E~0); 29002#L1555-1 assume !(1 == ~T13_E~0); 29003#L1560-1 assume !(1 == ~T14_E~0); 29303#L1565-1 assume !(1 == ~E_1~0); 30716#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 30194#L1575-1 assume !(1 == ~E_3~0); 29573#L1580-1 assume !(1 == ~E_4~0); 29574#L1585-1 assume !(1 == ~E_5~0); 30044#L1590-1 assume !(1 == ~E_6~0); 29608#L1595-1 assume !(1 == ~E_7~0); 29609#L1600-1 assume !(1 == ~E_8~0); 29981#L1605-1 assume !(1 == ~E_9~0); 29982#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 30499#L1615-1 assume !(1 == ~E_11~0); 29438#L1620-1 assume !(1 == ~E_12~0); 29439#L1625-1 assume !(1 == ~E_13~0); 30226#L1630-1 assume !(1 == ~E_14~0); 29607#L1635-1 assume { :end_inline_reset_delta_events } true; 29548#L2017-2 [2021-11-19 05:31:56,819 INFO L793 eck$LassoCheckResult]: Loop: 29548#L2017-2 assume !false; 28828#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28829#L1316 assume !false; 30157#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 30219#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 28766#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 28908#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28909#L1115 assume !(0 != eval_~tmp~0#1); 30242#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29663#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29664#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29846#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30347#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30016#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30017#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30579#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30754#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30749#L1372-3 assume !(0 == ~T7_E~0); 28810#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28811#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29480#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29481#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 30392#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 30702#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29960#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 29116#L1412-3 assume !(0 == ~E_1~0); 29117#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29881#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29882#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30576#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30263#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29975#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29976#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28876#L1452-3 assume !(0 == ~E_9~0); 28877#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 30515#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 30516#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 30320#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 30321#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 29114#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29115#L646-42 assume 1 == ~m_pc~0; 29700#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30548#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30549#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30687#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30688#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30480#L665-42 assume 1 == ~t1_pc~0; 30441#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30443#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30629#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29283#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29284#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30753#L684-42 assume 1 == ~t2_pc~0; 30132#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30133#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30743#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29912#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29913#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30035#L703-42 assume 1 == ~t3_pc~0; 30233#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30234#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29552#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29553#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30327#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29947#L722-42 assume 1 == ~t4_pc~0; 29948#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30358#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29601#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29428#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29429#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30723#L741-42 assume !(1 == ~t5_pc~0); 30340#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 29810#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29811#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30756#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29718#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29719#L760-42 assume !(1 == ~t6_pc~0); 29853#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 29988#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29989#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30377#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 29670#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29671#L779-42 assume 1 == ~t7_pc~0; 30500#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30448#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29357#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29358#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29211#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29212#L798-42 assume !(1 == ~t8_pc~0); 28822#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 28823#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30566#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30012#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29042#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29043#L817-42 assume 1 == ~t9_pc~0; 29816#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29326#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29327#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29453#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30258#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30259#L836-42 assume !(1 == ~t10_pc~0); 30352#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 29364#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29365#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30666#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30667#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30708#L855-42 assume 1 == ~t11_pc~0; 30721#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28915#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28916#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29665#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 30428#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29529#L874-42 assume 1 == ~t12_pc~0; 29530#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 29769#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28830#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28831#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29084#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29085#L893-42 assume 1 == ~t13_pc~0; 30288#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 30069#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30084#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29986#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 29458#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 29459#L912-42 assume !(1 == ~t14_pc~0); 30268#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 28776#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 28777#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30357#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 29204#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29205#L1495-3 assume !(1 == ~M_E~0); 29820#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30248#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30341#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29434#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29397#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29398#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30055#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30278#L1530-3 assume !(1 == ~T8_E~0); 29243#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29244#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29281#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30538#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30647#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 29687#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 29688#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30303#L1570-3 assume !(1 == ~E_2~0); 30254#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30255#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30610#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30654#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30700#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30077#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30078#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30553#L1610-3 assume !(1 == ~E_10~0); 29440#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29441#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 30045#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 30046#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 29950#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 29381#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 28986#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 29724#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 30280#L2036 assume !(0 == start_simulation_~tmp~3#1); 30281#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 30433#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 29593#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 30611#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 29993#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 29994#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30714#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 30715#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 29548#L2017-2 [2021-11-19 05:31:56,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:56,820 INFO L85 PathProgramCache]: Analyzing trace with hash -1911299672, now seen corresponding path program 1 times [2021-11-19 05:31:56,820 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:56,820 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1417043928] [2021-11-19 05:31:56,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:56,821 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:56,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:56,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:56,859 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:56,859 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1417043928] [2021-11-19 05:31:56,859 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1417043928] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:56,860 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:56,861 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:56,861 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2028836171] [2021-11-19 05:31:56,861 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:56,861 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:31:56,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:56,862 INFO L85 PathProgramCache]: Analyzing trace with hash 1991472556, now seen corresponding path program 1 times [2021-11-19 05:31:56,866 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:56,866 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973333860] [2021-11-19 05:31:56,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:56,866 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:56,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:56,916 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:56,916 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:56,918 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [973333860] [2021-11-19 05:31:56,920 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [973333860] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:56,920 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:56,920 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:56,921 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [626734996] [2021-11-19 05:31:56,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:56,922 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:31:56,922 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:31:56,923 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:31:56,923 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:31:56,923 INFO L87 Difference]: Start difference. First operand 2047 states and 3028 transitions. cyclomatic complexity: 982 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:56,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:31:56,971 INFO L93 Difference]: Finished difference Result 2047 states and 3027 transitions. [2021-11-19 05:31:56,972 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:31:56,974 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3027 transitions. [2021-11-19 05:31:56,985 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:57,000 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3027 transitions. [2021-11-19 05:31:57,000 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-11-19 05:31:57,003 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-11-19 05:31:57,003 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3027 transitions. [2021-11-19 05:31:57,006 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:31:57,006 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3027 transitions. [2021-11-19 05:31:57,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3027 transitions. [2021-11-19 05:31:57,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-11-19 05:31:57,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4787493893502688) internal successors, (3027), 2046 states have internal predecessors, (3027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:57,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3027 transitions. [2021-11-19 05:31:57,050 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3027 transitions. [2021-11-19 05:31:57,050 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3027 transitions. [2021-11-19 05:31:57,050 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-19 05:31:57,050 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3027 transitions. [2021-11-19 05:31:57,059 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:57,060 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:57,060 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:57,063 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:57,063 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:57,064 INFO L791 eck$LassoCheckResult]: Stem: 33747#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 33748#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 34350#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33467#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33468#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 33713#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33714#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33441#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33442#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34665#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34017#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34018#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34535#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33927#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33928#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33348#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33349#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33680#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 33878#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 32925#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32926#L1342 assume !(0 == ~M_E~0); 33091#L1342-2 assume !(0 == ~T1_E~0); 33647#L1347-1 assume !(0 == ~T2_E~0); 34648#L1352-1 assume !(0 == ~T3_E~0); 34444#L1357-1 assume !(0 == ~T4_E~0); 33672#L1362-1 assume !(0 == ~T5_E~0); 33673#L1367-1 assume !(0 == ~T6_E~0); 33270#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33271#L1377-1 assume !(0 == ~T8_E~0); 33601#L1382-1 assume !(0 == ~T9_E~0); 33602#L1387-1 assume !(0 == ~T10_E~0); 34329#L1392-1 assume !(0 == ~T11_E~0); 33633#L1397-1 assume !(0 == ~T12_E~0); 33634#L1402-1 assume !(0 == ~T13_E~0); 33286#L1407-1 assume !(0 == ~T14_E~0); 33287#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 34565#L1417-1 assume !(0 == ~E_2~0); 34566#L1422-1 assume !(0 == ~E_3~0); 34807#L1427-1 assume !(0 == ~E_4~0); 33474#L1432-1 assume !(0 == ~E_5~0); 33475#L1437-1 assume !(0 == ~E_6~0); 34483#L1442-1 assume !(0 == ~E_7~0); 34484#L1447-1 assume !(0 == ~E_8~0); 34326#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 33061#L1457-1 assume !(0 == ~E_10~0); 33062#L1462-1 assume !(0 == ~E_11~0); 34518#L1467-1 assume !(0 == ~E_12~0); 34530#L1472-1 assume !(0 == ~E_13~0); 34531#L1477-1 assume !(0 == ~E_14~0); 34273#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33260#L646 assume 1 == ~m_pc~0; 33261#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 33937#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33952#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33350#L1666 assume !(0 != activate_threads_~tmp~1#1); 33351#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34828#L665 assume !(1 == ~t1_pc~0); 33826#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33827#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33359#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33360#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 34150#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34151#L684 assume 1 == ~t2_pc~0; 34268#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34192#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34257#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34652#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 34653#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34841#L703 assume !(1 == ~t3_pc~0); 33496#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33497#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34143#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32895#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 32896#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33381#L722 assume 1 == ~t4_pc~0; 34119#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33562#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33907#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34467#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 33974#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33092#L741 assume 1 == ~t5_pc~0; 33093#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33403#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33557#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33558#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 34237#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33648#L760 assume !(1 == ~t6_pc~0); 33495#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33494#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33352#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33353#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34074#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34075#L779 assume 1 == ~t7_pc~0; 33137#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32983#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32984#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33392#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 33415#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33416#L798 assume !(1 == ~t8_pc~0); 34697#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 34620#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33139#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33140#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 34830#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32960#L817 assume 1 == ~t9_pc~0; 32961#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33755#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33756#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34278#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 33366#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33367#L836 assume !(1 == ~t10_pc~0); 33383#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 33314#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33315#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33563#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 33564#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34630#L855 assume 1 == ~t11_pc~0; 33948#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33949#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34513#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34322#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 34157#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33256#L874 assume !(1 == ~t12_pc~0); 33257#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33424#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33425#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33565#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 32933#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32934#L893 assume 1 == ~t13_pc~0; 34764#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33289#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33600#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34691#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 34699#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 34700#L912 assume 1 == ~t14_pc~0; 34490#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 34491#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 33259#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 33191#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 33192#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33967#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 34383#L1495-2 assume !(1 == ~T1_E~0); 34384#L1500-1 assume !(1 == ~T2_E~0); 34070#L1505-1 assume !(1 == ~T3_E~0); 34071#L1510-1 assume !(1 == ~T4_E~0); 34128#L1515-1 assume !(1 == ~T5_E~0); 34129#L1520-1 assume !(1 == ~T6_E~0); 34698#L1525-1 assume !(1 == ~T7_E~0); 34408#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33361#L1535-1 assume !(1 == ~T9_E~0); 33362#L1540-1 assume !(1 == ~T10_E~0); 32854#L1545-1 assume !(1 == ~T11_E~0); 32855#L1550-1 assume !(1 == ~T12_E~0); 33103#L1555-1 assume !(1 == ~T13_E~0); 33104#L1560-1 assume !(1 == ~T14_E~0); 33404#L1565-1 assume !(1 == ~E_1~0); 34817#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 34295#L1575-1 assume !(1 == ~E_3~0); 33674#L1580-1 assume !(1 == ~E_4~0); 33675#L1585-1 assume !(1 == ~E_5~0); 34145#L1590-1 assume !(1 == ~E_6~0); 33709#L1595-1 assume !(1 == ~E_7~0); 33710#L1600-1 assume !(1 == ~E_8~0); 34082#L1605-1 assume !(1 == ~E_9~0); 34083#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 34600#L1615-1 assume !(1 == ~E_11~0); 33539#L1620-1 assume !(1 == ~E_12~0); 33540#L1625-1 assume !(1 == ~E_13~0); 34327#L1630-1 assume !(1 == ~E_14~0); 33708#L1635-1 assume { :end_inline_reset_delta_events } true; 33649#L2017-2 [2021-11-19 05:31:57,065 INFO L793 eck$LassoCheckResult]: Loop: 33649#L2017-2 assume !false; 32929#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32930#L1316 assume !false; 34258#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 34320#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 32867#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 33009#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33010#L1115 assume !(0 != eval_~tmp~0#1); 34343#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33764#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33765#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33947#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34448#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34117#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34118#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34680#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34855#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34850#L1372-3 assume !(0 == ~T7_E~0); 32911#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32912#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33581#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33582#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 34493#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 34803#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34061#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 33217#L1412-3 assume !(0 == ~E_1~0); 33218#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33982#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33983#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 34677#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34364#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34076#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34077#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32977#L1452-3 assume !(0 == ~E_9~0); 32978#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34616#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34617#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 34421#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 34422#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 33215#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33216#L646-42 assume 1 == ~m_pc~0; 33801#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34649#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34650#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34788#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34789#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34581#L665-42 assume 1 == ~t1_pc~0; 34542#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34544#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34730#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33384#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33385#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34854#L684-42 assume 1 == ~t2_pc~0; 34233#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34234#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34844#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34013#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34014#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34136#L703-42 assume !(1 == ~t3_pc~0); 34336#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 34335#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33653#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33654#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34428#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34048#L722-42 assume 1 == ~t4_pc~0; 34049#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34459#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33702#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33529#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33530#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34824#L741-42 assume !(1 == ~t5_pc~0); 34441#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 33911#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33912#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34857#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33819#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33820#L760-42 assume !(1 == ~t6_pc~0); 33954#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 34089#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34090#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34478#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 33771#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33772#L779-42 assume !(1 == ~t7_pc~0); 34548#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 34549#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33458#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33459#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33312#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33313#L798-42 assume 1 == ~t8_pc~0; 33763#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32924#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34667#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34113#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33143#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33144#L817-42 assume 1 == ~t9_pc~0; 33917#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33427#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33428#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33554#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 34359#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34360#L836-42 assume 1 == ~t10_pc~0; 34452#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33465#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33466#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34767#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34768#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34809#L855-42 assume 1 == ~t11_pc~0; 34822#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33016#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33017#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33766#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 34529#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33630#L874-42 assume !(1 == ~t12_pc~0); 33632#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 33873#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32931#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32932#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33185#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33186#L893-42 assume 1 == ~t13_pc~0; 34389#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 34170#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34185#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34087#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 33559#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 33560#L912-42 assume !(1 == ~t14_pc~0); 34369#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 32877#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 32878#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 34458#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 33305#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33306#L1495-3 assume !(1 == ~M_E~0); 33921#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34349#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34442#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33535#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33498#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33499#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34156#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34379#L1530-3 assume !(1 == ~T8_E~0); 33344#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33345#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33382#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34639#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 34748#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 33788#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 33789#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34404#L1570-3 assume !(1 == ~E_2~0); 34355#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34356#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34711#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34755#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 34801#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 34178#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34179#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34654#L1610-3 assume !(1 == ~E_10~0); 33541#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33542#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 34146#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 34147#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 34051#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 33482#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 33087#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 33825#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 34381#L2036 assume !(0 == start_simulation_~tmp~3#1); 34382#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 34534#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 33694#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 34712#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 34094#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 34095#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34815#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 34816#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 33649#L2017-2 [2021-11-19 05:31:57,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:57,066 INFO L85 PathProgramCache]: Analyzing trace with hash 1716285734, now seen corresponding path program 1 times [2021-11-19 05:31:57,066 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:57,066 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1198709767] [2021-11-19 05:31:57,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:57,066 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:57,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:57,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:57,128 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:57,128 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1198709767] [2021-11-19 05:31:57,128 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1198709767] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:57,129 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:57,129 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:57,129 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618115128] [2021-11-19 05:31:57,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:57,130 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:31:57,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:57,130 INFO L85 PathProgramCache]: Analyzing trace with hash -1856485429, now seen corresponding path program 1 times [2021-11-19 05:31:57,131 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:57,131 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [998931228] [2021-11-19 05:31:57,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:57,131 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:57,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:57,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:57,188 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:57,188 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [998931228] [2021-11-19 05:31:57,188 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [998931228] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:57,188 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:57,188 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:57,189 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1905026573] [2021-11-19 05:31:57,189 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:57,189 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:31:57,189 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:31:57,190 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:31:57,190 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:31:57,190 INFO L87 Difference]: Start difference. First operand 2047 states and 3027 transitions. cyclomatic complexity: 981 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:57,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:31:57,238 INFO L93 Difference]: Finished difference Result 2047 states and 3026 transitions. [2021-11-19 05:31:57,239 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:31:57,240 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3026 transitions. [2021-11-19 05:31:57,251 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:57,275 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3026 transitions. [2021-11-19 05:31:57,275 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-11-19 05:31:57,277 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-11-19 05:31:57,278 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3026 transitions. [2021-11-19 05:31:57,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:31:57,281 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3026 transitions. [2021-11-19 05:31:57,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3026 transitions. [2021-11-19 05:31:57,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-11-19 05:31:57,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4782608695652173) internal successors, (3026), 2046 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:57,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3026 transitions. [2021-11-19 05:31:57,348 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3026 transitions. [2021-11-19 05:31:57,349 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3026 transitions. [2021-11-19 05:31:57,349 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-19 05:31:57,349 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3026 transitions. [2021-11-19 05:31:57,358 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:57,358 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:57,358 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:57,362 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:57,362 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:57,363 INFO L791 eck$LassoCheckResult]: Stem: 37848#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 37849#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 38451#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37568#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37569#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 37814#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37815#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37542#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37543#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38766#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38118#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38119#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38636#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38028#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38029#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37449#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37450#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37781#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37979#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 37026#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37027#L1342 assume !(0 == ~M_E~0); 37192#L1342-2 assume !(0 == ~T1_E~0); 37748#L1347-1 assume !(0 == ~T2_E~0); 38749#L1352-1 assume !(0 == ~T3_E~0); 38545#L1357-1 assume !(0 == ~T4_E~0); 37773#L1362-1 assume !(0 == ~T5_E~0); 37774#L1367-1 assume !(0 == ~T6_E~0); 37371#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37372#L1377-1 assume !(0 == ~T8_E~0); 37702#L1382-1 assume !(0 == ~T9_E~0); 37703#L1387-1 assume !(0 == ~T10_E~0); 38430#L1392-1 assume !(0 == ~T11_E~0); 37734#L1397-1 assume !(0 == ~T12_E~0); 37735#L1402-1 assume !(0 == ~T13_E~0); 37387#L1407-1 assume !(0 == ~T14_E~0); 37388#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 38666#L1417-1 assume !(0 == ~E_2~0); 38667#L1422-1 assume !(0 == ~E_3~0); 38908#L1427-1 assume !(0 == ~E_4~0); 37575#L1432-1 assume !(0 == ~E_5~0); 37576#L1437-1 assume !(0 == ~E_6~0); 38584#L1442-1 assume !(0 == ~E_7~0); 38585#L1447-1 assume !(0 == ~E_8~0); 38427#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 37162#L1457-1 assume !(0 == ~E_10~0); 37163#L1462-1 assume !(0 == ~E_11~0); 38619#L1467-1 assume !(0 == ~E_12~0); 38631#L1472-1 assume !(0 == ~E_13~0); 38632#L1477-1 assume !(0 == ~E_14~0); 38374#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37361#L646 assume 1 == ~m_pc~0; 37362#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38038#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38053#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37451#L1666 assume !(0 != activate_threads_~tmp~1#1); 37452#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38929#L665 assume !(1 == ~t1_pc~0); 37927#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 37928#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37460#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37461#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 38251#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38252#L684 assume 1 == ~t2_pc~0; 38369#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38293#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38358#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38753#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 38754#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38942#L703 assume !(1 == ~t3_pc~0); 37597#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37598#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38244#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36996#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 36997#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37482#L722 assume 1 == ~t4_pc~0; 38220#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37663#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38008#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38568#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 38075#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37193#L741 assume 1 == ~t5_pc~0; 37194#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37504#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37658#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37659#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 38338#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37749#L760 assume !(1 == ~t6_pc~0); 37596#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 37595#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37453#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37454#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38175#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38176#L779 assume 1 == ~t7_pc~0; 37238#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37084#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37085#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37493#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 37516#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37517#L798 assume !(1 == ~t8_pc~0); 38798#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 38721#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37240#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37241#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 38931#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37061#L817 assume 1 == ~t9_pc~0; 37062#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37856#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37857#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38379#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 37467#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37468#L836 assume !(1 == ~t10_pc~0); 37484#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 37415#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37416#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37664#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 37665#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38731#L855 assume 1 == ~t11_pc~0; 38049#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38050#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38614#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38423#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 38258#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37357#L874 assume !(1 == ~t12_pc~0); 37358#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 37525#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37526#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37666#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 37034#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37035#L893 assume 1 == ~t13_pc~0; 38865#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37390#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37701#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38792#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 38800#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 38801#L912 assume 1 == ~t14_pc~0; 38591#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 38592#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 37360#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 37292#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 37293#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38068#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 38484#L1495-2 assume !(1 == ~T1_E~0); 38485#L1500-1 assume !(1 == ~T2_E~0); 38171#L1505-1 assume !(1 == ~T3_E~0); 38172#L1510-1 assume !(1 == ~T4_E~0); 38229#L1515-1 assume !(1 == ~T5_E~0); 38230#L1520-1 assume !(1 == ~T6_E~0); 38799#L1525-1 assume !(1 == ~T7_E~0); 38509#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37462#L1535-1 assume !(1 == ~T9_E~0); 37463#L1540-1 assume !(1 == ~T10_E~0); 36955#L1545-1 assume !(1 == ~T11_E~0); 36956#L1550-1 assume !(1 == ~T12_E~0); 37204#L1555-1 assume !(1 == ~T13_E~0); 37205#L1560-1 assume !(1 == ~T14_E~0); 37505#L1565-1 assume !(1 == ~E_1~0); 38918#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 38396#L1575-1 assume !(1 == ~E_3~0); 37775#L1580-1 assume !(1 == ~E_4~0); 37776#L1585-1 assume !(1 == ~E_5~0); 38246#L1590-1 assume !(1 == ~E_6~0); 37810#L1595-1 assume !(1 == ~E_7~0); 37811#L1600-1 assume !(1 == ~E_8~0); 38183#L1605-1 assume !(1 == ~E_9~0); 38184#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 38701#L1615-1 assume !(1 == ~E_11~0); 37640#L1620-1 assume !(1 == ~E_12~0); 37641#L1625-1 assume !(1 == ~E_13~0); 38428#L1630-1 assume !(1 == ~E_14~0); 37809#L1635-1 assume { :end_inline_reset_delta_events } true; 37750#L2017-2 [2021-11-19 05:31:57,363 INFO L793 eck$LassoCheckResult]: Loop: 37750#L2017-2 assume !false; 37030#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37031#L1316 assume !false; 38359#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 38421#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 36968#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 37110#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 37111#L1115 assume !(0 != eval_~tmp~0#1); 38444#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37865#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37866#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38048#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38549#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38218#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38219#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38781#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 38956#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38951#L1372-3 assume !(0 == ~T7_E~0); 37012#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37013#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37682#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37683#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 38594#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 38904#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38162#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 37318#L1412-3 assume !(0 == ~E_1~0); 37319#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38083#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38084#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38778#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38465#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38177#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38178#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37078#L1452-3 assume !(0 == ~E_9~0); 37079#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38717#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38718#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 38522#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 38523#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 37316#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37317#L646-42 assume 1 == ~m_pc~0; 37902#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38750#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38751#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38889#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38890#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38682#L665-42 assume 1 == ~t1_pc~0; 38643#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38645#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38831#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37485#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37486#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38955#L684-42 assume !(1 == ~t2_pc~0); 38336#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 38335#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38945#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38114#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38115#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38237#L703-42 assume 1 == ~t3_pc~0; 38435#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38436#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37754#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37755#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38529#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38149#L722-42 assume 1 == ~t4_pc~0; 38150#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38560#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37803#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37630#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37631#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38925#L741-42 assume 1 == ~t5_pc~0; 38867#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38012#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38013#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38958#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37920#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37921#L760-42 assume !(1 == ~t6_pc~0); 38055#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 38190#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38191#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38579#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 37872#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37873#L779-42 assume !(1 == ~t7_pc~0); 38649#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 38650#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37559#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37560#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37413#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37414#L798-42 assume !(1 == ~t8_pc~0); 37024#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 37025#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38768#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38214#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37244#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37245#L817-42 assume 1 == ~t9_pc~0; 38018#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37528#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37529#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37655#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38460#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38461#L836-42 assume 1 == ~t10_pc~0; 38553#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37566#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37567#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38868#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38869#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38910#L855-42 assume 1 == ~t11_pc~0; 38923#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37117#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37118#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37867#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38630#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37731#L874-42 assume 1 == ~t12_pc~0; 37732#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37974#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37032#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37033#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37286#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37287#L893-42 assume 1 == ~t13_pc~0; 38490#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 38271#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38286#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38188#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 37660#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 37661#L912-42 assume !(1 == ~t14_pc~0); 38470#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 36978#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 36979#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38559#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 37406#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37407#L1495-3 assume !(1 == ~M_E~0); 38022#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38450#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38543#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37636#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37599#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37600#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38257#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38480#L1530-3 assume !(1 == ~T8_E~0); 37445#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37446#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37483#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38740#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38849#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 37889#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 37890#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38505#L1570-3 assume !(1 == ~E_2~0); 38456#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38457#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38812#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38856#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38902#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38279#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38280#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38755#L1610-3 assume !(1 == ~E_10~0); 37642#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37643#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 38247#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 38248#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 38152#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 37583#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 37188#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 37926#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 38482#L2036 assume !(0 == start_simulation_~tmp~3#1); 38483#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 38635#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 37795#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 38813#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 38195#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 38196#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38916#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 38917#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 37750#L2017-2 [2021-11-19 05:31:57,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:57,365 INFO L85 PathProgramCache]: Analyzing trace with hash -383452696, now seen corresponding path program 1 times [2021-11-19 05:31:57,365 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:57,365 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1597237804] [2021-11-19 05:31:57,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:57,365 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:57,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:57,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:57,411 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:57,411 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1597237804] [2021-11-19 05:31:57,411 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1597237804] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:57,411 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:57,411 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:57,411 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1823104206] [2021-11-19 05:31:57,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:57,413 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:31:57,413 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:57,414 INFO L85 PathProgramCache]: Analyzing trace with hash -1218842068, now seen corresponding path program 1 times [2021-11-19 05:31:57,414 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:57,414 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1400575460] [2021-11-19 05:31:57,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:57,415 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:57,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:57,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:57,469 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:57,469 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1400575460] [2021-11-19 05:31:57,469 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1400575460] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:57,469 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:57,470 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:57,470 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1613460028] [2021-11-19 05:31:57,470 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:57,470 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:31:57,471 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:31:57,471 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:31:57,471 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:31:57,472 INFO L87 Difference]: Start difference. First operand 2047 states and 3026 transitions. cyclomatic complexity: 980 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:57,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:31:57,517 INFO L93 Difference]: Finished difference Result 2047 states and 3025 transitions. [2021-11-19 05:31:57,517 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:31:57,519 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3025 transitions. [2021-11-19 05:31:57,529 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:57,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3025 transitions. [2021-11-19 05:31:57,540 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-11-19 05:31:57,542 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-11-19 05:31:57,543 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3025 transitions. [2021-11-19 05:31:57,546 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:31:57,546 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3025 transitions. [2021-11-19 05:31:57,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3025 transitions. [2021-11-19 05:31:57,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-11-19 05:31:57,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.477772349780166) internal successors, (3025), 2046 states have internal predecessors, (3025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:57,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3025 transitions. [2021-11-19 05:31:57,588 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3025 transitions. [2021-11-19 05:31:57,589 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3025 transitions. [2021-11-19 05:31:57,589 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-19 05:31:57,589 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3025 transitions. [2021-11-19 05:31:57,597 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:57,597 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:57,597 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:57,601 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:57,601 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:57,602 INFO L791 eck$LassoCheckResult]: Stem: 41949#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 41950#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 42552#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41669#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41670#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 41915#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41916#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41643#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41644#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42867#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42219#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42220#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42737#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42129#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 42130#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41550#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41551#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 41882#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42080#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 41127#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41128#L1342 assume !(0 == ~M_E~0); 41293#L1342-2 assume !(0 == ~T1_E~0); 41849#L1347-1 assume !(0 == ~T2_E~0); 42850#L1352-1 assume !(0 == ~T3_E~0); 42646#L1357-1 assume !(0 == ~T4_E~0); 41874#L1362-1 assume !(0 == ~T5_E~0); 41875#L1367-1 assume !(0 == ~T6_E~0); 41472#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41473#L1377-1 assume !(0 == ~T8_E~0); 41803#L1382-1 assume !(0 == ~T9_E~0); 41804#L1387-1 assume !(0 == ~T10_E~0); 42531#L1392-1 assume !(0 == ~T11_E~0); 41835#L1397-1 assume !(0 == ~T12_E~0); 41836#L1402-1 assume !(0 == ~T13_E~0); 41488#L1407-1 assume !(0 == ~T14_E~0); 41489#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 42767#L1417-1 assume !(0 == ~E_2~0); 42768#L1422-1 assume !(0 == ~E_3~0); 43009#L1427-1 assume !(0 == ~E_4~0); 41676#L1432-1 assume !(0 == ~E_5~0); 41677#L1437-1 assume !(0 == ~E_6~0); 42685#L1442-1 assume !(0 == ~E_7~0); 42686#L1447-1 assume !(0 == ~E_8~0); 42528#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 41263#L1457-1 assume !(0 == ~E_10~0); 41264#L1462-1 assume !(0 == ~E_11~0); 42720#L1467-1 assume !(0 == ~E_12~0); 42732#L1472-1 assume !(0 == ~E_13~0); 42733#L1477-1 assume !(0 == ~E_14~0); 42475#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41462#L646 assume 1 == ~m_pc~0; 41463#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42139#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42154#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41552#L1666 assume !(0 != activate_threads_~tmp~1#1); 41553#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43030#L665 assume !(1 == ~t1_pc~0); 42028#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42029#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41561#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41562#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 42352#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42353#L684 assume 1 == ~t2_pc~0; 42470#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42394#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42459#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42854#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 42855#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43043#L703 assume !(1 == ~t3_pc~0); 41698#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41699#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42345#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41097#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 41098#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41583#L722 assume 1 == ~t4_pc~0; 42321#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41764#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42109#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42669#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 42176#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41294#L741 assume 1 == ~t5_pc~0; 41295#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41605#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41759#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41760#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 42439#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41850#L760 assume !(1 == ~t6_pc~0); 41697#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41696#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41554#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41555#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42276#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42277#L779 assume 1 == ~t7_pc~0; 41339#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41185#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41186#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41594#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 41617#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41618#L798 assume !(1 == ~t8_pc~0); 42899#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 42822#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41341#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41342#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 43032#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41162#L817 assume 1 == ~t9_pc~0; 41163#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41957#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41958#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42480#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 41568#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41569#L836 assume !(1 == ~t10_pc~0); 41585#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 41516#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41517#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41765#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 41766#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42832#L855 assume 1 == ~t11_pc~0; 42150#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42151#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42715#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42524#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 42359#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41458#L874 assume !(1 == ~t12_pc~0); 41459#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 41626#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41627#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41767#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 41135#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41136#L893 assume 1 == ~t13_pc~0; 42966#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41491#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41802#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42893#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 42901#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 42902#L912 assume 1 == ~t14_pc~0; 42692#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 42693#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 41461#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 41393#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 41394#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42169#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 42585#L1495-2 assume !(1 == ~T1_E~0); 42586#L1500-1 assume !(1 == ~T2_E~0); 42272#L1505-1 assume !(1 == ~T3_E~0); 42273#L1510-1 assume !(1 == ~T4_E~0); 42330#L1515-1 assume !(1 == ~T5_E~0); 42331#L1520-1 assume !(1 == ~T6_E~0); 42900#L1525-1 assume !(1 == ~T7_E~0); 42610#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41563#L1535-1 assume !(1 == ~T9_E~0); 41564#L1540-1 assume !(1 == ~T10_E~0); 41056#L1545-1 assume !(1 == ~T11_E~0); 41057#L1550-1 assume !(1 == ~T12_E~0); 41305#L1555-1 assume !(1 == ~T13_E~0); 41306#L1560-1 assume !(1 == ~T14_E~0); 41606#L1565-1 assume !(1 == ~E_1~0); 43019#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 42497#L1575-1 assume !(1 == ~E_3~0); 41876#L1580-1 assume !(1 == ~E_4~0); 41877#L1585-1 assume !(1 == ~E_5~0); 42347#L1590-1 assume !(1 == ~E_6~0); 41911#L1595-1 assume !(1 == ~E_7~0); 41912#L1600-1 assume !(1 == ~E_8~0); 42284#L1605-1 assume !(1 == ~E_9~0); 42285#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 42802#L1615-1 assume !(1 == ~E_11~0); 41741#L1620-1 assume !(1 == ~E_12~0); 41742#L1625-1 assume !(1 == ~E_13~0); 42529#L1630-1 assume !(1 == ~E_14~0); 41910#L1635-1 assume { :end_inline_reset_delta_events } true; 41851#L2017-2 [2021-11-19 05:31:57,603 INFO L793 eck$LassoCheckResult]: Loop: 41851#L2017-2 assume !false; 41131#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41132#L1316 assume !false; 42460#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 42522#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 41069#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 41211#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 41212#L1115 assume !(0 != eval_~tmp~0#1); 42545#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41966#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41967#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42149#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42650#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42319#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42320#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 42882#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43057#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43052#L1372-3 assume !(0 == ~T7_E~0); 41113#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41114#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41783#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41784#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 42695#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43005#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42263#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 41419#L1412-3 assume !(0 == ~E_1~0); 41420#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42184#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42185#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42879#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42566#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42278#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42279#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41179#L1452-3 assume !(0 == ~E_9~0); 41180#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 42818#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 42819#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 42623#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 42624#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 41417#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41418#L646-42 assume 1 == ~m_pc~0; 42003#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42851#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42852#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42990#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42991#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42783#L665-42 assume 1 == ~t1_pc~0; 42744#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42746#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42932#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41586#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41587#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43056#L684-42 assume 1 == ~t2_pc~0; 42435#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42436#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43046#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42215#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42216#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42338#L703-42 assume 1 == ~t3_pc~0; 42536#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42537#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41855#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41856#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42630#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42250#L722-42 assume 1 == ~t4_pc~0; 42251#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42661#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41904#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41731#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41732#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43026#L741-42 assume !(1 == ~t5_pc~0); 42643#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 42113#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42114#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43059#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42021#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42022#L760-42 assume !(1 == ~t6_pc~0); 42156#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 42291#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42292#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42680#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 41973#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41974#L779-42 assume 1 == ~t7_pc~0; 42803#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42751#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41660#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41661#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41514#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41515#L798-42 assume !(1 == ~t8_pc~0); 41125#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 41126#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42869#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42315#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41345#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41346#L817-42 assume 1 == ~t9_pc~0; 42119#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41629#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41630#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41756#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42561#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42562#L836-42 assume 1 == ~t10_pc~0; 42654#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41667#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41668#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42969#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 42970#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43011#L855-42 assume 1 == ~t11_pc~0; 43024#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41218#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41219#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41968#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42731#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41832#L874-42 assume 1 == ~t12_pc~0; 41833#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42075#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41133#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41134#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 41387#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41388#L893-42 assume !(1 == ~t13_pc~0); 42371#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 42372#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42387#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42289#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 41761#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 41762#L912-42 assume !(1 == ~t14_pc~0); 42571#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 41079#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 41080#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42660#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 41507#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41508#L1495-3 assume !(1 == ~M_E~0); 42123#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42551#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42644#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41737#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41700#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41701#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42358#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42581#L1530-3 assume !(1 == ~T8_E~0); 41546#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41547#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41584#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 42841#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42950#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 41990#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 41991#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42606#L1570-3 assume !(1 == ~E_2~0); 42557#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42558#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 42913#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42958#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43003#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42380#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 42381#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 42856#L1610-3 assume !(1 == ~E_10~0); 41743#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41744#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 42348#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 42349#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 42253#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 41684#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 41289#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 42027#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 42583#L2036 assume !(0 == start_simulation_~tmp~3#1); 42584#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 42736#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 41896#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 42914#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 42296#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 42297#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43017#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 43018#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 41851#L2017-2 [2021-11-19 05:31:57,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:57,604 INFO L85 PathProgramCache]: Analyzing trace with hash -1364407510, now seen corresponding path program 1 times [2021-11-19 05:31:57,604 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:57,604 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1007009140] [2021-11-19 05:31:57,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:57,605 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:57,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:57,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:57,646 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:57,646 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1007009140] [2021-11-19 05:31:57,646 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1007009140] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:57,646 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:57,647 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:57,647 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [692312875] [2021-11-19 05:31:57,647 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:57,647 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:31:57,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:57,648 INFO L85 PathProgramCache]: Analyzing trace with hash -1715277972, now seen corresponding path program 2 times [2021-11-19 05:31:57,648 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:57,648 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421267247] [2021-11-19 05:31:57,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:57,649 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:57,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:57,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:57,708 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:57,708 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421267247] [2021-11-19 05:31:57,709 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [421267247] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:57,709 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:57,709 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:57,709 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1746672743] [2021-11-19 05:31:57,709 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:57,710 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:31:57,710 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:31:57,711 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:31:57,711 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:31:57,711 INFO L87 Difference]: Start difference. First operand 2047 states and 3025 transitions. cyclomatic complexity: 979 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:57,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:31:57,756 INFO L93 Difference]: Finished difference Result 2047 states and 3024 transitions. [2021-11-19 05:31:57,756 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:31:57,757 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3024 transitions. [2021-11-19 05:31:57,767 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:57,777 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3024 transitions. [2021-11-19 05:31:57,778 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-11-19 05:31:57,780 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-11-19 05:31:57,780 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3024 transitions. [2021-11-19 05:31:57,783 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:31:57,784 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3024 transitions. [2021-11-19 05:31:57,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3024 transitions. [2021-11-19 05:31:57,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-11-19 05:31:57,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4772838299951148) internal successors, (3024), 2046 states have internal predecessors, (3024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:57,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3024 transitions. [2021-11-19 05:31:57,866 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3024 transitions. [2021-11-19 05:31:57,866 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3024 transitions. [2021-11-19 05:31:57,866 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-19 05:31:57,866 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3024 transitions. [2021-11-19 05:31:57,874 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:57,875 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:57,875 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:57,878 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:57,878 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:57,879 INFO L791 eck$LassoCheckResult]: Stem: 46050#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 46051#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 46653#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45770#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45771#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 46016#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46017#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45744#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45745#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46968#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46320#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46321#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46838#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46230#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46231#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 45651#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45652#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 45983#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46181#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 45228#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45229#L1342 assume !(0 == ~M_E~0); 45394#L1342-2 assume !(0 == ~T1_E~0); 45950#L1347-1 assume !(0 == ~T2_E~0); 46951#L1352-1 assume !(0 == ~T3_E~0); 46747#L1357-1 assume !(0 == ~T4_E~0); 45975#L1362-1 assume !(0 == ~T5_E~0); 45976#L1367-1 assume !(0 == ~T6_E~0); 45573#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45574#L1377-1 assume !(0 == ~T8_E~0); 45904#L1382-1 assume !(0 == ~T9_E~0); 45905#L1387-1 assume !(0 == ~T10_E~0); 46632#L1392-1 assume !(0 == ~T11_E~0); 45936#L1397-1 assume !(0 == ~T12_E~0); 45937#L1402-1 assume !(0 == ~T13_E~0); 45589#L1407-1 assume !(0 == ~T14_E~0); 45590#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 46868#L1417-1 assume !(0 == ~E_2~0); 46869#L1422-1 assume !(0 == ~E_3~0); 47110#L1427-1 assume !(0 == ~E_4~0); 45777#L1432-1 assume !(0 == ~E_5~0); 45778#L1437-1 assume !(0 == ~E_6~0); 46786#L1442-1 assume !(0 == ~E_7~0); 46787#L1447-1 assume !(0 == ~E_8~0); 46629#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 45364#L1457-1 assume !(0 == ~E_10~0); 45365#L1462-1 assume !(0 == ~E_11~0); 46821#L1467-1 assume !(0 == ~E_12~0); 46833#L1472-1 assume !(0 == ~E_13~0); 46834#L1477-1 assume !(0 == ~E_14~0); 46576#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45563#L646 assume 1 == ~m_pc~0; 45564#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46240#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46255#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45653#L1666 assume !(0 != activate_threads_~tmp~1#1); 45654#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47131#L665 assume !(1 == ~t1_pc~0); 46129#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46130#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45662#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45663#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 46453#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46454#L684 assume 1 == ~t2_pc~0; 46571#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46495#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46560#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46955#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 46956#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47144#L703 assume !(1 == ~t3_pc~0); 45799#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45800#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46446#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45198#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 45199#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45684#L722 assume 1 == ~t4_pc~0; 46422#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45865#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46210#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46770#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 46277#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45395#L741 assume 1 == ~t5_pc~0; 45396#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45706#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45860#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45861#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 46540#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45951#L760 assume !(1 == ~t6_pc~0); 45798#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 45797#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45655#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45656#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46377#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46378#L779 assume 1 == ~t7_pc~0; 45440#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45286#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45287#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45695#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 45718#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45719#L798 assume !(1 == ~t8_pc~0); 47000#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46923#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45442#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45443#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 47133#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45263#L817 assume 1 == ~t9_pc~0; 45264#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46058#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46059#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46581#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 45669#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45670#L836 assume !(1 == ~t10_pc~0); 45686#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 45617#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45618#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45866#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 45867#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46933#L855 assume 1 == ~t11_pc~0; 46251#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46252#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46816#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46625#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 46460#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45559#L874 assume !(1 == ~t12_pc~0); 45560#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 45727#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45728#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45868#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 45236#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45237#L893 assume 1 == ~t13_pc~0; 47067#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45592#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45903#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46994#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 47002#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 47003#L912 assume 1 == ~t14_pc~0; 46793#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 46794#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 45562#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 45494#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 45495#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46270#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 46686#L1495-2 assume !(1 == ~T1_E~0); 46687#L1500-1 assume !(1 == ~T2_E~0); 46373#L1505-1 assume !(1 == ~T3_E~0); 46374#L1510-1 assume !(1 == ~T4_E~0); 46431#L1515-1 assume !(1 == ~T5_E~0); 46432#L1520-1 assume !(1 == ~T6_E~0); 47001#L1525-1 assume !(1 == ~T7_E~0); 46711#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 45664#L1535-1 assume !(1 == ~T9_E~0); 45665#L1540-1 assume !(1 == ~T10_E~0); 45157#L1545-1 assume !(1 == ~T11_E~0); 45158#L1550-1 assume !(1 == ~T12_E~0); 45406#L1555-1 assume !(1 == ~T13_E~0); 45407#L1560-1 assume !(1 == ~T14_E~0); 45707#L1565-1 assume !(1 == ~E_1~0); 47120#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 46598#L1575-1 assume !(1 == ~E_3~0); 45977#L1580-1 assume !(1 == ~E_4~0); 45978#L1585-1 assume !(1 == ~E_5~0); 46448#L1590-1 assume !(1 == ~E_6~0); 46012#L1595-1 assume !(1 == ~E_7~0); 46013#L1600-1 assume !(1 == ~E_8~0); 46385#L1605-1 assume !(1 == ~E_9~0); 46386#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 46903#L1615-1 assume !(1 == ~E_11~0); 45842#L1620-1 assume !(1 == ~E_12~0); 45843#L1625-1 assume !(1 == ~E_13~0); 46630#L1630-1 assume !(1 == ~E_14~0); 46011#L1635-1 assume { :end_inline_reset_delta_events } true; 45952#L2017-2 [2021-11-19 05:31:57,880 INFO L793 eck$LassoCheckResult]: Loop: 45952#L2017-2 assume !false; 45232#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45233#L1316 assume !false; 46561#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 46623#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45170#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 45312#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 45313#L1115 assume !(0 != eval_~tmp~0#1); 46646#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46067#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46068#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46250#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46751#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46420#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46421#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46983#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47158#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47153#L1372-3 assume !(0 == ~T7_E~0); 45214#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45215#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45884#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 45885#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 46796#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47106#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46364#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 45520#L1412-3 assume !(0 == ~E_1~0); 45521#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46285#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46286#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 46980#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46667#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46379#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46380#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45280#L1452-3 assume !(0 == ~E_9~0); 45281#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 46919#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46920#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 46724#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 46725#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 45518#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45519#L646-42 assume 1 == ~m_pc~0; 46104#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46952#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46953#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47091#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47092#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46884#L665-42 assume 1 == ~t1_pc~0; 46845#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46847#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47033#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45687#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45688#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47157#L684-42 assume 1 == ~t2_pc~0; 46536#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46537#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47147#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46316#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46317#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46439#L703-42 assume 1 == ~t3_pc~0; 46637#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46638#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45956#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45957#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46731#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46351#L722-42 assume 1 == ~t4_pc~0; 46352#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46762#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46005#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45832#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45833#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47127#L741-42 assume !(1 == ~t5_pc~0); 46744#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 46214#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46215#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47160#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46122#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46123#L760-42 assume !(1 == ~t6_pc~0); 46257#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 46392#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46393#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46781#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 46074#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46075#L779-42 assume !(1 == ~t7_pc~0); 46851#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 46852#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45761#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45762#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45615#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45616#L798-42 assume 1 == ~t8_pc~0; 46066#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45227#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46970#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46416#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45446#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45447#L817-42 assume 1 == ~t9_pc~0; 46220#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45730#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45731#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45857#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46662#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46663#L836-42 assume 1 == ~t10_pc~0; 46755#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45768#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45769#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47070#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47071#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47112#L855-42 assume 1 == ~t11_pc~0; 47125#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45319#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45320#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46069#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46832#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45933#L874-42 assume 1 == ~t12_pc~0; 45934#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46176#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45234#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45235#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 45488#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45489#L893-42 assume 1 == ~t13_pc~0; 46692#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46473#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46488#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46390#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 45862#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 45863#L912-42 assume !(1 == ~t14_pc~0); 46672#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 45180#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 45181#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46761#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 45608#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45609#L1495-3 assume !(1 == ~M_E~0); 46224#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46652#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46745#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45838#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45801#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45802#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46459#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46682#L1530-3 assume !(1 == ~T8_E~0); 45647#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45648#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 45685#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46942#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47051#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46091#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 46092#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46707#L1570-3 assume !(1 == ~E_2~0); 46658#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46659#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47014#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47059#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47104#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46481#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46482#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46957#L1610-3 assume !(1 == ~E_10~0); 45844#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 45845#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 46449#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46450#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 46354#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 45785#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45390#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 46128#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 46684#L2036 assume !(0 == start_simulation_~tmp~3#1); 46685#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 46837#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45997#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 47015#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 46397#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 46398#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47118#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 47119#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 45952#L2017-2 [2021-11-19 05:31:57,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:57,881 INFO L85 PathProgramCache]: Analyzing trace with hash 405064104, now seen corresponding path program 1 times [2021-11-19 05:31:57,881 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:57,881 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1711912534] [2021-11-19 05:31:57,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:57,881 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:57,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:57,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:57,912 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:57,912 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1711912534] [2021-11-19 05:31:57,913 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1711912534] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:57,913 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:57,913 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:57,913 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [980544808] [2021-11-19 05:31:57,913 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:57,914 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:31:57,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:57,914 INFO L85 PathProgramCache]: Analyzing trace with hash -1400619827, now seen corresponding path program 1 times [2021-11-19 05:31:57,915 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:57,915 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1404137119] [2021-11-19 05:31:57,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:57,915 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:57,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:57,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:57,961 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:57,961 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1404137119] [2021-11-19 05:31:57,962 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1404137119] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:57,962 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:57,962 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:57,962 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1962172043] [2021-11-19 05:31:57,962 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:57,963 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:31:57,963 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:31:57,963 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:31:57,964 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:31:57,964 INFO L87 Difference]: Start difference. First operand 2047 states and 3024 transitions. cyclomatic complexity: 978 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:58,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:31:58,006 INFO L93 Difference]: Finished difference Result 2047 states and 3023 transitions. [2021-11-19 05:31:58,006 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:31:58,007 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3023 transitions. [2021-11-19 05:31:58,017 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:58,028 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3023 transitions. [2021-11-19 05:31:58,028 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-11-19 05:31:58,030 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-11-19 05:31:58,030 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3023 transitions. [2021-11-19 05:31:58,034 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:31:58,034 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3023 transitions. [2021-11-19 05:31:58,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3023 transitions. [2021-11-19 05:31:58,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-11-19 05:31:58,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4767953102100635) internal successors, (3023), 2046 states have internal predecessors, (3023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:58,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3023 transitions. [2021-11-19 05:31:58,075 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3023 transitions. [2021-11-19 05:31:58,075 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3023 transitions. [2021-11-19 05:31:58,075 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-19 05:31:58,075 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3023 transitions. [2021-11-19 05:31:58,083 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:58,084 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:58,084 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:58,087 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:58,087 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:58,088 INFO L791 eck$LassoCheckResult]: Stem: 50151#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 50152#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 50754#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49871#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49872#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 50117#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50118#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49845#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49846#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51069#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50421#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50422#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50939#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50331#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50332#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49752#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49753#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50084#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 50282#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 49329#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49330#L1342 assume !(0 == ~M_E~0); 49495#L1342-2 assume !(0 == ~T1_E~0); 50051#L1347-1 assume !(0 == ~T2_E~0); 51052#L1352-1 assume !(0 == ~T3_E~0); 50848#L1357-1 assume !(0 == ~T4_E~0); 50076#L1362-1 assume !(0 == ~T5_E~0); 50077#L1367-1 assume !(0 == ~T6_E~0); 49674#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49675#L1377-1 assume !(0 == ~T8_E~0); 50005#L1382-1 assume !(0 == ~T9_E~0); 50006#L1387-1 assume !(0 == ~T10_E~0); 50733#L1392-1 assume !(0 == ~T11_E~0); 50037#L1397-1 assume !(0 == ~T12_E~0); 50038#L1402-1 assume !(0 == ~T13_E~0); 49690#L1407-1 assume !(0 == ~T14_E~0); 49691#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 50969#L1417-1 assume !(0 == ~E_2~0); 50970#L1422-1 assume !(0 == ~E_3~0); 51211#L1427-1 assume !(0 == ~E_4~0); 49878#L1432-1 assume !(0 == ~E_5~0); 49879#L1437-1 assume !(0 == ~E_6~0); 50887#L1442-1 assume !(0 == ~E_7~0); 50888#L1447-1 assume !(0 == ~E_8~0); 50730#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 49465#L1457-1 assume !(0 == ~E_10~0); 49466#L1462-1 assume !(0 == ~E_11~0); 50922#L1467-1 assume !(0 == ~E_12~0); 50934#L1472-1 assume !(0 == ~E_13~0); 50935#L1477-1 assume !(0 == ~E_14~0); 50677#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49664#L646 assume 1 == ~m_pc~0; 49665#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50341#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50356#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49754#L1666 assume !(0 != activate_threads_~tmp~1#1); 49755#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51232#L665 assume !(1 == ~t1_pc~0); 50230#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50231#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49763#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49764#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 50554#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50555#L684 assume 1 == ~t2_pc~0; 50672#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50596#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50661#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51056#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 51057#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51245#L703 assume !(1 == ~t3_pc~0); 49900#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49901#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50547#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49299#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 49300#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49785#L722 assume 1 == ~t4_pc~0; 50523#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49966#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50311#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50871#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 50378#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49496#L741 assume 1 == ~t5_pc~0; 49497#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49807#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49961#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49962#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 50641#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50052#L760 assume !(1 == ~t6_pc~0); 49899#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49898#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49756#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49757#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50478#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50479#L779 assume 1 == ~t7_pc~0; 49541#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49387#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49388#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49796#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 49819#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49820#L798 assume !(1 == ~t8_pc~0); 51101#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 51024#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49543#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49544#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 51234#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49364#L817 assume 1 == ~t9_pc~0; 49365#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50159#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50160#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50682#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 49770#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49771#L836 assume !(1 == ~t10_pc~0); 49787#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49718#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49719#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49967#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 49968#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51034#L855 assume 1 == ~t11_pc~0; 50352#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 50353#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50917#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50726#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 50561#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49660#L874 assume !(1 == ~t12_pc~0); 49661#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 49828#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49829#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49969#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 49337#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49338#L893 assume 1 == ~t13_pc~0; 51168#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 49693#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50004#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 51095#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 51103#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 51104#L912 assume 1 == ~t14_pc~0; 50894#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 50895#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 49663#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 49595#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 49596#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50371#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 50787#L1495-2 assume !(1 == ~T1_E~0); 50788#L1500-1 assume !(1 == ~T2_E~0); 50474#L1505-1 assume !(1 == ~T3_E~0); 50475#L1510-1 assume !(1 == ~T4_E~0); 50532#L1515-1 assume !(1 == ~T5_E~0); 50533#L1520-1 assume !(1 == ~T6_E~0); 51102#L1525-1 assume !(1 == ~T7_E~0); 50812#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49765#L1535-1 assume !(1 == ~T9_E~0); 49766#L1540-1 assume !(1 == ~T10_E~0); 49258#L1545-1 assume !(1 == ~T11_E~0); 49259#L1550-1 assume !(1 == ~T12_E~0); 49507#L1555-1 assume !(1 == ~T13_E~0); 49508#L1560-1 assume !(1 == ~T14_E~0); 49808#L1565-1 assume !(1 == ~E_1~0); 51221#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 50699#L1575-1 assume !(1 == ~E_3~0); 50078#L1580-1 assume !(1 == ~E_4~0); 50079#L1585-1 assume !(1 == ~E_5~0); 50549#L1590-1 assume !(1 == ~E_6~0); 50113#L1595-1 assume !(1 == ~E_7~0); 50114#L1600-1 assume !(1 == ~E_8~0); 50486#L1605-1 assume !(1 == ~E_9~0); 50487#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 51004#L1615-1 assume !(1 == ~E_11~0); 49943#L1620-1 assume !(1 == ~E_12~0); 49944#L1625-1 assume !(1 == ~E_13~0); 50731#L1630-1 assume !(1 == ~E_14~0); 50112#L1635-1 assume { :end_inline_reset_delta_events } true; 50053#L2017-2 [2021-11-19 05:31:58,088 INFO L793 eck$LassoCheckResult]: Loop: 50053#L2017-2 assume !false; 49333#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49334#L1316 assume !false; 50662#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 50724#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 49271#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 49413#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49414#L1115 assume !(0 != eval_~tmp~0#1); 50747#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50168#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50169#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50351#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50852#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50521#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50522#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51084#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51259#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51254#L1372-3 assume !(0 == ~T7_E~0); 49315#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49316#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 49985#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 49986#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 50897#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51207#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50465#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 49621#L1412-3 assume !(0 == ~E_1~0); 49622#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50386#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50387#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51081#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50768#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50480#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50481#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49381#L1452-3 assume !(0 == ~E_9~0); 49382#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 51020#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51021#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 50825#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 50826#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 49619#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49620#L646-42 assume 1 == ~m_pc~0; 50205#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 51053#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51054#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51192#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51193#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50985#L665-42 assume 1 == ~t1_pc~0; 50946#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50948#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51134#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49788#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49789#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51258#L684-42 assume 1 == ~t2_pc~0; 50637#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50638#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51248#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50417#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50418#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50540#L703-42 assume 1 == ~t3_pc~0; 50738#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50739#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50057#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50058#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50832#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50452#L722-42 assume 1 == ~t4_pc~0; 50453#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50863#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50106#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49933#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49934#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51228#L741-42 assume 1 == ~t5_pc~0; 51170#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50315#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50316#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51261#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50223#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50224#L760-42 assume !(1 == ~t6_pc~0); 50358#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 50493#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50494#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50882#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 50175#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50176#L779-42 assume !(1 == ~t7_pc~0); 50952#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 50953#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49862#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49863#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49716#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49717#L798-42 assume 1 == ~t8_pc~0; 50167#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49328#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51071#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50517#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49547#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49548#L817-42 assume 1 == ~t9_pc~0; 50323#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49831#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49832#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49958#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50763#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50764#L836-42 assume 1 == ~t10_pc~0; 50856#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49869#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49870#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 51171#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51172#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51213#L855-42 assume 1 == ~t11_pc~0; 51226#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49420#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49421#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50170#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50933#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50034#L874-42 assume 1 == ~t12_pc~0; 50035#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50277#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49335#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49336#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49589#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49590#L893-42 assume 1 == ~t13_pc~0; 50793#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50574#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50589#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50491#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 49963#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 49964#L912-42 assume !(1 == ~t14_pc~0); 50773#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 49281#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 49282#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50862#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 49709#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49710#L1495-3 assume !(1 == ~M_E~0); 50325#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50753#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50846#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49939#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49902#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49903#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50560#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50783#L1530-3 assume !(1 == ~T8_E~0); 49748#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49749#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 49786#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 51043#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51152#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50192#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 50193#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50808#L1570-3 assume !(1 == ~E_2~0); 50759#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50760#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51115#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51160#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51205#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50582#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50583#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51058#L1610-3 assume !(1 == ~E_10~0); 49945#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49946#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50550#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50551#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 50455#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 49886#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 49491#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 50229#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 50785#L2036 assume !(0 == start_simulation_~tmp~3#1); 50786#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 50938#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 50098#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 51116#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 50498#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 50499#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51219#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 51220#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 50053#L2017-2 [2021-11-19 05:31:58,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:58,089 INFO L85 PathProgramCache]: Analyzing trace with hash 1016333162, now seen corresponding path program 1 times [2021-11-19 05:31:58,089 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:58,089 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [270023360] [2021-11-19 05:31:58,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:58,090 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:58,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:58,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:58,120 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:58,120 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [270023360] [2021-11-19 05:31:58,120 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [270023360] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:58,120 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:58,120 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:58,120 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [340560998] [2021-11-19 05:31:58,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:58,121 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:31:58,121 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:58,122 INFO L85 PathProgramCache]: Analyzing trace with hash 464353134, now seen corresponding path program 1 times [2021-11-19 05:31:58,122 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:58,122 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1923737265] [2021-11-19 05:31:58,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:58,122 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:58,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:58,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:58,164 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:58,164 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1923737265] [2021-11-19 05:31:58,164 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1923737265] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:58,164 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:58,164 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:58,165 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741525481] [2021-11-19 05:31:58,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:58,165 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:31:58,166 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:31:58,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:31:58,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:31:58,166 INFO L87 Difference]: Start difference. First operand 2047 states and 3023 transitions. cyclomatic complexity: 977 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:58,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:31:58,204 INFO L93 Difference]: Finished difference Result 2047 states and 3022 transitions. [2021-11-19 05:31:58,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:31:58,205 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3022 transitions. [2021-11-19 05:31:58,215 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:58,223 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3022 transitions. [2021-11-19 05:31:58,224 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-11-19 05:31:58,226 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-11-19 05:31:58,226 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3022 transitions. [2021-11-19 05:31:58,230 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:31:58,230 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3022 transitions. [2021-11-19 05:31:58,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3022 transitions. [2021-11-19 05:31:58,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-11-19 05:31:58,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4763067904250122) internal successors, (3022), 2046 states have internal predecessors, (3022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:58,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3022 transitions. [2021-11-19 05:31:58,275 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3022 transitions. [2021-11-19 05:31:58,276 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3022 transitions. [2021-11-19 05:31:58,276 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-19 05:31:58,276 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3022 transitions. [2021-11-19 05:31:58,285 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:58,285 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:58,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:58,289 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:58,289 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:58,290 INFO L791 eck$LassoCheckResult]: Stem: 54252#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 54253#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 54855#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53972#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53973#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 54218#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54219#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53946#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53947#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55170#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54522#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54523#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55040#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 54432#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54433#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53853#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53854#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54185#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 54383#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 53430#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53431#L1342 assume !(0 == ~M_E~0); 53596#L1342-2 assume !(0 == ~T1_E~0); 54152#L1347-1 assume !(0 == ~T2_E~0); 55153#L1352-1 assume !(0 == ~T3_E~0); 54949#L1357-1 assume !(0 == ~T4_E~0); 54177#L1362-1 assume !(0 == ~T5_E~0); 54178#L1367-1 assume !(0 == ~T6_E~0); 53775#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53776#L1377-1 assume !(0 == ~T8_E~0); 54106#L1382-1 assume !(0 == ~T9_E~0); 54107#L1387-1 assume !(0 == ~T10_E~0); 54834#L1392-1 assume !(0 == ~T11_E~0); 54138#L1397-1 assume !(0 == ~T12_E~0); 54139#L1402-1 assume !(0 == ~T13_E~0); 53791#L1407-1 assume !(0 == ~T14_E~0); 53792#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 55070#L1417-1 assume !(0 == ~E_2~0); 55071#L1422-1 assume !(0 == ~E_3~0); 55312#L1427-1 assume !(0 == ~E_4~0); 53979#L1432-1 assume !(0 == ~E_5~0); 53980#L1437-1 assume !(0 == ~E_6~0); 54988#L1442-1 assume !(0 == ~E_7~0); 54989#L1447-1 assume !(0 == ~E_8~0); 54831#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 53566#L1457-1 assume !(0 == ~E_10~0); 53567#L1462-1 assume !(0 == ~E_11~0); 55023#L1467-1 assume !(0 == ~E_12~0); 55035#L1472-1 assume !(0 == ~E_13~0); 55036#L1477-1 assume !(0 == ~E_14~0); 54778#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53765#L646 assume 1 == ~m_pc~0; 53766#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 54442#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54457#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53855#L1666 assume !(0 != activate_threads_~tmp~1#1); 53856#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55333#L665 assume !(1 == ~t1_pc~0); 54331#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54332#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53864#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53865#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 54655#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54656#L684 assume 1 == ~t2_pc~0; 54773#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54697#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54762#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55157#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 55158#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55346#L703 assume !(1 == ~t3_pc~0); 54001#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54002#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54648#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53400#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 53401#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53886#L722 assume 1 == ~t4_pc~0; 54624#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54067#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54412#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54972#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 54479#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53597#L741 assume 1 == ~t5_pc~0; 53598#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53908#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54062#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54063#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 54742#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54153#L760 assume !(1 == ~t6_pc~0); 54000#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 53999#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53857#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53858#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54579#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54580#L779 assume 1 == ~t7_pc~0; 53642#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53488#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53489#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53897#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 53920#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53921#L798 assume !(1 == ~t8_pc~0); 55202#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 55125#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53644#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53645#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 55335#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53465#L817 assume 1 == ~t9_pc~0; 53466#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54260#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54261#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54783#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 53871#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53872#L836 assume !(1 == ~t10_pc~0); 53888#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53819#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53820#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54068#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 54069#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55135#L855 assume 1 == ~t11_pc~0; 54453#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54454#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 55018#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54827#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 54662#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53761#L874 assume !(1 == ~t12_pc~0); 53762#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 53929#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53930#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54070#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 53438#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53439#L893 assume 1 == ~t13_pc~0; 55269#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53794#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54105#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 55196#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 55204#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 55205#L912 assume 1 == ~t14_pc~0; 54995#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 54996#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 53764#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 53696#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 53697#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54472#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 54888#L1495-2 assume !(1 == ~T1_E~0); 54889#L1500-1 assume !(1 == ~T2_E~0); 54575#L1505-1 assume !(1 == ~T3_E~0); 54576#L1510-1 assume !(1 == ~T4_E~0); 54633#L1515-1 assume !(1 == ~T5_E~0); 54634#L1520-1 assume !(1 == ~T6_E~0); 55203#L1525-1 assume !(1 == ~T7_E~0); 54913#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 53866#L1535-1 assume !(1 == ~T9_E~0); 53867#L1540-1 assume !(1 == ~T10_E~0); 53359#L1545-1 assume !(1 == ~T11_E~0); 53360#L1550-1 assume !(1 == ~T12_E~0); 53608#L1555-1 assume !(1 == ~T13_E~0); 53609#L1560-1 assume !(1 == ~T14_E~0); 53909#L1565-1 assume !(1 == ~E_1~0); 55322#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 54800#L1575-1 assume !(1 == ~E_3~0); 54179#L1580-1 assume !(1 == ~E_4~0); 54180#L1585-1 assume !(1 == ~E_5~0); 54650#L1590-1 assume !(1 == ~E_6~0); 54214#L1595-1 assume !(1 == ~E_7~0); 54215#L1600-1 assume !(1 == ~E_8~0); 54587#L1605-1 assume !(1 == ~E_9~0); 54588#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 55105#L1615-1 assume !(1 == ~E_11~0); 54044#L1620-1 assume !(1 == ~E_12~0); 54045#L1625-1 assume !(1 == ~E_13~0); 54832#L1630-1 assume !(1 == ~E_14~0); 54213#L1635-1 assume { :end_inline_reset_delta_events } true; 54154#L2017-2 [2021-11-19 05:31:58,290 INFO L793 eck$LassoCheckResult]: Loop: 54154#L2017-2 assume !false; 53434#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53435#L1316 assume !false; 54763#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 54825#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 53372#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 53514#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 53515#L1115 assume !(0 != eval_~tmp~0#1); 54848#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54269#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54270#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54452#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54953#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54622#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54623#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55185#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55360#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55355#L1372-3 assume !(0 == ~T7_E~0); 53416#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53417#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54086#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 54087#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 54998#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 55308#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 54566#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 53722#L1412-3 assume !(0 == ~E_1~0); 53723#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54487#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54488#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55182#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54869#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54581#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54582#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53482#L1452-3 assume !(0 == ~E_9~0); 53483#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 55121#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 55122#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 54926#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 54927#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 53720#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53721#L646-42 assume 1 == ~m_pc~0; 54306#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 55154#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55155#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55293#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55294#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55086#L665-42 assume 1 == ~t1_pc~0; 55047#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 55049#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55235#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53889#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53890#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55359#L684-42 assume 1 == ~t2_pc~0; 54738#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54739#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55349#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54518#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54519#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54641#L703-42 assume 1 == ~t3_pc~0; 54839#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54840#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54158#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54159#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54933#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54553#L722-42 assume 1 == ~t4_pc~0; 54554#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54964#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54207#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54034#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54035#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55329#L741-42 assume !(1 == ~t5_pc~0); 54946#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 54416#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54417#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55362#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54324#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54325#L760-42 assume !(1 == ~t6_pc~0); 54459#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 54594#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54595#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54983#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 54276#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54277#L779-42 assume 1 == ~t7_pc~0; 55106#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55054#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53963#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53964#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53817#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53818#L798-42 assume !(1 == ~t8_pc~0); 53428#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 53429#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55172#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54618#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53648#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53649#L817-42 assume 1 == ~t9_pc~0; 54424#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53932#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53933#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54059#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 54864#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54865#L836-42 assume 1 == ~t10_pc~0; 54957#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53970#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53971#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 55272#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 55273#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55314#L855-42 assume !(1 == ~t11_pc~0); 55328#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 53521#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53522#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54271#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 55034#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54135#L874-42 assume 1 == ~t12_pc~0; 54136#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 54378#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53436#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53437#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 53690#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53691#L893-42 assume !(1 == ~t13_pc~0); 54674#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 54675#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54690#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54592#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 54064#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 54065#L912-42 assume !(1 == ~t14_pc~0); 54874#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 53382#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 53383#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54963#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 53810#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53811#L1495-3 assume !(1 == ~M_E~0); 54426#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54854#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54947#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54040#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54003#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54004#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54661#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54884#L1530-3 assume !(1 == ~T8_E~0); 53849#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 53850#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53887#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 55144#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 55253#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 54293#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 54294#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54909#L1570-3 assume !(1 == ~E_2~0); 54860#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54861#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55216#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 55261#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 55306#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 54683#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 54684#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 55159#L1610-3 assume !(1 == ~E_10~0); 54046#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 54047#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 54651#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 54652#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 54556#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 53987#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 53592#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 54330#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 54886#L2036 assume !(0 == start_simulation_~tmp~3#1); 54887#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 55039#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 54199#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 55217#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 54599#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 54600#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55320#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 55321#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 54154#L2017-2 [2021-11-19 05:31:58,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:58,291 INFO L85 PathProgramCache]: Analyzing trace with hash -1873442456, now seen corresponding path program 1 times [2021-11-19 05:31:58,291 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:58,292 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [601129168] [2021-11-19 05:31:58,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:58,292 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:58,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:58,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:58,324 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:58,324 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [601129168] [2021-11-19 05:31:58,324 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [601129168] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:58,324 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:58,325 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:58,325 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1211209896] [2021-11-19 05:31:58,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:58,325 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:31:58,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:58,326 INFO L85 PathProgramCache]: Analyzing trace with hash 1401714763, now seen corresponding path program 1 times [2021-11-19 05:31:58,326 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:58,326 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [472167625] [2021-11-19 05:31:58,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:58,327 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:58,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:58,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:58,410 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:58,411 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [472167625] [2021-11-19 05:31:58,411 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [472167625] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:58,411 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:58,411 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:58,412 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1663351598] [2021-11-19 05:31:58,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:58,412 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:31:58,413 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:31:58,413 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:31:58,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:31:58,414 INFO L87 Difference]: Start difference. First operand 2047 states and 3022 transitions. cyclomatic complexity: 976 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:58,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:31:58,457 INFO L93 Difference]: Finished difference Result 2047 states and 3021 transitions. [2021-11-19 05:31:58,458 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:31:58,458 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3021 transitions. [2021-11-19 05:31:58,469 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:58,477 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3021 transitions. [2021-11-19 05:31:58,478 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-11-19 05:31:58,480 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-11-19 05:31:58,480 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3021 transitions. [2021-11-19 05:31:58,484 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:31:58,484 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3021 transitions. [2021-11-19 05:31:58,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3021 transitions. [2021-11-19 05:31:58,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-11-19 05:31:58,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.475818270639961) internal successors, (3021), 2046 states have internal predecessors, (3021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:58,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3021 transitions. [2021-11-19 05:31:58,532 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3021 transitions. [2021-11-19 05:31:58,533 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3021 transitions. [2021-11-19 05:31:58,533 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-19 05:31:58,533 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3021 transitions. [2021-11-19 05:31:58,542 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:58,542 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:58,542 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:58,546 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:58,546 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:58,547 INFO L791 eck$LassoCheckResult]: Stem: 58353#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 58354#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 58956#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 58073#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 58074#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 58319#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58320#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58047#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58048#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59271#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 58623#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 58624#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59141#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 58533#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 58534#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 57954#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 57955#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 58286#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 58484#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 57531#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 57532#L1342 assume !(0 == ~M_E~0); 57697#L1342-2 assume !(0 == ~T1_E~0); 58253#L1347-1 assume !(0 == ~T2_E~0); 59254#L1352-1 assume !(0 == ~T3_E~0); 59050#L1357-1 assume !(0 == ~T4_E~0); 58278#L1362-1 assume !(0 == ~T5_E~0); 58279#L1367-1 assume !(0 == ~T6_E~0); 57876#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 57877#L1377-1 assume !(0 == ~T8_E~0); 58207#L1382-1 assume !(0 == ~T9_E~0); 58208#L1387-1 assume !(0 == ~T10_E~0); 58935#L1392-1 assume !(0 == ~T11_E~0); 58239#L1397-1 assume !(0 == ~T12_E~0); 58240#L1402-1 assume !(0 == ~T13_E~0); 57892#L1407-1 assume !(0 == ~T14_E~0); 57893#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 59171#L1417-1 assume !(0 == ~E_2~0); 59172#L1422-1 assume !(0 == ~E_3~0); 59413#L1427-1 assume !(0 == ~E_4~0); 58080#L1432-1 assume !(0 == ~E_5~0); 58081#L1437-1 assume !(0 == ~E_6~0); 59089#L1442-1 assume !(0 == ~E_7~0); 59090#L1447-1 assume !(0 == ~E_8~0); 58932#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 57667#L1457-1 assume !(0 == ~E_10~0); 57668#L1462-1 assume !(0 == ~E_11~0); 59124#L1467-1 assume !(0 == ~E_12~0); 59136#L1472-1 assume !(0 == ~E_13~0); 59137#L1477-1 assume !(0 == ~E_14~0); 58879#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57868#L646 assume 1 == ~m_pc~0; 57869#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 58543#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58558#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 57956#L1666 assume !(0 != activate_threads_~tmp~1#1); 57957#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59434#L665 assume !(1 == ~t1_pc~0); 58432#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 58433#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57965#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57966#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 58756#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58757#L684 assume 1 == ~t2_pc~0; 58874#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58798#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58863#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59258#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 59259#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59447#L703 assume !(1 == ~t3_pc~0); 58102#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 58103#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58749#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57501#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 57502#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57987#L722 assume 1 == ~t4_pc~0; 58725#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 58168#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58513#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59073#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 58580#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57698#L741 assume 1 == ~t5_pc~0; 57699#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58009#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58163#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58164#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 58843#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58254#L760 assume !(1 == ~t6_pc~0); 58101#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 58100#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57958#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 57959#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58680#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58681#L779 assume 1 == ~t7_pc~0; 57743#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 57589#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57590#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 57998#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 58021#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58022#L798 assume !(1 == ~t8_pc~0); 59303#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 59226#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57745#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 57746#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 59436#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57566#L817 assume 1 == ~t9_pc~0; 57567#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58361#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58362#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58884#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 57972#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57973#L836 assume !(1 == ~t10_pc~0); 57989#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 57920#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57921#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58169#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 58170#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59236#L855 assume 1 == ~t11_pc~0; 58554#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 58555#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59119#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58928#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 58763#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 57862#L874 assume !(1 == ~t12_pc~0); 57863#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 58030#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58031#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58171#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 57539#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 57540#L893 assume 1 == ~t13_pc~0; 59370#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 57895#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58206#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 59297#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 59305#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 59306#L912 assume 1 == ~t14_pc~0; 59096#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 59097#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 57865#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 57797#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 57798#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58573#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 58989#L1495-2 assume !(1 == ~T1_E~0); 58990#L1500-1 assume !(1 == ~T2_E~0); 58676#L1505-1 assume !(1 == ~T3_E~0); 58677#L1510-1 assume !(1 == ~T4_E~0); 58734#L1515-1 assume !(1 == ~T5_E~0); 58735#L1520-1 assume !(1 == ~T6_E~0); 59304#L1525-1 assume !(1 == ~T7_E~0); 59014#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 57967#L1535-1 assume !(1 == ~T9_E~0); 57968#L1540-1 assume !(1 == ~T10_E~0); 57460#L1545-1 assume !(1 == ~T11_E~0); 57461#L1550-1 assume !(1 == ~T12_E~0); 57709#L1555-1 assume !(1 == ~T13_E~0); 57710#L1560-1 assume !(1 == ~T14_E~0); 58010#L1565-1 assume !(1 == ~E_1~0); 59423#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 58901#L1575-1 assume !(1 == ~E_3~0); 58280#L1580-1 assume !(1 == ~E_4~0); 58281#L1585-1 assume !(1 == ~E_5~0); 58751#L1590-1 assume !(1 == ~E_6~0); 58315#L1595-1 assume !(1 == ~E_7~0); 58316#L1600-1 assume !(1 == ~E_8~0); 58688#L1605-1 assume !(1 == ~E_9~0); 58689#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 59206#L1615-1 assume !(1 == ~E_11~0); 58145#L1620-1 assume !(1 == ~E_12~0); 58146#L1625-1 assume !(1 == ~E_13~0); 58933#L1630-1 assume !(1 == ~E_14~0); 58314#L1635-1 assume { :end_inline_reset_delta_events } true; 58255#L2017-2 [2021-11-19 05:31:58,547 INFO L793 eck$LassoCheckResult]: Loop: 58255#L2017-2 assume !false; 57535#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57536#L1316 assume !false; 58864#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 58926#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 57473#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 57615#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 57616#L1115 assume !(0 != eval_~tmp~0#1); 58949#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58370#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58371#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 58553#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 59054#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 58723#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 58724#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 59286#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59461#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 59456#L1372-3 assume !(0 == ~T7_E~0); 57517#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57518#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 58187#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 58188#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 59099#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 59409#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 58667#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 57823#L1412-3 assume !(0 == ~E_1~0); 57824#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 58588#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 58589#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 59283#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 58970#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 58682#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 58683#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 57583#L1452-3 assume !(0 == ~E_9~0); 57584#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 59222#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 59223#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 59027#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 59028#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 57821#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57822#L646-42 assume 1 == ~m_pc~0; 58407#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 59255#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59256#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59394#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59395#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59187#L665-42 assume 1 == ~t1_pc~0; 59148#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59150#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59336#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57990#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57991#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59460#L684-42 assume 1 == ~t2_pc~0; 58839#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58840#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59450#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58619#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58620#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58742#L703-42 assume 1 == ~t3_pc~0; 58940#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58941#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58259#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58260#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59034#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58654#L722-42 assume !(1 == ~t4_pc~0); 58656#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 59065#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58308#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58135#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58136#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59430#L741-42 assume !(1 == ~t5_pc~0); 59047#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 58517#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58518#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59463#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 58425#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58426#L760-42 assume !(1 == ~t6_pc~0); 58560#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 58695#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58696#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59084#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 58377#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58378#L779-42 assume !(1 == ~t7_pc~0); 59154#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 59155#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58064#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58065#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 57918#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57919#L798-42 assume 1 == ~t8_pc~0; 58369#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 57530#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59273#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58719#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 57749#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57750#L817-42 assume 1 == ~t9_pc~0; 58525#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58033#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58034#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58160#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 58965#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58966#L836-42 assume 1 == ~t10_pc~0; 59058#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 58071#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58072#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59373#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59374#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59415#L855-42 assume 1 == ~t11_pc~0; 59428#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 57622#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 57623#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58372#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 59135#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58236#L874-42 assume 1 == ~t12_pc~0; 58237#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58479#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 57537#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 57538#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 57791#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 57792#L893-42 assume 1 == ~t13_pc~0; 58995#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 58776#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58791#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 58693#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 58165#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 58166#L912-42 assume 1 == ~t14_pc~0; 59410#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 57483#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 57484#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 59064#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 57911#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57912#L1495-3 assume !(1 == ~M_E~0); 58527#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 58955#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59048#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58141#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58104#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58105#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 58762#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 58985#L1530-3 assume !(1 == ~T8_E~0); 57950#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 57951#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 57988#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59245#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 59354#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 58394#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 58395#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 59010#L1570-3 assume !(1 == ~E_2~0); 58961#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 58962#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59317#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 59362#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 59407#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 58784#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 58785#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 59260#L1610-3 assume !(1 == ~E_10~0); 58147#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 58148#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 58752#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 58753#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 58657#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 58088#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 57693#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 58431#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 58987#L2036 assume !(0 == start_simulation_~tmp~3#1); 58988#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 59140#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 58300#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 59318#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 58700#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 58701#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 59421#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 59422#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 58255#L2017-2 [2021-11-19 05:31:58,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:58,548 INFO L85 PathProgramCache]: Analyzing trace with hash 527190954, now seen corresponding path program 1 times [2021-11-19 05:31:58,549 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:58,549 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760741291] [2021-11-19 05:31:58,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:58,549 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:58,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:58,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:58,593 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:58,593 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [760741291] [2021-11-19 05:31:58,593 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [760741291] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:58,594 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:58,594 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-19 05:31:58,594 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [976252506] [2021-11-19 05:31:58,594 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:58,595 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:31:58,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:58,595 INFO L85 PathProgramCache]: Analyzing trace with hash 1014754381, now seen corresponding path program 1 times [2021-11-19 05:31:58,596 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:58,596 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [492272804] [2021-11-19 05:31:58,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:58,596 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:58,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:58,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:58,645 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:58,645 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [492272804] [2021-11-19 05:31:58,646 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [492272804] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:58,646 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:58,646 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:58,646 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1764093530] [2021-11-19 05:31:58,647 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:58,647 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:31:58,647 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:31:58,648 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:31:58,648 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:31:58,648 INFO L87 Difference]: Start difference. First operand 2047 states and 3021 transitions. cyclomatic complexity: 975 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:58,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:31:58,694 INFO L93 Difference]: Finished difference Result 2047 states and 3016 transitions. [2021-11-19 05:31:58,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:31:58,695 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3016 transitions. [2021-11-19 05:31:58,705 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:58,713 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3016 transitions. [2021-11-19 05:31:58,713 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-11-19 05:31:58,716 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-11-19 05:31:58,716 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3016 transitions. [2021-11-19 05:31:58,720 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:31:58,720 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3016 transitions. [2021-11-19 05:31:58,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3016 transitions. [2021-11-19 05:31:58,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-11-19 05:31:58,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4733756717147044) internal successors, (3016), 2046 states have internal predecessors, (3016), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:58,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3016 transitions. [2021-11-19 05:31:58,768 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3016 transitions. [2021-11-19 05:31:58,768 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3016 transitions. [2021-11-19 05:31:58,768 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-19 05:31:58,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3016 transitions. [2021-11-19 05:31:58,776 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-11-19 05:31:58,776 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:58,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:58,780 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:58,780 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:58,780 INFO L791 eck$LassoCheckResult]: Stem: 62454#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 62455#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 63057#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62174#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62175#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 62420#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 62421#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62148#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62149#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63372#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62724#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 62725#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63242#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 62634#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 62635#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 62055#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 62056#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 62387#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 62585#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 61632#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61633#L1342 assume !(0 == ~M_E~0); 61798#L1342-2 assume !(0 == ~T1_E~0); 62354#L1347-1 assume !(0 == ~T2_E~0); 63355#L1352-1 assume !(0 == ~T3_E~0); 63151#L1357-1 assume !(0 == ~T4_E~0); 62379#L1362-1 assume !(0 == ~T5_E~0); 62380#L1367-1 assume !(0 == ~T6_E~0); 61977#L1372-1 assume !(0 == ~T7_E~0); 61978#L1377-1 assume !(0 == ~T8_E~0); 62308#L1382-1 assume !(0 == ~T9_E~0); 62309#L1387-1 assume !(0 == ~T10_E~0); 63036#L1392-1 assume !(0 == ~T11_E~0); 62340#L1397-1 assume !(0 == ~T12_E~0); 62341#L1402-1 assume !(0 == ~T13_E~0); 61993#L1407-1 assume !(0 == ~T14_E~0); 61994#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 63272#L1417-1 assume !(0 == ~E_2~0); 63273#L1422-1 assume !(0 == ~E_3~0); 63514#L1427-1 assume !(0 == ~E_4~0); 62181#L1432-1 assume !(0 == ~E_5~0); 62182#L1437-1 assume !(0 == ~E_6~0); 63190#L1442-1 assume !(0 == ~E_7~0); 63191#L1447-1 assume !(0 == ~E_8~0); 63033#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 61768#L1457-1 assume !(0 == ~E_10~0); 61769#L1462-1 assume !(0 == ~E_11~0); 63225#L1467-1 assume !(0 == ~E_12~0); 63237#L1472-1 assume !(0 == ~E_13~0); 63238#L1477-1 assume !(0 == ~E_14~0); 62980#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61969#L646 assume 1 == ~m_pc~0; 61970#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 62644#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62659#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62057#L1666 assume !(0 != activate_threads_~tmp~1#1); 62058#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63535#L665 assume !(1 == ~t1_pc~0); 62533#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 62534#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62066#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62067#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 62857#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62858#L684 assume 1 == ~t2_pc~0; 62975#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62899#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62964#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63359#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 63360#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63548#L703 assume !(1 == ~t3_pc~0); 62203#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62204#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62850#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61602#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 61603#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62088#L722 assume 1 == ~t4_pc~0; 62826#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 62269#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62614#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 63174#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 62681#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61799#L741 assume 1 == ~t5_pc~0; 61800#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 62110#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62264#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62265#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 62944#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62355#L760 assume !(1 == ~t6_pc~0); 62202#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 62201#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62059#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62060#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62781#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62782#L779 assume 1 == ~t7_pc~0; 61844#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 61690#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 61691#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62099#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 62122#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62123#L798 assume !(1 == ~t8_pc~0); 63404#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 63327#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61846#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 61847#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 63537#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61667#L817 assume 1 == ~t9_pc~0; 61668#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62462#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62463#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62985#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 62073#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62074#L836 assume !(1 == ~t10_pc~0); 62090#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 62021#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62022#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62270#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 62271#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 63337#L855 assume 1 == ~t11_pc~0; 62655#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 62656#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 63220#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 63029#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 62864#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 61963#L874 assume !(1 == ~t12_pc~0); 61964#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 62131#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 62132#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 62272#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 61640#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 61641#L893 assume 1 == ~t13_pc~0; 63471#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 61996#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 62307#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 63398#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 63406#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 63407#L912 assume 1 == ~t14_pc~0; 63197#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 63198#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 61966#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 61898#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 61899#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62674#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 63090#L1495-2 assume !(1 == ~T1_E~0); 63091#L1500-1 assume !(1 == ~T2_E~0); 62777#L1505-1 assume !(1 == ~T3_E~0); 62778#L1510-1 assume !(1 == ~T4_E~0); 62835#L1515-1 assume !(1 == ~T5_E~0); 62836#L1520-1 assume !(1 == ~T6_E~0); 63405#L1525-1 assume !(1 == ~T7_E~0); 63115#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 62068#L1535-1 assume !(1 == ~T9_E~0); 62069#L1540-1 assume !(1 == ~T10_E~0); 61561#L1545-1 assume !(1 == ~T11_E~0); 61562#L1550-1 assume !(1 == ~T12_E~0); 61810#L1555-1 assume !(1 == ~T13_E~0); 61811#L1560-1 assume !(1 == ~T14_E~0); 62111#L1565-1 assume !(1 == ~E_1~0); 63524#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 63002#L1575-1 assume !(1 == ~E_3~0); 62381#L1580-1 assume !(1 == ~E_4~0); 62382#L1585-1 assume !(1 == ~E_5~0); 62852#L1590-1 assume !(1 == ~E_6~0); 62416#L1595-1 assume !(1 == ~E_7~0); 62417#L1600-1 assume !(1 == ~E_8~0); 62789#L1605-1 assume !(1 == ~E_9~0); 62790#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 63307#L1615-1 assume !(1 == ~E_11~0); 62246#L1620-1 assume !(1 == ~E_12~0); 62247#L1625-1 assume !(1 == ~E_13~0); 63034#L1630-1 assume !(1 == ~E_14~0); 62415#L1635-1 assume { :end_inline_reset_delta_events } true; 62356#L2017-2 [2021-11-19 05:31:58,781 INFO L793 eck$LassoCheckResult]: Loop: 62356#L2017-2 assume !false; 61636#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 61637#L1316 assume !false; 62965#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 63027#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 61574#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 61716#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 61717#L1115 assume !(0 != eval_~tmp~0#1); 63050#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 62471#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 62472#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 62654#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 63155#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 62824#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62825#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 63387#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 63562#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 63557#L1372-3 assume !(0 == ~T7_E~0); 61618#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 61619#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 62288#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 62289#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 63200#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 63510#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 62768#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 61924#L1412-3 assume !(0 == ~E_1~0); 61925#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62689#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62690#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 63384#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 63071#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 62783#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62784#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 61684#L1452-3 assume !(0 == ~E_9~0); 61685#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 63323#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 63324#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 63128#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 63129#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 61922#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61923#L646-42 assume 1 == ~m_pc~0; 62508#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 63356#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63357#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63495#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 63496#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63288#L665-42 assume 1 == ~t1_pc~0; 63249#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 63251#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63437#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62091#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62092#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63561#L684-42 assume 1 == ~t2_pc~0; 62940#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62941#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63551#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62720#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62721#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62843#L703-42 assume 1 == ~t3_pc~0; 63041#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 63042#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62360#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62361#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 63135#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62755#L722-42 assume 1 == ~t4_pc~0; 62756#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 63166#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62409#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62236#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62237#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63531#L741-42 assume 1 == ~t5_pc~0; 63473#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 62618#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62619#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63564#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62526#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62527#L760-42 assume !(1 == ~t6_pc~0); 62661#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 62796#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62797#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 63185#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 62478#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62479#L779-42 assume !(1 == ~t7_pc~0); 63255#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 63256#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62165#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62166#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 62019#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62020#L798-42 assume 1 == ~t8_pc~0; 62470#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 61631#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63374#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62820#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 61850#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61851#L817-42 assume 1 == ~t9_pc~0; 62626#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62134#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62135#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62261#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 63066#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 63067#L836-42 assume 1 == ~t10_pc~0; 63159#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 62172#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62173#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 63474#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 63475#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 63516#L855-42 assume 1 == ~t11_pc~0; 63529#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 61723#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61724#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 62473#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 63236#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62337#L874-42 assume 1 == ~t12_pc~0; 62338#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 62580#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61638#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 61639#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 61892#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 61893#L893-42 assume 1 == ~t13_pc~0; 63096#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 62877#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 62892#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 62794#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 62266#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 62267#L912-42 assume !(1 == ~t14_pc~0); 63076#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 61584#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 61585#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 63165#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 62012#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62013#L1495-3 assume !(1 == ~M_E~0); 62628#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 63056#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63149#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62242#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62205#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 62206#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 62863#L1525-3 assume !(1 == ~T7_E~0); 63086#L1530-3 assume !(1 == ~T8_E~0); 62051#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62052#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 62089#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 63346#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 63455#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 62495#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 62496#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 63111#L1570-3 assume !(1 == ~E_2~0); 63062#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 63063#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 63418#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63463#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 63508#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 62885#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 62886#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 63361#L1610-3 assume !(1 == ~E_10~0); 62248#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 62249#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 62853#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 62854#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 62758#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 62189#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 61794#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 62532#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 63088#L2036 assume !(0 == start_simulation_~tmp~3#1); 63089#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 63241#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 62401#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 63419#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 62801#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 62802#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63522#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 63523#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 62356#L2017-2 [2021-11-19 05:31:58,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:58,782 INFO L85 PathProgramCache]: Analyzing trace with hash 953745452, now seen corresponding path program 1 times [2021-11-19 05:31:58,782 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:58,782 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2058248470] [2021-11-19 05:31:58,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:58,783 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:58,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:58,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:58,830 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:58,830 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2058248470] [2021-11-19 05:31:58,830 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2058248470] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:58,831 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:58,831 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:58,831 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1918313391] [2021-11-19 05:31:58,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:58,832 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:31:58,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:58,832 INFO L85 PathProgramCache]: Analyzing trace with hash -379652368, now seen corresponding path program 1 times [2021-11-19 05:31:58,833 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:58,833 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1257464513] [2021-11-19 05:31:58,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:58,833 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:58,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:58,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:58,882 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:58,883 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1257464513] [2021-11-19 05:31:58,883 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1257464513] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:58,883 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:58,883 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:58,883 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [560741237] [2021-11-19 05:31:58,883 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:58,884 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:31:58,884 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:31:58,885 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-19 05:31:58,885 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-19 05:31:58,885 INFO L87 Difference]: Start difference. First operand 2047 states and 3016 transitions. cyclomatic complexity: 970 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:59,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:31:59,158 INFO L93 Difference]: Finished difference Result 3831 states and 5642 transitions. [2021-11-19 05:31:59,158 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-19 05:31:59,159 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3831 states and 5642 transitions. [2021-11-19 05:31:59,176 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3616 [2021-11-19 05:31:59,189 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3831 states to 3831 states and 5642 transitions. [2021-11-19 05:31:59,190 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3831 [2021-11-19 05:31:59,194 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3831 [2021-11-19 05:31:59,194 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3831 states and 5642 transitions. [2021-11-19 05:31:59,198 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:31:59,199 INFO L681 BuchiCegarLoop]: Abstraction has 3831 states and 5642 transitions. [2021-11-19 05:31:59,203 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3831 states and 5642 transitions. [2021-11-19 05:31:59,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3831 to 3829. [2021-11-19 05:31:59,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3829 states, 3829 states have (on average 1.4729694437189866) internal successors, (5640), 3828 states have internal predecessors, (5640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:59,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3829 states to 3829 states and 5640 transitions. [2021-11-19 05:31:59,273 INFO L704 BuchiCegarLoop]: Abstraction has 3829 states and 5640 transitions. [2021-11-19 05:31:59,273 INFO L587 BuchiCegarLoop]: Abstraction has 3829 states and 5640 transitions. [2021-11-19 05:31:59,273 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-19 05:31:59,274 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3829 states and 5640 transitions. [2021-11-19 05:31:59,287 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3616 [2021-11-19 05:31:59,288 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:59,288 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:59,291 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:59,292 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:59,292 INFO L791 eck$LassoCheckResult]: Stem: 68346#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 68347#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 68964#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68065#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68066#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 68312#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68313#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68038#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68039#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69308#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68620#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68621#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 69161#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68526#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 68527#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 67945#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 67946#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 68278#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 68477#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 67520#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67521#L1342 assume !(0 == ~M_E~0); 67686#L1342-2 assume !(0 == ~T1_E~0); 68245#L1347-1 assume !(0 == ~T2_E~0); 69286#L1352-1 assume !(0 == ~T3_E~0); 69063#L1357-1 assume !(0 == ~T4_E~0); 68270#L1362-1 assume !(0 == ~T5_E~0); 68271#L1367-1 assume !(0 == ~T6_E~0); 67866#L1372-1 assume !(0 == ~T7_E~0); 67867#L1377-1 assume !(0 == ~T8_E~0); 68199#L1382-1 assume !(0 == ~T9_E~0); 68200#L1387-1 assume !(0 == ~T10_E~0); 68944#L1392-1 assume !(0 == ~T11_E~0); 68233#L1397-1 assume !(0 == ~T12_E~0); 68234#L1402-1 assume !(0 == ~T13_E~0); 67881#L1407-1 assume !(0 == ~T14_E~0); 67882#L1412-1 assume !(0 == ~E_1~0); 69195#L1417-1 assume !(0 == ~E_2~0); 69196#L1422-1 assume !(0 == ~E_3~0); 69492#L1427-1 assume !(0 == ~E_4~0); 68071#L1432-1 assume !(0 == ~E_5~0); 68072#L1437-1 assume !(0 == ~E_6~0); 69105#L1442-1 assume !(0 == ~E_7~0); 69106#L1447-1 assume !(0 == ~E_8~0); 68939#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 67656#L1457-1 assume !(0 == ~E_10~0); 67657#L1462-1 assume !(0 == ~E_11~0); 69143#L1467-1 assume !(0 == ~E_12~0); 69156#L1472-1 assume !(0 == ~E_13~0); 69157#L1477-1 assume !(0 == ~E_14~0); 68883#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67857#L646 assume 1 == ~m_pc~0; 67858#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 68536#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68552#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67947#L1666 assume !(0 != activate_threads_~tmp~1#1); 67948#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69523#L665 assume !(1 == ~t1_pc~0); 68425#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68426#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67954#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 67955#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 68756#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68757#L684 assume 1 == ~t2_pc~0; 68880#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 68800#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68867#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69292#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 69293#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69545#L703 assume !(1 == ~t3_pc~0); 68093#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 68094#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68749#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 67490#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 67491#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67976#L722 assume 1 == ~t4_pc~0; 68725#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68159#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68506#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69088#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 68576#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67687#L741 assume 1 == ~t5_pc~0; 67688#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 67998#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68156#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68157#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 68846#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68246#L760 assume !(1 == ~t6_pc~0); 68092#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 68091#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 67949#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 67950#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 68679#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68680#L779 assume 1 == ~t7_pc~0; 67732#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 67578#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 67579#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 67987#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 68010#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68011#L798 assume !(1 == ~t8_pc~0); 69342#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 69254#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 67734#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 67735#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 69525#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 67555#L817 assume 1 == ~t9_pc~0; 67556#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 68354#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 68355#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 68889#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 67961#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 67962#L836 assume !(1 == ~t10_pc~0); 67978#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 67909#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 67910#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 68160#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 68161#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69268#L855 assume 1 == ~t11_pc~0; 68547#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68548#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 69137#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68935#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 68763#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 67851#L874 assume !(1 == ~t12_pc~0); 67852#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 68021#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68022#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 68162#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 67530#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 67531#L893 assume 1 == ~t13_pc~0; 69438#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 67884#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 68198#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 69336#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 69344#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 69345#L912 assume 1 == ~t14_pc~0; 69112#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 69113#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 67854#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 67786#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 67787#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68570#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 68997#L1495-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68998#L1500-1 assume !(1 == ~T2_E~0); 70368#L1505-1 assume !(1 == ~T3_E~0); 70366#L1510-1 assume !(1 == ~T4_E~0); 70364#L1515-1 assume !(1 == ~T5_E~0); 69513#L1520-1 assume !(1 == ~T6_E~0); 69514#L1525-1 assume !(1 == ~T7_E~0); 70229#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 70226#L1535-1 assume !(1 == ~T9_E~0); 70224#L1540-1 assume !(1 == ~T10_E~0); 70222#L1545-1 assume !(1 == ~T11_E~0); 70220#L1550-1 assume !(1 == ~T12_E~0); 70218#L1555-1 assume !(1 == ~T13_E~0); 69883#L1560-1 assume !(1 == ~T14_E~0); 69882#L1565-1 assume !(1 == ~E_1~0); 69503#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 69878#L1575-1 assume !(1 == ~E_3~0); 69876#L1580-1 assume !(1 == ~E_4~0); 69874#L1585-1 assume !(1 == ~E_5~0); 69675#L1590-1 assume !(1 == ~E_6~0); 69673#L1595-1 assume !(1 == ~E_7~0); 69646#L1600-1 assume !(1 == ~E_8~0); 69645#L1605-1 assume !(1 == ~E_9~0); 69644#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 69236#L1615-1 assume !(1 == ~E_11~0); 68136#L1620-1 assume !(1 == ~E_12~0); 68137#L1625-1 assume !(1 == ~E_13~0); 68940#L1630-1 assume !(1 == ~E_14~0); 68307#L1635-1 assume { :end_inline_reset_delta_events } true; 68247#L2017-2 [2021-11-19 05:31:59,293 INFO L793 eck$LassoCheckResult]: Loop: 68247#L2017-2 assume !false; 67524#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 67525#L1316 assume !false; 68868#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 68933#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 67462#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 67606#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 67607#L1115 assume !(0 != eval_~tmp~0#1); 68956#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 69591#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 69590#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 69588#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69589#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70776#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70775#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 70774#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 70773#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 70772#L1372-3 assume !(0 == ~T7_E~0); 70771#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 70769#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 70766#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 70764#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 70762#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 70760#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 70758#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 70757#L1412-3 assume !(0 == ~E_1~0); 70756#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 70755#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 70754#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 70753#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 70752#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 70751#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 70750#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 70749#L1452-3 assume !(0 == ~E_9~0); 70748#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 70747#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 70746#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 70745#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 70744#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 70743#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70742#L646-42 assume !(1 == ~m_pc~0); 70741#L646-44 is_master_triggered_~__retres1~0#1 := 0; 70739#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70738#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 70737#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 70736#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70735#L665-42 assume !(1 == ~t1_pc~0); 70733#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 70732#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70731#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 70730#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70729#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70728#L684-42 assume !(1 == ~t2_pc~0); 70727#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 70725#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70724#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70723#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 70722#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70721#L703-42 assume 1 == ~t3_pc~0; 70720#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 70718#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70717#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 70716#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 70715#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70714#L722-42 assume !(1 == ~t4_pc~0); 70713#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 70711#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70709#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 70706#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70704#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70702#L741-42 assume !(1 == ~t5_pc~0); 70699#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 70697#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70695#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 70692#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 70690#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70688#L760-42 assume 1 == ~t6_pc~0; 70685#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 70683#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70682#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 70679#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 70677#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 70675#L779-42 assume !(1 == ~t7_pc~0); 70673#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 70671#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 70669#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 70667#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 70664#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70662#L798-42 assume !(1 == ~t8_pc~0); 70659#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 70657#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 70655#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 70653#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 70650#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 70648#L817-42 assume !(1 == ~t9_pc~0); 70643#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 70639#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 70637#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 70635#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 70633#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69416#L836-42 assume 1 == ~t10_pc~0; 69069#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 68062#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 68063#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69441#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69442#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69494#L855-42 assume 1 == ~t11_pc~0; 69511#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 67611#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 67612#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68363#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 69155#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 68228#L874-42 assume 1 == ~t12_pc~0; 68229#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 68469#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 70547#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 70544#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 70542#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 70540#L893-42 assume 1 == ~t13_pc~0; 70537#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 70535#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 70533#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 70532#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 70531#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 70530#L912-42 assume 1 == ~t14_pc~0; 69489#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 67470#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 67471#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 69079#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 70521#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70520#L1495-3 assume !(1 == ~M_E~0); 70479#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68962#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 70478#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70477#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 70476#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 70475#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70474#L1525-3 assume !(1 == ~T7_E~0); 69454#L1530-3 assume !(1 == ~T8_E~0); 67939#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 67940#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 67977#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69277#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 69428#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 70459#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 70454#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 69019#L1570-3 assume !(1 == ~E_2~0); 70147#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 70146#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69423#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69424#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 69486#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 68785#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 68786#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 69346#L1610-3 assume !(1 == ~E_10~0); 68138#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 68139#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 68752#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 68753#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 69586#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 69704#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 69689#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 69685#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 69682#L2036 assume !(0 == start_simulation_~tmp~3#1); 69680#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 69653#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 69651#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 69649#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 69643#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 69517#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69501#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 69502#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 68247#L2017-2 [2021-11-19 05:31:59,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:59,294 INFO L85 PathProgramCache]: Analyzing trace with hash 966495660, now seen corresponding path program 1 times [2021-11-19 05:31:59,294 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:59,294 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1356188803] [2021-11-19 05:31:59,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:59,294 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:59,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:59,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:59,369 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:59,369 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1356188803] [2021-11-19 05:31:59,369 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1356188803] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:59,369 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:59,370 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:59,370 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [880239843] [2021-11-19 05:31:59,370 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:59,370 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:31:59,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:59,371 INFO L85 PathProgramCache]: Analyzing trace with hash 1197395403, now seen corresponding path program 1 times [2021-11-19 05:31:59,371 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:59,371 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2138230143] [2021-11-19 05:31:59,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:59,372 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:59,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:59,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:59,417 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:59,417 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2138230143] [2021-11-19 05:31:59,418 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2138230143] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:59,418 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:59,418 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:59,418 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [582478541] [2021-11-19 05:31:59,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:59,419 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:31:59,419 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:31:59,419 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-19 05:31:59,419 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-19 05:31:59,420 INFO L87 Difference]: Start difference. First operand 3829 states and 5640 transitions. cyclomatic complexity: 1813 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:59,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:31:59,669 INFO L93 Difference]: Finished difference Result 7253 states and 10670 transitions. [2021-11-19 05:31:59,669 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-19 05:31:59,670 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7253 states and 10670 transitions. [2021-11-19 05:31:59,703 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7018 [2021-11-19 05:31:59,730 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7253 states to 7253 states and 10670 transitions. [2021-11-19 05:31:59,730 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7253 [2021-11-19 05:31:59,738 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7253 [2021-11-19 05:31:59,738 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7253 states and 10670 transitions. [2021-11-19 05:31:59,746 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:31:59,746 INFO L681 BuchiCegarLoop]: Abstraction has 7253 states and 10670 transitions. [2021-11-19 05:31:59,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7253 states and 10670 transitions. [2021-11-19 05:31:59,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7253 to 7251. [2021-11-19 05:31:59,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7251 states, 7251 states have (on average 1.4712453454695904) internal successors, (10668), 7250 states have internal predecessors, (10668), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:31:59,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7251 states to 7251 states and 10668 transitions. [2021-11-19 05:31:59,875 INFO L704 BuchiCegarLoop]: Abstraction has 7251 states and 10668 transitions. [2021-11-19 05:31:59,875 INFO L587 BuchiCegarLoop]: Abstraction has 7251 states and 10668 transitions. [2021-11-19 05:31:59,875 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-19 05:31:59,875 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7251 states and 10668 transitions. [2021-11-19 05:31:59,899 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7018 [2021-11-19 05:31:59,899 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:31:59,900 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:31:59,903 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:59,903 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:31:59,903 INFO L791 eck$LassoCheckResult]: Stem: 79452#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 79453#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 80089#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 79162#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 79163#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 79418#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 79419#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 79135#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 79136#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 80460#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 79733#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 79734#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 80307#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 79638#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 79639#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 79039#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 79040#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 79384#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 79587#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 78613#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 78614#L1342 assume !(0 == ~M_E~0); 78779#L1342-2 assume !(0 == ~T1_E~0); 79351#L1347-1 assume !(0 == ~T2_E~0); 80439#L1352-1 assume !(0 == ~T3_E~0); 80202#L1357-1 assume !(0 == ~T4_E~0); 79376#L1362-1 assume !(0 == ~T5_E~0); 79377#L1367-1 assume !(0 == ~T6_E~0); 78959#L1372-1 assume !(0 == ~T7_E~0); 78960#L1377-1 assume !(0 == ~T8_E~0); 79300#L1382-1 assume !(0 == ~T9_E~0); 79301#L1387-1 assume !(0 == ~T10_E~0); 80066#L1392-1 assume !(0 == ~T11_E~0); 79337#L1397-1 assume !(0 == ~T12_E~0); 79338#L1402-1 assume !(0 == ~T13_E~0); 78976#L1407-1 assume !(0 == ~T14_E~0); 78977#L1412-1 assume !(0 == ~E_1~0); 80338#L1417-1 assume !(0 == ~E_2~0); 80339#L1422-1 assume !(0 == ~E_3~0); 80671#L1427-1 assume !(0 == ~E_4~0); 79169#L1432-1 assume !(0 == ~E_5~0); 79170#L1437-1 assume !(0 == ~E_6~0); 80245#L1442-1 assume !(0 == ~E_7~0); 80246#L1447-1 assume !(0 == ~E_8~0); 80063#L1452-1 assume !(0 == ~E_9~0); 78749#L1457-1 assume !(0 == ~E_10~0); 78750#L1462-1 assume !(0 == ~E_11~0); 80288#L1467-1 assume !(0 == ~E_12~0); 80302#L1472-1 assume !(0 == ~E_13~0); 80303#L1477-1 assume !(0 == ~E_14~0); 80006#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78949#L646 assume 1 == ~m_pc~0; 78950#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 79649#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79664#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 79041#L1666 assume !(0 != activate_threads_~tmp~1#1); 79042#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80701#L665 assume !(1 == ~t1_pc~0); 79532#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 79533#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79050#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 79051#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 79876#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 79877#L684 assume 1 == ~t2_pc~0; 80001#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 79920#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79990#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 80443#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 80444#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80717#L703 assume !(1 == ~t3_pc~0); 79191#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 79192#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 79867#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78583#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 78584#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 79073#L722 assume 1 == ~t4_pc~0; 79843#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 79258#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 79617#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 80228#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 79687#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78780#L741 assume 1 == ~t5_pc~0; 78781#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 79095#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 79253#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 79254#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 79969#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 79352#L760 assume !(1 == ~t6_pc~0); 79190#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 79189#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 79043#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 79044#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 79795#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 79796#L779 assume 1 == ~t7_pc~0; 78825#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 78671#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78672#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 79084#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 79107#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 79108#L798 assume !(1 == ~t8_pc~0); 80501#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 80403#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78827#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78828#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 80703#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78648#L817 assume 1 == ~t9_pc~0; 78649#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 79460#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 79461#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 80011#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 79057#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 79058#L836 assume !(1 == ~t10_pc~0); 79075#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 79005#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 79006#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 79259#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 79260#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 80416#L855 assume 1 == ~t11_pc~0; 79660#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 79661#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 80281#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 80059#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 79883#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 78945#L874 assume !(1 == ~t12_pc~0); 78946#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 79118#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 79119#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 79261#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 78621#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 78622#L893 assume 1 == ~t13_pc~0; 80603#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 78979#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 79299#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 80495#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 80503#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 80504#L912 assume 1 == ~t14_pc~0; 80253#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 80254#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 78948#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 78880#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 78881#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79680#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 80125#L1495-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 80126#L1500-1 assume !(1 == ~T2_E~0); 79791#L1505-1 assume !(1 == ~T3_E~0); 79792#L1510-1 assume !(1 == ~T4_E~0); 79852#L1515-1 assume !(1 == ~T5_E~0); 79853#L1520-1 assume !(1 == ~T6_E~0); 80502#L1525-1 assume !(1 == ~T7_E~0); 80160#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 79052#L1535-1 assume !(1 == ~T9_E~0); 79053#L1540-1 assume !(1 == ~T10_E~0); 78541#L1545-1 assume !(1 == ~T11_E~0); 78542#L1550-1 assume !(1 == ~T12_E~0); 78791#L1555-1 assume !(1 == ~T13_E~0); 78792#L1560-1 assume !(1 == ~T14_E~0); 79096#L1565-1 assume !(1 == ~E_1~0); 80684#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 81033#L1575-1 assume !(1 == ~E_3~0); 81031#L1580-1 assume !(1 == ~E_4~0); 81029#L1585-1 assume !(1 == ~E_5~0); 81028#L1590-1 assume !(1 == ~E_6~0); 81027#L1595-1 assume !(1 == ~E_7~0); 80752#L1600-1 assume !(1 == ~E_8~0); 80753#L1605-1 assume !(1 == ~E_9~0); 80867#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 80866#L1615-1 assume !(1 == ~E_11~0); 80854#L1620-1 assume !(1 == ~E_12~0); 80846#L1625-1 assume !(1 == ~E_13~0); 80838#L1630-1 assume !(1 == ~E_14~0); 80830#L1635-1 assume { :end_inline_reset_delta_events } true; 80823#L2017-2 [2021-11-19 05:31:59,904 INFO L793 eck$LassoCheckResult]: Loop: 80823#L2017-2 assume !false; 80820#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 80816#L1316 assume !false; 80815#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 80810#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 80799#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 80798#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 80796#L1115 assume !(0 != eval_~tmp~0#1); 80795#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 80794#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 80793#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 80792#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 80299#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 79841#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 79842#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 80477#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 80748#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 80737#L1372-3 assume !(0 == ~T7_E~0); 78599#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 78600#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 79279#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 79280#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 80256#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 80666#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 79781#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 78906#L1412-3 assume !(0 == ~E_1~0); 78907#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 79695#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 79696#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 84045#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 84043#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 84041#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 80124#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 78665#L1452-3 assume !(0 == ~E_9~0); 78666#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 80397#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 80398#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 80176#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 80177#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 78904#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78905#L646-42 assume 1 == ~m_pc~0; 79507#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 80440#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 80441#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 80642#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 80643#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80356#L665-42 assume !(1 == ~t1_pc~0); 80315#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 80316#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 80554#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 79076#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 79077#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80747#L684-42 assume 1 == ~t2_pc~0; 79965#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 79966#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80722#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 79729#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 79730#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79860#L703-42 assume 1 == ~t3_pc~0; 80071#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 80072#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 79357#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 79358#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 80184#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 79768#L722-42 assume 1 == ~t4_pc~0; 79769#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 80219#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 79407#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 79224#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 79225#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 80697#L741-42 assume !(1 == ~t5_pc~0); 80197#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 79621#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 79622#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 80754#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 79525#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 79526#L760-42 assume !(1 == ~t6_pc~0); 79667#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 79811#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 79812#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 80240#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 79477#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 79478#L779-42 assume !(1 == ~t7_pc~0); 80320#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 80321#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 79150#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 79151#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 79003#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 79004#L798-42 assume !(1 == ~t8_pc~0); 78611#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 78612#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 80462#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 79836#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 78831#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78832#L817-42 assume 1 == ~t9_pc~0; 79627#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 79121#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 79122#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 79249#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 80098#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 80099#L836-42 assume 1 == ~t10_pc~0; 80583#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 81838#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 81837#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 81836#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 81835#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 81834#L855-42 assume !(1 == ~t11_pc~0); 81833#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 81831#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 81830#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 81829#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 81828#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 81827#L874-42 assume !(1 == ~t12_pc~0); 81825#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 81824#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 81823#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 81822#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 81821#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 81820#L893-42 assume 1 == ~t13_pc~0; 81783#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 81781#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 81779#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 81777#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 81775#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 81773#L912-42 assume !(1 == ~t14_pc~0); 81769#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 81766#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 81764#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 81762#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 81760#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81757#L1495-3 assume !(1 == ~M_E~0); 81755#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 80087#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 81752#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 81750#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 81748#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81745#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 81743#L1525-3 assume !(1 == ~T7_E~0); 81741#L1530-3 assume !(1 == ~T8_E~0); 81739#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 81737#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 81735#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 81732#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 81730#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 81728#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 81492#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 80153#L1570-3 assume !(1 == ~E_2~0); 81488#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 81486#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 81484#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 81482#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 81480#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 81477#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 81316#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 81312#L1610-3 assume !(1 == ~E_10~0); 81310#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 81308#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 81306#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 81303#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 81301#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 81117#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 81101#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 81099#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 80968#L2036 assume !(0 == start_simulation_~tmp~3#1); 80965#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 80913#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 80886#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 80865#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 80853#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 80845#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 80837#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 80829#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 80823#L2017-2 [2021-11-19 05:31:59,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:59,905 INFO L85 PathProgramCache]: Analyzing trace with hash 531990062, now seen corresponding path program 1 times [2021-11-19 05:31:59,905 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:59,905 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [495003425] [2021-11-19 05:31:59,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:59,906 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:59,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:59,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:59,941 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:59,941 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [495003425] [2021-11-19 05:31:59,942 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [495003425] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:59,942 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:59,942 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-19 05:31:59,942 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1463617873] [2021-11-19 05:31:59,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:59,943 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:31:59,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:31:59,943 INFO L85 PathProgramCache]: Analyzing trace with hash -817649461, now seen corresponding path program 1 times [2021-11-19 05:31:59,943 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:31:59,944 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032022040] [2021-11-19 05:31:59,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:31:59,944 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:31:59,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:31:59,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:31:59,987 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:31:59,988 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2032022040] [2021-11-19 05:31:59,988 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2032022040] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:31:59,988 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:31:59,988 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:31:59,988 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1160203047] [2021-11-19 05:31:59,988 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:31:59,989 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:31:59,989 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:31:59,989 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:31:59,990 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:31:59,990 INFO L87 Difference]: Start difference. First operand 7251 states and 10668 transitions. cyclomatic complexity: 3421 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:32:00,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:32:00,155 INFO L93 Difference]: Finished difference Result 10799 states and 15776 transitions. [2021-11-19 05:32:00,156 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:32:00,156 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10799 states and 15776 transitions. [2021-11-19 05:32:00,203 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 10563 [2021-11-19 05:32:00,240 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10799 states to 10799 states and 15776 transitions. [2021-11-19 05:32:00,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10799 [2021-11-19 05:32:00,251 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10799 [2021-11-19 05:32:00,251 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10799 states and 15776 transitions. [2021-11-19 05:32:00,262 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:32:00,262 INFO L681 BuchiCegarLoop]: Abstraction has 10799 states and 15776 transitions. [2021-11-19 05:32:00,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10799 states and 15776 transitions. [2021-11-19 05:32:00,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10799 to 10585. [2021-11-19 05:32:00,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10585 states, 10585 states have (on average 1.4620689655172414) internal successors, (15476), 10584 states have internal predecessors, (15476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:32:00,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10585 states to 10585 states and 15476 transitions. [2021-11-19 05:32:00,559 INFO L704 BuchiCegarLoop]: Abstraction has 10585 states and 15476 transitions. [2021-11-19 05:32:00,559 INFO L587 BuchiCegarLoop]: Abstraction has 10585 states and 15476 transitions. [2021-11-19 05:32:00,559 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-19 05:32:00,560 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10585 states and 15476 transitions. [2021-11-19 05:32:00,595 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 10351 [2021-11-19 05:32:00,595 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:32:00,595 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:32:00,598 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:32:00,599 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:32:00,599 INFO L791 eck$LassoCheckResult]: Stem: 97492#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 97493#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 98114#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 97209#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 97210#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 97458#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 97459#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97183#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 97184#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 98458#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 97764#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 97765#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 98320#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 97672#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 97673#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 97090#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 97091#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 97425#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 97623#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 96669#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96670#L1342 assume !(0 == ~M_E~0); 96835#L1342-2 assume !(0 == ~T1_E~0); 97392#L1347-1 assume !(0 == ~T2_E~0); 98440#L1352-1 assume !(0 == ~T3_E~0); 98216#L1357-1 assume !(0 == ~T4_E~0); 97417#L1362-1 assume !(0 == ~T5_E~0); 97418#L1367-1 assume !(0 == ~T6_E~0); 97012#L1372-1 assume !(0 == ~T7_E~0); 97013#L1377-1 assume !(0 == ~T8_E~0); 97346#L1382-1 assume !(0 == ~T9_E~0); 97347#L1387-1 assume !(0 == ~T10_E~0); 98092#L1392-1 assume !(0 == ~T11_E~0); 97378#L1397-1 assume !(0 == ~T12_E~0); 97379#L1402-1 assume !(0 == ~T13_E~0); 97028#L1407-1 assume !(0 == ~T14_E~0); 97029#L1412-1 assume !(0 == ~E_1~0); 98353#L1417-1 assume !(0 == ~E_2~0); 98354#L1422-1 assume !(0 == ~E_3~0); 98626#L1427-1 assume !(0 == ~E_4~0); 97216#L1432-1 assume !(0 == ~E_5~0); 97217#L1437-1 assume !(0 == ~E_6~0); 98264#L1442-1 assume !(0 == ~E_7~0); 98265#L1447-1 assume !(0 == ~E_8~0); 98089#L1452-1 assume !(0 == ~E_9~0); 96805#L1457-1 assume !(0 == ~E_10~0); 96806#L1462-1 assume !(0 == ~E_11~0); 98303#L1467-1 assume !(0 == ~E_12~0); 98315#L1472-1 assume !(0 == ~E_13~0); 98316#L1477-1 assume !(0 == ~E_14~0); 98034#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97003#L646 assume !(1 == ~m_pc~0); 97004#L646-2 is_master_triggered_~__retres1~0#1 := 0; 97699#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 97700#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 97092#L1666 assume !(0 != activate_threads_~tmp~1#1); 97093#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 98651#L665 assume !(1 == ~t1_pc~0); 97571#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 97572#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97101#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 97102#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 97904#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97905#L684 assume 1 == ~t2_pc~0; 98029#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 97946#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 98018#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 98444#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 98445#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98668#L703 assume !(1 == ~t3_pc~0); 97238#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 97239#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 97896#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 96639#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 96640#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97123#L722 assume 1 == ~t4_pc~0; 97871#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 97307#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97652#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 98245#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 97722#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96836#L741 assume 1 == ~t5_pc~0; 96837#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 97145#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 97302#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 97303#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 97997#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 97393#L760 assume !(1 == ~t6_pc~0); 97237#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 97236#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 97094#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 97095#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 97822#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 97823#L779 assume 1 == ~t7_pc~0; 96880#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 96727#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96728#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 97134#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 97157#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 97158#L798 assume !(1 == ~t8_pc~0); 98494#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 98411#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96882#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 96883#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 98653#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 96704#L817 assume 1 == ~t9_pc~0; 96705#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 97500#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 97501#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 98039#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 97108#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 97109#L836 assume !(1 == ~t10_pc~0); 97125#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 97056#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 97057#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 97308#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 97309#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 98421#L855 assume 1 == ~t11_pc~0; 97695#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 97696#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 98298#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 98085#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 97911#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 96999#L874 assume !(1 == ~t12_pc~0); 97000#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 97166#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 97167#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 97310#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 96677#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 96678#L893 assume 1 == ~t13_pc~0; 98573#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 97031#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 97345#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 98488#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 98496#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 98497#L912 assume 1 == ~t14_pc~0; 98272#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 98273#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 97002#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 96934#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 96935#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97715#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 98148#L1495-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 98149#L1500-1 assume !(1 == ~T2_E~0); 102359#L1505-1 assume !(1 == ~T3_E~0); 102358#L1510-1 assume !(1 == ~T4_E~0); 102357#L1515-1 assume !(1 == ~T5_E~0); 102356#L1520-1 assume !(1 == ~T6_E~0); 102355#L1525-1 assume !(1 == ~T7_E~0); 102354#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 102353#L1535-1 assume !(1 == ~T9_E~0); 102352#L1540-1 assume !(1 == ~T10_E~0); 102351#L1545-1 assume !(1 == ~T11_E~0); 102350#L1550-1 assume !(1 == ~T12_E~0); 102349#L1555-1 assume !(1 == ~T13_E~0); 102348#L1560-1 assume !(1 == ~T14_E~0); 102347#L1565-1 assume !(1 == ~E_1~0); 102346#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 102345#L1575-1 assume !(1 == ~E_3~0); 102343#L1580-1 assume !(1 == ~E_4~0); 97898#L1585-1 assume !(1 == ~E_5~0); 97899#L1590-1 assume !(1 == ~E_6~0); 102218#L1595-1 assume !(1 == ~E_7~0); 102216#L1600-1 assume !(1 == ~E_8~0); 102215#L1605-1 assume !(1 == ~E_9~0); 102213#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 102211#L1615-1 assume !(1 == ~E_11~0); 102196#L1620-1 assume !(1 == ~E_12~0); 102188#L1625-1 assume !(1 == ~E_13~0); 102180#L1630-1 assume !(1 == ~E_14~0); 102172#L1635-1 assume { :end_inline_reset_delta_events } true; 102165#L2017-2 [2021-11-19 05:32:00,600 INFO L793 eck$LassoCheckResult]: Loop: 102165#L2017-2 assume !false; 102162#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 102158#L1316 assume !false; 102157#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 102152#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 102141#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 102140#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 102138#L1115 assume !(0 != eval_~tmp~0#1); 102137#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 102136#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 102135#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 102133#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 102134#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 104573#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 104570#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 104085#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 104083#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 104081#L1372-3 assume !(0 == ~T7_E~0); 104079#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 104077#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 104074#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 104072#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 104070#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 103950#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 103948#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 103946#L1412-3 assume !(0 == ~E_1~0); 103945#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 103943#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 103852#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 103779#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 103777#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 103775#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 103773#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 103771#L1452-3 assume !(0 == ~E_9~0); 103768#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 103767#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 103766#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 103763#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 103761#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 103759#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103757#L646-42 assume !(1 == ~m_pc~0); 103755#L646-44 is_master_triggered_~__retres1~0#1 := 0; 103753#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103750#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 103748#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 103746#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 103685#L665-42 assume !(1 == ~t1_pc~0); 103611#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 103609#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103552#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 103550#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 103548#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103546#L684-42 assume !(1 == ~t2_pc~0); 103543#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 103539#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103537#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 103536#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 103533#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103531#L703-42 assume !(1 == ~t3_pc~0); 103527#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 103525#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 103523#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 103438#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 103435#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103433#L722-42 assume !(1 == ~t4_pc~0); 103429#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 103426#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103425#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 103422#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 103420#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 103418#L741-42 assume !(1 == ~t5_pc~0); 103415#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 103413#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 103411#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 103408#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 103406#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 103404#L760-42 assume !(1 == ~t6_pc~0); 103327#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 103251#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 103249#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 103246#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 103244#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 103242#L779-42 assume 1 == ~t7_pc~0; 103239#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 103237#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 103235#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 103233#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 103231#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 103228#L798-42 assume !(1 == ~t8_pc~0); 103225#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 103223#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 103119#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 103116#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 103114#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 103113#L817-42 assume 1 == ~t9_pc~0; 103109#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 103107#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 103105#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 103103#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 103101#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 103099#L836-42 assume !(1 == ~t10_pc~0); 103049#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 103047#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 103045#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 103043#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 103042#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 103039#L855-42 assume !(1 == ~t11_pc~0); 103037#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 103034#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 103032#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 103030#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 103028#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 102939#L874-42 assume 1 == ~t12_pc~0; 102839#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 102836#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 102834#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 102832#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 102829#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 102827#L893-42 assume !(1 == ~t13_pc~0); 102825#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 102822#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 102755#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 102752#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 102750#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 102748#L912-42 assume !(1 == ~t14_pc~0); 102745#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 102742#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 102687#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 102645#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 102643#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102641#L1495-3 assume !(1 == ~M_E~0); 102639#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 98112#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 102635#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 102633#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 102631#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 102629#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 102627#L1525-3 assume !(1 == ~T7_E~0); 102624#L1530-3 assume !(1 == ~T8_E~0); 102622#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 102620#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 102618#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 102517#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 102515#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 102512#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 102510#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 102507#L1570-3 assume !(1 == ~E_2~0); 102505#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 102503#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 102501#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 102498#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 102496#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 102494#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 102492#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 102489#L1610-3 assume !(1 == ~E_10~0); 102487#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 102484#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 102482#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 102480#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 102478#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 102293#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 102278#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 102277#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 102274#L2036 assume !(0 == start_simulation_~tmp~3#1); 102271#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 102235#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 102212#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 102210#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 102195#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 102187#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 102179#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 102171#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 102165#L2017-2 [2021-11-19 05:32:00,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:32:00,601 INFO L85 PathProgramCache]: Analyzing trace with hash -696299059, now seen corresponding path program 1 times [2021-11-19 05:32:00,601 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:32:00,601 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1637835150] [2021-11-19 05:32:00,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:32:00,601 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:32:00,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:32:00,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:32:00,643 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:32:00,643 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1637835150] [2021-11-19 05:32:00,644 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1637835150] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:32:00,644 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:32:00,644 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:32:00,644 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [323747258] [2021-11-19 05:32:00,644 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:32:00,645 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:32:00,647 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:32:00,648 INFO L85 PathProgramCache]: Analyzing trace with hash -104511609, now seen corresponding path program 1 times [2021-11-19 05:32:00,648 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:32:00,648 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715798609] [2021-11-19 05:32:00,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:32:00,648 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:32:00,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:32:00,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:32:00,693 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:32:00,693 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1715798609] [2021-11-19 05:32:00,694 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1715798609] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:32:00,694 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:32:00,694 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:32:00,694 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [94279313] [2021-11-19 05:32:00,694 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:32:00,695 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:32:00,696 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:32:00,696 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-19 05:32:00,696 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-19 05:32:00,696 INFO L87 Difference]: Start difference. First operand 10585 states and 15476 transitions. cyclomatic complexity: 4897 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:32:01,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:32:01,058 INFO L93 Difference]: Finished difference Result 27224 states and 39535 transitions. [2021-11-19 05:32:01,059 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-19 05:32:01,059 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27224 states and 39535 transitions. [2021-11-19 05:32:01,185 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 26755 [2021-11-19 05:32:01,482 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27224 states to 27224 states and 39535 transitions. [2021-11-19 05:32:01,482 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27224 [2021-11-19 05:32:01,511 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27224 [2021-11-19 05:32:01,511 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27224 states and 39535 transitions. [2021-11-19 05:32:01,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:32:01,534 INFO L681 BuchiCegarLoop]: Abstraction has 27224 states and 39535 transitions. [2021-11-19 05:32:01,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27224 states and 39535 transitions. [2021-11-19 05:32:01,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27224 to 20204. [2021-11-19 05:32:01,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20204 states, 20204 states have (on average 1.4561472975648386) internal successors, (29420), 20203 states have internal predecessors, (29420), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:32:02,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20204 states to 20204 states and 29420 transitions. [2021-11-19 05:32:02,029 INFO L704 BuchiCegarLoop]: Abstraction has 20204 states and 29420 transitions. [2021-11-19 05:32:02,029 INFO L587 BuchiCegarLoop]: Abstraction has 20204 states and 29420 transitions. [2021-11-19 05:32:02,029 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-19 05:32:02,029 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20204 states and 29420 transitions. [2021-11-19 05:32:02,103 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 19969 [2021-11-19 05:32:02,103 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:32:02,103 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:32:02,107 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:32:02,107 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:32:02,108 INFO L791 eck$LassoCheckResult]: Stem: 135311#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 135312#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 135939#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 135029#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 135030#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 135277#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 135278#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 135003#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 135004#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 136279#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 135586#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 135587#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 136147#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 135493#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 135494#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 134909#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 134910#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 135243#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 135443#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 134488#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 134489#L1342 assume !(0 == ~M_E~0); 134653#L1342-2 assume !(0 == ~T1_E~0); 135210#L1347-1 assume !(0 == ~T2_E~0); 136262#L1352-1 assume !(0 == ~T3_E~0); 136046#L1357-1 assume !(0 == ~T4_E~0); 135235#L1362-1 assume !(0 == ~T5_E~0); 135236#L1367-1 assume !(0 == ~T6_E~0); 134831#L1372-1 assume !(0 == ~T7_E~0); 134832#L1377-1 assume !(0 == ~T8_E~0); 135164#L1382-1 assume !(0 == ~T9_E~0); 135165#L1387-1 assume !(0 == ~T10_E~0); 135917#L1392-1 assume !(0 == ~T11_E~0); 135198#L1397-1 assume !(0 == ~T12_E~0); 135199#L1402-1 assume !(0 == ~T13_E~0); 134847#L1407-1 assume !(0 == ~T14_E~0); 134848#L1412-1 assume !(0 == ~E_1~0); 136177#L1417-1 assume !(0 == ~E_2~0); 136178#L1422-1 assume !(0 == ~E_3~0); 136457#L1427-1 assume !(0 == ~E_4~0); 135036#L1432-1 assume !(0 == ~E_5~0); 135037#L1437-1 assume !(0 == ~E_6~0); 136089#L1442-1 assume !(0 == ~E_7~0); 136090#L1447-1 assume !(0 == ~E_8~0); 135913#L1452-1 assume !(0 == ~E_9~0); 134623#L1457-1 assume !(0 == ~E_10~0); 134624#L1462-1 assume !(0 == ~E_11~0); 136128#L1467-1 assume !(0 == ~E_12~0); 136142#L1472-1 assume !(0 == ~E_13~0); 136143#L1477-1 assume !(0 == ~E_14~0); 135856#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 134824#L646 assume !(1 == ~m_pc~0); 134825#L646-2 is_master_triggered_~__retres1~0#1 := 0; 135521#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 135522#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 134911#L1666 assume !(0 != activate_threads_~tmp~1#1); 134912#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 136488#L665 assume !(1 == ~t1_pc~0); 135390#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 135391#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 134920#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 134921#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 135728#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 135729#L684 assume !(1 == ~t2_pc~0); 135770#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 135771#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 135841#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 136266#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 136267#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 136504#L703 assume !(1 == ~t3_pc~0); 135058#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 135059#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 135718#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 134458#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 134459#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 134942#L722 assume 1 == ~t4_pc~0; 135694#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 135125#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 135473#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 136073#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 135543#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 134654#L741 assume 1 == ~t5_pc~0; 134655#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 134964#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 135122#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 135123#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 135821#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 135211#L760 assume !(1 == ~t6_pc~0); 135057#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 135056#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 134913#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 134914#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 135647#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 135648#L779 assume 1 == ~t7_pc~0; 134699#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 134546#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 134547#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 134953#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 134977#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 134978#L798 assume !(1 == ~t8_pc~0); 136319#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 136234#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 134701#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 134702#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 136490#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 134523#L817 assume 1 == ~t9_pc~0; 134524#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 135319#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 135320#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 135861#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 134927#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 134928#L836 assume !(1 == ~t10_pc~0); 134944#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 134875#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 134876#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 135126#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 135127#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 136244#L855 assume 1 == ~t11_pc~0; 135516#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 135517#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 136122#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 135909#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 135735#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 134818#L874 assume !(1 == ~t12_pc~0); 134819#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 134986#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 134987#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 135128#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 134496#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 134497#L893 assume 1 == ~t13_pc~0; 136395#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 134850#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 135163#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 136313#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 136322#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 136323#L912 assume 1 == ~t14_pc~0; 136096#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 136097#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 134821#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 134754#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 134755#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 135536#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 135973#L1495-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 135974#L1500-1 assume !(1 == ~T2_E~0); 135643#L1505-1 assume !(1 == ~T3_E~0); 135644#L1510-1 assume !(1 == ~T4_E~0); 135703#L1515-1 assume !(1 == ~T5_E~0); 135704#L1520-1 assume !(1 == ~T6_E~0); 136320#L1525-1 assume !(1 == ~T7_E~0); 136321#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 134922#L1535-1 assume !(1 == ~T9_E~0); 134923#L1540-1 assume !(1 == ~T10_E~0); 134417#L1545-1 assume !(1 == ~T11_E~0); 134418#L1550-1 assume !(1 == ~T12_E~0); 134664#L1555-1 assume !(1 == ~T13_E~0); 134665#L1560-1 assume !(1 == ~T14_E~0); 136470#L1565-1 assume !(1 == ~E_1~0); 136471#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 135879#L1575-1 assume !(1 == ~E_3~0); 135880#L1580-1 assume !(1 == ~E_4~0); 135720#L1585-1 assume !(1 == ~E_5~0); 135721#L1590-1 assume !(1 == ~E_6~0); 135273#L1595-1 assume !(1 == ~E_7~0); 135274#L1600-1 assume !(1 == ~E_8~0); 135655#L1605-1 assume !(1 == ~E_9~0); 135656#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 152564#L1615-1 assume !(1 == ~E_11~0); 152563#L1620-1 assume !(1 == ~E_12~0); 152562#L1625-1 assume !(1 == ~E_13~0); 152561#L1630-1 assume !(1 == ~E_14~0); 135272#L1635-1 assume { :end_inline_reset_delta_events } true; 135212#L2017-2 [2021-11-19 05:32:02,108 INFO L793 eck$LassoCheckResult]: Loop: 135212#L2017-2 assume !false; 134492#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 134493#L1316 assume !false; 135842#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 135907#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 134430#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 134571#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 134572#L1115 assume !(0 != eval_~tmp~0#1); 135931#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 135329#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 135330#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 135515#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 136050#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 135692#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 135693#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 136296#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 136535#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 136526#L1372-3 assume !(0 == ~T7_E~0); 134474#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 134475#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 135144#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 135145#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 136099#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 136448#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 135634#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 134780#L1412-3 assume !(0 == ~E_1~0); 134781#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 135551#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 135552#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 136293#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 135956#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 135649#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 135650#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 134540#L1452-3 assume !(0 == ~E_9~0); 134541#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 136230#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 136231#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 136018#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 136019#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 134778#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 134779#L646-42 assume !(1 == ~m_pc~0); 135363#L646-44 is_master_triggered_~__retres1~0#1 := 0; 136263#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 136264#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 136430#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 136431#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 136194#L665-42 assume 1 == ~t1_pc~0; 136155#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 136157#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 136357#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 134945#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 134946#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 136534#L684-42 assume !(1 == ~t2_pc~0); 136508#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 136509#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 136513#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 135582#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 135583#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 135710#L703-42 assume 1 == ~t3_pc~0; 135923#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 135924#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 135216#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 135217#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 136025#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 135617#L722-42 assume 1 == ~t4_pc~0; 135618#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 136062#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 135266#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 135091#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 135092#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 136482#L741-42 assume !(1 == ~t5_pc~0); 136041#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 136042#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 154171#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 154170#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 154169#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 154168#L760-42 assume 1 == ~t6_pc~0; 154166#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 154165#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 154164#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 154163#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 153500#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 153499#L779-42 assume !(1 == ~t7_pc~0); 153498#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 153496#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 153495#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 153494#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 153493#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 153492#L798-42 assume !(1 == ~t8_pc~0); 153490#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 153488#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 153486#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 153484#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 153482#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 153480#L817-42 assume !(1 == ~t9_pc~0); 153478#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 153475#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 153472#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 153470#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 153468#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 153466#L836-42 assume !(1 == ~t10_pc~0); 153463#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 153461#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 153460#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 153459#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 153458#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 153457#L855-42 assume !(1 == ~t11_pc~0); 153456#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 153454#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 153453#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 153452#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 153451#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 153450#L874-42 assume !(1 == ~t12_pc~0); 153448#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 153446#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 153443#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 153441#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 153439#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 153437#L893-42 assume 1 == ~t13_pc~0; 153434#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 153432#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 153429#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 153427#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 153425#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 153423#L912-42 assume 1 == ~t14_pc~0; 153420#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 153418#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 153415#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 153413#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 153411#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 153409#L1495-3 assume !(1 == ~M_E~0); 153407#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 135937#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 153403#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 153401#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 153399#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 153397#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 153395#L1525-3 assume !(1 == ~T7_E~0); 153393#L1530-3 assume !(1 == ~T8_E~0); 153390#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 153388#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 153386#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 153384#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 153382#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 153380#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 153377#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 135998#L1570-3 assume !(1 == ~E_2~0); 153374#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 153372#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 153370#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 153368#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 136444#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 135759#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 135760#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 136268#L1610-3 assume !(1 == ~E_10~0); 135103#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 135104#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 135722#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 135723#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 136567#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 135044#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 134649#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 135389#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 135971#L2036 assume !(0 == start_simulation_~tmp~3#1); 135972#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 136146#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 135249#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 136338#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 135667#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 135668#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 136468#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 136469#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 135212#L2017-2 [2021-11-19 05:32:02,109 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:32:02,109 INFO L85 PathProgramCache]: Analyzing trace with hash -1143057428, now seen corresponding path program 1 times [2021-11-19 05:32:02,109 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:32:02,109 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1505502024] [2021-11-19 05:32:02,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:32:02,110 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:32:02,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:32:02,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:32:02,168 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:32:02,168 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1505502024] [2021-11-19 05:32:02,168 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1505502024] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:32:02,169 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:32:02,169 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-19 05:32:02,169 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [644324403] [2021-11-19 05:32:02,171 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:32:02,172 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:32:02,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:32:02,173 INFO L85 PathProgramCache]: Analyzing trace with hash 1697873386, now seen corresponding path program 1 times [2021-11-19 05:32:02,173 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:32:02,173 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [981268426] [2021-11-19 05:32:02,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:32:02,174 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:32:02,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:32:02,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:32:02,223 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:32:02,224 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [981268426] [2021-11-19 05:32:02,224 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [981268426] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:32:02,224 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:32:02,224 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:32:02,224 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [926525174] [2021-11-19 05:32:02,225 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:32:02,225 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:32:02,225 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:32:02,226 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:32:02,226 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:32:02,226 INFO L87 Difference]: Start difference. First operand 20204 states and 29420 transitions. cyclomatic complexity: 9222 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:32:02,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:32:02,489 INFO L93 Difference]: Finished difference Result 38746 states and 56216 transitions. [2021-11-19 05:32:02,489 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:32:02,490 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38746 states and 56216 transitions. [2021-11-19 05:32:02,870 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 38484 [2021-11-19 05:32:03,134 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38746 states to 38746 states and 56216 transitions. [2021-11-19 05:32:03,134 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38746 [2021-11-19 05:32:03,163 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38746 [2021-11-19 05:32:03,163 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38746 states and 56216 transitions. [2021-11-19 05:32:03,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:32:03,192 INFO L681 BuchiCegarLoop]: Abstraction has 38746 states and 56216 transitions. [2021-11-19 05:32:03,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38746 states and 56216 transitions. [2021-11-19 05:32:03,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38746 to 38722. [2021-11-19 05:32:03,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38722 states, 38722 states have (on average 1.4511647125664997) internal successors, (56192), 38721 states have internal predecessors, (56192), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:32:03,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38722 states to 38722 states and 56192 transitions. [2021-11-19 05:32:03,855 INFO L704 BuchiCegarLoop]: Abstraction has 38722 states and 56192 transitions. [2021-11-19 05:32:03,855 INFO L587 BuchiCegarLoop]: Abstraction has 38722 states and 56192 transitions. [2021-11-19 05:32:03,856 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-19 05:32:03,856 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38722 states and 56192 transitions. [2021-11-19 05:32:04,150 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 38460 [2021-11-19 05:32:04,171 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:32:04,171 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:32:04,175 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:32:04,176 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:32:04,176 INFO L791 eck$LassoCheckResult]: Stem: 194276#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 194277#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 194940#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 193989#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 193990#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 194242#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 194243#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 193961#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 193962#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 195348#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 194565#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 194566#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 195178#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 194463#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 194464#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 193866#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 193867#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 194206#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 194411#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 193445#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 193446#L1342 assume !(0 == ~M_E~0); 193612#L1342-2 assume !(0 == ~T1_E~0); 194173#L1347-1 assume !(0 == ~T2_E~0); 195324#L1352-1 assume !(0 == ~T3_E~0); 195058#L1357-1 assume !(0 == ~T4_E~0); 194198#L1362-1 assume !(0 == ~T5_E~0); 194199#L1367-1 assume !(0 == ~T6_E~0); 193788#L1372-1 assume !(0 == ~T7_E~0); 193789#L1377-1 assume !(0 == ~T8_E~0); 194126#L1382-1 assume !(0 == ~T9_E~0); 194127#L1387-1 assume !(0 == ~T10_E~0); 194918#L1392-1 assume !(0 == ~T11_E~0); 194159#L1397-1 assume !(0 == ~T12_E~0); 194160#L1402-1 assume !(0 == ~T13_E~0); 193804#L1407-1 assume !(0 == ~T14_E~0); 193805#L1412-1 assume !(0 == ~E_1~0); 195211#L1417-1 assume !(0 == ~E_2~0); 195212#L1422-1 assume !(0 == ~E_3~0); 195586#L1427-1 assume !(0 == ~E_4~0); 193996#L1432-1 assume !(0 == ~E_5~0); 193997#L1437-1 assume !(0 == ~E_6~0); 195111#L1442-1 assume !(0 == ~E_7~0); 195112#L1447-1 assume !(0 == ~E_8~0); 194915#L1452-1 assume !(0 == ~E_9~0); 193581#L1457-1 assume !(0 == ~E_10~0); 193582#L1462-1 assume !(0 == ~E_11~0); 195152#L1467-1 assume !(0 == ~E_12~0); 195171#L1472-1 assume !(0 == ~E_13~0); 195172#L1477-1 assume !(0 == ~E_14~0); 194852#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 193779#L646 assume !(1 == ~m_pc~0); 193780#L646-2 is_master_triggered_~__retres1~0#1 := 0; 194492#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 194493#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 193868#L1666 assume !(0 != activate_threads_~tmp~1#1); 193869#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 195629#L665 assume !(1 == ~t1_pc~0); 194356#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 194357#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 193877#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 193878#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 194705#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 194706#L684 assume !(1 == ~t2_pc~0); 194750#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 194751#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 194836#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 195331#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 195332#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 195651#L703 assume !(1 == ~t3_pc~0); 194017#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 194018#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 194698#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 193415#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 193416#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 193898#L722 assume !(1 == ~t4_pc~0); 194084#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 194085#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 194442#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 195093#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 194520#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 193613#L741 assume 1 == ~t5_pc~0; 193614#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 193920#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 194080#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 194081#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 194813#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 194174#L760 assume !(1 == ~t6_pc~0); 194016#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 194015#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 193870#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 193871#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 194624#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 194625#L779 assume 1 == ~t7_pc~0; 193656#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 193503#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 193504#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 193909#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 193933#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 193934#L798 assume !(1 == ~t8_pc~0); 195395#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 195280#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 193658#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 193659#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 195631#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 193480#L817 assume 1 == ~t9_pc~0; 193481#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 194284#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 194285#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 194859#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 193883#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 193884#L836 assume !(1 == ~t10_pc~0); 193900#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 193832#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 193833#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 194086#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 194087#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 195296#L855 assume 1 == ~t11_pc~0; 194488#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 194489#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 195147#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 194910#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 194715#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 193775#L874 assume !(1 == ~t12_pc~0); 193776#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 193942#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 193943#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 194088#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 193453#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 193454#L893 assume 1 == ~t13_pc~0; 195510#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 193807#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 194125#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 195389#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 195398#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 195399#L912 assume 1 == ~t14_pc~0; 195119#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 195120#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 193778#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 193708#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 193709#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 194511#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 194978#L1495-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 194979#L1500-1 assume !(1 == ~T2_E~0); 195579#L1505-1 assume !(1 == ~T3_E~0); 195704#L1510-1 assume !(1 == ~T4_E~0); 195705#L1515-1 assume !(1 == ~T5_E~0); 195617#L1520-1 assume !(1 == ~T6_E~0); 195618#L1525-1 assume !(1 == ~T7_E~0); 195007#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 195008#L1535-1 assume !(1 == ~T9_E~0); 195671#L1540-1 assume !(1 == ~T10_E~0); 195672#L1545-1 assume !(1 == ~T11_E~0); 195733#L1550-1 assume !(1 == ~T12_E~0); 195734#L1555-1 assume !(1 == ~T13_E~0); 193921#L1560-1 assume !(1 == ~T14_E~0); 193922#L1565-1 assume !(1 == ~E_1~0); 209239#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 209238#L1575-1 assume !(1 == ~E_3~0); 209237#L1580-1 assume !(1 == ~E_4~0); 209236#L1585-1 assume !(1 == ~E_5~0); 209235#L1590-1 assume !(1 == ~E_6~0); 209234#L1595-1 assume !(1 == ~E_7~0); 209233#L1600-1 assume !(1 == ~E_8~0); 209232#L1605-1 assume !(1 == ~E_9~0); 195567#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 195568#L1615-1 assume !(1 == ~E_11~0); 209230#L1620-1 assume !(1 == ~E_12~0); 195092#L1625-1 assume !(1 == ~E_13~0); 194916#L1630-1 assume !(1 == ~E_14~0); 194236#L1635-1 assume { :end_inline_reset_delta_events } true; 194237#L2017-2 [2021-11-19 05:32:04,177 INFO L793 eck$LassoCheckResult]: Loop: 194237#L2017-2 assume !false; 213340#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 213333#L1316 assume !false; 194907#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 194908#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 193387#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 193529#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 193530#L1115 assume !(0 != eval_~tmp~0#1); 194932#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 194293#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 194294#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 231826#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 195168#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 194671#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 194672#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 195371#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 195692#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 195676#L1372-3 assume !(0 == ~T7_E~0); 193431#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 193432#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 194106#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 194107#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 195122#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 195575#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 194611#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 193737#L1412-3 assume !(0 == ~E_1~0); 193738#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 194528#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 194529#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 195365#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 194952#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 194626#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 194627#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 193497#L1452-3 assume !(0 == ~E_9~0); 193498#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 195274#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 195275#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 231384#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 231382#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 231381#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 194328#L646-42 assume !(1 == ~m_pc~0); 194329#L646-44 is_master_triggered_~__retres1~0#1 := 0; 195326#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 195327#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 195580#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 218242#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 218241#L665-42 assume 1 == ~t1_pc~0; 218240#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 218238#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 218237#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 218236#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 218235#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 195690#L684-42 assume !(1 == ~t2_pc~0); 195691#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 231110#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 231108#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 231106#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 231104#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 231102#L703-42 assume !(1 == ~t3_pc~0); 231099#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 231096#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 231090#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 231084#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 195033#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 194596#L722-42 assume !(1 == ~t4_pc~0); 194597#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 219277#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 219275#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 219273#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 219270#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 219269#L741-42 assume 1 == ~t5_pc~0; 219266#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 219263#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 219261#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 219259#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 217446#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 217445#L760-42 assume 1 == ~t6_pc~0; 217443#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 217442#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 217441#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 217440#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 217439#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 217438#L779-42 assume !(1 == ~t7_pc~0); 217437#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 217435#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 217434#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 217433#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 217432#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 217431#L798-42 assume 1 == ~t8_pc~0; 217430#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 217427#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 217425#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 217423#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 217421#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 217419#L817-42 assume !(1 == ~t9_pc~0); 217414#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 217411#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 217409#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 217407#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 217405#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 217402#L836-42 assume 1 == ~t10_pc~0; 217399#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 217396#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 217394#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 217392#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 217390#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 217388#L855-42 assume !(1 == ~t11_pc~0); 217385#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 217382#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 217380#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 217378#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 217376#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 217374#L874-42 assume !(1 == ~t12_pc~0); 217371#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 217369#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 217367#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 217365#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 217363#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 217361#L893-42 assume !(1 == ~t13_pc~0); 217358#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 217355#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 217353#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 217351#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 217349#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 217347#L912-42 assume !(1 == ~t14_pc~0); 217344#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 217341#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 214226#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 214225#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 214224#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 214223#L1495-3 assume !(1 == ~M_E~0); 214222#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 209687#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 214220#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 214218#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 214216#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 214214#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 214212#L1525-3 assume !(1 == ~T7_E~0); 214210#L1530-3 assume !(1 == ~T8_E~0); 214208#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 214207#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 214206#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 214205#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 214203#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 214201#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 214199#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 214197#L1570-3 assume !(1 == ~E_2~0); 214195#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 214193#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 214191#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 214188#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 214186#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 214184#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 214182#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 214179#L1610-3 assume !(1 == ~E_10~0); 214177#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 214175#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 214173#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 214157#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 214155#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 214152#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 214136#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 214134#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 214132#L2036 assume !(0 == start_simulation_~tmp~3#1); 214129#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 213801#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 213451#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 213421#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 213412#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 213406#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 213405#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 213359#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 194237#L2017-2 [2021-11-19 05:32:04,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:32:04,178 INFO L85 PathProgramCache]: Analyzing trace with hash -787460981, now seen corresponding path program 1 times [2021-11-19 05:32:04,178 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:32:04,178 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [180038793] [2021-11-19 05:32:04,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:32:04,194 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:32:04,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:32:04,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:32:04,267 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:32:04,268 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [180038793] [2021-11-19 05:32:04,268 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [180038793] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:32:04,268 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:32:04,268 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-19 05:32:04,268 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [129696174] [2021-11-19 05:32:04,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:32:04,269 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:32:04,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:32:04,270 INFO L85 PathProgramCache]: Analyzing trace with hash -1547270455, now seen corresponding path program 1 times [2021-11-19 05:32:04,270 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:32:04,270 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1506998794] [2021-11-19 05:32:04,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:32:04,271 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:32:04,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:32:04,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:32:04,322 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:32:04,323 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1506998794] [2021-11-19 05:32:04,323 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1506998794] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:32:04,323 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:32:04,323 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:32:04,323 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [271606544] [2021-11-19 05:32:04,324 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:32:04,324 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:32:04,324 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:32:04,325 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-19 05:32:04,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-19 05:32:04,325 INFO L87 Difference]: Start difference. First operand 38722 states and 56192 transitions. cyclomatic complexity: 17482 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:32:04,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:32:04,813 INFO L93 Difference]: Finished difference Result 74377 states and 107585 transitions. [2021-11-19 05:32:04,818 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-19 05:32:04,820 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74377 states and 107585 transitions. [2021-11-19 05:32:05,290 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 74036 [2021-11-19 05:32:05,648 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74377 states to 74377 states and 107585 transitions. [2021-11-19 05:32:05,648 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 74377 [2021-11-19 05:32:05,684 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 74377 [2021-11-19 05:32:05,684 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74377 states and 107585 transitions. [2021-11-19 05:32:05,739 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:32:05,739 INFO L681 BuchiCegarLoop]: Abstraction has 74377 states and 107585 transitions. [2021-11-19 05:32:05,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74377 states and 107585 transitions. [2021-11-19 05:32:06,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74377 to 74329. [2021-11-19 05:32:06,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74329 states, 74329 states have (on average 1.4467704395323495) internal successors, (107537), 74328 states have internal predecessors, (107537), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:32:06,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74329 states to 74329 states and 107537 transitions. [2021-11-19 05:32:06,965 INFO L704 BuchiCegarLoop]: Abstraction has 74329 states and 107537 transitions. [2021-11-19 05:32:06,965 INFO L587 BuchiCegarLoop]: Abstraction has 74329 states and 107537 transitions. [2021-11-19 05:32:06,965 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-19 05:32:06,966 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74329 states and 107537 transitions. [2021-11-19 05:32:07,387 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 73988 [2021-11-19 05:32:07,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:32:07,387 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:32:07,390 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:32:07,391 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:32:07,391 INFO L791 eck$LassoCheckResult]: Stem: 307374#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 307375#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 308023#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 307090#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 307091#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 307343#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 307344#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 307064#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 307065#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 308404#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 307664#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 307665#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 308259#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 307565#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 307566#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 306970#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 306971#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 307307#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 307513#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 306551#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 306552#L1342 assume !(0 == ~M_E~0); 306715#L1342-2 assume !(0 == ~T1_E~0); 307273#L1347-1 assume !(0 == ~T2_E~0); 308385#L1352-1 assume !(0 == ~T3_E~0); 308139#L1357-1 assume !(0 == ~T4_E~0); 307298#L1362-1 assume !(0 == ~T5_E~0); 307299#L1367-1 assume !(0 == ~T6_E~0); 306892#L1372-1 assume !(0 == ~T7_E~0); 306893#L1377-1 assume !(0 == ~T8_E~0); 307226#L1382-1 assume !(0 == ~T9_E~0); 307227#L1387-1 assume !(0 == ~T10_E~0); 308002#L1392-1 assume !(0 == ~T11_E~0); 307261#L1397-1 assume !(0 == ~T12_E~0); 307262#L1402-1 assume !(0 == ~T13_E~0); 306907#L1407-1 assume !(0 == ~T14_E~0); 306908#L1412-1 assume !(0 == ~E_1~0); 308296#L1417-1 assume !(0 == ~E_2~0); 308297#L1422-1 assume !(0 == ~E_3~0); 308625#L1427-1 assume !(0 == ~E_4~0); 307096#L1432-1 assume !(0 == ~E_5~0); 307097#L1437-1 assume !(0 == ~E_6~0); 308193#L1442-1 assume !(0 == ~E_7~0); 308194#L1447-1 assume !(0 == ~E_8~0); 307997#L1452-1 assume !(0 == ~E_9~0); 306687#L1457-1 assume !(0 == ~E_10~0); 306688#L1462-1 assume !(0 == ~E_11~0); 308238#L1467-1 assume !(0 == ~E_12~0); 308254#L1472-1 assume !(0 == ~E_13~0); 308255#L1477-1 assume !(0 == ~E_14~0); 307939#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 306886#L646 assume !(1 == ~m_pc~0); 306887#L646-2 is_master_triggered_~__retres1~0#1 := 0; 307594#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 307595#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 306972#L1666 assume !(0 != activate_threads_~tmp~1#1); 306973#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 308662#L665 assume !(1 == ~t1_pc~0); 307456#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 307457#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 306979#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 306980#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 307804#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 307805#L684 assume !(1 == ~t2_pc~0); 307851#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 307852#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 307924#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 308389#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 308390#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 308680#L703 assume !(1 == ~t3_pc~0); 307118#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 307119#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 307794#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 306521#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 306522#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 307000#L722 assume !(1 == ~t4_pc~0); 307186#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 307187#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 307543#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 308176#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 307619#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 306716#L741 assume !(1 == ~t5_pc~0); 306717#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 307842#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 307184#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 307185#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 307902#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 307274#L760 assume !(1 == ~t6_pc~0); 307117#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 307116#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 306974#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 306975#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 307725#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 307726#L779 assume 1 == ~t7_pc~0; 306759#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 306609#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 306610#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 307011#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 307033#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 307034#L798 assume !(1 == ~t8_pc~0); 308450#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 308353#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 306761#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 306762#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 308664#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 306586#L817 assume 1 == ~t9_pc~0; 306587#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 307383#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 307384#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 307945#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 306985#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 306986#L836 assume !(1 == ~t10_pc~0); 307002#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 306934#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 306935#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 307188#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 307189#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 308366#L855 assume 1 == ~t11_pc~0; 307589#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 307590#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 308232#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 307993#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 307812#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 306878#L874 assume !(1 == ~t12_pc~0); 306879#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 307044#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 307045#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 307190#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 306561#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 306562#L893 assume 1 == ~t13_pc~0; 308549#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 306910#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 307225#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 308443#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 308452#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 308453#L912 assume 1 == ~t14_pc~0; 308204#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 308205#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 306881#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 306812#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 306813#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 307612#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 308061#L1495-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 308062#L1500-1 assume !(1 == ~T2_E~0); 325898#L1505-1 assume !(1 == ~T3_E~0); 325897#L1510-1 assume !(1 == ~T4_E~0); 325896#L1515-1 assume !(1 == ~T5_E~0); 325895#L1520-1 assume !(1 == ~T6_E~0); 325894#L1525-1 assume !(1 == ~T7_E~0); 325893#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 325892#L1535-1 assume !(1 == ~T9_E~0); 325891#L1540-1 assume !(1 == ~T10_E~0); 325890#L1545-1 assume !(1 == ~T11_E~0); 325889#L1550-1 assume !(1 == ~T12_E~0); 325888#L1555-1 assume !(1 == ~T13_E~0); 325887#L1560-1 assume !(1 == ~T14_E~0); 325886#L1565-1 assume !(1 == ~E_1~0); 325885#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 325884#L1575-1 assume !(1 == ~E_3~0); 325883#L1580-1 assume !(1 == ~E_4~0); 325882#L1585-1 assume !(1 == ~E_5~0); 325881#L1590-1 assume !(1 == ~E_6~0); 325880#L1595-1 assume !(1 == ~E_7~0); 325879#L1600-1 assume !(1 == ~E_8~0); 325877#L1605-1 assume !(1 == ~E_9~0); 325878#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 376267#L1615-1 assume !(1 == ~E_11~0); 376265#L1620-1 assume !(1 == ~E_12~0); 376263#L1625-1 assume !(1 == ~E_13~0); 376261#L1630-1 assume !(1 == ~E_14~0); 376258#L1635-1 assume { :end_inline_reset_delta_events } true; 376255#L2017-2 [2021-11-19 05:32:07,392 INFO L793 eck$LassoCheckResult]: Loop: 376255#L2017-2 assume !false; 375165#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 375161#L1316 assume !false; 375160#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 374991#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 374979#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 374977#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 325798#L1115 assume !(0 != eval_~tmp~0#1); 325799#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 380721#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 380719#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 380717#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 380715#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 380713#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 380712#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 380711#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 380710#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 380708#L1372-3 assume !(0 == ~T7_E~0); 380706#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 380704#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 307206#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 307207#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 380699#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 380661#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 307710#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 306841#L1412-3 assume !(0 == ~E_1~0); 306842#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 307626#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 307627#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 308420#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 308041#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 307731#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 307732#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 306603#L1452-3 assume !(0 == ~E_9~0); 306604#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 377748#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 377747#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 377746#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 377745#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 377744#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 377743#L646-42 assume !(1 == ~m_pc~0); 377741#L646-44 is_master_triggered_~__retres1~0#1 := 0; 377739#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 377737#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 377735#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 377733#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 377731#L665-42 assume 1 == ~t1_pc~0; 377729#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 377725#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 377723#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 377721#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 377719#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 376518#L684-42 assume !(1 == ~t2_pc~0); 376516#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 376514#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 376512#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 376510#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 376508#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 376505#L703-42 assume 1 == ~t3_pc~0; 376503#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 376500#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 376498#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 376496#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 376494#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 376491#L722-42 assume !(1 == ~t4_pc~0); 376489#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 376487#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 376485#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 376483#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 376481#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 376478#L741-42 assume !(1 == ~t5_pc~0); 376476#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 376474#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 376472#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 376470#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 376468#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 376465#L760-42 assume !(1 == ~t6_pc~0); 376463#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 376460#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 376458#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 376456#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 376454#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 376452#L779-42 assume !(1 == ~t7_pc~0); 376451#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 376448#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 376446#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 376444#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 376442#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 376440#L798-42 assume !(1 == ~t8_pc~0); 376437#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 376435#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 376433#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 376431#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 376429#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 376427#L817-42 assume !(1 == ~t9_pc~0); 376425#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 376422#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 376421#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 376419#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 376417#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 376415#L836-42 assume 1 == ~t10_pc~0; 376413#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 376410#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 376408#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 376406#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 376405#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 376403#L855-42 assume !(1 == ~t11_pc~0); 376401#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 376398#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 376396#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 376395#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 376394#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 376393#L874-42 assume !(1 == ~t12_pc~0); 376391#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 376390#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 376389#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 376388#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 376387#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 376386#L893-42 assume !(1 == ~t13_pc~0); 376385#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 376383#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 376382#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 376381#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 376380#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 376379#L912-42 assume 1 == ~t14_pc~0; 376377#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 376376#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 376375#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 376374#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 376373#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 376372#L1495-3 assume !(1 == ~M_E~0); 376371#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 308021#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 376370#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 376369#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 376368#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 376367#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 376366#L1525-3 assume !(1 == ~T7_E~0); 376365#L1530-3 assume !(1 == ~T8_E~0); 376364#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 376363#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 376362#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 376361#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 376360#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 376359#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 376358#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 367759#L1570-3 assume !(1 == ~E_2~0); 376357#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 376356#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 376355#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 376354#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 376353#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 376352#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 376351#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 357480#L1610-3 assume !(1 == ~E_10~0); 376350#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 376349#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 376348#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 376347#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 376346#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 376345#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 376330#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 376329#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 376327#L2036 assume !(0 == start_simulation_~tmp~3#1); 376325#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 376292#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 376290#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 376288#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 376286#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 376284#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 376282#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 376257#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 376255#L2017-2 [2021-11-19 05:32:07,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:32:07,393 INFO L85 PathProgramCache]: Analyzing trace with hash -824907670, now seen corresponding path program 1 times [2021-11-19 05:32:07,393 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:32:07,393 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1180318597] [2021-11-19 05:32:07,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:32:07,393 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:32:07,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:32:07,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:32:07,444 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:32:07,445 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1180318597] [2021-11-19 05:32:07,445 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1180318597] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:32:07,445 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:32:07,445 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-19 05:32:07,445 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [92452058] [2021-11-19 05:32:07,446 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:32:07,446 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:32:07,446 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:32:07,447 INFO L85 PathProgramCache]: Analyzing trace with hash -2100039064, now seen corresponding path program 1 times [2021-11-19 05:32:07,447 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:32:07,447 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [370127177] [2021-11-19 05:32:07,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:32:07,448 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:32:07,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:32:07,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:32:07,487 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:32:07,487 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [370127177] [2021-11-19 05:32:07,487 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [370127177] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:32:07,488 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:32:07,488 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:32:07,488 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1796887341] [2021-11-19 05:32:07,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:32:07,489 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:32:07,489 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:32:07,489 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-19 05:32:07,489 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-19 05:32:07,490 INFO L87 Difference]: Start difference. First operand 74329 states and 107537 transitions. cyclomatic complexity: 33232 Second operand has 5 states, 5 states have (on average 34.0) internal successors, (170), 5 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:32:08,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:32:08,599 INFO L93 Difference]: Finished difference Result 193830 states and 281638 transitions. [2021-11-19 05:32:08,599 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-19 05:32:08,600 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 193830 states and 281638 transitions. [2021-11-19 05:32:09,505 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 192992 [2021-11-19 05:32:10,457 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 193830 states to 193830 states and 281638 transitions. [2021-11-19 05:32:10,457 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 193830 [2021-11-19 05:32:10,594 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 193830 [2021-11-19 05:32:10,594 INFO L73 IsDeterministic]: Start isDeterministic. Operand 193830 states and 281638 transitions. [2021-11-19 05:32:10,805 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:32:10,805 INFO L681 BuchiCegarLoop]: Abstraction has 193830 states and 281638 transitions. [2021-11-19 05:32:10,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193830 states and 281638 transitions. [2021-11-19 05:32:12,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193830 to 76108. [2021-11-19 05:32:12,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76108 states, 76108 states have (on average 1.4363273243285857) internal successors, (109316), 76107 states have internal predecessors, (109316), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:32:12,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76108 states to 76108 states and 109316 transitions. [2021-11-19 05:32:12,326 INFO L704 BuchiCegarLoop]: Abstraction has 76108 states and 109316 transitions. [2021-11-19 05:32:12,326 INFO L587 BuchiCegarLoop]: Abstraction has 76108 states and 109316 transitions. [2021-11-19 05:32:12,327 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-19 05:32:12,327 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76108 states and 109316 transitions. [2021-11-19 05:32:12,503 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 75764 [2021-11-19 05:32:12,503 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:32:12,503 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:32:12,505 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:32:12,505 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:32:12,506 INFO L791 eck$LassoCheckResult]: Stem: 575547#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 575548#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 576204#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 575262#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 575263#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 575513#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 575514#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 575235#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 575236#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 576599#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 575832#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 575833#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 576446#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 575737#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 575738#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 575139#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 575140#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 575479#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 575684#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 574723#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 574724#L1342 assume !(0 == ~M_E~0); 574888#L1342-2 assume !(0 == ~T1_E~0); 575445#L1347-1 assume !(0 == ~T2_E~0); 576579#L1352-1 assume !(0 == ~T3_E~0); 576327#L1357-1 assume !(0 == ~T4_E~0); 575470#L1362-1 assume !(0 == ~T5_E~0); 575471#L1367-1 assume !(0 == ~T6_E~0); 575061#L1372-1 assume !(0 == ~T7_E~0); 575062#L1377-1 assume !(0 == ~T8_E~0); 575398#L1382-1 assume !(0 == ~T9_E~0); 575399#L1387-1 assume !(0 == ~T10_E~0); 576180#L1392-1 assume !(0 == ~T11_E~0); 575433#L1397-1 assume !(0 == ~T12_E~0); 575434#L1402-1 assume !(0 == ~T13_E~0); 575076#L1407-1 assume !(0 == ~T14_E~0); 575077#L1412-1 assume !(0 == ~E_1~0); 576478#L1417-1 assume !(0 == ~E_2~0); 576479#L1422-1 assume !(0 == ~E_3~0); 576822#L1427-1 assume !(0 == ~E_4~0); 575268#L1432-1 assume !(0 == ~E_5~0); 575269#L1437-1 assume !(0 == ~E_6~0); 576384#L1442-1 assume !(0 == ~E_7~0); 576385#L1447-1 assume !(0 == ~E_8~0); 576174#L1452-1 assume !(0 == ~E_9~0); 574858#L1457-1 assume !(0 == ~E_10~0); 574859#L1462-1 assume !(0 == ~E_11~0); 576426#L1467-1 assume !(0 == ~E_12~0); 576440#L1472-1 assume !(0 == ~E_13~0); 576441#L1477-1 assume !(0 == ~E_14~0); 576113#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 575053#L646 assume !(1 == ~m_pc~0); 575054#L646-2 is_master_triggered_~__retres1~0#1 := 0; 575765#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 575766#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 575141#L1666 assume !(0 != activate_threads_~tmp~1#1); 575142#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 576853#L665 assume !(1 == ~t1_pc~0); 575627#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 575628#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 575150#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 575151#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 575978#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 575979#L684 assume !(1 == ~t2_pc~0); 576024#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 576025#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 576098#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 576584#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 576585#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 576871#L703 assume !(1 == ~t3_pc~0); 575289#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 575290#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 575971#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 574693#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 574694#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 575172#L722 assume !(1 == ~t4_pc~0); 575357#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 575358#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 575716#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 576363#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 575791#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 574889#L741 assume !(1 == ~t5_pc~0); 574890#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 576014#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 575355#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 575356#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 576075#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 575446#L760 assume !(1 == ~t6_pc~0); 575288#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 575929#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 576230#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 576809#L1714 assume !(0 != activate_threads_~tmp___5~0#1); 575896#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 575897#L779 assume 1 == ~t7_pc~0; 574931#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 574781#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 574782#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 575183#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 575207#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 575208#L798 assume !(1 == ~t8_pc~0); 576648#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 576545#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 574933#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 574934#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 576855#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 574758#L817 assume 1 == ~t9_pc~0; 574759#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 575555#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 575556#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 576118#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 575156#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 575157#L836 assume !(1 == ~t10_pc~0); 575174#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 575105#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 575106#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 575359#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 575360#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 576560#L855 assume 1 == ~t11_pc~0; 575760#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 575761#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 576419#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 576170#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 575985#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 575047#L874 assume !(1 == ~t12_pc~0); 575048#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 575216#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 575217#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 575361#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 574731#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 574732#L893 assume 1 == ~t13_pc~0; 576747#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 575079#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 575397#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 576642#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 576653#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 576654#L912 assume 1 == ~t14_pc~0; 576391#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 576392#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 575050#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 574983#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 574984#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 575785#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 576243#L1495-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 576244#L1500-1 assume !(1 == ~T2_E~0); 576815#L1505-1 assume !(1 == ~T3_E~0); 576920#L1510-1 assume !(1 == ~T4_E~0); 576921#L1515-1 assume !(1 == ~T5_E~0); 576846#L1520-1 assume !(1 == ~T6_E~0); 576847#L1525-1 assume !(1 == ~T7_E~0); 576274#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 576275#L1535-1 assume !(1 == ~T9_E~0); 576889#L1540-1 assume !(1 == ~T10_E~0); 576890#L1545-1 assume !(1 == ~T11_E~0); 576945#L1550-1 assume !(1 == ~T12_E~0); 576946#L1555-1 assume !(1 == ~T13_E~0); 575194#L1560-1 assume !(1 == ~T14_E~0); 575195#L1565-1 assume !(1 == ~E_1~0); 593565#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 593564#L1575-1 assume !(1 == ~E_3~0); 593563#L1580-1 assume !(1 == ~E_4~0); 593562#L1585-1 assume !(1 == ~E_5~0); 593561#L1590-1 assume !(1 == ~E_6~0); 593560#L1595-1 assume !(1 == ~E_7~0); 593559#L1600-1 assume !(1 == ~E_8~0); 593558#L1605-1 assume !(1 == ~E_9~0); 575906#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 576522#L1615-1 assume !(1 == ~E_11~0); 575334#L1620-1 assume !(1 == ~E_12~0); 575335#L1625-1 assume !(1 == ~E_13~0); 576362#L1630-1 assume !(1 == ~E_14~0); 575507#L1635-1 assume { :end_inline_reset_delta_events } true; 575508#L2017-2 [2021-11-19 05:32:12,506 INFO L793 eck$LassoCheckResult]: Loop: 575508#L2017-2 assume !false; 590456#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 590453#L1316 assume !false; 590445#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 590446#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 613385#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 613383#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 613380#L1115 assume !(0 != eval_~tmp~0#1); 613381#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 619144#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 619143#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 619142#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 619141#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 619140#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 619139#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 619138#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 619137#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 619136#L1372-3 assume !(0 == ~T7_E~0); 619135#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 619134#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 619133#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 619132#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 619131#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 619130#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 619129#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 619128#L1412-3 assume !(0 == ~E_1~0); 619127#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 619126#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 619125#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 619124#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 619123#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 619122#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 619121#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 619120#L1452-3 assume !(0 == ~E_9~0); 619119#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 619118#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 619117#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 619116#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 619115#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 619114#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 619113#L646-42 assume !(1 == ~m_pc~0); 619112#L646-44 is_master_triggered_~__retres1~0#1 := 0; 619110#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 619108#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 619106#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 619104#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 619102#L665-42 assume !(1 == ~t1_pc~0); 619099#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 619097#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 619094#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 619092#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 619090#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 601983#L684-42 assume !(1 == ~t2_pc~0); 601984#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 601979#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 601980#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 601975#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 601976#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 601972#L703-42 assume 1 == ~t3_pc~0; 601971#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 601969#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 601968#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 601967#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 601966#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 601965#L722-42 assume !(1 == ~t4_pc~0); 601964#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 601963#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 601962#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 601961#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 601960#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 601959#L741-42 assume !(1 == ~t5_pc~0); 601958#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 601957#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 601956#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 601954#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 601955#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 601949#L760-42 assume 1 == ~t6_pc~0; 601951#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 601943#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 601944#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 601936#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 601931#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 601932#L779-42 assume !(1 == ~t7_pc~0); 601925#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 601922#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 601920#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 601918#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 601914#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 601915#L798-42 assume !(1 == ~t8_pc~0); 601907#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 601905#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 601903#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 601901#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 601899#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 601900#L817-42 assume !(1 == ~t9_pc~0); 601895#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 601893#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 601825#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 601823#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 601820#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 601821#L836-42 assume 1 == ~t10_pc~0; 601813#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 601810#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 601808#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 601777#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 598996#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 598997#L855-42 assume !(1 == ~t11_pc~0); 598989#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 598986#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 598984#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 598982#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 598979#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 598980#L874-42 assume 1 == ~t12_pc~0; 598971#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 598968#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 598966#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 598963#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 598964#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 598955#L893-42 assume 1 == ~t13_pc~0; 598957#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 598948#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 598949#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 598942#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 598943#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 598935#L912-42 assume !(1 == ~t14_pc~0); 598937#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 598928#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 598929#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 598922#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 598923#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 598915#L1495-3 assume !(1 == ~M_E~0); 598916#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 593638#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 598910#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 598904#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 598905#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 598898#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 598899#L1525-3 assume !(1 == ~T7_E~0); 598893#L1530-3 assume !(1 == ~T8_E~0); 598894#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 598887#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 598888#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 598881#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 598882#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 598875#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 598876#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 598869#L1570-3 assume !(1 == ~E_2~0); 598870#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 598863#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 598864#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 598857#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 598858#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 598851#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 598852#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 598846#L1610-3 assume !(1 == ~E_10~0); 598847#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 598840#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 598841#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 598834#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 598835#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 598828#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 598812#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 598810#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 598808#L2036 assume !(0 == start_simulation_~tmp~3#1); 598807#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 598789#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 598788#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 598787#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 598786#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 598785#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 598784#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 598783#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 575508#L2017-2 [2021-11-19 05:32:12,507 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:32:12,507 INFO L85 PathProgramCache]: Analyzing trace with hash -1967410136, now seen corresponding path program 1 times [2021-11-19 05:32:12,507 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:32:12,507 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1141414563] [2021-11-19 05:32:12,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:32:12,507 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:32:12,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:32:12,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:32:12,548 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:32:12,549 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1141414563] [2021-11-19 05:32:12,549 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1141414563] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:32:12,549 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:32:12,549 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:32:12,549 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547986599] [2021-11-19 05:32:12,549 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:32:12,550 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:32:12,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:32:12,551 INFO L85 PathProgramCache]: Analyzing trace with hash 1452255561, now seen corresponding path program 1 times [2021-11-19 05:32:12,551 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:32:12,551 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1247871633] [2021-11-19 05:32:12,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:32:12,551 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:32:12,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:32:12,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:32:12,594 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:32:12,594 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1247871633] [2021-11-19 05:32:12,594 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1247871633] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:32:12,594 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:32:12,594 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:32:12,595 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1947917976] [2021-11-19 05:32:12,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:32:12,595 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:32:12,595 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:32:12,596 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-19 05:32:12,596 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-19 05:32:12,596 INFO L87 Difference]: Start difference. First operand 76108 states and 109316 transitions. cyclomatic complexity: 33232 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:32:13,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:32:13,926 INFO L93 Difference]: Finished difference Result 195991 states and 280149 transitions. [2021-11-19 05:32:13,934 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-19 05:32:13,934 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 195991 states and 280149 transitions. [2021-11-19 05:32:15,139 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 193576 [2021-11-19 05:32:15,560 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 195991 states to 195991 states and 280149 transitions. [2021-11-19 05:32:15,560 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195991 [2021-11-19 05:32:15,636 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195991 [2021-11-19 05:32:15,636 INFO L73 IsDeterministic]: Start isDeterministic. Operand 195991 states and 280149 transitions. [2021-11-19 05:32:15,717 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:32:15,717 INFO L681 BuchiCegarLoop]: Abstraction has 195991 states and 280149 transitions. [2021-11-19 05:32:15,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195991 states and 280149 transitions. [2021-11-19 05:32:17,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195991 to 146119. [2021-11-19 05:32:17,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 146119 states, 146119 states have (on average 1.4324557381312493) internal successors, (209309), 146118 states have internal predecessors, (209309), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:32:18,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146119 states to 146119 states and 209309 transitions. [2021-11-19 05:32:18,512 INFO L704 BuchiCegarLoop]: Abstraction has 146119 states and 209309 transitions. [2021-11-19 05:32:18,512 INFO L587 BuchiCegarLoop]: Abstraction has 146119 states and 209309 transitions. [2021-11-19 05:32:18,512 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-19 05:32:18,512 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 146119 states and 209309 transitions. [2021-11-19 05:32:18,873 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 145664 [2021-11-19 05:32:18,874 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:32:18,874 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:32:18,876 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:32:18,876 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:32:18,876 INFO L791 eck$LassoCheckResult]: Stem: 847653#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 847654#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 848297#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 847369#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 847370#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 847621#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 847622#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 847341#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 847342#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 848665#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 847934#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 847935#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 848522#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 847843#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 847844#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 847248#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 847249#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 847585#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 847792#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 846832#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 846833#L1342 assume !(0 == ~M_E~0); 846997#L1342-2 assume !(0 == ~T1_E~0); 847552#L1347-1 assume !(0 == ~T2_E~0); 848644#L1352-1 assume !(0 == ~T3_E~0); 848412#L1357-1 assume !(0 == ~T4_E~0); 847577#L1362-1 assume !(0 == ~T5_E~0); 847578#L1367-1 assume !(0 == ~T6_E~0); 847171#L1372-1 assume !(0 == ~T7_E~0); 847172#L1377-1 assume !(0 == ~T8_E~0); 847506#L1382-1 assume !(0 == ~T9_E~0); 847507#L1387-1 assume !(0 == ~T10_E~0); 848276#L1392-1 assume !(0 == ~T11_E~0); 847540#L1397-1 assume !(0 == ~T12_E~0); 847541#L1402-1 assume !(0 == ~T13_E~0); 847186#L1407-1 assume !(0 == ~T14_E~0); 847187#L1412-1 assume !(0 == ~E_1~0); 848556#L1417-1 assume !(0 == ~E_2~0); 848557#L1422-1 assume !(0 == ~E_3~0); 848857#L1427-1 assume !(0 == ~E_4~0); 847375#L1432-1 assume !(0 == ~E_5~0); 847376#L1437-1 assume !(0 == ~E_6~0); 848459#L1442-1 assume !(0 == ~E_7~0); 848460#L1447-1 assume !(0 == ~E_8~0); 848271#L1452-1 assume !(0 == ~E_9~0); 846967#L1457-1 assume !(0 == ~E_10~0); 846968#L1462-1 assume !(0 == ~E_11~0); 848498#L1467-1 assume !(0 == ~E_12~0); 848515#L1472-1 assume !(0 == ~E_13~0); 848516#L1477-1 assume !(0 == ~E_14~0); 848211#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 847165#L646 assume !(1 == ~m_pc~0); 847166#L646-2 is_master_triggered_~__retres1~0#1 := 0; 847871#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 847872#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 847250#L1666 assume !(0 != activate_threads_~tmp~1#1); 847251#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 848891#L665 assume !(1 == ~t1_pc~0); 847736#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 847737#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 847259#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 847260#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 848076#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 848077#L684 assume !(1 == ~t2_pc~0); 848119#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 848120#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 848196#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 848649#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 848650#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 848907#L703 assume !(1 == ~t3_pc~0); 847397#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 847398#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 848068#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 846802#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 846803#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 847281#L722 assume !(1 == ~t4_pc~0); 847464#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 847465#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 847823#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 848440#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 847896#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 846998#L741 assume !(1 == ~t5_pc~0); 846999#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 848110#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 847462#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 847463#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 848173#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 847553#L760 assume !(1 == ~t6_pc~0); 847396#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 848025#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 848975#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 848844#L1714 assume !(0 != activate_threads_~tmp___5~0#1); 847994#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 847995#L779 assume !(1 == ~t7_pc~0); 848710#L779-2 is_transmit7_triggered_~__retres1~7#1 := 0; 846890#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 846891#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 847292#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 847315#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 847316#L798 assume !(1 == ~t8_pc~0); 848702#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 848614#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 847041#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 847042#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 848893#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 846867#L817 assume 1 == ~t9_pc~0; 846868#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 847661#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 847662#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 848217#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 847266#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 847267#L836 assume !(1 == ~t10_pc~0); 847283#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 847214#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 847215#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 847466#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 847467#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 848626#L855 assume 1 == ~t11_pc~0; 847867#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 847868#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 848493#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 848267#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 848083#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 847157#L874 assume !(1 == ~t12_pc~0); 847158#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 847324#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 847325#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 847468#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 846840#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 846841#L893 assume 1 == ~t13_pc~0; 848797#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 847189#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 847505#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 848696#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 848707#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 848708#L912 assume 1 == ~t14_pc~0; 848466#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 848467#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 847160#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 847091#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 847092#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 847889#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 848336#L1495-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 848337#L1500-1 assume !(1 == ~T2_E~0); 847990#L1505-1 assume !(1 == ~T3_E~0); 847991#L1510-1 assume !(1 == ~T4_E~0); 848051#L1515-1 assume !(1 == ~T5_E~0); 848052#L1520-1 assume !(1 == ~T6_E~0); 848704#L1525-1 assume !(1 == ~T7_E~0); 848705#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 847261#L1535-1 assume !(1 == ~T9_E~0); 847262#L1540-1 assume !(1 == ~T10_E~0); 846761#L1545-1 assume !(1 == ~T11_E~0); 846762#L1550-1 assume !(1 == ~T12_E~0); 847007#L1555-1 assume !(1 == ~T13_E~0); 847008#L1560-1 assume !(1 == ~T14_E~0); 848870#L1565-1 assume !(1 == ~E_1~0); 848871#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 848237#L1575-1 assume !(1 == ~E_3~0); 848238#L1580-1 assume !(1 == ~E_4~0); 848070#L1585-1 assume !(1 == ~E_5~0); 848071#L1590-1 assume !(1 == ~E_6~0); 847615#L1595-1 assume !(1 == ~E_7~0); 847616#L1600-1 assume !(1 == ~E_8~0); 848002#L1605-1 assume !(1 == ~E_9~0); 848003#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 848596#L1615-1 assume !(1 == ~E_11~0); 847440#L1620-1 assume !(1 == ~E_12~0); 847441#L1625-1 assume !(1 == ~E_13~0); 848272#L1630-1 assume !(1 == ~E_14~0); 847613#L1635-1 assume { :end_inline_reset_delta_events } true; 847614#L2017-2 [2021-11-19 05:32:18,877 INFO L793 eck$LassoCheckResult]: Loop: 847614#L2017-2 assume !false; 914992#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 914985#L1316 assume !false; 914981#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 914949#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 914933#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 914928#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 914922#L1115 assume !(0 != eval_~tmp~0#1); 914923#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 917552#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 917517#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 917506#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 917075#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 917074#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 917073#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 917040#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 917033#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 917031#L1372-3 assume !(0 == ~T7_E~0); 917029#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 917027#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 917025#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 917023#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 917020#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 917018#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 917016#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 917014#L1412-3 assume !(0 == ~E_1~0); 917012#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 917010#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 917007#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 917005#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 917003#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 917001#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 916999#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 916997#L1452-3 assume !(0 == ~E_9~0); 916994#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 916992#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 916990#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 916988#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 916932#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 916930#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 916928#L646-42 assume !(1 == ~m_pc~0); 916926#L646-44 is_master_triggered_~__retres1~0#1 := 0; 916924#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 916922#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 916919#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 916917#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 916869#L665-42 assume !(1 == ~t1_pc~0); 916861#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 916856#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 916850#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 916845#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 916840#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 916834#L684-42 assume !(1 == ~t2_pc~0); 903951#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 916823#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 916818#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 916813#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 916808#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 916802#L703-42 assume 1 == ~t3_pc~0; 916795#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 916789#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 916784#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 916779#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 916774#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 916770#L722-42 assume !(1 == ~t4_pc~0); 916763#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 916757#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 916751#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 916745#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 916739#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 916738#L741-42 assume !(1 == ~t5_pc~0); 916737#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 916735#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 916733#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 916731#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 916729#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 916728#L760-42 assume 1 == ~t6_pc~0; 916727#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 916725#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 916723#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 916711#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 916704#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 916698#L779-42 assume !(1 == ~t7_pc~0); 889949#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 916687#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 916682#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 916678#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 916673#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 916668#L798-42 assume 1 == ~t8_pc~0; 916664#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 916658#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 916653#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 916647#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 916642#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 916637#L817-42 assume !(1 == ~t9_pc~0); 916631#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 916624#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 916618#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 916610#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 916603#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 916596#L836-42 assume 1 == ~t10_pc~0; 916589#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 916582#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 916576#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 916570#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 916564#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 916559#L855-42 assume 1 == ~t11_pc~0; 916553#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 916548#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 916543#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 916535#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 916529#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 916523#L874-42 assume 1 == ~t12_pc~0; 916517#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 916509#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 916503#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 916495#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 916488#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 916482#L893-42 assume !(1 == ~t13_pc~0); 916476#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 916471#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 916466#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 916460#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 916457#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 916452#L912-42 assume 1 == ~t14_pc~0; 916447#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 916444#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 915991#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 915988#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 915986#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 915984#L1495-3 assume !(1 == ~M_E~0); 915982#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 899291#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 915979#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 915976#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 915974#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 915859#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 915845#L1525-3 assume !(1 == ~T7_E~0); 915838#L1530-3 assume !(1 == ~T8_E~0); 915831#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 915824#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 915814#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 915807#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 915800#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 915793#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 915786#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 915775#L1570-3 assume !(1 == ~E_2~0); 915199#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 915198#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 915197#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 915196#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 915195#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 915194#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 915193#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 906674#L1610-3 assume !(1 == ~E_10~0); 915191#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 915189#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 915187#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 915185#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 915183#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 915180#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 915164#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 915162#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 915160#L2036 assume !(0 == start_simulation_~tmp~3#1); 915158#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 915060#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 915058#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 915056#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 915054#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 915053#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 915052#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 915007#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 847614#L2017-2 [2021-11-19 05:32:18,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:32:18,878 INFO L85 PathProgramCache]: Analyzing trace with hash 1050404487, now seen corresponding path program 1 times [2021-11-19 05:32:18,878 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:32:18,878 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1344154355] [2021-11-19 05:32:18,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:32:18,879 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:32:18,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:32:18,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:32:18,922 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:32:18,922 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1344154355] [2021-11-19 05:32:18,922 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1344154355] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:32:18,922 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:32:18,922 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:32:18,923 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [98530009] [2021-11-19 05:32:18,923 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:32:18,923 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:32:18,923 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:32:18,924 INFO L85 PathProgramCache]: Analyzing trace with hash 1755102731, now seen corresponding path program 1 times [2021-11-19 05:32:18,924 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:32:18,924 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887320191] [2021-11-19 05:32:18,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:32:18,924 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:32:18,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:32:18,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:32:18,972 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:32:18,972 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1887320191] [2021-11-19 05:32:18,972 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1887320191] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:32:18,972 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:32:18,973 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:32:18,973 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1383472415] [2021-11-19 05:32:18,973 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:32:18,973 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:32:18,973 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:32:18,974 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-19 05:32:18,974 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-19 05:32:18,974 INFO L87 Difference]: Start difference. First operand 146119 states and 209309 transitions. cyclomatic complexity: 63214 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:32:20,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:32:20,767 INFO L93 Difference]: Finished difference Result 374934 states and 534634 transitions. [2021-11-19 05:32:20,768 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-19 05:32:20,768 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 374934 states and 534634 transitions. [2021-11-19 05:32:23,094 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 370352 [2021-11-19 05:32:24,615 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 374934 states to 374934 states and 534634 transitions. [2021-11-19 05:32:24,615 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 374934 [2021-11-19 05:32:24,701 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 374934 [2021-11-19 05:32:24,701 INFO L73 IsDeterministic]: Start isDeterministic. Operand 374934 states and 534634 transitions. [2021-11-19 05:32:24,821 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-19 05:32:24,822 INFO L681 BuchiCegarLoop]: Abstraction has 374934 states and 534634 transitions. [2021-11-19 05:32:24,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 374934 states and 534634 transitions. [2021-11-19 05:32:27,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 374934 to 280374. [2021-11-19 05:32:27,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 280374 states, 280374 states have (on average 1.4289270759770878) internal successors, (400634), 280373 states have internal predecessors, (400634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:32:28,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280374 states to 280374 states and 400634 transitions. [2021-11-19 05:32:28,521 INFO L704 BuchiCegarLoop]: Abstraction has 280374 states and 400634 transitions. [2021-11-19 05:32:28,521 INFO L587 BuchiCegarLoop]: Abstraction has 280374 states and 400634 transitions. [2021-11-19 05:32:28,521 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-11-19 05:32:28,521 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 280374 states and 400634 transitions. [2021-11-19 05:32:30,222 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 279696 [2021-11-19 05:32:30,223 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-19 05:32:30,223 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-19 05:32:30,226 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:32:30,226 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-19 05:32:30,227 INFO L791 eck$LassoCheckResult]: Stem: 1368713#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 1368714#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 1369359#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1368428#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1368429#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 1368680#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1368681#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1368400#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1368401#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1369743#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1368997#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1368998#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1369590#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1368899#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1368900#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1368306#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1368307#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1368644#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1368850#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 1367894#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1367895#L1342 assume !(0 == ~M_E~0); 1368058#L1342-2 assume !(0 == ~T1_E~0); 1368610#L1347-1 assume !(0 == ~T2_E~0); 1369720#L1352-1 assume !(0 == ~T3_E~0); 1369474#L1357-1 assume !(0 == ~T4_E~0); 1368635#L1362-1 assume !(0 == ~T5_E~0); 1368636#L1367-1 assume !(0 == ~T6_E~0); 1368227#L1372-1 assume !(0 == ~T7_E~0); 1368228#L1377-1 assume !(0 == ~T8_E~0); 1368563#L1382-1 assume !(0 == ~T9_E~0); 1368564#L1387-1 assume !(0 == ~T10_E~0); 1369337#L1392-1 assume !(0 == ~T11_E~0); 1368598#L1397-1 assume !(0 == ~T12_E~0); 1368599#L1402-1 assume !(0 == ~T13_E~0); 1368242#L1407-1 assume !(0 == ~T14_E~0); 1368243#L1412-1 assume !(0 == ~E_1~0); 1369627#L1417-1 assume !(0 == ~E_2~0); 1369628#L1422-1 assume !(0 == ~E_3~0); 1369988#L1427-1 assume !(0 == ~E_4~0); 1368434#L1432-1 assume !(0 == ~E_5~0); 1368435#L1437-1 assume !(0 == ~E_6~0); 1369526#L1442-1 assume !(0 == ~E_7~0); 1369527#L1447-1 assume !(0 == ~E_8~0); 1369332#L1452-1 assume !(0 == ~E_9~0); 1368030#L1457-1 assume !(0 == ~E_10~0); 1368031#L1462-1 assume !(0 == ~E_11~0); 1369569#L1467-1 assume !(0 == ~E_12~0); 1369585#L1472-1 assume !(0 == ~E_13~0); 1369586#L1477-1 assume !(0 == ~E_14~0); 1369274#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1368221#L646 assume !(1 == ~m_pc~0); 1368222#L646-2 is_master_triggered_~__retres1~0#1 := 0; 1368928#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1368929#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1368308#L1666 assume !(0 != activate_threads_~tmp~1#1); 1368309#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1370030#L665 assume !(1 == ~t1_pc~0); 1368795#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1368796#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1368315#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1368316#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 1369137#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1369138#L684 assume !(1 == ~t2_pc~0); 1369180#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1369181#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1369258#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1369727#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 1369728#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1370047#L703 assume !(1 == ~t3_pc~0); 1368456#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1368457#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1369129#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1367865#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 1367866#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1368337#L722 assume !(1 == ~t4_pc~0); 1368522#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1368523#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1368879#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1369509#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 1368953#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1368059#L741 assume !(1 == ~t5_pc~0); 1368060#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1369171#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1368520#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1368521#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 1369236#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1368611#L760 assume !(1 == ~t6_pc~0); 1368455#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1369088#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1370133#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1369973#L1714 assume !(0 != activate_threads_~tmp___5~0#1); 1369058#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1369059#L779 assume !(1 == ~t7_pc~0); 1369802#L779-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1367951#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1367952#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1368348#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 1368372#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1368373#L798 assume !(1 == ~t8_pc~0); 1369793#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1369684#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1368101#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1368102#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 1370032#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1367929#L817 assume !(1 == ~t9_pc~0); 1367930#L817-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1368721#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1368722#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1369280#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 1368322#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1368323#L836 assume !(1 == ~t10_pc~0); 1368339#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1368270#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1368271#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1368524#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 1368525#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1369697#L855 assume 1 == ~t11_pc~0; 1368924#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1368925#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1369558#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1369329#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 1369144#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1368213#L874 assume !(1 == ~t12_pc~0); 1368214#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1368381#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1368382#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1368526#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 1367904#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1367905#L893 assume 1 == ~t13_pc~0; 1369906#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1368245#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1368562#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1369787#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 1369797#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1369798#L912 assume 1 == ~t14_pc~0; 1369534#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 1369535#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1368216#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1368151#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 1368152#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1368946#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 1369398#L1495-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1369399#L1500-1 assume !(1 == ~T2_E~0); 1369054#L1505-1 assume !(1 == ~T3_E~0); 1369055#L1510-1 assume !(1 == ~T4_E~0); 1369113#L1515-1 assume !(1 == ~T5_E~0); 1369114#L1520-1 assume !(1 == ~T6_E~0); 1369795#L1525-1 assume !(1 == ~T7_E~0); 1369796#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1368317#L1535-1 assume !(1 == ~T9_E~0); 1368318#L1540-1 assume !(1 == ~T10_E~0); 1367824#L1545-1 assume !(1 == ~T11_E~0); 1367825#L1550-1 assume !(1 == ~T12_E~0); 1368068#L1555-1 assume !(1 == ~T13_E~0); 1368069#L1560-1 assume !(1 == ~T14_E~0); 1370003#L1565-1 assume !(1 == ~E_1~0); 1370004#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1369299#L1575-1 assume !(1 == ~E_3~0); 1369300#L1580-1 assume !(1 == ~E_4~0); 1369131#L1585-1 assume !(1 == ~E_5~0); 1369132#L1590-1 assume !(1 == ~E_6~0); 1368674#L1595-1 assume !(1 == ~E_7~0); 1368675#L1600-1 assume !(1 == ~E_8~0); 1369067#L1605-1 assume !(1 == ~E_9~0); 1369068#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1593121#L1615-1 assume !(1 == ~E_11~0); 1593120#L1620-1 assume !(1 == ~E_12~0); 1593119#L1625-1 assume !(1 == ~E_13~0); 1369333#L1630-1 assume !(1 == ~E_14~0); 1368672#L1635-1 assume { :end_inline_reset_delta_events } true; 1368673#L2017-2 [2021-11-19 05:32:30,228 INFO L793 eck$LassoCheckResult]: Loop: 1368673#L2017-2 assume !false; 1596699#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1596694#L1316 assume !false; 1596692#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1596303#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1596291#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1596282#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1596271#L1115 assume !(0 != eval_~tmp~0#1); 1596272#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1646283#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1646281#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1646279#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1646277#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1646275#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1646274#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1646272#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1646270#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1646268#L1372-3 assume !(0 == ~T7_E~0); 1646266#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1646264#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1646261#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1646259#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1646257#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1646255#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1646253#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 1646251#L1412-3 assume !(0 == ~E_1~0); 1646248#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1646246#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1646244#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1646242#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1646240#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1646238#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1646235#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1646233#L1452-3 assume !(0 == ~E_9~0); 1646231#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1646229#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1646227#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1646224#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1646217#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 1646216#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1646215#L646-42 assume !(1 == ~m_pc~0); 1646214#L646-44 is_master_triggered_~__retres1~0#1 := 0; 1646213#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1646212#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1646210#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1646209#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1646205#L665-42 assume 1 == ~t1_pc~0; 1646200#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1646194#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1646187#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1646183#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1646181#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1597293#L684-42 assume !(1 == ~t2_pc~0); 1597291#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1597288#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1597286#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1597284#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1597282#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1597280#L703-42 assume !(1 == ~t3_pc~0); 1597277#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1597275#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1597274#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1597272#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1597270#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1597268#L722-42 assume !(1 == ~t4_pc~0); 1597266#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1597264#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1597262#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1597260#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1597258#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1597256#L741-42 assume !(1 == ~t5_pc~0); 1597254#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1597252#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1597250#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1597248#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1597247#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1597245#L760-42 assume 1 == ~t6_pc~0; 1597242#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1597240#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1597238#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1597236#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 1597233#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1597231#L779-42 assume !(1 == ~t7_pc~0); 1595820#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1597229#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1597227#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1597225#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1597223#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1597222#L798-42 assume !(1 == ~t8_pc~0); 1597220#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1597219#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1597218#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1597217#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1597216#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1597215#L817-42 assume !(1 == ~t9_pc~0); 1433908#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1597214#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1597213#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1597212#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1597211#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1597210#L836-42 assume !(1 == ~t10_pc~0); 1597208#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1597207#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1597206#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1597205#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1597204#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1597203#L855-42 assume 1 == ~t11_pc~0; 1597201#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1597199#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1597198#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1597197#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1597196#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1597195#L874-42 assume !(1 == ~t12_pc~0); 1597193#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 1597192#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1597190#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1597188#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1597186#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1597184#L893-42 assume 1 == ~t13_pc~0; 1597181#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1597179#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1597177#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1597174#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 1597172#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1597170#L912-42 assume 1 == ~t14_pc~0; 1597167#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 1597165#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1597163#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1597161#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 1597159#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1597157#L1495-3 assume !(1 == ~M_E~0); 1597155#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1575195#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1597152#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1597150#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1597148#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1597146#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1597144#L1525-3 assume !(1 == ~T7_E~0); 1597142#L1530-3 assume !(1 == ~T8_E~0); 1597138#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1597136#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1597134#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1597132#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1597129#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1597127#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 1597125#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1593408#L1570-3 assume !(1 == ~E_2~0); 1597123#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1597121#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1597119#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1597117#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1597115#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1597112#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1597110#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1592129#L1610-3 assume !(1 == ~E_10~0); 1597107#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1597105#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1597103#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1597102#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 1597100#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1597097#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1597081#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1597079#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1597075#L2036 assume !(0 == start_simulation_~tmp~3#1); 1597072#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1596747#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1596736#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1596728#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1596718#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1596714#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1596712#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1596710#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 1368673#L2017-2 [2021-11-19 05:32:30,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:32:30,228 INFO L85 PathProgramCache]: Analyzing trace with hash -127570074, now seen corresponding path program 1 times [2021-11-19 05:32:30,229 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:32:30,229 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [304383810] [2021-11-19 05:32:30,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:32:30,229 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:32:30,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:32:30,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:32:30,277 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:32:30,277 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [304383810] [2021-11-19 05:32:30,277 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [304383810] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:32:30,277 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:32:30,277 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:32:30,278 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386115807] [2021-11-19 05:32:30,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:32:30,279 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-19 05:32:30,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-19 05:32:30,279 INFO L85 PathProgramCache]: Analyzing trace with hash -415259127, now seen corresponding path program 1 times [2021-11-19 05:32:30,279 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-19 05:32:30,280 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2138124734] [2021-11-19 05:32:30,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-19 05:32:30,280 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-19 05:32:30,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-19 05:32:30,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-19 05:32:30,325 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-19 05:32:30,326 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2138124734] [2021-11-19 05:32:30,326 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2138124734] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-19 05:32:30,326 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-19 05:32:30,326 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-19 05:32:30,326 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1728730756] [2021-11-19 05:32:30,327 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-19 05:32:30,327 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-19 05:32:30,327 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-19 05:32:30,328 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-19 05:32:30,328 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-19 05:32:30,328 INFO L87 Difference]: Start difference. First operand 280374 states and 400634 transitions. cyclomatic complexity: 120284 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-19 05:32:33,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-19 05:32:33,362 INFO L93 Difference]: Finished difference Result 716261 states and 1019079 transitions. [2021-11-19 05:32:33,363 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-19 05:32:33,363 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 716261 states and 1019079 transitions.