./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-15/array16_alloca_fixed.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 53f42b1a Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-15/array16_alloca_fixed.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 2a580f3a42bca030605af1bbd4c6a77550e46d88a6197c1e34cf45bb050eadef --- Real Ultimate output --- This is Ultimate 0.2.1-dev-53f42b1 [2021-11-20 05:56:26,368 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-20 05:56:26,370 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-20 05:56:26,428 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-20 05:56:26,429 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-20 05:56:26,435 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-20 05:56:26,437 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-20 05:56:26,440 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-20 05:56:26,442 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-20 05:56:26,444 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-20 05:56:26,445 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-20 05:56:26,447 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-20 05:56:26,447 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-20 05:56:26,449 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-20 05:56:26,451 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-20 05:56:26,452 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-20 05:56:26,454 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-20 05:56:26,459 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-20 05:56:26,467 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-20 05:56:26,475 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-20 05:56:26,478 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-20 05:56:26,486 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-20 05:56:26,488 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-20 05:56:26,489 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-20 05:56:26,493 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-20 05:56:26,494 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-20 05:56:26,494 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-20 05:56:26,496 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-20 05:56:26,496 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-20 05:56:26,498 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-20 05:56:26,498 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-20 05:56:26,507 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-20 05:56:26,509 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-20 05:56:26,510 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-20 05:56:26,513 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-20 05:56:26,513 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-20 05:56:26,514 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-20 05:56:26,514 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-20 05:56:26,515 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-20 05:56:26,516 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-20 05:56:26,517 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-20 05:56:26,518 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/config/svcomp-Termination-64bit-Automizer_Default.epf [2021-11-20 05:56:26,575 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-20 05:56:26,575 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-20 05:56:26,576 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-20 05:56:26,576 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-20 05:56:26,577 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-20 05:56:26,578 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-20 05:56:26,578 INFO L138 SettingsManager]: * Use SBE=true [2021-11-20 05:56:26,578 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-20 05:56:26,579 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-20 05:56:26,579 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-20 05:56:26,579 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-20 05:56:26,579 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-20 05:56:26,580 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-20 05:56:26,580 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-20 05:56:26,580 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-20 05:56:26,581 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-20 05:56:26,581 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-20 05:56:26,581 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-20 05:56:26,581 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-20 05:56:26,582 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-20 05:56:26,582 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-20 05:56:26,582 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-20 05:56:26,582 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-20 05:56:26,583 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-20 05:56:26,583 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-20 05:56:26,583 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-20 05:56:26,584 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-20 05:56:26,584 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-20 05:56:26,584 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-20 05:56:26,585 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-20 05:56:26,586 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2a580f3a42bca030605af1bbd4c6a77550e46d88a6197c1e34cf45bb050eadef [2021-11-20 05:56:26,884 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-20 05:56:26,909 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-20 05:56:26,912 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-20 05:56:26,913 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-20 05:56:26,914 INFO L275 PluginConnector]: CDTParser initialized [2021-11-20 05:56:26,916 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/../../sv-benchmarks/c/termination-15/array16_alloca_fixed.i [2021-11-20 05:56:26,977 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/data/07867e5ea/7aacdade14944b5089315fa52eb76cdc/FLAG8b76da17d [2021-11-20 05:56:27,502 INFO L306 CDTParser]: Found 1 translation units. [2021-11-20 05:56:27,502 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/sv-benchmarks/c/termination-15/array16_alloca_fixed.i [2021-11-20 05:56:27,513 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/data/07867e5ea/7aacdade14944b5089315fa52eb76cdc/FLAG8b76da17d [2021-11-20 05:56:27,947 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/data/07867e5ea/7aacdade14944b5089315fa52eb76cdc [2021-11-20 05:56:27,953 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-20 05:56:27,958 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-20 05:56:27,963 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-20 05:56:27,964 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-20 05:56:27,969 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-20 05:56:27,969 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 05:56:27" (1/1) ... [2021-11-20 05:56:27,972 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@597b92ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:56:27, skipping insertion in model container [2021-11-20 05:56:27,972 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 05:56:27" (1/1) ... [2021-11-20 05:56:27,981 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-20 05:56:28,039 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-20 05:56:28,462 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-20 05:56:28,473 INFO L203 MainTranslator]: Completed pre-run [2021-11-20 05:56:28,548 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-20 05:56:28,589 INFO L208 MainTranslator]: Completed translation [2021-11-20 05:56:28,589 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:56:28 WrapperNode [2021-11-20 05:56:28,589 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-20 05:56:28,590 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-20 05:56:28,591 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-20 05:56:28,591 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-20 05:56:28,598 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:56:28" (1/1) ... [2021-11-20 05:56:28,610 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:56:28" (1/1) ... [2021-11-20 05:56:28,631 INFO L137 Inliner]: procedures = 151, calls = 10, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 54 [2021-11-20 05:56:28,631 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-20 05:56:28,632 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-20 05:56:28,632 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-20 05:56:28,632 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-20 05:56:28,640 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:56:28" (1/1) ... [2021-11-20 05:56:28,641 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:56:28" (1/1) ... [2021-11-20 05:56:28,643 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:56:28" (1/1) ... [2021-11-20 05:56:28,643 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:56:28" (1/1) ... [2021-11-20 05:56:28,648 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:56:28" (1/1) ... [2021-11-20 05:56:28,651 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:56:28" (1/1) ... [2021-11-20 05:56:28,653 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:56:28" (1/1) ... [2021-11-20 05:56:28,655 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-20 05:56:28,656 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-20 05:56:28,656 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-20 05:56:28,656 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-20 05:56:28,657 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:56:28" (1/1) ... [2021-11-20 05:56:28,665 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:56:28,677 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:28,692 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 05:56:28,702 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-20 05:56:28,729 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2021-11-20 05:56:28,729 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-11-20 05:56:28,730 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-20 05:56:28,730 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-11-20 05:56:28,730 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-20 05:56:28,730 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-20 05:56:28,798 INFO L236 CfgBuilder]: Building ICFG [2021-11-20 05:56:28,800 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-11-20 05:56:28,917 INFO L277 CfgBuilder]: Performing block encoding [2021-11-20 05:56:28,922 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-20 05:56:28,923 INFO L301 CfgBuilder]: Removed 2 assume(true) statements. [2021-11-20 05:56:28,924 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 05:56:28 BoogieIcfgContainer [2021-11-20 05:56:28,925 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-20 05:56:28,925 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-20 05:56:28,926 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-20 05:56:28,929 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-20 05:56:28,932 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 05:56:28,932 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 20.11 05:56:27" (1/3) ... [2021-11-20 05:56:28,933 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4a17a963 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 05:56:28, skipping insertion in model container [2021-11-20 05:56:28,933 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 05:56:28,933 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:56:28" (2/3) ... [2021-11-20 05:56:28,933 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4a17a963 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 05:56:28, skipping insertion in model container [2021-11-20 05:56:28,934 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 05:56:28,934 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 05:56:28" (3/3) ... [2021-11-20 05:56:28,935 INFO L388 chiAutomizerObserver]: Analyzing ICFG array16_alloca_fixed.i [2021-11-20 05:56:29,005 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-20 05:56:29,006 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-20 05:56:29,006 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-20 05:56:29,006 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-20 05:56:29,006 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-20 05:56:29,007 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-20 05:56:29,007 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-20 05:56:29,007 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-20 05:56:29,021 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:29,040 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2021-11-20 05:56:29,040 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:56:29,040 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:56:29,046 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2021-11-20 05:56:29,046 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-20 05:56:29,047 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-20 05:56:29,047 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:29,049 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2021-11-20 05:56:29,050 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:56:29,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:56:29,051 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2021-11-20 05:56:29,051 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-20 05:56:29,058 INFO L791 eck$LassoCheckResult]: Stem: 4#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11#L367true assume !(main_~length~0#1 < 1); 8#L367-2true call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5#L369true assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6#L370-3true [2021-11-20 05:56:29,058 INFO L793 eck$LassoCheckResult]: Loop: 6#L370-3true assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13#L372true assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16#L370-2true main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6#L370-3true [2021-11-20 05:56:29,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:29,083 INFO L85 PathProgramCache]: Analyzing trace with hash 28695753, now seen corresponding path program 1 times [2021-11-20 05:56:29,093 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:29,094 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [901190241] [2021-11-20 05:56:29,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:29,095 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:29,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:29,272 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:56:29,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:29,331 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:56:29,335 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:29,335 INFO L85 PathProgramCache]: Analyzing trace with hash 51737, now seen corresponding path program 1 times [2021-11-20 05:56:29,336 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:29,337 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2003996252] [2021-11-20 05:56:29,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:29,339 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:29,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:29,387 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:56:29,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:29,424 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:56:29,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:29,428 INFO L85 PathProgramCache]: Analyzing trace with hash 176707665, now seen corresponding path program 1 times [2021-11-20 05:56:29,428 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:29,429 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1540009926] [2021-11-20 05:56:29,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:29,429 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:29,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:29,485 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:56:29,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:29,600 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:56:29,961 INFO L210 LassoAnalysis]: Preferences: [2021-11-20 05:56:29,962 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-11-20 05:56:29,962 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-11-20 05:56:29,962 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-11-20 05:56:29,963 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-11-20 05:56:29,963 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:56:29,963 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-11-20 05:56:29,963 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-11-20 05:56:29,964 INFO L133 ssoRankerPreferences]: Filename of dumped script: array16_alloca_fixed.i_Iteration1_Lasso [2021-11-20 05:56:29,964 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-11-20 05:56:29,964 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-11-20 05:56:29,983 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:29,989 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:29,992 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:29,995 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:29,998 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:30,096 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:30,099 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:30,101 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:30,104 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:30,107 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:30,110 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:30,113 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:30,348 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-11-20 05:56:30,352 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-11-20 05:56:30,354 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:56:30,354 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:30,360 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 05:56:30,364 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2021-11-20 05:56:30,364 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-20 05:56:30,375 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-20 05:56:30,375 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-20 05:56:30,376 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-20 05:56:30,376 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-20 05:56:30,376 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-20 05:56:30,379 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-20 05:56:30,379 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-20 05:56:30,396 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-20 05:56:30,421 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2021-11-20 05:56:30,421 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:56:30,421 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:30,423 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 05:56:30,426 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2021-11-20 05:56:30,426 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-20 05:56:30,435 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-20 05:56:30,436 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-20 05:56:30,436 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-20 05:56:30,436 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-20 05:56:30,440 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-20 05:56:30,440 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-20 05:56:30,451 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-20 05:56:30,491 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2021-11-20 05:56:30,492 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:56:30,492 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:30,493 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 05:56:30,503 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2021-11-20 05:56:30,503 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-20 05:56:30,513 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-20 05:56:30,513 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-20 05:56:30,513 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-20 05:56:30,513 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-20 05:56:30,514 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-20 05:56:30,515 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-20 05:56:30,515 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-20 05:56:30,531 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-20 05:56:30,567 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2021-11-20 05:56:30,567 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:56:30,568 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:30,569 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 05:56:30,580 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-20 05:56:30,589 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-20 05:56:30,590 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-20 05:56:30,590 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-20 05:56:30,590 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-20 05:56:30,590 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-20 05:56:30,591 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-20 05:56:30,592 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-20 05:56:30,593 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2021-11-20 05:56:30,603 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-20 05:56:30,643 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2021-11-20 05:56:30,643 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:56:30,643 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:30,644 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 05:56:30,648 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-20 05:56:30,648 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2021-11-20 05:56:30,658 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-20 05:56:30,658 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-20 05:56:30,658 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-20 05:56:30,659 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-20 05:56:30,659 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-20 05:56:30,660 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-20 05:56:30,660 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-20 05:56:30,675 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-20 05:56:30,710 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2021-11-20 05:56:30,711 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:56:30,711 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:30,712 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 05:56:30,736 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-20 05:56:30,748 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-20 05:56:30,748 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-20 05:56:30,748 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-20 05:56:30,748 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-20 05:56:30,755 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-20 05:56:30,755 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-20 05:56:30,760 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2021-11-20 05:56:30,790 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-20 05:56:30,832 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2021-11-20 05:56:30,832 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:56:30,832 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:30,833 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 05:56:30,834 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2021-11-20 05:56:30,835 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-20 05:56:30,846 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-20 05:56:30,847 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-20 05:56:30,847 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-20 05:56:30,847 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-20 05:56:30,852 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-20 05:56:30,852 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-20 05:56:30,875 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-20 05:56:30,908 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2021-11-20 05:56:30,908 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:56:30,908 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:30,910 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 05:56:30,912 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2021-11-20 05:56:30,913 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-20 05:56:30,922 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-20 05:56:30,923 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-20 05:56:30,923 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-20 05:56:30,923 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-20 05:56:30,934 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-20 05:56:30,934 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-20 05:56:30,963 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-11-20 05:56:31,007 INFO L443 ModelExtractionUtils]: Simplification made 13 calls to the SMT solver. [2021-11-20 05:56:31,007 INFO L444 ModelExtractionUtils]: 6 out of 22 variables were initially zero. Simplification set additionally 12 variables to zero. [2021-11-20 05:56:31,009 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:56:31,009 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:31,040 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 05:56:31,103 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2021-11-20 05:56:31,104 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-11-20 05:56:31,126 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2021-11-20 05:56:31,126 INFO L513 LassoAnalysis]: Proved termination. [2021-11-20 05:56:31,127 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1, ULTIMATE.start_main_~arr~0#1.offset) = -4*ULTIMATE.start_main_~i~0#1 + 1*v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1 - 1*ULTIMATE.start_main_~arr~0#1.offset Supporting invariants [] [2021-11-20 05:56:31,168 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2021-11-20 05:56:31,180 INFO L297 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2021-11-20 05:56:31,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:31,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:56:31,229 INFO L263 TraceCheckSpWp]: Trace formula consists of 26 conjuncts, 2 conjunts are in the unsatisfiable core [2021-11-20 05:56:31,231 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 05:56:31,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:56:31,283 INFO L263 TraceCheckSpWp]: Trace formula consists of 18 conjuncts, 4 conjunts are in the unsatisfiable core [2021-11-20 05:56:31,283 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 05:56:31,344 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2021-11-20 05:56:31,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:31,435 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-11-20 05:56:31,437 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:31,503 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 35 states and 50 transitions. Complement of second has 7 states. [2021-11-20 05:56:31,508 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2021-11-20 05:56:31,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:31,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 33 transitions. [2021-11-20 05:56:31,516 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 3 letters. [2021-11-20 05:56:31,517 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-20 05:56:31,518 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 8 letters. Loop has 3 letters. [2021-11-20 05:56:31,518 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-20 05:56:31,518 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 6 letters. [2021-11-20 05:56:31,519 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-20 05:56:31,520 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 50 transitions. [2021-11-20 05:56:31,524 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:56:31,528 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 12 states and 17 transitions. [2021-11-20 05:56:31,529 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-20 05:56:31,530 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2021-11-20 05:56:31,530 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 17 transitions. [2021-11-20 05:56:31,531 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:56:31,531 INFO L681 BuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2021-11-20 05:56:31,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 17 transitions. [2021-11-20 05:56:31,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 12. [2021-11-20 05:56:31,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 11 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:31,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 17 transitions. [2021-11-20 05:56:31,563 INFO L704 BuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2021-11-20 05:56:31,563 INFO L587 BuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2021-11-20 05:56:31,563 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-20 05:56:31,563 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 17 transitions. [2021-11-20 05:56:31,564 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:56:31,565 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:56:31,565 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:56:31,565 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:56:31,565 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 05:56:31,566 INFO L791 eck$LassoCheckResult]: Stem: 113#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 114#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 121#L367 assume !(main_~length~0#1 < 1); 115#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 116#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 117#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 118#L370-4 main_~j~0#1 := 0; 119#L378-2 [2021-11-20 05:56:31,566 INFO L793 eck$LassoCheckResult]: Loop: 119#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 120#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 119#L378-2 [2021-11-20 05:56:31,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:31,567 INFO L85 PathProgramCache]: Analyzing trace with hash 1806815510, now seen corresponding path program 1 times [2021-11-20 05:56:31,567 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:31,567 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1507777287] [2021-11-20 05:56:31,568 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:31,568 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:31,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:56:31,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:31,623 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:56:31,623 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1507777287] [2021-11-20 05:56:31,624 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1507777287] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:56:31,624 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:56:31,625 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-11-20 05:56:31,625 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1235856999] [2021-11-20 05:56:31,626 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:56:31,628 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:56:31,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:31,629 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 1 times [2021-11-20 05:56:31,629 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:31,629 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [614710088] [2021-11-20 05:56:31,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:31,630 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:31,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:31,639 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:56:31,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:31,649 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:56:31,738 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:56:31,741 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 05:56:31,742 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2021-11-20 05:56:31,744 INFO L87 Difference]: Start difference. First operand 12 states and 17 transitions. cyclomatic complexity: 7 Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 4 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:31,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:56:31,777 INFO L93 Difference]: Finished difference Result 14 states and 19 transitions. [2021-11-20 05:56:31,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 05:56:31,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 19 transitions. [2021-11-20 05:56:31,780 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:56:31,781 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 14 states and 19 transitions. [2021-11-20 05:56:31,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2021-11-20 05:56:31,781 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2021-11-20 05:56:31,781 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 19 transitions. [2021-11-20 05:56:31,782 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:56:31,782 INFO L681 BuchiCegarLoop]: Abstraction has 14 states and 19 transitions. [2021-11-20 05:56:31,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 19 transitions. [2021-11-20 05:56:31,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 12. [2021-11-20 05:56:31,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 11 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:31,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 16 transitions. [2021-11-20 05:56:31,785 INFO L704 BuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2021-11-20 05:56:31,785 INFO L587 BuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2021-11-20 05:56:31,785 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-20 05:56:31,785 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 16 transitions. [2021-11-20 05:56:31,786 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:56:31,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:56:31,786 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:56:31,787 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:56:31,787 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 05:56:31,788 INFO L791 eck$LassoCheckResult]: Stem: 146#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 147#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 154#L367 assume !(main_~length~0#1 < 1); 148#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 149#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 150#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 155#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 157#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 156#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 151#L370-4 main_~j~0#1 := 0; 152#L378-2 [2021-11-20 05:56:31,788 INFO L793 eck$LassoCheckResult]: Loop: 152#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 153#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 152#L378-2 [2021-11-20 05:56:31,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:31,788 INFO L85 PathProgramCache]: Analyzing trace with hash -1982565540, now seen corresponding path program 1 times [2021-11-20 05:56:31,789 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:31,789 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251983386] [2021-11-20 05:56:31,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:31,790 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:31,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:31,807 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:56:31,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:31,843 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:56:31,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:31,844 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 2 times [2021-11-20 05:56:31,844 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:31,844 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1846249306] [2021-11-20 05:56:31,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:31,844 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:31,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:31,851 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:56:31,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:31,873 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:56:31,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:31,875 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996831, now seen corresponding path program 1 times [2021-11-20 05:56:31,875 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:31,876 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739972521] [2021-11-20 05:56:31,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:31,876 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:31,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:31,922 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:56:31,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:31,968 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:56:32,410 INFO L210 LassoAnalysis]: Preferences: [2021-11-20 05:56:32,411 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-11-20 05:56:32,411 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-11-20 05:56:32,411 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-11-20 05:56:32,411 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-11-20 05:56:32,411 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:56:32,411 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-11-20 05:56:32,411 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-11-20 05:56:32,411 INFO L133 ssoRankerPreferences]: Filename of dumped script: array16_alloca_fixed.i_Iteration3_Lasso [2021-11-20 05:56:32,411 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-11-20 05:56:32,412 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-11-20 05:56:32,424 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:32,428 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:32,430 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:32,433 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:32,565 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:32,573 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:32,575 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:32,577 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:32,579 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:32,580 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:32,583 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-20 05:56:32,904 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-11-20 05:56:32,904 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-11-20 05:56:32,904 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:56:32,904 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:32,911 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 05:56:32,919 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-20 05:56:32,930 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-20 05:56:32,930 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-20 05:56:32,931 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-20 05:56:32,931 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-20 05:56:32,931 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-20 05:56:32,932 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-20 05:56:32,932 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-20 05:56:32,935 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2021-11-20 05:56:32,947 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-20 05:56:32,987 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2021-11-20 05:56:32,988 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:56:32,988 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:32,991 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 05:56:33,002 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-20 05:56:33,013 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-20 05:56:33,013 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-20 05:56:33,014 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-20 05:56:33,014 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-20 05:56:33,014 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-20 05:56:33,015 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-20 05:56:33,015 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-20 05:56:33,017 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2021-11-20 05:56:33,035 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-20 05:56:33,077 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2021-11-20 05:56:33,078 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:56:33,078 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:33,079 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 05:56:33,087 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-20 05:56:33,099 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-20 05:56:33,099 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-20 05:56:33,099 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-20 05:56:33,099 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-20 05:56:33,103 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-20 05:56:33,103 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-20 05:56:33,108 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2021-11-20 05:56:33,123 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-20 05:56:33,165 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2021-11-20 05:56:33,166 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:56:33,166 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:33,167 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 05:56:33,176 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-20 05:56:33,187 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-20 05:56:33,187 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-20 05:56:33,187 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-20 05:56:33,188 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-20 05:56:33,202 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-20 05:56:33,202 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-20 05:56:33,206 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2021-11-20 05:56:33,223 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-11-20 05:56:33,261 INFO L443 ModelExtractionUtils]: Simplification made 9 calls to the SMT solver. [2021-11-20 05:56:33,261 INFO L444 ModelExtractionUtils]: 5 out of 25 variables were initially zero. Simplification set additionally 16 variables to zero. [2021-11-20 05:56:33,261 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:56:33,261 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:33,262 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 05:56:33,273 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-11-20 05:56:33,284 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2021-11-20 05:56:33,308 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2021-11-20 05:56:33,308 INFO L513 LassoAnalysis]: Proved termination. [2021-11-20 05:56:33,308 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~arr~0#1.offset, ULTIMATE.start_main_~j~0#1, v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_2) = -1*ULTIMATE.start_main_~arr~0#1.offset - 4*ULTIMATE.start_main_~j~0#1 + 1*v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_2 Supporting invariants [] [2021-11-20 05:56:33,357 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2021-11-20 05:56:33,365 INFO L297 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2021-11-20 05:56:33,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:33,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:56:33,397 INFO L263 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 2 conjunts are in the unsatisfiable core [2021-11-20 05:56:33,399 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 05:56:33,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:56:33,436 INFO L263 TraceCheckSpWp]: Trace formula consists of 14 conjuncts, 4 conjunts are in the unsatisfiable core [2021-11-20 05:56:33,437 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 05:56:33,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:33,462 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-11-20 05:56:33,463 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 12 states and 16 transitions. cyclomatic complexity: 6 Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:33,488 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 12 states and 16 transitions. cyclomatic complexity: 6. Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 16 states and 22 transitions. Complement of second has 5 states. [2021-11-20 05:56:33,488 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-11-20 05:56:33,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:33,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 14 transitions. [2021-11-20 05:56:33,494 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 14 transitions. Stem has 10 letters. Loop has 2 letters. [2021-11-20 05:56:33,494 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-20 05:56:33,494 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 14 transitions. Stem has 12 letters. Loop has 2 letters. [2021-11-20 05:56:33,494 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-20 05:56:33,495 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 14 transitions. Stem has 10 letters. Loop has 4 letters. [2021-11-20 05:56:33,495 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-20 05:56:33,495 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16 states and 22 transitions. [2021-11-20 05:56:33,502 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:56:33,504 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16 states to 16 states and 22 transitions. [2021-11-20 05:56:33,504 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2021-11-20 05:56:33,504 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-11-20 05:56:33,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16 states and 22 transitions. [2021-11-20 05:56:33,505 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 05:56:33,505 INFO L681 BuchiCegarLoop]: Abstraction has 16 states and 22 transitions. [2021-11-20 05:56:33,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states and 22 transitions. [2021-11-20 05:56:33,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2021-11-20 05:56:33,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.375) internal successors, (22), 15 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:33,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 22 transitions. [2021-11-20 05:56:33,518 INFO L704 BuchiCegarLoop]: Abstraction has 16 states and 22 transitions. [2021-11-20 05:56:33,518 INFO L587 BuchiCegarLoop]: Abstraction has 16 states and 22 transitions. [2021-11-20 05:56:33,518 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-20 05:56:33,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 22 transitions. [2021-11-20 05:56:33,520 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:56:33,522 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:56:33,522 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:56:33,523 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:56:33,525 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 05:56:33,525 INFO L791 eck$LassoCheckResult]: Stem: 243#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 244#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 254#L367 assume !(main_~length~0#1 < 1); 245#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 246#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 247#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 255#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 257#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 256#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 248#L370-4 main_~j~0#1 := 0; 249#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 250#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 251#L378-2 [2021-11-20 05:56:33,526 INFO L793 eck$LassoCheckResult]: Loop: 251#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 258#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 251#L378-2 [2021-11-20 05:56:33,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:33,526 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996833, now seen corresponding path program 1 times [2021-11-20 05:56:33,527 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:33,527 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1076341179] [2021-11-20 05:56:33,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:33,527 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:33,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:56:33,845 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:33,845 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:56:33,845 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1076341179] [2021-11-20 05:56:33,846 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1076341179] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 05:56:33,846 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [167948124] [2021-11-20 05:56:33,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:33,847 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 05:56:33,847 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:33,852 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 05:56:33,875 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2021-11-20 05:56:33,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:56:33,900 INFO L263 TraceCheckSpWp]: Trace formula consists of 52 conjuncts, 16 conjunts are in the unsatisfiable core [2021-11-20 05:56:33,901 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 05:56:33,966 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2021-11-20 05:56:34,059 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 11 [2021-11-20 05:56:34,073 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:34,073 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 05:56:34,157 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2021-11-20 05:56:34,224 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-20 05:56:34,231 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2021-11-20 05:56:34,253 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:34,254 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [167948124] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 05:56:34,254 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 05:56:34,254 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 6] total 15 [2021-11-20 05:56:34,254 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1972177463] [2021-11-20 05:56:34,255 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 05:56:34,255 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:56:34,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:34,256 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 3 times [2021-11-20 05:56:34,256 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:34,256 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2051228421] [2021-11-20 05:56:34,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:34,257 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:34,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:34,263 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:56:34,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:34,269 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:56:34,315 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:56:34,315 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2021-11-20 05:56:34,316 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=186, Unknown=0, NotChecked=0, Total=240 [2021-11-20 05:56:34,316 INFO L87 Difference]: Start difference. First operand 16 states and 22 transitions. cyclomatic complexity: 9 Second operand has 16 states, 15 states have (on average 1.7333333333333334) internal successors, (26), 16 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:34,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:56:34,525 INFO L93 Difference]: Finished difference Result 30 states and 41 transitions. [2021-11-20 05:56:34,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-11-20 05:56:34,527 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 41 transitions. [2021-11-20 05:56:34,528 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-20 05:56:34,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 29 states and 40 transitions. [2021-11-20 05:56:34,529 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2021-11-20 05:56:34,529 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2021-11-20 05:56:34,529 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 40 transitions. [2021-11-20 05:56:34,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 05:56:34,530 INFO L681 BuchiCegarLoop]: Abstraction has 29 states and 40 transitions. [2021-11-20 05:56:34,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 40 transitions. [2021-11-20 05:56:34,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 22. [2021-11-20 05:56:34,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.4090909090909092) internal successors, (31), 21 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:34,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 31 transitions. [2021-11-20 05:56:34,533 INFO L704 BuchiCegarLoop]: Abstraction has 22 states and 31 transitions. [2021-11-20 05:56:34,533 INFO L587 BuchiCegarLoop]: Abstraction has 22 states and 31 transitions. [2021-11-20 05:56:34,534 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-20 05:56:34,534 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 31 transitions. [2021-11-20 05:56:34,535 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:56:34,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:56:34,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:56:34,535 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:56:34,536 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 05:56:34,536 INFO L791 eck$LassoCheckResult]: Stem: 380#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 381#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 391#L367 assume !(main_~length~0#1 < 1); 382#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 383#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 384#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 392#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 395#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 400#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 399#L370-4 main_~j~0#1 := 0; 398#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 389#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 390#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 387#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 388#L378-2 [2021-11-20 05:56:34,536 INFO L793 eck$LassoCheckResult]: Loop: 388#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 396#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 388#L378-2 [2021-11-20 05:56:34,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:34,537 INFO L85 PathProgramCache]: Analyzing trace with hash -645453020, now seen corresponding path program 1 times [2021-11-20 05:56:34,537 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:34,537 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [50596599] [2021-11-20 05:56:34,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:34,537 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:34,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:56:34,696 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:34,696 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:56:34,702 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [50596599] [2021-11-20 05:56:34,703 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [50596599] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 05:56:34,703 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1699471259] [2021-11-20 05:56:34,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:34,703 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 05:56:34,704 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:34,705 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 05:56:34,731 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2021-11-20 05:56:34,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:56:34,767 INFO L263 TraceCheckSpWp]: Trace formula consists of 64 conjuncts, 6 conjunts are in the unsatisfiable core [2021-11-20 05:56:34,768 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 05:56:34,875 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:34,876 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 05:56:34,950 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:34,951 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1699471259] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 05:56:34,951 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 05:56:34,951 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 15 [2021-11-20 05:56:34,951 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [89011245] [2021-11-20 05:56:34,952 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 05:56:34,952 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:56:34,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:34,953 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 4 times [2021-11-20 05:56:34,953 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:34,953 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381824091] [2021-11-20 05:56:34,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:34,954 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:34,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:34,960 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:56:34,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:34,966 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:56:35,025 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:56:35,026 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2021-11-20 05:56:35,026 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2021-11-20 05:56:35,027 INFO L87 Difference]: Start difference. First operand 22 states and 31 transitions. cyclomatic complexity: 13 Second operand has 15 states, 15 states have (on average 1.8666666666666667) internal successors, (28), 15 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:35,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:56:35,208 INFO L93 Difference]: Finished difference Result 47 states and 63 transitions. [2021-11-20 05:56:35,208 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-11-20 05:56:35,209 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 63 transitions. [2021-11-20 05:56:35,211 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-20 05:56:35,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 42 states and 56 transitions. [2021-11-20 05:56:35,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2021-11-20 05:56:35,212 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2021-11-20 05:56:35,212 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 56 transitions. [2021-11-20 05:56:35,212 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 05:56:35,212 INFO L681 BuchiCegarLoop]: Abstraction has 42 states and 56 transitions. [2021-11-20 05:56:35,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states and 56 transitions. [2021-11-20 05:56:35,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 37. [2021-11-20 05:56:35,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.3513513513513513) internal successors, (50), 36 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:35,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 50 transitions. [2021-11-20 05:56:35,217 INFO L704 BuchiCegarLoop]: Abstraction has 37 states and 50 transitions. [2021-11-20 05:56:35,217 INFO L587 BuchiCegarLoop]: Abstraction has 37 states and 50 transitions. [2021-11-20 05:56:35,217 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-20 05:56:35,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 50 transitions. [2021-11-20 05:56:35,218 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-20 05:56:35,218 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:56:35,218 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:56:35,219 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:56:35,219 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 05:56:35,219 INFO L791 eck$LassoCheckResult]: Stem: 553#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 554#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 564#L367 assume main_~length~0#1 < 1;main_~length~0#1 := 1; 565#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 557#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 558#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 583#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 581#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 582#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 580#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 579#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 577#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 559#L370-4 main_~j~0#1 := 0; 560#L378-2 [2021-11-20 05:56:35,219 INFO L793 eck$LassoCheckResult]: Loop: 560#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 561#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 560#L378-2 [2021-11-20 05:56:35,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:35,220 INFO L85 PathProgramCache]: Analyzing trace with hash 1080825110, now seen corresponding path program 1 times [2021-11-20 05:56:35,220 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:35,220 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2144774052] [2021-11-20 05:56:35,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:35,220 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:35,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:56:35,308 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:35,308 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:56:35,309 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2144774052] [2021-11-20 05:56:35,309 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2144774052] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 05:56:35,309 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [624934013] [2021-11-20 05:56:35,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:35,309 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 05:56:35,310 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:35,345 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 05:56:35,347 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2021-11-20 05:56:35,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:56:35,391 INFO L263 TraceCheckSpWp]: Trace formula consists of 59 conjuncts, 4 conjunts are in the unsatisfiable core [2021-11-20 05:56:35,392 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 05:56:35,483 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:35,483 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2021-11-20 05:56:35,483 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [624934013] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:56:35,484 INFO L186 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2021-11-20 05:56:35,484 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [6] total 8 [2021-11-20 05:56:35,484 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [871205200] [2021-11-20 05:56:35,484 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:56:35,484 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:56:35,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:35,485 INFO L85 PathProgramCache]: Analyzing trace with hash 2310, now seen corresponding path program 1 times [2021-11-20 05:56:35,485 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:35,485 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [538508530] [2021-11-20 05:56:35,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:35,485 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:35,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:35,492 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:56:35,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:35,498 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:56:35,554 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:56:35,555 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-20 05:56:35,555 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2021-11-20 05:56:35,555 INFO L87 Difference]: Start difference. First operand 37 states and 50 transitions. cyclomatic complexity: 20 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:35,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:56:35,586 INFO L93 Difference]: Finished difference Result 30 states and 39 transitions. [2021-11-20 05:56:35,587 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-11-20 05:56:35,588 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 39 transitions. [2021-11-20 05:56:35,589 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:56:35,590 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 24 states and 32 transitions. [2021-11-20 05:56:35,590 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-20 05:56:35,590 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-20 05:56:35,590 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24 states and 32 transitions. [2021-11-20 05:56:35,590 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 05:56:35,590 INFO L681 BuchiCegarLoop]: Abstraction has 24 states and 32 transitions. [2021-11-20 05:56:35,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states and 32 transitions. [2021-11-20 05:56:35,592 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 24. [2021-11-20 05:56:35,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.3333333333333333) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:35,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 32 transitions. [2021-11-20 05:56:35,593 INFO L704 BuchiCegarLoop]: Abstraction has 24 states and 32 transitions. [2021-11-20 05:56:35,593 INFO L587 BuchiCegarLoop]: Abstraction has 24 states and 32 transitions. [2021-11-20 05:56:35,594 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-20 05:56:35,594 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 32 transitions. [2021-11-20 05:56:35,594 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:56:35,594 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:56:35,595 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:56:35,595 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:56:35,595 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 05:56:35,596 INFO L791 eck$LassoCheckResult]: Stem: 669#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 670#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 678#L367 assume !(main_~length~0#1 < 1); 667#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 668#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 671#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 679#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 688#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 680#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 681#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 682#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 689#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 687#L370-4 main_~j~0#1 := 0; 686#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 674#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 675#L378-2 [2021-11-20 05:56:35,596 INFO L793 eck$LassoCheckResult]: Loop: 675#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 684#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 675#L378-2 [2021-11-20 05:56:35,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:35,596 INFO L85 PathProgramCache]: Analyzing trace with hash -1295959587, now seen corresponding path program 1 times [2021-11-20 05:56:35,596 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:35,597 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1515911747] [2021-11-20 05:56:35,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:35,597 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:35,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:56:35,925 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:35,926 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:56:35,926 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1515911747] [2021-11-20 05:56:35,926 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1515911747] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 05:56:35,926 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1467597440] [2021-11-20 05:56:35,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:35,926 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 05:56:35,927 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:35,933 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 05:56:35,938 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2021-11-20 05:56:35,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:56:35,978 INFO L263 TraceCheckSpWp]: Trace formula consists of 68 conjuncts, 19 conjunts are in the unsatisfiable core [2021-11-20 05:56:35,979 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 05:56:36,013 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-20 05:56:36,113 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-20 05:56:36,115 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2021-11-20 05:56:36,156 INFO L354 Elim1Store]: treesize reduction 25, result has 21.9 percent of original size [2021-11-20 05:56:36,157 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 29 [2021-11-20 05:56:36,722 INFO L354 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2021-11-20 05:56:36,723 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 17 [2021-11-20 05:56:36,741 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:36,741 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 05:56:40,298 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-20 05:56:40,302 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2021-11-20 05:56:40,333 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-11-20 05:56:40,333 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1467597440] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 05:56:40,334 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 05:56:40,334 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 7] total 20 [2021-11-20 05:56:40,334 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [791754162] [2021-11-20 05:56:40,334 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 05:56:40,335 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:56:40,335 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:40,335 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 5 times [2021-11-20 05:56:40,336 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:40,336 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [717518250] [2021-11-20 05:56:40,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:40,336 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:40,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:40,341 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:56:40,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:40,346 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:56:40,411 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:56:40,413 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-11-20 05:56:40,414 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=106, Invalid=314, Unknown=0, NotChecked=0, Total=420 [2021-11-20 05:56:40,417 INFO L87 Difference]: Start difference. First operand 24 states and 32 transitions. cyclomatic complexity: 12 Second operand has 21 states, 20 states have (on average 1.8) internal successors, (36), 21 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:40,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:56:40,691 INFO L93 Difference]: Finished difference Result 46 states and 62 transitions. [2021-11-20 05:56:40,691 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-11-20 05:56:40,692 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46 states and 62 transitions. [2021-11-20 05:56:40,693 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:56:40,693 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46 states to 44 states and 59 transitions. [2021-11-20 05:56:40,693 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2021-11-20 05:56:40,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2021-11-20 05:56:40,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44 states and 59 transitions. [2021-11-20 05:56:40,694 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 05:56:40,694 INFO L681 BuchiCegarLoop]: Abstraction has 44 states and 59 transitions. [2021-11-20 05:56:40,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states and 59 transitions. [2021-11-20 05:56:40,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 28. [2021-11-20 05:56:40,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.3928571428571428) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:40,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 39 transitions. [2021-11-20 05:56:40,697 INFO L704 BuchiCegarLoop]: Abstraction has 28 states and 39 transitions. [2021-11-20 05:56:40,697 INFO L587 BuchiCegarLoop]: Abstraction has 28 states and 39 transitions. [2021-11-20 05:56:40,697 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-20 05:56:40,697 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 39 transitions. [2021-11-20 05:56:40,698 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:56:40,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:56:40,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:56:40,698 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:56:40,698 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 05:56:40,698 INFO L791 eck$LassoCheckResult]: Stem: 853#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 854#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 864#L367 assume !(main_~length~0#1 < 1); 855#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 856#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 857#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 865#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 880#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 879#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 878#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 877#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 876#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 858#L370-4 main_~j~0#1 := 0; 859#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 862#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 863#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 860#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 861#L378-2 [2021-11-20 05:56:40,699 INFO L793 eck$LassoCheckResult]: Loop: 861#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 869#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 861#L378-2 [2021-11-20 05:56:40,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:40,699 INFO L85 PathProgramCache]: Analyzing trace with hash 123352160, now seen corresponding path program 1 times [2021-11-20 05:56:40,701 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:40,702 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2142202994] [2021-11-20 05:56:40,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:40,702 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:40,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:56:40,883 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:40,883 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:56:40,883 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2142202994] [2021-11-20 05:56:40,883 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2142202994] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 05:56:40,884 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1826025966] [2021-11-20 05:56:40,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:40,884 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 05:56:40,884 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:40,886 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 05:56:40,896 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2021-11-20 05:56:40,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:56:40,959 INFO L263 TraceCheckSpWp]: Trace formula consists of 80 conjuncts, 16 conjunts are in the unsatisfiable core [2021-11-20 05:56:40,961 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 05:56:41,060 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-11-20 05:56:41,198 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-20 05:56:41,202 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:41,202 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 05:56:41,314 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-11-20 05:56:41,317 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 26 [2021-11-20 05:56:41,354 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:41,354 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1826025966] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 05:56:41,354 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 05:56:41,355 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 7] total 18 [2021-11-20 05:56:41,355 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679893602] [2021-11-20 05:56:41,355 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 05:56:41,357 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:56:41,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:41,358 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 6 times [2021-11-20 05:56:41,358 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:41,358 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [708128419] [2021-11-20 05:56:41,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:41,359 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:41,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:41,384 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:56:41,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:41,389 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:56:41,455 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:56:41,456 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-11-20 05:56:41,456 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=279, Unknown=0, NotChecked=0, Total=342 [2021-11-20 05:56:41,456 INFO L87 Difference]: Start difference. First operand 28 states and 39 transitions. cyclomatic complexity: 15 Second operand has 19 states, 18 states have (on average 2.111111111111111) internal successors, (38), 19 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:41,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:56:41,646 INFO L93 Difference]: Finished difference Result 40 states and 53 transitions. [2021-11-20 05:56:41,647 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-11-20 05:56:41,648 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40 states and 53 transitions. [2021-11-20 05:56:41,649 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-20 05:56:41,650 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40 states to 39 states and 52 transitions. [2021-11-20 05:56:41,650 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-11-20 05:56:41,650 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-11-20 05:56:41,650 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 52 transitions. [2021-11-20 05:56:41,650 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 05:56:41,650 INFO L681 BuchiCegarLoop]: Abstraction has 39 states and 52 transitions. [2021-11-20 05:56:41,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 52 transitions. [2021-11-20 05:56:41,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 32. [2021-11-20 05:56:41,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 1.34375) internal successors, (43), 31 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:41,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 43 transitions. [2021-11-20 05:56:41,654 INFO L704 BuchiCegarLoop]: Abstraction has 32 states and 43 transitions. [2021-11-20 05:56:41,654 INFO L587 BuchiCegarLoop]: Abstraction has 32 states and 43 transitions. [2021-11-20 05:56:41,654 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-20 05:56:41,654 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32 states and 43 transitions. [2021-11-20 05:56:41,654 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:56:41,654 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:56:41,655 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:56:41,659 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:56:41,660 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 05:56:41,661 INFO L791 eck$LassoCheckResult]: Stem: 1043#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1044#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1054#L367 assume !(main_~length~0#1 < 1); 1045#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1046#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1047#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1055#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1065#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1056#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1057#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1061#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1074#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1072#L370-4 main_~j~0#1 := 0; 1066#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1050#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1051#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1048#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1049#L378-2 [2021-11-20 05:56:41,662 INFO L793 eck$LassoCheckResult]: Loop: 1049#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1058#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1049#L378-2 [2021-11-20 05:56:41,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:41,662 INFO L85 PathProgramCache]: Analyzing trace with hash -685994466, now seen corresponding path program 2 times [2021-11-20 05:56:41,662 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:41,663 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2112357419] [2021-11-20 05:56:41,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:41,663 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:41,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:56:41,881 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:41,881 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:56:41,881 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2112357419] [2021-11-20 05:56:41,881 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2112357419] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 05:56:41,882 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [124650235] [2021-11-20 05:56:41,882 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-20 05:56:41,882 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 05:56:41,882 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:41,888 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 05:56:41,907 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2021-11-20 05:56:41,936 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-20 05:56:41,936 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 05:56:41,937 INFO L263 TraceCheckSpWp]: Trace formula consists of 76 conjuncts, 16 conjunts are in the unsatisfiable core [2021-11-20 05:56:41,938 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 05:56:41,973 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-20 05:56:42,081 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2021-11-20 05:56:42,084 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:42,084 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 05:56:42,173 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-11-20 05:56:42,177 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-11-20 05:56:42,199 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:42,199 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [124650235] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 05:56:42,199 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 05:56:42,200 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8] total 13 [2021-11-20 05:56:42,200 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1396041383] [2021-11-20 05:56:42,200 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 05:56:42,201 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:56:42,201 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:42,202 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 7 times [2021-11-20 05:56:42,202 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:42,202 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [11461106] [2021-11-20 05:56:42,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:42,202 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:42,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:42,209 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:56:42,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:56:42,230 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:56:42,279 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:56:42,279 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2021-11-20 05:56:42,279 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=143, Unknown=0, NotChecked=0, Total=182 [2021-11-20 05:56:42,280 INFO L87 Difference]: Start difference. First operand 32 states and 43 transitions. cyclomatic complexity: 15 Second operand has 14 states, 13 states have (on average 2.076923076923077) internal successors, (27), 14 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:42,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:56:42,460 INFO L93 Difference]: Finished difference Result 53 states and 71 transitions. [2021-11-20 05:56:42,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-11-20 05:56:42,461 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53 states and 71 transitions. [2021-11-20 05:56:42,467 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-20 05:56:42,470 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53 states to 52 states and 70 transitions. [2021-11-20 05:56:42,471 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2021-11-20 05:56:42,471 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2021-11-20 05:56:42,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 70 transitions. [2021-11-20 05:56:42,471 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 05:56:42,471 INFO L681 BuchiCegarLoop]: Abstraction has 52 states and 70 transitions. [2021-11-20 05:56:42,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 70 transitions. [2021-11-20 05:56:42,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 40. [2021-11-20 05:56:42,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 40 states have (on average 1.4) internal successors, (56), 39 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:56:42,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 56 transitions. [2021-11-20 05:56:42,477 INFO L704 BuchiCegarLoop]: Abstraction has 40 states and 56 transitions. [2021-11-20 05:56:42,477 INFO L587 BuchiCegarLoop]: Abstraction has 40 states and 56 transitions. [2021-11-20 05:56:42,477 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-20 05:56:42,477 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40 states and 56 transitions. [2021-11-20 05:56:42,478 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:56:42,478 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:56:42,478 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:56:42,479 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:56:42,479 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 05:56:42,484 INFO L791 eck$LassoCheckResult]: Stem: 1243#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1244#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1254#L367 assume !(main_~length~0#1 < 1); 1245#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1246#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1247#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1255#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1265#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1256#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1257#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1258#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1282#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1281#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1280#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1276#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1271#L370-4 main_~j~0#1 := 0; 1268#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1250#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1251#L378-2 [2021-11-20 05:56:42,485 INFO L793 eck$LassoCheckResult]: Loop: 1251#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1260#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1251#L378-2 [2021-11-20 05:56:42,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:56:42,485 INFO L85 PathProgramCache]: Analyzing trace with hash 1119422815, now seen corresponding path program 2 times [2021-11-20 05:56:42,485 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:56:42,485 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [581617508] [2021-11-20 05:56:42,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:56:42,486 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:56:42,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:56:42,863 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:42,863 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:56:42,864 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [581617508] [2021-11-20 05:56:42,864 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [581617508] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 05:56:42,864 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1633302445] [2021-11-20 05:56:42,864 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-20 05:56:42,864 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 05:56:42,864 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:56:42,876 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 05:56:42,895 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2021-11-20 05:56:42,931 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-20 05:56:42,932 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 05:56:42,933 INFO L263 TraceCheckSpWp]: Trace formula consists of 80 conjuncts, 20 conjunts are in the unsatisfiable core [2021-11-20 05:56:42,935 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 05:56:42,989 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-20 05:56:43,082 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-20 05:56:43,083 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-11-20 05:56:43,102 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-20 05:56:43,103 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-11-20 05:56:43,207 INFO L354 Elim1Store]: treesize reduction 72, result has 20.9 percent of original size [2021-11-20 05:56:43,208 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 44 treesize of output 46 [2021-11-20 05:56:43,372 INFO L354 Elim1Store]: treesize reduction 38, result has 7.3 percent of original size [2021-11-20 05:56:43,372 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 51 treesize of output 34 [2021-11-20 05:56:43,389 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:56:43,389 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 05:58:03,676 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 58 [2021-11-20 05:58:03,684 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 481 treesize of output 469 [2021-11-20 05:58:03,914 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:58:03,914 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1633302445] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 05:58:03,915 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 05:58:03,915 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11, 10] total 28 [2021-11-20 05:58:03,915 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [579462353] [2021-11-20 05:58:03,915 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 05:58:03,917 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:58:03,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:58:03,917 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 8 times [2021-11-20 05:58:03,917 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:58:03,918 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598068485] [2021-11-20 05:58:03,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:58:03,918 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:58:03,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:58:03,924 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:58:03,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:58:03,936 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:58:04,003 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:58:04,003 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2021-11-20 05:58:04,004 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=653, Unknown=6, NotChecked=0, Total=812 [2021-11-20 05:58:04,004 INFO L87 Difference]: Start difference. First operand 40 states and 56 transitions. cyclomatic complexity: 22 Second operand has 29 states, 28 states have (on average 1.6785714285714286) internal successors, (47), 29 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:58:04,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:58:04,438 INFO L93 Difference]: Finished difference Result 62 states and 86 transitions. [2021-11-20 05:58:04,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-11-20 05:58:04,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62 states and 86 transitions. [2021-11-20 05:58:04,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:58:04,441 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62 states to 61 states and 82 transitions. [2021-11-20 05:58:04,442 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-11-20 05:58:04,442 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-11-20 05:58:04,442 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61 states and 82 transitions. [2021-11-20 05:58:04,443 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 05:58:04,443 INFO L681 BuchiCegarLoop]: Abstraction has 61 states and 82 transitions. [2021-11-20 05:58:04,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states and 82 transitions. [2021-11-20 05:58:04,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 27. [2021-11-20 05:58:04,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.2962962962962963) internal successors, (35), 26 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:58:04,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 35 transitions. [2021-11-20 05:58:04,447 INFO L704 BuchiCegarLoop]: Abstraction has 27 states and 35 transitions. [2021-11-20 05:58:04,447 INFO L587 BuchiCegarLoop]: Abstraction has 27 states and 35 transitions. [2021-11-20 05:58:04,447 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-20 05:58:04,447 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 35 transitions. [2021-11-20 05:58:04,447 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:58:04,448 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:58:04,448 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:58:04,448 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:58:04,449 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 05:58:04,449 INFO L791 eck$LassoCheckResult]: Stem: 1495#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1496#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1506#L367 assume !(main_~length~0#1 < 1); 1497#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1498#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1499#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1507#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1520#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1508#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1509#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1521#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1518#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1517#L370-4 main_~j~0#1 := 0; 1516#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1515#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1512#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1504#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1505#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1502#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1503#L378-2 [2021-11-20 05:58:04,449 INFO L793 eck$LassoCheckResult]: Loop: 1503#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1514#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1503#L378-2 [2021-11-20 05:58:04,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:58:04,450 INFO L85 PathProgramCache]: Analyzing trace with hash -2110686111, now seen corresponding path program 3 times [2021-11-20 05:58:04,450 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:58:04,450 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [275022658] [2021-11-20 05:58:04,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:58:04,451 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:58:04,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:58:04,702 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:58:04,702 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:58:04,702 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [275022658] [2021-11-20 05:58:04,702 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [275022658] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 05:58:04,703 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1665973039] [2021-11-20 05:58:04,703 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-20 05:58:04,703 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 05:58:04,703 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:58:04,709 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 05:58:04,716 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2021-11-20 05:58:04,762 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2021-11-20 05:58:04,762 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 05:58:04,763 INFO L263 TraceCheckSpWp]: Trace formula consists of 88 conjuncts, 8 conjunts are in the unsatisfiable core [2021-11-20 05:58:04,764 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 05:58:04,970 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:58:04,970 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 05:58:05,087 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:58:05,088 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1665973039] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 05:58:05,088 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 05:58:05,088 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9] total 20 [2021-11-20 05:58:05,088 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1220073750] [2021-11-20 05:58:05,089 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 05:58:05,089 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:58:05,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:58:05,089 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 9 times [2021-11-20 05:58:05,090 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:58:05,090 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305103169] [2021-11-20 05:58:05,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:58:05,090 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:58:05,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:58:05,094 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:58:05,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:58:05,098 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:58:05,183 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:58:05,184 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2021-11-20 05:58:05,184 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=298, Unknown=0, NotChecked=0, Total=380 [2021-11-20 05:58:05,184 INFO L87 Difference]: Start difference. First operand 27 states and 35 transitions. cyclomatic complexity: 12 Second operand has 20 states, 20 states have (on average 2.0) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:58:05,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:58:05,460 INFO L93 Difference]: Finished difference Result 38 states and 47 transitions. [2021-11-20 05:58:05,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-11-20 05:58:05,461 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38 states and 47 transitions. [2021-11-20 05:58:05,462 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:58:05,462 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38 states to 32 states and 41 transitions. [2021-11-20 05:58:05,462 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-20 05:58:05,462 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-20 05:58:05,462 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 41 transitions. [2021-11-20 05:58:05,463 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 05:58:05,463 INFO L681 BuchiCegarLoop]: Abstraction has 32 states and 41 transitions. [2021-11-20 05:58:05,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 41 transitions. [2021-11-20 05:58:05,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 29. [2021-11-20 05:58:05,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 29 states have (on average 1.2758620689655173) internal successors, (37), 28 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:58:05,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 37 transitions. [2021-11-20 05:58:05,466 INFO L704 BuchiCegarLoop]: Abstraction has 29 states and 37 transitions. [2021-11-20 05:58:05,466 INFO L587 BuchiCegarLoop]: Abstraction has 29 states and 37 transitions. [2021-11-20 05:58:05,466 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-20 05:58:05,466 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29 states and 37 transitions. [2021-11-20 05:58:05,466 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:58:05,466 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:58:05,466 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:58:05,472 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:58:05,472 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 05:58:05,473 INFO L791 eck$LassoCheckResult]: Stem: 1699#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1700#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1710#L367 assume !(main_~length~0#1 < 1); 1701#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1702#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1703#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1711#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1717#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1712#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1713#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1727#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1726#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1719#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1715#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1725#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1724#L370-4 main_~j~0#1 := 0; 1723#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1716#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1722#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1706#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1707#L378-2 [2021-11-20 05:58:05,473 INFO L793 eck$LassoCheckResult]: Loop: 1707#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1721#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1707#L378-2 [2021-11-20 05:58:05,473 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:58:05,473 INFO L85 PathProgramCache]: Analyzing trace with hash -761055450, now seen corresponding path program 2 times [2021-11-20 05:58:05,474 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:58:05,474 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281919641] [2021-11-20 05:58:05,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:58:05,474 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:58:05,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:58:05,795 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:58:05,795 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:58:05,795 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [281919641] [2021-11-20 05:58:05,795 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [281919641] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 05:58:05,795 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2062537846] [2021-11-20 05:58:05,795 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-20 05:58:05,796 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 05:58:05,796 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:58:05,797 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 05:58:05,799 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2021-11-20 05:58:05,840 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-20 05:58:05,840 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 05:58:05,841 INFO L263 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 19 conjunts are in the unsatisfiable core [2021-11-20 05:58:05,842 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 05:58:05,893 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-20 05:58:06,082 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-11-20 05:58:06,083 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 50 treesize of output 41 [2021-11-20 05:58:06,137 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-11-20 05:58:06,138 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 50 treesize of output 41 [2021-11-20 05:58:06,693 INFO L354 Elim1Store]: treesize reduction 42, result has 6.7 percent of original size [2021-11-20 05:58:06,693 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 55 treesize of output 28 [2021-11-20 05:58:06,698 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:58:06,699 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 05:58:09,593 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-11-20 05:58:09,598 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-11-20 05:58:09,634 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-11-20 05:58:09,634 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2062537846] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 05:58:09,634 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 05:58:09,634 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 9] total 18 [2021-11-20 05:58:09,635 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [827256307] [2021-11-20 05:58:09,635 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 05:58:09,635 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:58:09,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:58:09,636 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 10 times [2021-11-20 05:58:09,636 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:58:09,636 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [550535986] [2021-11-20 05:58:09,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:58:09,636 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:58:09,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:58:09,642 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:58:09,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:58:09,646 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:58:09,724 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:58:09,725 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-11-20 05:58:09,725 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=270, Unknown=0, NotChecked=0, Total=342 [2021-11-20 05:58:09,725 INFO L87 Difference]: Start difference. First operand 29 states and 37 transitions. cyclomatic complexity: 12 Second operand has 19 states, 18 states have (on average 2.111111111111111) internal successors, (38), 19 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:58:09,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:58:09,916 INFO L93 Difference]: Finished difference Result 56 states and 71 transitions. [2021-11-20 05:58:09,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-11-20 05:58:09,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56 states and 71 transitions. [2021-11-20 05:58:09,918 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:58:09,919 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56 states to 55 states and 69 transitions. [2021-11-20 05:58:09,919 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2021-11-20 05:58:09,919 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2021-11-20 05:58:09,919 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55 states and 69 transitions. [2021-11-20 05:58:09,920 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 05:58:09,920 INFO L681 BuchiCegarLoop]: Abstraction has 55 states and 69 transitions. [2021-11-20 05:58:09,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states and 69 transitions. [2021-11-20 05:58:09,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 38. [2021-11-20 05:58:09,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38 states, 38 states have (on average 1.3421052631578947) internal successors, (51), 37 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:58:09,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 51 transitions. [2021-11-20 05:58:09,924 INFO L704 BuchiCegarLoop]: Abstraction has 38 states and 51 transitions. [2021-11-20 05:58:09,924 INFO L587 BuchiCegarLoop]: Abstraction has 38 states and 51 transitions. [2021-11-20 05:58:09,924 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-20 05:58:09,924 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38 states and 51 transitions. [2021-11-20 05:58:09,924 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:58:09,924 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:58:09,924 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:58:09,925 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:58:09,925 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 05:58:09,926 INFO L791 eck$LassoCheckResult]: Stem: 1922#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1923#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1933#L367 assume !(main_~length~0#1 < 1); 1924#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1925#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1926#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1934#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1938#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1935#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1936#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1958#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1953#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1952#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1949#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1951#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1931#L370-4 main_~j~0#1 := 0; 1932#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1929#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1930#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1937#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1940#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1927#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1928#L378-2 [2021-11-20 05:58:09,926 INFO L793 eck$LassoCheckResult]: Loop: 1928#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1939#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1928#L378-2 [2021-11-20 05:58:09,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:58:09,926 INFO L85 PathProgramCache]: Analyzing trace with hash -643041689, now seen corresponding path program 3 times [2021-11-20 05:58:09,926 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:58:09,926 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [969165039] [2021-11-20 05:58:09,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:58:09,927 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:58:09,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:58:10,126 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:58:10,127 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:58:10,127 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [969165039] [2021-11-20 05:58:10,127 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [969165039] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 05:58:10,127 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1202267433] [2021-11-20 05:58:10,127 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-20 05:58:10,127 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 05:58:10,127 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:58:10,129 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 05:58:10,130 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2021-11-20 05:58:10,184 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2021-11-20 05:58:10,184 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 05:58:10,185 INFO L263 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 23 conjunts are in the unsatisfiable core [2021-11-20 05:58:10,186 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 05:58:10,231 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-20 05:58:10,364 INFO L354 Elim1Store]: treesize reduction 29, result has 39.6 percent of original size [2021-11-20 05:58:10,365 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 38 treesize of output 45 [2021-11-20 05:58:10,480 INFO L354 Elim1Store]: treesize reduction 29, result has 39.6 percent of original size [2021-11-20 05:58:10,480 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 46 treesize of output 53 [2021-11-20 05:58:11,250 INFO L354 Elim1Store]: treesize reduction 46, result has 6.1 percent of original size [2021-11-20 05:58:11,250 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 53 treesize of output 32 [2021-11-20 05:58:11,256 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:58:11,256 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 05:58:24,070 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 67 treesize of output 63 [2021-11-20 05:58:24,080 INFO L354 Elim1Store]: treesize reduction 13, result has 7.1 percent of original size [2021-11-20 05:58:24,080 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 126 treesize of output 116 [2021-11-20 05:58:24,202 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 2 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:58:24,202 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1202267433] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 05:58:24,203 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 05:58:24,203 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 14, 13] total 32 [2021-11-20 05:58:24,203 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [3586883] [2021-11-20 05:58:24,203 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 05:58:24,203 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:58:24,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:58:24,204 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 11 times [2021-11-20 05:58:24,204 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:58:24,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619886584] [2021-11-20 05:58:24,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:58:24,204 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:58:24,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:58:24,208 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:58:24,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:58:24,211 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:58:24,267 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:58:24,267 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2021-11-20 05:58:24,268 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=159, Invalid=893, Unknown=4, NotChecked=0, Total=1056 [2021-11-20 05:58:24,268 INFO L87 Difference]: Start difference. First operand 38 states and 51 transitions. cyclomatic complexity: 18 Second operand has 33 states, 32 states have (on average 1.625) internal successors, (52), 33 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:58:25,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:58:25,296 INFO L93 Difference]: Finished difference Result 75 states and 93 transitions. [2021-11-20 05:58:25,296 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2021-11-20 05:58:25,297 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 93 transitions. [2021-11-20 05:58:25,298 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:58:25,299 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 62 states and 79 transitions. [2021-11-20 05:58:25,299 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-11-20 05:58:25,299 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-11-20 05:58:25,299 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62 states and 79 transitions. [2021-11-20 05:58:25,299 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 05:58:25,300 INFO L681 BuchiCegarLoop]: Abstraction has 62 states and 79 transitions. [2021-11-20 05:58:25,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states and 79 transitions. [2021-11-20 05:58:25,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 48. [2021-11-20 05:58:25,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48 states, 48 states have (on average 1.3333333333333333) internal successors, (64), 47 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:58:25,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 64 transitions. [2021-11-20 05:58:25,304 INFO L704 BuchiCegarLoop]: Abstraction has 48 states and 64 transitions. [2021-11-20 05:58:25,304 INFO L587 BuchiCegarLoop]: Abstraction has 48 states and 64 transitions. [2021-11-20 05:58:25,304 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-20 05:58:25,305 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48 states and 64 transitions. [2021-11-20 05:58:25,305 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 05:58:25,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:58:25,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:58:25,306 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:58:25,306 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 05:58:25,307 INFO L791 eck$LassoCheckResult]: Stem: 2235#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2236#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2246#L367 assume !(main_~length~0#1 < 1); 2237#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2238#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2239#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2247#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2251#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2248#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2249#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2281#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2282#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2270#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2264#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2267#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2244#L370-4 main_~j~0#1 := 0; 2245#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2242#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2243#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2256#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2255#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2240#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 2241#L378-2 [2021-11-20 05:58:25,307 INFO L793 eck$LassoCheckResult]: Loop: 2241#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2254#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2241#L378-2 [2021-11-20 05:58:25,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:58:25,308 INFO L85 PathProgramCache]: Analyzing trace with hash -1036068699, now seen corresponding path program 4 times [2021-11-20 05:58:25,308 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:58:25,308 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [223719772] [2021-11-20 05:58:25,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:58:25,308 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:58:25,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:58:25,579 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:58:25,579 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:58:25,580 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [223719772] [2021-11-20 05:58:25,580 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [223719772] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 05:58:25,580 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1487348272] [2021-11-20 05:58:25,580 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-20 05:58:25,580 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 05:58:25,580 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:58:25,589 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 05:58:25,590 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2021-11-20 05:58:25,629 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-20 05:58:25,629 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 05:58:25,630 INFO L263 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 24 conjunts are in the unsatisfiable core [2021-11-20 05:58:25,632 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 05:58:25,785 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-11-20 05:58:26,053 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2021-11-20 05:58:26,078 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:58:26,078 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 05:58:26,221 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-11-20 05:58:26,229 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-11-20 05:58:26,282 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:58:26,283 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1487348272] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 05:58:26,283 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 05:58:26,283 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 10] total 22 [2021-11-20 05:58:26,283 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [415832888] [2021-11-20 05:58:26,283 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 05:58:26,283 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:58:26,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:58:26,283 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 12 times [2021-11-20 05:58:26,284 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:58:26,284 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1432238218] [2021-11-20 05:58:26,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:58:26,287 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:58:26,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:58:26,292 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:58:26,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:58:26,303 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:58:26,375 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:58:26,376 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2021-11-20 05:58:26,376 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=428, Unknown=0, NotChecked=0, Total=506 [2021-11-20 05:58:26,376 INFO L87 Difference]: Start difference. First operand 48 states and 64 transitions. cyclomatic complexity: 22 Second operand has 23 states, 22 states have (on average 2.090909090909091) internal successors, (46), 23 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:58:26,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:58:26,910 INFO L93 Difference]: Finished difference Result 85 states and 110 transitions. [2021-11-20 05:58:26,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2021-11-20 05:58:26,913 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 85 states and 110 transitions. [2021-11-20 05:58:26,914 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8 [2021-11-20 05:58:26,915 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 85 states to 84 states and 109 transitions. [2021-11-20 05:58:26,915 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31 [2021-11-20 05:58:26,915 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31 [2021-11-20 05:58:26,915 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84 states and 109 transitions. [2021-11-20 05:58:26,916 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 05:58:26,916 INFO L681 BuchiCegarLoop]: Abstraction has 84 states and 109 transitions. [2021-11-20 05:58:26,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states and 109 transitions. [2021-11-20 05:58:26,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 65. [2021-11-20 05:58:26,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 65 states have (on average 1.353846153846154) internal successors, (88), 64 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:58:26,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 88 transitions. [2021-11-20 05:58:26,921 INFO L704 BuchiCegarLoop]: Abstraction has 65 states and 88 transitions. [2021-11-20 05:58:26,921 INFO L587 BuchiCegarLoop]: Abstraction has 65 states and 88 transitions. [2021-11-20 05:58:26,921 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-20 05:58:26,921 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65 states and 88 transitions. [2021-11-20 05:58:26,921 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2021-11-20 05:58:26,922 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:58:26,922 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:58:26,922 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:58:26,922 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-11-20 05:58:26,923 INFO L791 eck$LassoCheckResult]: Stem: 2528#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2529#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2539#L367 assume !(main_~length~0#1 < 1); 2530#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2531#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2532#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2540#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2557#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2562#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2560#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2559#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2558#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2556#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2547#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2548#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2577#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2574#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2571#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2568#L370-4 main_~j~0#1 := 0; 2566#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2565#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2551#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2552#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 2590#L378-2 [2021-11-20 05:58:26,923 INFO L793 eck$LassoCheckResult]: Loop: 2590#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2592#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2591#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2589#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 2590#L378-2 [2021-11-20 05:58:26,923 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:58:26,923 INFO L85 PathProgramCache]: Analyzing trace with hash 976902046, now seen corresponding path program 5 times [2021-11-20 05:58:26,924 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:58:26,924 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684486488] [2021-11-20 05:58:26,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:58:26,924 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:58:26,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:58:27,107 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:58:27,107 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:58:27,107 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [684486488] [2021-11-20 05:58:27,107 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [684486488] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 05:58:27,107 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [530801583] [2021-11-20 05:58:27,108 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-20 05:58:27,108 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 05:58:27,108 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:58:27,115 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 05:58:27,131 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2021-11-20 05:58:27,177 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2021-11-20 05:58:27,177 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 05:58:27,178 INFO L263 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 21 conjunts are in the unsatisfiable core [2021-11-20 05:58:27,180 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 05:58:27,257 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-20 05:58:27,314 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-20 05:58:27,315 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-11-20 05:58:27,329 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-20 05:58:27,329 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2021-11-20 05:58:27,439 INFO L354 Elim1Store]: treesize reduction 80, result has 20.8 percent of original size [2021-11-20 05:58:27,439 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 44 treesize of output 46 [2021-11-20 05:58:27,858 INFO L354 Elim1Store]: treesize reduction 30, result has 9.1 percent of original size [2021-11-20 05:58:27,859 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 35 treesize of output 22 [2021-11-20 05:58:27,864 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 1 proven. 23 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:58:27,864 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 05:58:49,118 WARN L838 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_98| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_98| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((|v_ULTIMATE.start_main_~j~0#1_98| Int) (|ULTIMATE.start_main_#t~nondet208#1| Int)) (or (< 0 |v_ULTIMATE.start_main_~j~0#1_98|) (< |v_ULTIMATE.start_main_~j~0#1_98| 0) (= (mod (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_98| 4)) |ULTIMATE.start_main_#t~nondet208#1|) (+ (* |v_ULTIMATE.start_main_~j~0#1_98| 4) |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0))))) is different from false [2021-11-20 05:58:50,587 WARN L838 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_98| Int) (|v_ULTIMATE.start_main_~j~0#1_98| Int) (|ULTIMATE.start_main_#t~nondet208#1| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_98| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (< 0 |v_ULTIMATE.start_main_~j~0#1_98|) (< |v_ULTIMATE.start_main_~j~0#1_98| 0) (= 0 (mod (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_98| 4)) |ULTIMATE.start_main_#t~nondet208#1|) (+ (* |v_ULTIMATE.start_main_~j~0#1_98| 4) |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2)))) is different from false [2021-11-20 05:58:52,204 WARN L838 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_98| Int) (|v_ULTIMATE.start_main_#t~nondet208#1_51| Int) (|v_ULTIMATE.start_main_~j~0#1_98| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_98| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (< 0 |v_ULTIMATE.start_main_~j~0#1_98|) (= (mod (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_98| 4)) |v_ULTIMATE.start_main_#t~nondet208#1_51|) (+ (* |v_ULTIMATE.start_main_~j~0#1_98| 4) |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0) (< |v_ULTIMATE.start_main_~j~0#1_98| 0))) is different from false [2021-11-20 06:00:19,953 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 50 [2021-11-20 06:00:19,959 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 467 treesize of output 453 [2021-11-20 06:00:20,258 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 10 not checked. [2021-11-20 06:00:20,258 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [530801583] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:00:20,258 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:00:20,258 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 13, 13] total 31 [2021-11-20 06:00:20,258 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1428664808] [2021-11-20 06:00:20,259 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:00:20,259 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:00:20,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:00:20,259 INFO L85 PathProgramCache]: Analyzing trace with hash 2219337, now seen corresponding path program 1 times [2021-11-20 06:00:20,260 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:00:20,260 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842121803] [2021-11-20 06:00:20,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:00:20,260 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:00:20,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:00:20,265 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:00:20,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:00:20,271 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:00:20,413 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:00:20,414 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2021-11-20 06:00:20,414 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=665, Unknown=18, NotChecked=168, Total=992 [2021-11-20 06:00:20,415 INFO L87 Difference]: Start difference. First operand 65 states and 88 transitions. cyclomatic complexity: 31 Second operand has 32 states, 31 states have (on average 1.8064516129032258) internal successors, (56), 32 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:00:21,931 WARN L838 $PredicateComparison]: unable to prove that (and (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 0) (= |c_ULTIMATE.start_main_~arr~0#1.offset| 0) (<= 2 |c_ULTIMATE.start_main_~i~0#1|) (forall ((|v_ULTIMATE.start_main_~i~0#1_98| Int) (|v_ULTIMATE.start_main_#t~nondet208#1_51| Int) (|v_ULTIMATE.start_main_~j~0#1_98| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_98| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (< 0 |v_ULTIMATE.start_main_~j~0#1_98|) (= (mod (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_98| 4)) |v_ULTIMATE.start_main_#t~nondet208#1_51|) (+ (* |v_ULTIMATE.start_main_~j~0#1_98| 4) |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0) (< |v_ULTIMATE.start_main_~j~0#1_98| 0)))) is different from false [2021-11-20 06:00:23,479 WARN L838 $PredicateComparison]: unable to prove that (and (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 0) (= |c_ULTIMATE.start_main_~arr~0#1.offset| 0) (<= 2 |c_ULTIMATE.start_main_~i~0#1|) (forall ((|v_ULTIMATE.start_main_~i~0#1_98| Int) (|v_ULTIMATE.start_main_~j~0#1_98| Int) (|ULTIMATE.start_main_#t~nondet208#1| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_98| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (< 0 |v_ULTIMATE.start_main_~j~0#1_98|) (< |v_ULTIMATE.start_main_~j~0#1_98| 0) (= 0 (mod (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_98| 4)) |ULTIMATE.start_main_#t~nondet208#1|) (+ (* |v_ULTIMATE.start_main_~j~0#1_98| 4) |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2))))) is different from false [2021-11-20 06:00:35,483 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|))) (and (= (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 0) (= |c_ULTIMATE.start_main_~arr~0#1.offset| 0) (<= 2 |c_ULTIMATE.start_main_~i~0#1|) (= 0 (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)))) (forall ((|v_ULTIMATE.start_main_~i~0#1_98| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_98| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((|v_ULTIMATE.start_main_~j~0#1_98| Int) (|ULTIMATE.start_main_#t~nondet208#1| Int)) (or (< 0 |v_ULTIMATE.start_main_~j~0#1_98|) (< |v_ULTIMATE.start_main_~j~0#1_98| 0) (= (mod (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_98| 4)) |ULTIMATE.start_main_#t~nondet208#1|) (+ (* |v_ULTIMATE.start_main_~j~0#1_98| 4) |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0))))))) is different from false [2021-11-20 06:00:37,079 WARN L838 $PredicateComparison]: unable to prove that (and (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 0) (= |c_ULTIMATE.start_main_~arr~0#1.offset| 0) (forall ((|v_ULTIMATE.start_main_~i~0#1_98| Int) (|v_ULTIMATE.start_main_#t~nondet208#1_51| Int) (|v_ULTIMATE.start_main_~j~0#1_98| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_98| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (< 0 |v_ULTIMATE.start_main_~j~0#1_98|) (= (mod (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_98| 4)) |v_ULTIMATE.start_main_#t~nondet208#1_51|) (+ (* |v_ULTIMATE.start_main_~j~0#1_98| 4) |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0) (< |v_ULTIMATE.start_main_~j~0#1_98| 0))) (exists ((|v_ULTIMATE.start_main_~i~0#1_96| Int)) (and (<= 2 |v_ULTIMATE.start_main_~i~0#1_96|) (<= (+ |v_ULTIMATE.start_main_~i~0#1_96| 1) |c_ULTIMATE.start_main_~i~0#1|) (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_96| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|)) 0)))) is different from false [2021-11-20 06:00:38,670 WARN L838 $PredicateComparison]: unable to prove that (and (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 0) (= |c_ULTIMATE.start_main_~arr~0#1.offset| 0) (exists ((|v_ULTIMATE.start_main_~i~0#1_96| Int)) (and (<= 2 |v_ULTIMATE.start_main_~i~0#1_96|) (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_96| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|)) 0))) (not (= (* 4 |c_ULTIMATE.start_main_~i~0#1|) 4)) (forall ((|v_ULTIMATE.start_main_~i~0#1_98| Int) (|v_ULTIMATE.start_main_#t~nondet208#1_51| Int) (|v_ULTIMATE.start_main_~j~0#1_98| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_98| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (< 0 |v_ULTIMATE.start_main_~j~0#1_98|) (= (mod (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_98| 4)) |v_ULTIMATE.start_main_#t~nondet208#1_51|) (+ (* |v_ULTIMATE.start_main_~j~0#1_98| 4) |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0) (< |v_ULTIMATE.start_main_~j~0#1_98| 0)))) is different from false [2021-11-20 06:00:40,088 WARN L838 $PredicateComparison]: unable to prove that (and (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 0) (= |c_ULTIMATE.start_main_~arr~0#1.offset| 0) (<= 2 |c_ULTIMATE.start_main_~i~0#1|) (exists ((|v_ULTIMATE.start_main_~i~0#1_96| Int)) (and (<= 2 |v_ULTIMATE.start_main_~i~0#1_96|) (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_96| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|)) 0))) (forall ((|v_ULTIMATE.start_main_~i~0#1_98| Int) (|v_ULTIMATE.start_main_~j~0#1_98| Int) (|ULTIMATE.start_main_#t~nondet208#1| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_98| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (< 0 |v_ULTIMATE.start_main_~j~0#1_98|) (< |v_ULTIMATE.start_main_~j~0#1_98| 0) (= 0 (mod (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_98| 4)) |ULTIMATE.start_main_#t~nondet208#1|) (+ (* |v_ULTIMATE.start_main_~j~0#1_98| 4) |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2))))) is different from false [2021-11-20 06:00:41,802 WARN L838 $PredicateComparison]: unable to prove that (and (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 0) (forall ((|v_ULTIMATE.start_main_~i~0#1_98| Int) (|v_ULTIMATE.start_main_~j~0#1_98| Int) (|ULTIMATE.start_main_#t~nondet208#1| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_98| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (< 0 |v_ULTIMATE.start_main_~j~0#1_98|) (< |v_ULTIMATE.start_main_~j~0#1_98| 0) (= 0 (mod (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_98| 4)) |ULTIMATE.start_main_#t~nondet208#1|) (+ (* |v_ULTIMATE.start_main_~j~0#1_98| 4) |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2))))) is different from false [2021-11-20 06:01:10,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:01:10,998 INFO L93 Difference]: Finished difference Result 176 states and 230 transitions. [2021-11-20 06:01:10,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2021-11-20 06:01:10,999 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 176 states and 230 transitions. [2021-11-20 06:01:11,001 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 16 [2021-11-20 06:01:11,003 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 176 states to 171 states and 225 transitions. [2021-11-20 06:01:11,003 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62 [2021-11-20 06:01:11,003 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62 [2021-11-20 06:01:11,003 INFO L73 IsDeterministic]: Start isDeterministic. Operand 171 states and 225 transitions. [2021-11-20 06:01:11,004 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:01:11,004 INFO L681 BuchiCegarLoop]: Abstraction has 171 states and 225 transitions. [2021-11-20 06:01:11,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states and 225 transitions. [2021-11-20 06:01:11,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 85. [2021-11-20 06:01:11,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 85 states, 85 states have (on average 1.423529411764706) internal successors, (121), 84 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:01:11,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 121 transitions. [2021-11-20 06:01:11,012 INFO L704 BuchiCegarLoop]: Abstraction has 85 states and 121 transitions. [2021-11-20 06:01:11,012 INFO L587 BuchiCegarLoop]: Abstraction has 85 states and 121 transitions. [2021-11-20 06:01:11,012 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-20 06:01:11,013 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 85 states and 121 transitions. [2021-11-20 06:01:11,013 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2021-11-20 06:01:11,014 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:01:11,014 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:01:11,015 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:01:11,015 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 06:01:11,015 INFO L791 eck$LassoCheckResult]: Stem: 2966#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2967#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2977#L367 assume !(main_~length~0#1 < 1); 2968#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2969#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2970#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2978#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 3019#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3018#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3016#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3017#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2979#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2980#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 3005#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3036#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3004#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3002#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2998#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2996#L370-4 main_~j~0#1 := 0; 2993#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2991#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2992#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2971#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 2972#L378-2 [2021-11-20 06:01:11,015 INFO L793 eck$LassoCheckResult]: Loop: 2972#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2990#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2972#L378-2 [2021-11-20 06:01:11,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:01:11,016 INFO L85 PathProgramCache]: Analyzing trace with hash -1807654046, now seen corresponding path program 6 times [2021-11-20 06:01:11,016 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:01:11,016 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1147450004] [2021-11-20 06:01:11,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:01:11,017 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:01:11,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:01:11,258 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:01:11,258 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:01:11,258 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1147450004] [2021-11-20 06:01:11,258 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1147450004] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:01:11,258 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1871380714] [2021-11-20 06:01:11,258 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-20 06:01:11,259 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:01:11,259 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:01:11,260 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:01:11,261 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2021-11-20 06:01:11,327 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2021-11-20 06:01:11,327 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 06:01:11,329 INFO L263 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 17 conjunts are in the unsatisfiable core [2021-11-20 06:01:11,330 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:01:11,392 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-20 06:01:11,456 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-20 06:01:11,456 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-11-20 06:01:11,511 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-20 06:01:11,511 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2021-11-20 06:01:11,536 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-20 06:01:11,537 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-20 06:01:11,742 INFO L354 Elim1Store]: treesize reduction 13, result has 7.1 percent of original size [2021-11-20 06:01:11,743 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 33 treesize of output 13 [2021-11-20 06:01:11,746 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:01:11,747 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:01:36,795 WARN L838 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_107| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_107| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((|ULTIMATE.start_main_#t~nondet208#1| Int)) (= (mod (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_107| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) |ULTIMATE.start_main_#t~nondet208#1|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0)))) is different from false [2021-11-20 06:01:36,804 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 29 [2021-11-20 06:01:36,807 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 89 treesize of output 85 [2021-11-20 06:01:36,875 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 1 proven. 19 refuted. 0 times theorem prover too weak. 1 trivial. 3 not checked. [2021-11-20 06:01:36,875 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1871380714] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:01:36,875 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:01:36,875 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10] total 22 [2021-11-20 06:01:36,876 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1934637616] [2021-11-20 06:01:36,876 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:01:36,876 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:01:36,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:01:36,876 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 13 times [2021-11-20 06:01:36,876 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:01:36,877 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [888452582] [2021-11-20 06:01:36,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:01:36,877 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:01:36,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:01:36,880 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:01:36,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:01:36,884 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:01:36,948 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:01:36,949 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2021-11-20 06:01:36,949 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=100, Invalid=365, Unknown=1, NotChecked=40, Total=506 [2021-11-20 06:01:36,949 INFO L87 Difference]: Start difference. First operand 85 states and 121 transitions. cyclomatic complexity: 45 Second operand has 23 states, 22 states have (on average 2.090909090909091) internal successors, (46), 23 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:01:49,037 WARN L838 $PredicateComparison]: unable to prove that (and (<= 1 |c_ULTIMATE.start_main_~i~0#1|) (forall ((|v_ULTIMATE.start_main_~i~0#1_107| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_107| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((|ULTIMATE.start_main_#t~nondet208#1| Int)) (= (mod (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_107| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) |ULTIMATE.start_main_#t~nondet208#1|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 4)) 2) 0)))) (= 0 (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)))) (<= |c_ULTIMATE.start_main_~i~0#1| 1)) is different from false [2021-11-20 06:01:54,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:01:54,038 INFO L93 Difference]: Finished difference Result 129 states and 174 transitions. [2021-11-20 06:01:54,038 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-11-20 06:01:54,039 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 129 states and 174 transitions. [2021-11-20 06:01:54,041 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10 [2021-11-20 06:01:54,042 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 129 states to 127 states and 172 transitions. [2021-11-20 06:01:54,042 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38 [2021-11-20 06:01:54,043 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38 [2021-11-20 06:01:54,043 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127 states and 172 transitions. [2021-11-20 06:01:54,043 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:01:54,043 INFO L681 BuchiCegarLoop]: Abstraction has 127 states and 172 transitions. [2021-11-20 06:01:54,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states and 172 transitions. [2021-11-20 06:01:54,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 91. [2021-11-20 06:01:54,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91 states, 91 states have (on average 1.4395604395604396) internal successors, (131), 90 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:01:54,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 131 transitions. [2021-11-20 06:01:54,050 INFO L704 BuchiCegarLoop]: Abstraction has 91 states and 131 transitions. [2021-11-20 06:01:54,050 INFO L587 BuchiCegarLoop]: Abstraction has 91 states and 131 transitions. [2021-11-20 06:01:54,050 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-20 06:01:54,051 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91 states and 131 transitions. [2021-11-20 06:01:54,051 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2021-11-20 06:01:54,051 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:01:54,052 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:01:54,052 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:01:54,053 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-11-20 06:01:54,053 INFO L791 eck$LassoCheckResult]: Stem: 3359#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3360#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3370#L367 assume !(main_~length~0#1 < 1); 3361#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3362#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3363#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3371#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 3429#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3427#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3423#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 3421#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3419#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3415#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3413#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3409#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3406#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 3401#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3398#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3395#L370-4 main_~j~0#1 := 0; 3392#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3390#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3382#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3383#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 3389#L378-2 [2021-11-20 06:01:54,053 INFO L793 eck$LassoCheckResult]: Loop: 3389#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3393#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3391#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3388#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 3389#L378-2 [2021-11-20 06:01:54,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:01:54,054 INFO L85 PathProgramCache]: Analyzing trace with hash -34215204, now seen corresponding path program 7 times [2021-11-20 06:01:54,054 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:01:54,054 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126513436] [2021-11-20 06:01:54,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:01:54,054 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:01:54,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:01:54,405 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:01:54,405 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:01:54,406 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2126513436] [2021-11-20 06:01:54,406 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2126513436] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:01:54,406 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1425721183] [2021-11-20 06:01:54,406 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-20 06:01:54,406 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:01:54,406 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:01:54,408 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:01:54,433 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2021-11-20 06:01:54,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:01:54,468 INFO L263 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 32 conjunts are in the unsatisfiable core [2021-11-20 06:01:54,470 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:01:54,487 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 9 [2021-11-20 06:01:54,571 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2021-11-20 06:01:54,667 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-20 06:01:54,829 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-20 06:01:54,834 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2021-11-20 06:01:54,858 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-20 06:01:54,859 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2021-11-20 06:01:55,068 INFO L354 Elim1Store]: treesize reduction 80, result has 20.8 percent of original size [2021-11-20 06:01:55,069 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 46 treesize of output 48 [2021-11-20 06:01:55,959 INFO L354 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2021-11-20 06:01:55,959 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 29 treesize of output 15 [2021-11-20 06:01:55,974 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 1 proven. 23 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:01:55,974 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:02:10,089 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 61 treesize of output 57 [2021-11-20 06:02:10,092 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 67 treesize of output 59 [2021-11-20 06:02:10,160 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 1 proven. 23 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:10,161 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1425721183] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:02:10,161 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:02:10,161 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 14, 13] total 29 [2021-11-20 06:02:10,161 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1868952482] [2021-11-20 06:02:10,161 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:02:10,161 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:02:10,162 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:10,162 INFO L85 PathProgramCache]: Analyzing trace with hash 2219337, now seen corresponding path program 2 times [2021-11-20 06:02:10,162 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:10,162 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [162902671] [2021-11-20 06:02:10,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:10,162 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:10,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:10,167 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:02:10,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:10,171 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:02:10,298 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:02:10,299 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2021-11-20 06:02:10,299 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=135, Invalid=726, Unknown=9, NotChecked=0, Total=870 [2021-11-20 06:02:10,299 INFO L87 Difference]: Start difference. First operand 91 states and 131 transitions. cyclomatic complexity: 51 Second operand has 30 states, 29 states have (on average 1.8275862068965518) internal successors, (53), 30 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:02:12,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:02:12,519 INFO L93 Difference]: Finished difference Result 121 states and 168 transitions. [2021-11-20 06:02:12,519 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2021-11-20 06:02:12,519 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121 states and 168 transitions. [2021-11-20 06:02:12,521 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:02:12,522 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121 states to 119 states and 164 transitions. [2021-11-20 06:02:12,522 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-11-20 06:02:12,522 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-11-20 06:02:12,523 INFO L73 IsDeterministic]: Start isDeterministic. Operand 119 states and 164 transitions. [2021-11-20 06:02:12,523 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:02:12,523 INFO L681 BuchiCegarLoop]: Abstraction has 119 states and 164 transitions. [2021-11-20 06:02:12,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states and 164 transitions. [2021-11-20 06:02:12,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 43. [2021-11-20 06:02:12,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 43 states have (on average 1.3255813953488371) internal successors, (57), 42 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:02:12,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 57 transitions. [2021-11-20 06:02:12,527 INFO L704 BuchiCegarLoop]: Abstraction has 43 states and 57 transitions. [2021-11-20 06:02:12,527 INFO L587 BuchiCegarLoop]: Abstraction has 43 states and 57 transitions. [2021-11-20 06:02:12,527 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-20 06:02:12,527 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43 states and 57 transitions. [2021-11-20 06:02:12,527 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:02:12,527 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:02:12,528 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:02:12,528 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:02:12,528 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 06:02:12,529 INFO L791 eck$LassoCheckResult]: Stem: 3763#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3764#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3774#L367 assume !(main_~length~0#1 < 1); 3765#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3766#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3767#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3775#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 3792#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3796#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3795#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3794#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3793#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3790#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 3779#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3782#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3768#L370-4 main_~j~0#1 := 0; 3769#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3787#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3781#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3772#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3773#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3785#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3784#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3770#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 3771#L378-2 [2021-11-20 06:02:12,529 INFO L793 eck$LassoCheckResult]: Loop: 3771#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3783#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3771#L378-2 [2021-11-20 06:02:12,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:12,529 INFO L85 PathProgramCache]: Analyzing trace with hash 770392360, now seen corresponding path program 8 times [2021-11-20 06:02:12,530 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:12,530 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1191156293] [2021-11-20 06:02:12,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:12,530 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:12,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:02:12,724 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 7 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:12,725 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:02:12,725 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1191156293] [2021-11-20 06:02:12,725 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1191156293] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:02:12,725 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1535929867] [2021-11-20 06:02:12,725 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-20 06:02:12,725 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:02:12,725 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:02:12,726 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:02:12,727 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2021-11-20 06:02:12,764 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-20 06:02:12,764 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 06:02:12,765 INFO L263 TraceCheckSpWp]: Trace formula consists of 116 conjuncts, 10 conjunts are in the unsatisfiable core [2021-11-20 06:02:12,765 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:02:12,980 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:12,981 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:02:13,124 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:13,124 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1535929867] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:02:13,124 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:02:13,124 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11, 11] total 25 [2021-11-20 06:02:13,124 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1852806971] [2021-11-20 06:02:13,124 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:02:13,125 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:02:13,125 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:13,125 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 14 times [2021-11-20 06:02:13,125 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:13,126 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [30291092] [2021-11-20 06:02:13,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:13,126 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:13,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:13,129 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:02:13,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:13,133 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:02:13,199 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:02:13,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2021-11-20 06:02:13,200 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=121, Invalid=479, Unknown=0, NotChecked=0, Total=600 [2021-11-20 06:02:13,200 INFO L87 Difference]: Start difference. First operand 43 states and 57 transitions. cyclomatic complexity: 19 Second operand has 25 states, 25 states have (on average 2.08) internal successors, (52), 25 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:02:13,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:02:13,447 INFO L93 Difference]: Finished difference Result 57 states and 72 transitions. [2021-11-20 06:02:13,448 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2021-11-20 06:02:13,448 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57 states and 72 transitions. [2021-11-20 06:02:13,449 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:02:13,449 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57 states to 49 states and 63 transitions. [2021-11-20 06:02:13,449 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-20 06:02:13,450 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-20 06:02:13,450 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49 states and 63 transitions. [2021-11-20 06:02:13,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:02:13,450 INFO L681 BuchiCegarLoop]: Abstraction has 49 states and 63 transitions. [2021-11-20 06:02:13,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states and 63 transitions. [2021-11-20 06:02:13,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 40. [2021-11-20 06:02:13,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 40 states have (on average 1.3) internal successors, (52), 39 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:02:13,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 52 transitions. [2021-11-20 06:02:13,453 INFO L704 BuchiCegarLoop]: Abstraction has 40 states and 52 transitions. [2021-11-20 06:02:13,453 INFO L587 BuchiCegarLoop]: Abstraction has 40 states and 52 transitions. [2021-11-20 06:02:13,453 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-20 06:02:13,454 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40 states and 52 transitions. [2021-11-20 06:02:13,454 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:02:13,454 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:02:13,454 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:02:13,455 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:02:13,455 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 06:02:13,456 INFO L791 eck$LassoCheckResult]: Stem: 4039#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4040#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4050#L367 assume !(main_~length~0#1 < 1); 4041#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4042#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4043#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4051#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4078#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4052#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4053#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4054#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4057#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4076#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4075#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4074#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4066#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4067#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4058#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4044#L370-4 main_~j~0#1 := 0; 4045#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4056#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4063#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4061#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4060#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4046#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 4047#L378-2 [2021-11-20 06:02:13,456 INFO L793 eck$LassoCheckResult]: Loop: 4047#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4062#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4047#L378-2 [2021-11-20 06:02:13,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:13,457 INFO L85 PathProgramCache]: Analyzing trace with hash 1285147747, now seen corresponding path program 9 times [2021-11-20 06:02:13,457 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:13,457 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2005143531] [2021-11-20 06:02:13,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:13,457 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:13,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:02:13,794 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:13,794 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:02:13,795 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2005143531] [2021-11-20 06:02:13,795 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2005143531] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:02:13,795 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1544927877] [2021-11-20 06:02:13,795 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-20 06:02:13,795 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:02:13,795 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:02:13,804 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:02:13,808 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2021-11-20 06:02:13,881 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2021-11-20 06:02:13,882 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 06:02:13,883 INFO L263 TraceCheckSpWp]: Trace formula consists of 116 conjuncts, 23 conjunts are in the unsatisfiable core [2021-11-20 06:02:13,884 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:02:13,951 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-20 06:02:14,126 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-11-20 06:02:14,126 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 50 treesize of output 41 [2021-11-20 06:02:14,177 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-11-20 06:02:14,177 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 50 treesize of output 41 [2021-11-20 06:02:14,760 INFO L354 Elim1Store]: treesize reduction 42, result has 6.7 percent of original size [2021-11-20 06:02:14,760 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 55 treesize of output 28 [2021-11-20 06:02:14,765 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:14,766 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:02:16,266 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-11-20 06:02:16,269 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-11-20 06:02:16,317 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-11-20 06:02:16,317 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1544927877] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:02:16,317 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:02:16,318 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12, 11] total 21 [2021-11-20 06:02:16,318 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [944815772] [2021-11-20 06:02:16,318 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:02:16,318 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:02:16,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:16,319 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 15 times [2021-11-20 06:02:16,319 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:16,319 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2138253623] [2021-11-20 06:02:16,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:16,320 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:16,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:16,323 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:02:16,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:16,327 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:02:16,410 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:02:16,410 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2021-11-20 06:02:16,411 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=379, Unknown=0, NotChecked=0, Total=462 [2021-11-20 06:02:16,411 INFO L87 Difference]: Start difference. First operand 40 states and 52 transitions. cyclomatic complexity: 17 Second operand has 22 states, 21 states have (on average 2.142857142857143) internal successors, (45), 22 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:02:16,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:02:16,622 INFO L93 Difference]: Finished difference Result 79 states and 99 transitions. [2021-11-20 06:02:16,623 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-11-20 06:02:16,623 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79 states and 99 transitions. [2021-11-20 06:02:16,624 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:02:16,625 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79 states to 78 states and 97 transitions. [2021-11-20 06:02:16,625 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2021-11-20 06:02:16,626 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2021-11-20 06:02:16,626 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78 states and 97 transitions. [2021-11-20 06:02:16,626 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:02:16,626 INFO L681 BuchiCegarLoop]: Abstraction has 78 states and 97 transitions. [2021-11-20 06:02:16,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states and 97 transitions. [2021-11-20 06:02:16,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 41. [2021-11-20 06:02:16,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 41 states have (on average 1.3414634146341464) internal successors, (55), 40 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:02:16,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 55 transitions. [2021-11-20 06:02:16,641 INFO L704 BuchiCegarLoop]: Abstraction has 41 states and 55 transitions. [2021-11-20 06:02:16,642 INFO L587 BuchiCegarLoop]: Abstraction has 41 states and 55 transitions. [2021-11-20 06:02:16,642 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-20 06:02:16,642 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41 states and 55 transitions. [2021-11-20 06:02:16,643 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:02:16,643 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:02:16,643 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:02:16,644 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:02:16,644 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 06:02:16,644 INFO L791 eck$LassoCheckResult]: Stem: 4327#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4328#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4338#L367 assume !(main_~length~0#1 < 1); 4329#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4330#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4331#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4339#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4342#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4340#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4341#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4367#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4366#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4365#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4364#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4363#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4362#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4356#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4358#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4332#L370-4 main_~j~0#1 := 0; 4333#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4336#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4337#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4343#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4347#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4345#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4344#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4334#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 4335#L378-2 [2021-11-20 06:02:16,645 INFO L793 eck$LassoCheckResult]: Loop: 4335#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4346#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4335#L378-2 [2021-11-20 06:02:16,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:16,645 INFO L85 PathProgramCache]: Analyzing trace with hash -1923596954, now seen corresponding path program 10 times [2021-11-20 06:02:16,645 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:16,646 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1830647442] [2021-11-20 06:02:16,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:16,646 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:16,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:02:16,968 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:16,968 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:02:16,968 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1830647442] [2021-11-20 06:02:16,969 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1830647442] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:02:16,969 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [955094272] [2021-11-20 06:02:16,969 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-20 06:02:16,969 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:02:16,969 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:02:16,973 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:02:16,988 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2021-11-20 06:02:17,035 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-20 06:02:17,035 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 06:02:17,037 INFO L263 TraceCheckSpWp]: Trace formula consists of 128 conjuncts, 24 conjunts are in the unsatisfiable core [2021-11-20 06:02:17,038 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:02:17,235 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-11-20 06:02:17,444 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-20 06:02:17,447 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:17,447 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:02:17,622 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-11-20 06:02:17,624 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 26 [2021-11-20 06:02:17,682 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:17,682 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [955094272] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:02:17,682 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:02:17,682 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 11] total 28 [2021-11-20 06:02:17,683 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [886583183] [2021-11-20 06:02:17,683 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:02:17,683 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:02:17,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:17,683 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 16 times [2021-11-20 06:02:17,683 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:17,683 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1020835434] [2021-11-20 06:02:17,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:17,683 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:17,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:17,686 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:02:17,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:17,688 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:02:17,745 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:02:17,745 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2021-11-20 06:02:17,746 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=711, Unknown=0, NotChecked=0, Total=812 [2021-11-20 06:02:17,746 INFO L87 Difference]: Start difference. First operand 41 states and 55 transitions. cyclomatic complexity: 19 Second operand has 29 states, 28 states have (on average 2.2142857142857144) internal successors, (62), 29 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:02:18,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:02:18,234 INFO L93 Difference]: Finished difference Result 58 states and 75 transitions. [2021-11-20 06:02:18,234 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2021-11-20 06:02:18,234 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 58 states and 75 transitions. [2021-11-20 06:02:18,235 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-20 06:02:18,236 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 58 states to 57 states and 74 transitions. [2021-11-20 06:02:18,236 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-11-20 06:02:18,236 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-11-20 06:02:18,236 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57 states and 74 transitions. [2021-11-20 06:02:18,236 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:02:18,236 INFO L681 BuchiCegarLoop]: Abstraction has 57 states and 74 transitions. [2021-11-20 06:02:18,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states and 74 transitions. [2021-11-20 06:02:18,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 47. [2021-11-20 06:02:18,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.3191489361702127) internal successors, (62), 46 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:02:18,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 62 transitions. [2021-11-20 06:02:18,239 INFO L704 BuchiCegarLoop]: Abstraction has 47 states and 62 transitions. [2021-11-20 06:02:18,239 INFO L587 BuchiCegarLoop]: Abstraction has 47 states and 62 transitions. [2021-11-20 06:02:18,240 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-20 06:02:18,240 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 62 transitions. [2021-11-20 06:02:18,240 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:02:18,240 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:02:18,240 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:02:18,241 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:02:18,242 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 06:02:18,242 INFO L791 eck$LassoCheckResult]: Stem: 4618#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4619#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4629#L367 assume !(main_~length~0#1 < 1); 4620#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4621#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4622#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4630#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4634#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4631#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4632#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4664#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4663#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4662#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4661#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4660#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4659#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4635#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4636#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4627#L370-4 main_~j~0#1 := 0; 4628#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4625#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4626#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4642#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4641#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4639#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4638#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4623#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 4624#L378-2 [2021-11-20 06:02:18,242 INFO L793 eck$LassoCheckResult]: Loop: 4624#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4640#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4624#L378-2 [2021-11-20 06:02:18,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:18,243 INFO L85 PathProgramCache]: Analyzing trace with hash -1665431516, now seen corresponding path program 4 times [2021-11-20 06:02:18,243 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:18,243 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1700947567] [2021-11-20 06:02:18,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:18,243 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:18,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:02:18,590 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:18,590 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:02:18,590 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1700947567] [2021-11-20 06:02:18,590 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1700947567] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:02:18,591 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2146950000] [2021-11-20 06:02:18,591 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-20 06:02:18,591 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:02:18,591 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:02:18,593 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:02:18,594 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2021-11-20 06:02:18,640 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-20 06:02:18,641 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 06:02:18,642 INFO L263 TraceCheckSpWp]: Trace formula consists of 124 conjuncts, 28 conjunts are in the unsatisfiable core [2021-11-20 06:02:18,644 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:02:18,840 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-11-20 06:02:19,169 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2021-11-20 06:02:19,191 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:19,191 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:02:19,352 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-11-20 06:02:19,355 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-11-20 06:02:19,423 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:19,424 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2146950000] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:02:19,424 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:02:19,424 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 12] total 26 [2021-11-20 06:02:19,424 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [928591596] [2021-11-20 06:02:19,424 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:02:19,424 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:02:19,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:19,425 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 17 times [2021-11-20 06:02:19,425 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:19,425 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [322519121] [2021-11-20 06:02:19,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:19,426 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:19,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:19,429 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:02:19,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:19,433 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:02:19,498 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:02:19,498 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2021-11-20 06:02:19,498 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=609, Unknown=0, NotChecked=0, Total=702 [2021-11-20 06:02:19,498 INFO L87 Difference]: Start difference. First operand 47 states and 62 transitions. cyclomatic complexity: 20 Second operand has 27 states, 26 states have (on average 2.1538461538461537) internal successors, (56), 27 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:02:20,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:02:20,138 INFO L93 Difference]: Finished difference Result 85 states and 109 transitions. [2021-11-20 06:02:20,138 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2021-11-20 06:02:20,138 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 85 states and 109 transitions. [2021-11-20 06:02:20,139 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 10 [2021-11-20 06:02:20,140 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 85 states to 84 states and 108 transitions. [2021-11-20 06:02:20,140 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31 [2021-11-20 06:02:20,140 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31 [2021-11-20 06:02:20,140 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84 states and 108 transitions. [2021-11-20 06:02:20,140 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:02:20,140 INFO L681 BuchiCegarLoop]: Abstraction has 84 states and 108 transitions. [2021-11-20 06:02:20,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states and 108 transitions. [2021-11-20 06:02:20,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 66. [2021-11-20 06:02:20,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 66 states have (on average 1.3333333333333333) internal successors, (88), 65 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:02:20,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 88 transitions. [2021-11-20 06:02:20,143 INFO L704 BuchiCegarLoop]: Abstraction has 66 states and 88 transitions. [2021-11-20 06:02:20,143 INFO L587 BuchiCegarLoop]: Abstraction has 66 states and 88 transitions. [2021-11-20 06:02:20,144 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-20 06:02:20,144 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66 states and 88 transitions. [2021-11-20 06:02:20,144 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 8 [2021-11-20 06:02:20,144 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:02:20,144 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:02:20,145 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:02:20,146 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-11-20 06:02:20,146 INFO L791 eck$LassoCheckResult]: Stem: 4944#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4945#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4955#L367 assume !(main_~length~0#1 < 1); 4946#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4947#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4948#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4956#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4968#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4969#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4970#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4966#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4967#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4972#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4971#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4957#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4958#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4990#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4989#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4988#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4987#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4985#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4984#L370-4 main_~j~0#1 := 0; 4983#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4982#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4981#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4980#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4973#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4975#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 5005#L378-2 [2021-11-20 06:02:20,146 INFO L793 eck$LassoCheckResult]: Loop: 5005#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5007#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 5008#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5009#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5005#L378-2 [2021-11-20 06:02:20,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:20,146 INFO L85 PathProgramCache]: Analyzing trace with hash 3898981, now seen corresponding path program 11 times [2021-11-20 06:02:20,147 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:20,147 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885391632] [2021-11-20 06:02:20,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:20,147 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:20,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:02:20,467 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 41 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:20,467 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:02:20,467 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [885391632] [2021-11-20 06:02:20,467 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [885391632] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:02:20,467 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [986743881] [2021-11-20 06:02:20,467 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-20 06:02:20,468 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:02:20,468 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:02:20,472 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:02:20,490 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2021-11-20 06:02:20,557 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2021-11-20 06:02:20,557 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 06:02:20,559 INFO L263 TraceCheckSpWp]: Trace formula consists of 128 conjuncts, 25 conjunts are in the unsatisfiable core [2021-11-20 06:02:20,560 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:02:20,601 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-20 06:02:20,691 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-20 06:02:20,692 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 28 [2021-11-20 06:02:20,712 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-20 06:02:20,713 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 28 [2021-11-20 06:02:20,865 INFO L354 Elim1Store]: treesize reduction 80, result has 20.8 percent of original size [2021-11-20 06:02:20,865 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 54 treesize of output 50 [2021-11-20 06:02:21,284 INFO L354 Elim1Store]: treesize reduction 42, result has 6.7 percent of original size [2021-11-20 06:02:21,284 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 51 treesize of output 26 [2021-11-20 06:02:21,288 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:21,288 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:02:46,789 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 61 treesize of output 57 [2021-11-20 06:02:46,792 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 146 treesize of output 130 [2021-11-20 06:02:46,840 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 39 refuted. 1 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:46,841 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [986743881] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:02:46,841 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:02:46,841 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 15, 15] total 27 [2021-11-20 06:02:46,841 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1212487497] [2021-11-20 06:02:46,841 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:02:46,841 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:02:46,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:46,841 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 3 times [2021-11-20 06:02:46,841 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:46,842 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2067558436] [2021-11-20 06:02:46,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:46,842 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:46,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:46,845 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:02:46,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:46,849 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:02:46,964 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:02:46,964 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2021-11-20 06:02:46,964 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=114, Invalid=626, Unknown=16, NotChecked=0, Total=756 [2021-11-20 06:02:46,964 INFO L87 Difference]: Start difference. First operand 66 states and 88 transitions. cyclomatic complexity: 29 Second operand has 28 states, 27 states have (on average 1.8888888888888888) internal successors, (51), 28 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:02:48,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:02:48,807 INFO L93 Difference]: Finished difference Result 93 states and 117 transitions. [2021-11-20 06:02:48,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2021-11-20 06:02:48,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 93 states and 117 transitions. [2021-11-20 06:02:48,810 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:02:48,811 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 93 states to 91 states and 113 transitions. [2021-11-20 06:02:48,811 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2021-11-20 06:02:48,811 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2021-11-20 06:02:48,811 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91 states and 113 transitions. [2021-11-20 06:02:48,812 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:02:48,812 INFO L681 BuchiCegarLoop]: Abstraction has 91 states and 113 transitions. [2021-11-20 06:02:48,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states and 113 transitions. [2021-11-20 06:02:48,813 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 37. [2021-11-20 06:02:48,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.2702702702702702) internal successors, (47), 36 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:02:48,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 47 transitions. [2021-11-20 06:02:48,814 INFO L704 BuchiCegarLoop]: Abstraction has 37 states and 47 transitions. [2021-11-20 06:02:48,815 INFO L587 BuchiCegarLoop]: Abstraction has 37 states and 47 transitions. [2021-11-20 06:02:48,815 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-20 06:02:48,815 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 47 transitions. [2021-11-20 06:02:48,815 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:02:48,815 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:02:48,816 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:02:48,816 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:02:48,817 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 06:02:48,817 INFO L791 eck$LassoCheckResult]: Stem: 5301#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5302#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5312#L367 assume !(main_~length~0#1 < 1); 5303#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5304#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5305#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5313#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5330#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5333#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5334#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5327#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5328#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5336#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5335#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5314#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5315#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5316#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5319#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5310#L370-4 main_~j~0#1 := 0; 5311#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5326#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5318#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5308#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5309#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5324#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5323#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5321#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5320#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5306#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 5307#L378-2 [2021-11-20 06:02:48,817 INFO L793 eck$LassoCheckResult]: Loop: 5307#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5322#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5307#L378-2 [2021-11-20 06:02:48,817 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:48,818 INFO L85 PathProgramCache]: Analyzing trace with hash 1543113959, now seen corresponding path program 5 times [2021-11-20 06:02:48,818 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:48,818 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [18795026] [2021-11-20 06:02:48,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:48,818 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:48,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:02:49,068 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 13 proven. 29 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:49,069 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:02:49,069 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [18795026] [2021-11-20 06:02:49,069 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [18795026] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:02:49,069 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2005509879] [2021-11-20 06:02:49,069 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-20 06:02:49,069 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:02:49,069 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:02:49,071 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:02:49,072 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2021-11-20 06:02:49,156 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2021-11-20 06:02:49,156 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 06:02:49,157 INFO L263 TraceCheckSpWp]: Trace formula consists of 136 conjuncts, 12 conjunts are in the unsatisfiable core [2021-11-20 06:02:49,157 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:02:49,380 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:49,381 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:02:49,508 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 16 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:49,508 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2005509879] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:02:49,508 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:02:49,509 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13] total 30 [2021-11-20 06:02:49,509 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [456674563] [2021-11-20 06:02:49,509 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:02:49,509 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:02:49,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:49,509 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 18 times [2021-11-20 06:02:49,509 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:49,510 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [352855540] [2021-11-20 06:02:49,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:49,510 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:49,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:49,513 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:02:49,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:49,515 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:02:49,583 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:02:49,583 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2021-11-20 06:02:49,583 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=168, Invalid=702, Unknown=0, NotChecked=0, Total=870 [2021-11-20 06:02:49,584 INFO L87 Difference]: Start difference. First operand 37 states and 47 transitions. cyclomatic complexity: 14 Second operand has 30 states, 30 states have (on average 2.1) internal successors, (63), 30 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:02:49,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:02:49,923 INFO L93 Difference]: Finished difference Result 52 states and 63 transitions. [2021-11-20 06:02:49,923 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2021-11-20 06:02:49,924 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52 states and 63 transitions. [2021-11-20 06:02:49,924 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:02:49,925 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52 states to 42 states and 53 transitions. [2021-11-20 06:02:49,925 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-20 06:02:49,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-20 06:02:49,926 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 53 transitions. [2021-11-20 06:02:49,926 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:02:49,926 INFO L681 BuchiCegarLoop]: Abstraction has 42 states and 53 transitions. [2021-11-20 06:02:49,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states and 53 transitions. [2021-11-20 06:02:49,927 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 39. [2021-11-20 06:02:49,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.2564102564102564) internal successors, (49), 38 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:02:49,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 49 transitions. [2021-11-20 06:02:49,928 INFO L704 BuchiCegarLoop]: Abstraction has 39 states and 49 transitions. [2021-11-20 06:02:49,928 INFO L587 BuchiCegarLoop]: Abstraction has 39 states and 49 transitions. [2021-11-20 06:02:49,928 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-20 06:02:49,929 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 49 transitions. [2021-11-20 06:02:49,929 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:02:49,929 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:02:49,929 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:02:49,930 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:02:49,930 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 06:02:49,930 INFO L791 eck$LassoCheckResult]: Stem: 5603#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5604#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5614#L367 assume !(main_~length~0#1 < 1); 5605#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5606#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5607#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5615#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5641#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5616#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5617#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5621#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5622#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5640#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5639#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5638#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5637#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5636#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5635#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5633#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5619#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5623#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5608#L370-4 main_~j~0#1 := 0; 5609#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5620#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5629#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5628#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5627#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5626#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5625#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5610#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 5611#L378-2 [2021-11-20 06:02:49,931 INFO L793 eck$LassoCheckResult]: Loop: 5611#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5624#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5611#L378-2 [2021-11-20 06:02:49,931 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:49,931 INFO L85 PathProgramCache]: Analyzing trace with hash -2086076244, now seen corresponding path program 12 times [2021-11-20 06:02:49,931 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:49,932 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1258232690] [2021-11-20 06:02:49,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:49,932 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:49,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:02:50,343 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:50,343 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:02:50,343 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1258232690] [2021-11-20 06:02:50,343 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1258232690] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:02:50,343 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2079144936] [2021-11-20 06:02:50,343 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-20 06:02:50,343 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:02:50,343 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:02:50,345 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:02:50,347 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2021-11-20 06:02:50,419 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 6 check-sat command(s) [2021-11-20 06:02:50,419 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 06:02:50,420 INFO L263 TraceCheckSpWp]: Trace formula consists of 140 conjuncts, 27 conjunts are in the unsatisfiable core [2021-11-20 06:02:50,421 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:02:50,491 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-20 06:02:50,659 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-11-20 06:02:50,659 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 50 treesize of output 41 [2021-11-20 06:02:50,696 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-11-20 06:02:50,697 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 50 treesize of output 41 [2021-11-20 06:02:51,535 INFO L354 Elim1Store]: treesize reduction 42, result has 6.7 percent of original size [2021-11-20 06:02:51,535 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 55 treesize of output 28 [2021-11-20 06:02:51,562 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:51,562 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:02:53,208 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-11-20 06:02:53,211 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-11-20 06:02:53,272 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 1 proven. 45 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-11-20 06:02:53,273 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2079144936] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:02:53,273 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:02:53,273 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 14, 13] total 24 [2021-11-20 06:02:53,273 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1221183440] [2021-11-20 06:02:53,273 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:02:53,274 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:02:53,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:53,274 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 19 times [2021-11-20 06:02:53,274 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:53,274 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [790001535] [2021-11-20 06:02:53,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:53,275 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:53,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:53,277 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:02:53,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:53,280 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:02:53,332 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:02:53,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2021-11-20 06:02:53,332 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=94, Invalid=506, Unknown=0, NotChecked=0, Total=600 [2021-11-20 06:02:53,332 INFO L87 Difference]: Start difference. First operand 39 states and 49 transitions. cyclomatic complexity: 14 Second operand has 25 states, 24 states have (on average 2.1666666666666665) internal successors, (52), 25 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:02:53,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:02:53,493 INFO L93 Difference]: Finished difference Result 76 states and 93 transitions. [2021-11-20 06:02:53,493 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-11-20 06:02:53,494 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76 states and 93 transitions. [2021-11-20 06:02:53,495 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:02:53,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76 states to 75 states and 91 transitions. [2021-11-20 06:02:53,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2021-11-20 06:02:53,496 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2021-11-20 06:02:53,496 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75 states and 91 transitions. [2021-11-20 06:02:53,496 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:02:53,496 INFO L681 BuchiCegarLoop]: Abstraction has 75 states and 91 transitions. [2021-11-20 06:02:53,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states and 91 transitions. [2021-11-20 06:02:53,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 46. [2021-11-20 06:02:53,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 46 states have (on average 1.326086956521739) internal successors, (61), 45 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:02:53,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 61 transitions. [2021-11-20 06:02:53,498 INFO L704 BuchiCegarLoop]: Abstraction has 46 states and 61 transitions. [2021-11-20 06:02:53,498 INFO L587 BuchiCegarLoop]: Abstraction has 46 states and 61 transitions. [2021-11-20 06:02:53,498 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-11-20 06:02:53,498 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46 states and 61 transitions. [2021-11-20 06:02:53,499 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:02:53,499 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:02:53,499 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:02:53,500 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:02:53,500 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 06:02:53,500 INFO L791 eck$LassoCheckResult]: Stem: 5920#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5921#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5931#L367 assume !(main_~length~0#1 < 1); 5922#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5923#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5924#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5932#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5936#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5933#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5934#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5937#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5938#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5965#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5964#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5963#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5962#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5961#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5960#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5959#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5953#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5955#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5929#L370-4 main_~j~0#1 := 0; 5930#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5927#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5928#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5935#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5944#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5943#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5942#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5940#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5939#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5925#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 5926#L378-2 [2021-11-20 06:02:53,500 INFO L793 eck$LassoCheckResult]: Loop: 5926#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5941#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5926#L378-2 [2021-11-20 06:02:53,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:53,501 INFO L85 PathProgramCache]: Analyzing trace with hash 1030456175, now seen corresponding path program 13 times [2021-11-20 06:02:53,501 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:53,501 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [741750328] [2021-11-20 06:02:53,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:53,501 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:53,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:02:53,727 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:53,728 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:02:53,728 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [741750328] [2021-11-20 06:02:53,728 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [741750328] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:02:53,728 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [865437055] [2021-11-20 06:02:53,728 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-20 06:02:53,728 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:02:53,728 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:02:53,730 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:02:53,731 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2021-11-20 06:02:53,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:02:53,774 INFO L263 TraceCheckSpWp]: Trace formula consists of 152 conjuncts, 28 conjunts are in the unsatisfiable core [2021-11-20 06:02:53,775 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:02:53,987 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-11-20 06:02:54,328 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-20 06:02:54,331 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:54,331 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:02:54,625 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2021-11-20 06:02:54,630 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 26 [2021-11-20 06:02:54,730 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:54,730 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [865437055] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:02:54,730 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:02:54,731 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 13] total 33 [2021-11-20 06:02:54,731 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1274926192] [2021-11-20 06:02:54,731 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:02:54,731 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:02:54,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:54,732 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 20 times [2021-11-20 06:02:54,732 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:54,732 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [703624257] [2021-11-20 06:02:54,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:54,732 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:54,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:54,736 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:02:54,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:54,739 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:02:54,822 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:02:54,822 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2021-11-20 06:02:54,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=1002, Unknown=0, NotChecked=0, Total=1122 [2021-11-20 06:02:54,823 INFO L87 Difference]: Start difference. First operand 46 states and 61 transitions. cyclomatic complexity: 20 Second operand has 34 states, 33 states have (on average 2.242424242424242) internal successors, (74), 34 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:02:55,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:02:55,464 INFO L93 Difference]: Finished difference Result 65 states and 83 transitions. [2021-11-20 06:02:55,465 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2021-11-20 06:02:55,465 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65 states and 83 transitions. [2021-11-20 06:02:55,466 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-20 06:02:55,466 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65 states to 64 states and 82 transitions. [2021-11-20 06:02:55,467 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-11-20 06:02:55,467 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-11-20 06:02:55,467 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64 states and 82 transitions. [2021-11-20 06:02:55,467 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:02:55,468 INFO L681 BuchiCegarLoop]: Abstraction has 64 states and 82 transitions. [2021-11-20 06:02:55,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states and 82 transitions. [2021-11-20 06:02:55,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 52. [2021-11-20 06:02:55,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.3076923076923077) internal successors, (68), 51 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:02:55,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 68 transitions. [2021-11-20 06:02:55,470 INFO L704 BuchiCegarLoop]: Abstraction has 52 states and 68 transitions. [2021-11-20 06:02:55,470 INFO L587 BuchiCegarLoop]: Abstraction has 52 states and 68 transitions. [2021-11-20 06:02:55,471 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-11-20 06:02:55,471 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 68 transitions. [2021-11-20 06:02:55,471 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:02:55,471 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:02:55,472 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:02:55,472 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:02:55,473 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 06:02:55,473 INFO L791 eck$LassoCheckResult]: Stem: 6258#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6259#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6269#L367 assume !(main_~length~0#1 < 1); 6260#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6261#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6262#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6270#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6273#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6271#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6272#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6309#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6308#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6307#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6306#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6305#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6304#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6303#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6301#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6298#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6299#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6302#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6263#L370-4 main_~j~0#1 := 0; 6264#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6267#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6268#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6283#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6282#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6281#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6280#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6279#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6278#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6265#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 6266#L378-2 [2021-11-20 06:02:55,473 INFO L793 eck$LassoCheckResult]: Loop: 6266#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6277#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6266#L378-2 [2021-11-20 06:02:55,473 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:55,474 INFO L85 PathProgramCache]: Analyzing trace with hash 19338925, now seen corresponding path program 6 times [2021-11-20 06:02:55,474 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:55,474 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476737364] [2021-11-20 06:02:55,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:55,474 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:55,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:02:55,940 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:55,940 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:02:55,940 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [476737364] [2021-11-20 06:02:55,940 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [476737364] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:02:55,940 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1896569533] [2021-11-20 06:02:55,940 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-20 06:02:55,941 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:02:55,941 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:02:55,942 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:02:55,943 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2021-11-20 06:02:56,010 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 6 check-sat command(s) [2021-11-20 06:02:56,010 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 06:02:56,025 INFO L263 TraceCheckSpWp]: Trace formula consists of 148 conjuncts, 21 conjunts are in the unsatisfiable core [2021-11-20 06:02:56,026 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:02:56,203 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-20 06:02:56,853 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-11-20 06:02:56,854 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 23 [2021-11-20 06:02:56,874 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 16 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:56,874 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:02:59,346 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 50 treesize of output 46 [2021-11-20 06:02:59,350 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 40 [2021-11-20 06:02:59,398 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 12 proven. 43 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:02:59,398 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1896569533] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:02:59,399 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:02:59,399 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 16, 16] total 38 [2021-11-20 06:02:59,399 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1881283570] [2021-11-20 06:02:59,399 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:02:59,399 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:02:59,400 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:02:59,400 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 21 times [2021-11-20 06:02:59,400 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:02:59,400 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892113330] [2021-11-20 06:02:59,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:02:59,401 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:02:59,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:59,404 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:02:59,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:02:59,407 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:02:59,475 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:02:59,475 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2021-11-20 06:02:59,476 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=1291, Unknown=1, NotChecked=0, Total=1482 [2021-11-20 06:02:59,476 INFO L87 Difference]: Start difference. First operand 52 states and 68 transitions. cyclomatic complexity: 21 Second operand has 39 states, 38 states have (on average 1.9210526315789473) internal successors, (73), 39 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:03:00,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:03:00,589 INFO L93 Difference]: Finished difference Result 71 states and 88 transitions. [2021-11-20 06:03:00,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2021-11-20 06:03:00,590 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71 states and 88 transitions. [2021-11-20 06:03:00,591 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:03:00,591 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71 states to 48 states and 62 transitions. [2021-11-20 06:03:00,591 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-20 06:03:00,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-20 06:03:00,592 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48 states and 62 transitions. [2021-11-20 06:03:00,592 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:03:00,592 INFO L681 BuchiCegarLoop]: Abstraction has 48 states and 62 transitions. [2021-11-20 06:03:00,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states and 62 transitions. [2021-11-20 06:03:00,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 48. [2021-11-20 06:03:00,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48 states, 48 states have (on average 1.2916666666666667) internal successors, (62), 47 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:03:00,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 62 transitions. [2021-11-20 06:03:00,594 INFO L704 BuchiCegarLoop]: Abstraction has 48 states and 62 transitions. [2021-11-20 06:03:00,594 INFO L587 BuchiCegarLoop]: Abstraction has 48 states and 62 transitions. [2021-11-20 06:03:00,594 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-11-20 06:03:00,594 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48 states and 62 transitions. [2021-11-20 06:03:00,595 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:03:00,595 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:03:00,595 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:03:00,596 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:03:00,596 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 06:03:00,596 INFO L791 eck$LassoCheckResult]: Stem: 6659#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6660#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6670#L367 assume !(main_~length~0#1 < 1); 6661#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6662#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6663#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6671#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6675#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6672#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6673#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6706#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6705#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6704#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6703#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6702#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6701#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6700#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6699#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6696#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6694#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6692#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6690#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6688#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6684#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6668#L370-4 main_~j~0#1 := 0; 6669#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6666#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6667#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6680#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6679#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6678#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6677#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6664#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 6665#L378-2 [2021-11-20 06:03:00,596 INFO L793 eck$LassoCheckResult]: Loop: 6665#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6676#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6665#L378-2 [2021-11-20 06:03:00,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:03:00,597 INFO L85 PathProgramCache]: Analyzing trace with hash -540432926, now seen corresponding path program 14 times [2021-11-20 06:03:00,597 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:03:00,597 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1157363522] [2021-11-20 06:03:00,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:03:00,598 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:03:00,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:03:01,086 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:03:01,086 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:03:01,086 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1157363522] [2021-11-20 06:03:01,086 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1157363522] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:03:01,086 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1437750959] [2021-11-20 06:03:01,086 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-20 06:03:01,087 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:03:01,087 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:03:01,093 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:03:01,120 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2021-11-20 06:03:01,168 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-20 06:03:01,168 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 06:03:01,170 INFO L263 TraceCheckSpWp]: Trace formula consists of 152 conjuncts, 29 conjunts are in the unsatisfiable core [2021-11-20 06:03:01,172 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:03:01,261 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-20 06:03:01,414 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-20 06:03:01,414 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 28 [2021-11-20 06:03:01,445 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-20 06:03:01,445 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 28 [2021-11-20 06:03:01,642 INFO L354 Elim1Store]: treesize reduction 80, result has 20.8 percent of original size [2021-11-20 06:03:01,642 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 54 treesize of output 50 [2021-11-20 06:03:04,373 INFO L354 Elim1Store]: treesize reduction 13, result has 7.1 percent of original size [2021-11-20 06:03:04,374 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 43 treesize of output 17 [2021-11-20 06:03:04,377 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:03:04,378 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:03:26,010 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 61 treesize of output 57 [2021-11-20 06:03:26,013 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 146 treesize of output 130 [2021-11-20 06:03:26,109 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 61 refuted. 1 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:03:26,109 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1437750959] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:03:26,110 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:03:26,110 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 16, 16] total 28 [2021-11-20 06:03:26,110 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [917269988] [2021-11-20 06:03:26,110 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:03:26,110 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:03:26,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:03:26,111 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 22 times [2021-11-20 06:03:26,111 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:03:26,111 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1566324968] [2021-11-20 06:03:26,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:03:26,111 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:03:26,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:03:26,115 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:03:26,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:03:26,119 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:03:26,201 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:03:26,202 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2021-11-20 06:03:26,202 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=112, Invalid=686, Unknown=14, NotChecked=0, Total=812 [2021-11-20 06:03:26,203 INFO L87 Difference]: Start difference. First operand 48 states and 62 transitions. cyclomatic complexity: 19 Second operand has 29 states, 28 states have (on average 2.0714285714285716) internal successors, (58), 29 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:03:29,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:03:29,774 INFO L93 Difference]: Finished difference Result 78 states and 96 transitions. [2021-11-20 06:03:29,775 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2021-11-20 06:03:29,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78 states and 96 transitions. [2021-11-20 06:03:29,776 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:03:29,776 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78 states to 77 states and 94 transitions. [2021-11-20 06:03:29,777 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-11-20 06:03:29,779 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-11-20 06:03:29,779 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77 states and 94 transitions. [2021-11-20 06:03:29,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:03:29,780 INFO L681 BuchiCegarLoop]: Abstraction has 77 states and 94 transitions. [2021-11-20 06:03:29,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states and 94 transitions. [2021-11-20 06:03:29,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 37. [2021-11-20 06:03:29,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.2432432432432432) internal successors, (46), 36 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:03:29,781 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 46 transitions. [2021-11-20 06:03:29,781 INFO L704 BuchiCegarLoop]: Abstraction has 37 states and 46 transitions. [2021-11-20 06:03:29,781 INFO L587 BuchiCegarLoop]: Abstraction has 37 states and 46 transitions. [2021-11-20 06:03:29,782 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-11-20 06:03:29,782 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 46 transitions. [2021-11-20 06:03:29,782 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:03:29,782 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:03:29,782 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:03:29,783 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:03:29,783 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 06:03:29,783 INFO L791 eck$LassoCheckResult]: Stem: 7014#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7015#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7025#L367 assume !(main_~length~0#1 < 1); 7016#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7017#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7018#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7026#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7029#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7027#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7028#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7050#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7049#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7048#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7047#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7046#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7045#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7044#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7043#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7042#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7041#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7040#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7036#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7039#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7035#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7019#L370-4 main_~j~0#1 := 0; 7020#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7023#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7024#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7030#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7038#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7037#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7034#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7033#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7032#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7021#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 7022#L378-2 [2021-11-20 06:03:29,783 INFO L793 eck$LassoCheckResult]: Loop: 7022#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7031#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7022#L378-2 [2021-11-20 06:03:29,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:03:29,784 INFO L85 PathProgramCache]: Analyzing trace with hash -1253347545, now seen corresponding path program 7 times [2021-11-20 06:03:29,784 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:03:29,784 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [502676131] [2021-11-20 06:03:29,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:03:29,784 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:03:29,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:03:30,265 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:03:30,266 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:03:30,266 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [502676131] [2021-11-20 06:03:30,266 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [502676131] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:03:30,266 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1203332246] [2021-11-20 06:03:30,266 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-20 06:03:30,266 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:03:30,266 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:03:30,268 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:03:30,269 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2021-11-20 06:03:30,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:03:30,321 INFO L263 TraceCheckSpWp]: Trace formula consists of 160 conjuncts, 34 conjunts are in the unsatisfiable core [2021-11-20 06:03:30,322 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:03:30,592 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-20 06:03:30,793 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-20 06:03:30,793 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 30 treesize of output 29 [2021-11-20 06:03:31,199 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2021-11-20 06:03:31,227 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:03:31,227 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:03:31,538 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-11-20 06:03:31,542 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-11-20 06:03:31,628 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:03:31,628 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1203332246] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:03:31,629 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:03:31,629 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 17, 16] total 34 [2021-11-20 06:03:31,629 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [337155410] [2021-11-20 06:03:31,629 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:03:31,629 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:03:31,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:03:31,629 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 23 times [2021-11-20 06:03:31,629 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:03:31,630 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1686640727] [2021-11-20 06:03:31,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:03:31,630 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:03:31,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:03:31,636 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:03:31,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:03:31,639 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:03:31,705 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:03:31,706 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2021-11-20 06:03:31,706 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=129, Invalid=1061, Unknown=0, NotChecked=0, Total=1190 [2021-11-20 06:03:31,706 INFO L87 Difference]: Start difference. First operand 37 states and 46 transitions. cyclomatic complexity: 12 Second operand has 35 states, 34 states have (on average 2.1176470588235294) internal successors, (72), 35 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:03:32,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:03:32,503 INFO L93 Difference]: Finished difference Result 41 states and 50 transitions. [2021-11-20 06:03:32,503 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-11-20 06:03:32,504 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41 states and 50 transitions. [2021-11-20 06:03:32,509 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:03:32,510 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41 states to 40 states and 49 transitions. [2021-11-20 06:03:32,510 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-11-20 06:03:32,510 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-11-20 06:03:32,510 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40 states and 49 transitions. [2021-11-20 06:03:32,510 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:03:32,511 INFO L681 BuchiCegarLoop]: Abstraction has 40 states and 49 transitions. [2021-11-20 06:03:32,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states and 49 transitions. [2021-11-20 06:03:32,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 39. [2021-11-20 06:03:32,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.2307692307692308) internal successors, (48), 38 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:03:32,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 48 transitions. [2021-11-20 06:03:32,518 INFO L704 BuchiCegarLoop]: Abstraction has 39 states and 48 transitions. [2021-11-20 06:03:32,518 INFO L587 BuchiCegarLoop]: Abstraction has 39 states and 48 transitions. [2021-11-20 06:03:32,518 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-11-20 06:03:32,518 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 48 transitions. [2021-11-20 06:03:32,518 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:03:32,518 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:03:32,519 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:03:32,519 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:03:32,519 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 06:03:32,519 INFO L791 eck$LassoCheckResult]: Stem: 7348#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7349#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7357#L367 assume !(main_~length~0#1 < 1); 7346#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7347#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7350#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7358#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7361#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7359#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7360#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7377#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7376#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7375#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7374#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7373#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7372#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7371#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7370#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7369#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7368#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7367#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7365#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7366#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7364#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7351#L370-4 main_~j~0#1 := 0; 7352#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7362#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7363#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7355#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7356#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7384#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7383#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7382#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7381#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7380#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7379#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7353#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 7354#L378-2 [2021-11-20 06:03:32,519 INFO L793 eck$LassoCheckResult]: Loop: 7354#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7378#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7354#L378-2 [2021-11-20 06:03:32,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:03:32,520 INFO L85 PathProgramCache]: Analyzing trace with hash -1876148438, now seen corresponding path program 8 times [2021-11-20 06:03:32,520 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:03:32,520 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [204051973] [2021-11-20 06:03:32,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:03:32,520 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:03:32,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:03:33,104 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:03:33,105 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:03:33,105 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [204051973] [2021-11-20 06:03:33,105 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [204051973] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:03:33,105 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1328219636] [2021-11-20 06:03:33,105 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-20 06:03:33,105 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:03:33,105 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:03:33,107 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:03:33,108 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2021-11-20 06:03:33,165 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-20 06:03:33,165 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 06:03:33,167 INFO L263 TraceCheckSpWp]: Trace formula consists of 172 conjuncts, 32 conjunts are in the unsatisfiable core [2021-11-20 06:03:33,167 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:03:33,270 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-20 06:03:33,760 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 13 [2021-11-20 06:03:33,792 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:03:33,793 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:03:34,062 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 35 [2021-11-20 06:03:34,065 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 44 [2021-11-20 06:03:34,164 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:03:34,165 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1328219636] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:03:34,165 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:03:34,165 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 16, 16] total 25 [2021-11-20 06:03:34,165 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [83304454] [2021-11-20 06:03:34,165 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:03:34,165 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:03:34,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:03:34,166 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 24 times [2021-11-20 06:03:34,166 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:03:34,166 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437894401] [2021-11-20 06:03:34,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:03:34,166 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:03:34,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:03:34,168 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:03:34,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:03:34,170 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:03:34,239 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:03:34,240 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2021-11-20 06:03:34,240 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=577, Unknown=0, NotChecked=0, Total=650 [2021-11-20 06:03:34,240 INFO L87 Difference]: Start difference. First operand 39 states and 48 transitions. cyclomatic complexity: 12 Second operand has 26 states, 25 states have (on average 2.2) internal successors, (55), 26 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:03:35,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:03:35,103 INFO L93 Difference]: Finished difference Result 63 states and 77 transitions. [2021-11-20 06:03:35,103 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-11-20 06:03:35,104 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 77 transitions. [2021-11-20 06:03:35,105 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-20 06:03:35,105 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 62 states and 76 transitions. [2021-11-20 06:03:35,105 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2021-11-20 06:03:35,105 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2021-11-20 06:03:35,106 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62 states and 76 transitions. [2021-11-20 06:03:35,106 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:03:35,106 INFO L681 BuchiCegarLoop]: Abstraction has 62 states and 76 transitions. [2021-11-20 06:03:35,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states and 76 transitions. [2021-11-20 06:03:35,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 46. [2021-11-20 06:03:35,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 46 states have (on average 1.2391304347826086) internal successors, (57), 45 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:03:35,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 57 transitions. [2021-11-20 06:03:35,107 INFO L704 BuchiCegarLoop]: Abstraction has 46 states and 57 transitions. [2021-11-20 06:03:35,107 INFO L587 BuchiCegarLoop]: Abstraction has 46 states and 57 transitions. [2021-11-20 06:03:35,107 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-11-20 06:03:35,108 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46 states and 57 transitions. [2021-11-20 06:03:35,108 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:03:35,108 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:03:35,108 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:03:35,109 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:03:35,109 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 06:03:35,109 INFO L791 eck$LassoCheckResult]: Stem: 7697#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7698#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7708#L367 assume !(main_~length~0#1 < 1); 7699#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7700#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7701#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7709#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7714#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7710#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7711#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7715#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7716#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7729#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7728#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7727#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7726#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7725#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7724#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7723#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7722#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7721#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7718#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7720#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7741#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7740#L370-4 main_~j~0#1 := 0; 7712#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7704#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7705#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7738#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7737#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7736#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7735#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7734#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7733#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7732#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7731#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7702#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 7703#L378-2 [2021-11-20 06:03:35,110 INFO L793 eck$LassoCheckResult]: Loop: 7703#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7730#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7703#L378-2 [2021-11-20 06:03:35,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:03:35,110 INFO L85 PathProgramCache]: Analyzing trace with hash -855080084, now seen corresponding path program 15 times [2021-11-20 06:03:35,110 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:03:35,111 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [579524598] [2021-11-20 06:03:35,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:03:35,111 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:03:35,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:03:35,438 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:03:35,438 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:03:35,439 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [579524598] [2021-11-20 06:03:35,439 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [579524598] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:03:35,439 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1678982740] [2021-11-20 06:03:35,439 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-20 06:03:35,439 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:03:35,439 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:03:35,441 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:03:35,443 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2021-11-20 06:03:35,567 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2021-11-20 06:03:35,567 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 06:03:35,569 INFO L263 TraceCheckSpWp]: Trace formula consists of 176 conjuncts, 19 conjunts are in the unsatisfiable core [2021-11-20 06:03:35,570 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:03:35,842 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-20 06:03:36,572 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-11-20 06:03:36,573 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 21 [2021-11-20 06:03:36,576 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 25 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:03:36,576 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:03:37,382 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 27 [2021-11-20 06:03:37,385 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 38 [2021-11-20 06:03:37,448 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 20 proven. 61 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:03:37,448 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1678982740] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:03:37,448 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:03:37,449 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 17, 17] total 41 [2021-11-20 06:03:37,449 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1416273593] [2021-11-20 06:03:37,449 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:03:37,449 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:03:37,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:03:37,449 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 25 times [2021-11-20 06:03:37,449 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:03:37,450 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1234253904] [2021-11-20 06:03:37,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:03:37,450 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:03:37,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:03:37,452 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:03:37,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:03:37,455 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:03:37,514 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:03:37,515 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2021-11-20 06:03:37,515 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=214, Invalid=1508, Unknown=0, NotChecked=0, Total=1722 [2021-11-20 06:03:37,515 INFO L87 Difference]: Start difference. First operand 46 states and 57 transitions. cyclomatic complexity: 15 Second operand has 42 states, 41 states have (on average 2.073170731707317) internal successors, (85), 42 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:03:38,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:03:38,517 INFO L93 Difference]: Finished difference Result 75 states and 89 transitions. [2021-11-20 06:03:38,518 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2021-11-20 06:03:38,518 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 89 transitions. [2021-11-20 06:03:38,519 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:03:38,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 60 states and 72 transitions. [2021-11-20 06:03:38,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-20 06:03:38,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-20 06:03:38,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 72 transitions. [2021-11-20 06:03:38,520 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:03:38,520 INFO L681 BuchiCegarLoop]: Abstraction has 60 states and 72 transitions. [2021-11-20 06:03:38,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 72 transitions. [2021-11-20 06:03:38,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 49. [2021-11-20 06:03:38,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 49 states have (on average 1.2448979591836735) internal successors, (61), 48 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:03:38,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 61 transitions. [2021-11-20 06:03:38,521 INFO L704 BuchiCegarLoop]: Abstraction has 49 states and 61 transitions. [2021-11-20 06:03:38,521 INFO L587 BuchiCegarLoop]: Abstraction has 49 states and 61 transitions. [2021-11-20 06:03:38,521 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-11-20 06:03:38,521 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49 states and 61 transitions. [2021-11-20 06:03:38,522 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:03:38,522 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:03:38,522 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:03:38,522 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:03:38,522 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 06:03:38,523 INFO L791 eck$LassoCheckResult]: Stem: 8122#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8123#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8133#L367 assume !(main_~length~0#1 < 1); 8124#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8125#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8126#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8134#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8137#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8135#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8136#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8170#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8169#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8168#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8167#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8166#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8165#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8164#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8163#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8162#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8161#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8160#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8159#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8156#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8154#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8153#L370-4 main_~j~0#1 := 0; 8152#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8131#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8132#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8138#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8150#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8149#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8148#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8147#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8146#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8145#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8144#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8142#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8141#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8129#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 8130#L378-2 [2021-11-20 06:03:38,523 INFO L793 eck$LassoCheckResult]: Loop: 8130#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8143#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8130#L378-2 [2021-11-20 06:03:38,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:03:38,523 INFO L85 PathProgramCache]: Analyzing trace with hash 907614829, now seen corresponding path program 9 times [2021-11-20 06:03:38,523 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:03:38,523 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [361171473] [2021-11-20 06:03:38,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:03:38,523 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:03:38,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:03:38,962 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 31 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:03:38,962 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:03:38,962 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [361171473] [2021-11-20 06:03:38,962 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [361171473] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:03:38,962 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [23378753] [2021-11-20 06:03:38,962 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-20 06:03:38,962 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:03:38,962 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:03:38,964 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:03:39,015 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2021-11-20 06:03:39,081 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2021-11-20 06:03:39,081 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 06:03:39,083 INFO L263 TraceCheckSpWp]: Trace formula consists of 184 conjuncts, 16 conjunts are in the unsatisfiable core [2021-11-20 06:03:39,083 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:03:39,546 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 42 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:03:39,546 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:03:39,869 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 42 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:03:39,869 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [23378753] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:03:39,869 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:03:39,869 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17, 17] total 40 [2021-11-20 06:03:39,869 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [888216077] [2021-11-20 06:03:39,869 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:03:39,870 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:03:39,870 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:03:39,870 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 26 times [2021-11-20 06:03:39,870 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:03:39,870 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [662301341] [2021-11-20 06:03:39,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:03:39,871 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:03:39,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:03:39,874 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:03:39,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:03:39,877 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:03:39,971 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:03:39,971 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2021-11-20 06:03:39,972 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=1274, Unknown=0, NotChecked=0, Total=1560 [2021-11-20 06:03:39,972 INFO L87 Difference]: Start difference. First operand 49 states and 61 transitions. cyclomatic complexity: 16 Second operand has 40 states, 40 states have (on average 2.2) internal successors, (88), 40 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:03:40,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:03:40,608 INFO L93 Difference]: Finished difference Result 69 states and 83 transitions. [2021-11-20 06:03:40,608 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-11-20 06:03:40,608 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69 states and 83 transitions. [2021-11-20 06:03:40,609 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:03:40,610 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69 states to 55 states and 69 transitions. [2021-11-20 06:03:40,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-20 06:03:40,610 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-20 06:03:40,610 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55 states and 69 transitions. [2021-11-20 06:03:40,611 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:03:40,611 INFO L681 BuchiCegarLoop]: Abstraction has 55 states and 69 transitions. [2021-11-20 06:03:40,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states and 69 transitions. [2021-11-20 06:03:40,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 51. [2021-11-20 06:03:40,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.2352941176470589) internal successors, (63), 50 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:03:40,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 63 transitions. [2021-11-20 06:03:40,613 INFO L704 BuchiCegarLoop]: Abstraction has 51 states and 63 transitions. [2021-11-20 06:03:40,613 INFO L587 BuchiCegarLoop]: Abstraction has 51 states and 63 transitions. [2021-11-20 06:03:40,613 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-11-20 06:03:40,614 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 63 transitions. [2021-11-20 06:03:40,614 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:03:40,614 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:03:40,614 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:03:40,615 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:03:40,615 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 06:03:40,615 INFO L791 eck$LassoCheckResult]: Stem: 8527#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8528#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8538#L367 assume !(main_~length~0#1 < 1); 8529#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8530#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8531#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8539#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8542#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8544#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8577#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8576#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8575#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8574#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8573#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8572#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8571#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8570#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8569#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8568#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8567#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8566#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8564#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8565#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8540#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8541#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8556#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8545#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8532#L370-4 main_~j~0#1 := 0; 8533#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8543#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8555#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8554#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8553#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8552#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8551#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8550#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8549#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8547#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8546#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8534#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 8535#L378-2 [2021-11-20 06:03:40,616 INFO L793 eck$LassoCheckResult]: Loop: 8535#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8548#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8535#L378-2 [2021-11-20 06:03:40,616 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:03:40,616 INFO L85 PathProgramCache]: Analyzing trace with hash 836329326, now seen corresponding path program 16 times [2021-11-20 06:03:40,616 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:03:40,617 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815993898] [2021-11-20 06:03:40,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:03:40,617 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:03:40,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:03:41,017 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:03:41,017 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:03:41,017 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1815993898] [2021-11-20 06:03:41,017 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1815993898] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:03:41,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [585072229] [2021-11-20 06:03:41,018 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-20 06:03:41,018 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:03:41,018 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:03:41,021 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:03:41,022 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2021-11-20 06:03:41,067 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-20 06:03:41,067 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 06:03:41,069 INFO L263 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 34 conjunts are in the unsatisfiable core [2021-11-20 06:03:41,069 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:03:41,300 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-20 06:03:41,379 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-20 06:03:41,379 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-20 06:03:41,693 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-20 06:03:41,696 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:03:41,696 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:03:54,214 WARN L838 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_268| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_268| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((|ULTIMATE.start_main_#t~nondet208#1| Int)) (= (mod (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_268| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) |ULTIMATE.start_main_#t~nondet208#1|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 20)) 2) 0)))) is different from false [2021-11-20 06:03:54,235 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 29 [2021-11-20 06:03:54,239 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 195 treesize of output 187 [2021-11-20 06:03:54,418 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 94 refuted. 0 times theorem prover too weak. 0 trivial. 6 not checked. [2021-11-20 06:03:54,418 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [585072229] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:03:54,418 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:03:54,419 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 18, 17] total 43 [2021-11-20 06:03:54,419 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1613034251] [2021-11-20 06:03:54,419 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:03:54,419 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:03:54,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:03:54,420 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 27 times [2021-11-20 06:03:54,420 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:03:54,420 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815110318] [2021-11-20 06:03:54,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:03:54,420 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:03:54,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:03:54,424 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:03:54,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:03:54,428 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:03:54,528 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:03:54,529 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2021-11-20 06:03:54,530 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=1643, Unknown=1, NotChecked=82, Total=1892 [2021-11-20 06:03:54,530 INFO L87 Difference]: Start difference. First operand 51 states and 63 transitions. cyclomatic complexity: 16 Second operand has 44 states, 43 states have (on average 2.2093023255813953) internal successors, (95), 44 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:04:06,935 WARN L838 $PredicateComparison]: unable to prove that (and (= 5 |c_ULTIMATE.start_main_~i~0#1|) (= |c_ULTIMATE.start_main_~arr~0#1.offset| 0) (forall ((|v_ULTIMATE.start_main_~i~0#1_268| Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_268| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (forall ((|ULTIMATE.start_main_#t~nondet208#1| Int)) (= (mod (select (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ (* |v_ULTIMATE.start_main_~i~0#1_268| 4) |c_ULTIMATE.start_main_~arr~0#1.offset|) |ULTIMATE.start_main_#t~nondet208#1|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 20)) 2) 0)))) (= 0 (select (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4))))) is different from false [2021-11-20 06:04:07,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:04:07,296 INFO L93 Difference]: Finished difference Result 73 states and 89 transitions. [2021-11-20 06:04:07,297 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-11-20 06:04:07,297 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73 states and 89 transitions. [2021-11-20 06:04:07,298 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-20 06:04:07,298 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73 states to 72 states and 88 transitions. [2021-11-20 06:04:07,298 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-11-20 06:04:07,299 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-11-20 06:04:07,299 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72 states and 88 transitions. [2021-11-20 06:04:07,299 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:04:07,299 INFO L681 BuchiCegarLoop]: Abstraction has 72 states and 88 transitions. [2021-11-20 06:04:07,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states and 88 transitions. [2021-11-20 06:04:07,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 54. [2021-11-20 06:04:07,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54 states, 54 states have (on average 1.2592592592592593) internal successors, (68), 53 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:04:07,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 68 transitions. [2021-11-20 06:04:07,302 INFO L704 BuchiCegarLoop]: Abstraction has 54 states and 68 transitions. [2021-11-20 06:04:07,302 INFO L587 BuchiCegarLoop]: Abstraction has 54 states and 68 transitions. [2021-11-20 06:04:07,302 INFO L425 BuchiCegarLoop]: ======== Iteration 33============ [2021-11-20 06:04:07,302 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54 states and 68 transitions. [2021-11-20 06:04:07,303 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:04:07,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:04:07,303 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:04:07,304 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:04:07,304 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 06:04:07,304 INFO L791 eck$LassoCheckResult]: Stem: 8936#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8937#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8947#L367 assume !(main_~length~0#1 < 1); 8938#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8939#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8940#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8948#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8974#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8949#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8950#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8951#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8954#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8973#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8972#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8971#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8970#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8969#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8968#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8967#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8966#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8965#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8963#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8964#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8960#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8956#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8988#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8986#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8985#L370-4 main_~j~0#1 := 0; 8952#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8945#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8946#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8983#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8982#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8981#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8980#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8979#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8978#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8976#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8975#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8943#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 8944#L378-2 [2021-11-20 06:04:07,304 INFO L793 eck$LassoCheckResult]: Loop: 8944#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8977#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8944#L378-2 [2021-11-20 06:04:07,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:04:07,305 INFO L85 PathProgramCache]: Analyzing trace with hash 168453938, now seen corresponding path program 17 times [2021-11-20 06:04:07,305 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:04:07,305 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [635175897] [2021-11-20 06:04:07,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:04:07,306 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:04:07,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:04:08,027 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:04:08,027 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:04:08,027 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [635175897] [2021-11-20 06:04:08,027 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [635175897] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:04:08,027 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [458792150] [2021-11-20 06:04:08,027 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-20 06:04:08,027 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:04:08,028 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:04:08,033 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:04:08,056 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2021-11-20 06:04:08,128 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2021-11-20 06:04:08,128 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 06:04:08,130 INFO L263 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 35 conjunts are in the unsatisfiable core [2021-11-20 06:04:08,131 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:04:08,239 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-20 06:04:08,401 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-11-20 06:04:08,402 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 52 treesize of output 43 [2021-11-20 06:04:08,432 INFO L354 Elim1Store]: treesize reduction 37, result has 22.9 percent of original size [2021-11-20 06:04:08,432 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 52 treesize of output 43 [2021-11-20 06:04:09,650 INFO L354 Elim1Store]: treesize reduction 46, result has 6.1 percent of original size [2021-11-20 06:04:09,651 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 65 treesize of output 36 [2021-11-20 06:04:09,689 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:04:09,689 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:04:11,622 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 35 [2021-11-20 06:04:11,624 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 44 [2021-11-20 06:04:11,719 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 98 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-11-20 06:04:11,719 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [458792150] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:04:11,719 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:04:11,720 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 18] total 32 [2021-11-20 06:04:11,720 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [475074881] [2021-11-20 06:04:11,720 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:04:11,720 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:04:11,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:04:11,720 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 28 times [2021-11-20 06:04:11,720 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:04:11,720 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [123254264] [2021-11-20 06:04:11,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:04:11,721 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:04:11,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:04:11,723 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:04:11,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:04:11,725 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:04:11,789 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:04:11,790 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2021-11-20 06:04:11,790 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=129, Invalid=927, Unknown=0, NotChecked=0, Total=1056 [2021-11-20 06:04:11,790 INFO L87 Difference]: Start difference. First operand 54 states and 68 transitions. cyclomatic complexity: 18 Second operand has 33 states, 32 states have (on average 2.0625) internal successors, (66), 33 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:04:12,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:04:12,242 INFO L93 Difference]: Finished difference Result 117 states and 139 transitions. [2021-11-20 06:04:12,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2021-11-20 06:04:12,243 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 139 transitions. [2021-11-20 06:04:12,244 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:04:12,245 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 116 states and 137 transitions. [2021-11-20 06:04:12,245 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2021-11-20 06:04:12,245 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2021-11-20 06:04:12,245 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116 states and 137 transitions. [2021-11-20 06:04:12,246 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:04:12,246 INFO L681 BuchiCegarLoop]: Abstraction has 116 states and 137 transitions. [2021-11-20 06:04:12,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states and 137 transitions. [2021-11-20 06:04:12,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 59. [2021-11-20 06:04:12,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 59 states have (on average 1.305084745762712) internal successors, (77), 58 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:04:12,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 77 transitions. [2021-11-20 06:04:12,248 INFO L704 BuchiCegarLoop]: Abstraction has 59 states and 77 transitions. [2021-11-20 06:04:12,248 INFO L587 BuchiCegarLoop]: Abstraction has 59 states and 77 transitions. [2021-11-20 06:04:12,248 INFO L425 BuchiCegarLoop]: ======== Iteration 34============ [2021-11-20 06:04:12,248 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59 states and 77 transitions. [2021-11-20 06:04:12,248 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:04:12,248 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:04:12,249 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:04:12,249 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:04:12,249 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 06:04:12,249 INFO L791 eck$LassoCheckResult]: Stem: 9378#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9379#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9389#L367 assume !(main_~length~0#1 < 1); 9380#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9381#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9382#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9390#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9436#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9435#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9434#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9433#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9432#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9431#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9430#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9429#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9428#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9427#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9426#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9425#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9424#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9423#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9422#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9395#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9391#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9392#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9393#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9415#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9383#L370-4 main_~j~0#1 := 0; 9384#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9387#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9388#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9394#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9405#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9404#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9403#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9402#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9401#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9400#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9399#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9398#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9397#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9385#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 9386#L378-2 [2021-11-20 06:04:12,249 INFO L793 eck$LassoCheckResult]: Loop: 9386#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9396#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9386#L378-2 [2021-11-20 06:04:12,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:04:12,250 INFO L85 PathProgramCache]: Analyzing trace with hash 553597361, now seen corresponding path program 18 times [2021-11-20 06:04:12,250 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:04:12,250 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2030178794] [2021-11-20 06:04:12,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:04:12,250 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:04:12,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:04:12,864 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:04:12,864 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:04:12,864 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2030178794] [2021-11-20 06:04:12,865 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2030178794] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:04:12,865 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1978465355] [2021-11-20 06:04:12,865 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-20 06:04:12,865 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:04:12,865 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:04:12,867 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:04:12,869 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2021-11-20 06:04:12,950 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2021-11-20 06:04:12,950 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 06:04:12,952 INFO L263 TraceCheckSpWp]: Trace formula consists of 200 conjuncts, 25 conjunts are in the unsatisfiable core [2021-11-20 06:04:12,953 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:04:13,237 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-20 06:04:14,190 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-11-20 06:04:14,190 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 23 [2021-11-20 06:04:14,223 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 36 proven. 76 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:04:14,223 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:04:16,843 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 50 treesize of output 46 [2021-11-20 06:04:16,846 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 40 [2021-11-20 06:04:16,905 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 30 proven. 82 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:04:16,905 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1978465355] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:04:16,906 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:04:16,906 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 20, 20] total 48 [2021-11-20 06:04:16,906 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2034941384] [2021-11-20 06:04:16,906 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:04:16,906 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:04:16,906 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:04:16,906 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 29 times [2021-11-20 06:04:16,906 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:04:16,906 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [154651150] [2021-11-20 06:04:16,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:04:16,907 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:04:16,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:04:16,909 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:04:16,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:04:16,911 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:04:16,987 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:04:16,988 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2021-11-20 06:04:16,988 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=283, Invalid=2068, Unknown=1, NotChecked=0, Total=2352 [2021-11-20 06:04:16,989 INFO L87 Difference]: Start difference. First operand 59 states and 77 transitions. cyclomatic complexity: 23 Second operand has 49 states, 48 states have (on average 2.0208333333333335) internal successors, (97), 49 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:04:19,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:04:19,433 INFO L93 Difference]: Finished difference Result 143 states and 175 transitions. [2021-11-20 06:04:19,434 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2021-11-20 06:04:19,434 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 143 states and 175 transitions. [2021-11-20 06:04:19,435 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-20 06:04:19,436 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 143 states to 123 states and 154 transitions. [2021-11-20 06:04:19,436 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-11-20 06:04:19,437 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-11-20 06:04:19,437 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123 states and 154 transitions. [2021-11-20 06:04:19,437 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:04:19,437 INFO L681 BuchiCegarLoop]: Abstraction has 123 states and 154 transitions. [2021-11-20 06:04:19,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states and 154 transitions. [2021-11-20 06:04:19,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 85. [2021-11-20 06:04:19,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 85 states, 85 states have (on average 1.2941176470588236) internal successors, (110), 84 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:04:19,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 110 transitions. [2021-11-20 06:04:19,440 INFO L704 BuchiCegarLoop]: Abstraction has 85 states and 110 transitions. [2021-11-20 06:04:19,440 INFO L587 BuchiCegarLoop]: Abstraction has 85 states and 110 transitions. [2021-11-20 06:04:19,440 INFO L425 BuchiCegarLoop]: ======== Iteration 35============ [2021-11-20 06:04:19,440 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 85 states and 110 transitions. [2021-11-20 06:04:19,441 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-20 06:04:19,441 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:04:19,441 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:04:19,442 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:04:19,442 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-20 06:04:19,442 INFO L791 eck$LassoCheckResult]: Stem: 9955#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9956#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9966#L367 assume !(main_~length~0#1 < 1); 9957#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9958#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9959#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9967#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10033#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10039#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9970#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9971#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9968#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9969#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10027#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10038#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10037#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10023#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10036#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10035#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10018#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10034#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10019#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10016#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10013#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10012#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9997#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10000#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9975#L370-4 main_~j~0#1 := 0; 9972#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9964#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9965#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9987#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9986#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9985#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9984#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9983#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9982#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9981#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9980#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9979#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9978#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9962#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 9963#L378-2 [2021-11-20 06:04:19,443 INFO L793 eck$LassoCheckResult]: Loop: 9963#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9977#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9963#L378-2 [2021-11-20 06:04:19,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:04:19,443 INFO L85 PathProgramCache]: Analyzing trace with hash 947964147, now seen corresponding path program 19 times [2021-11-20 06:04:19,443 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:04:19,443 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1379001233] [2021-11-20 06:04:19,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:04:19,444 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:04:19,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:04:19,976 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:04:19,976 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:04:19,976 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1379001233] [2021-11-20 06:04:19,977 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1379001233] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:04:19,977 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [253701156] [2021-11-20 06:04:19,977 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-20 06:04:19,977 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:04:19,977 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:04:19,978 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:04:19,979 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2021-11-20 06:04:20,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:04:20,049 INFO L263 TraceCheckSpWp]: Trace formula consists of 204 conjuncts, 40 conjunts are in the unsatisfiable core [2021-11-20 06:04:20,050 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:04:20,465 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2021-11-20 06:04:21,078 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2021-11-20 06:04:21,107 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:04:21,107 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-20 06:04:21,309 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-11-20 06:04:21,312 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 28 [2021-11-20 06:04:21,417 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:04:21,417 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [253701156] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-20 06:04:21,418 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-20 06:04:21,418 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 18] total 38 [2021-11-20 06:04:21,418 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1850141225] [2021-11-20 06:04:21,418 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-20 06:04:21,418 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:04:21,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:04:21,419 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 30 times [2021-11-20 06:04:21,419 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:04:21,419 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1737644738] [2021-11-20 06:04:21,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:04:21,419 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:04:21,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:04:21,421 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:04:21,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:04:21,423 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:04:21,478 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:04:21,479 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2021-11-20 06:04:21,479 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=138, Invalid=1344, Unknown=0, NotChecked=0, Total=1482 [2021-11-20 06:04:21,479 INFO L87 Difference]: Start difference. First operand 85 states and 110 transitions. cyclomatic complexity: 30 Second operand has 39 states, 38 states have (on average 2.263157894736842) internal successors, (86), 39 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:04:22,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:04:22,833 INFO L93 Difference]: Finished difference Result 149 states and 187 transitions. [2021-11-20 06:04:22,833 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2021-11-20 06:04:22,834 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 149 states and 187 transitions. [2021-11-20 06:04:22,836 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16 [2021-11-20 06:04:22,837 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 149 states to 148 states and 186 transitions. [2021-11-20 06:04:22,837 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37 [2021-11-20 06:04:22,837 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37 [2021-11-20 06:04:22,838 INFO L73 IsDeterministic]: Start isDeterministic. Operand 148 states and 186 transitions. [2021-11-20 06:04:22,838 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-11-20 06:04:22,838 INFO L681 BuchiCegarLoop]: Abstraction has 148 states and 186 transitions. [2021-11-20 06:04:22,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states and 186 transitions. [2021-11-20 06:04:22,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 116. [2021-11-20 06:04:22,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 116 states, 116 states have (on average 1.3017241379310345) internal successors, (151), 115 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:04:22,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 151 transitions. [2021-11-20 06:04:22,842 INFO L704 BuchiCegarLoop]: Abstraction has 116 states and 151 transitions. [2021-11-20 06:04:22,842 INFO L587 BuchiCegarLoop]: Abstraction has 116 states and 151 transitions. [2021-11-20 06:04:22,842 INFO L425 BuchiCegarLoop]: ======== Iteration 36============ [2021-11-20 06:04:22,842 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 116 states and 151 transitions. [2021-11-20 06:04:22,843 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2021-11-20 06:04:22,843 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:04:22,843 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:04:22,844 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 8, 6, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:04:22,844 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-11-20 06:04:22,844 INFO L791 eck$LassoCheckResult]: Stem: 10485#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10486#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10496#L367 assume !(main_~length~0#1 < 1); 10487#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10488#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10489#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10497#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10503#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10504#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10500#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10501#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10535#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10536#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10529#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10544#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10543#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10525#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10542#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10541#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10521#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10540#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10538#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10539#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10498#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10499#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10510#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10567#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10566#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10565#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10563#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10562#L370-4 main_~j~0#1 := 0; 10561#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10560#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10559#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10558#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10557#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10556#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10555#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10554#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10553#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10552#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10546#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10547#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 10590#L378-2 [2021-11-20 06:04:22,844 INFO L793 eck$LassoCheckResult]: Loop: 10590#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10592#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 10593#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10594#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10590#L378-2 [2021-11-20 06:04:22,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:04:22,848 INFO L85 PathProgramCache]: Analyzing trace with hash 398214442, now seen corresponding path program 20 times [2021-11-20 06:04:22,848 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:04:22,848 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1998576495] [2021-11-20 06:04:22,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:04:22,848 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:04:22,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:04:23,322 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:04:23,322 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:04:23,322 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1998576495] [2021-11-20 06:04:23,323 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1998576495] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-20 06:04:23,323 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1802444138] [2021-11-20 06:04:23,323 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-20 06:04:23,323 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-20 06:04:23,323 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:04:23,325 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-20 06:04:23,326 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a6be4a5-02d6-42a2-974d-36678ad07d5d/bin/uautomizer-DQz5hQGWxF/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2021-11-20 06:04:23,380 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-20 06:04:23,380 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-20 06:04:23,382 INFO L263 TraceCheckSpWp]: Trace formula consists of 204 conjuncts, 53 conjunts are in the unsatisfiable core [2021-11-20 06:04:23,383 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-20 06:04:23,395 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 9 [2021-11-20 06:04:23,476 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-20 06:04:23,575 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-20 06:04:23,576 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2021-11-20 06:04:23,649 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-20 06:04:23,650 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2021-11-20 06:04:23,730 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-20 06:04:23,730 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2021-11-20 06:04:23,811 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-20 06:04:23,812 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2021-11-20 06:04:23,891 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-20 06:04:23,891 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2021-11-20 06:04:23,905 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-20 06:04:23,906 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2021-11-20 06:04:24,033 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-20 06:04:24,034 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-20 06:04:24,035 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-20 06:04:24,036 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 34 [2021-11-20 06:04:24,138 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-11-20 06:04:24,156 INFO L354 Elim1Store]: treesize reduction 54, result has 23.9 percent of original size [2021-11-20 06:04:24,156 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 35 treesize of output 37 [2021-11-20 06:04:24,769 INFO L354 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2021-11-20 06:04:24,770 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 15 [2021-11-20 06:04:24,774 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:04:24,775 INFO L328 TraceCheckSpWp]: Computing backward predicates...