./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.02.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 53f42b1a Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/bin/uautomizer-DQz5hQGWxF/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/bin/uautomizer-DQz5hQGWxF/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/bin/uautomizer-DQz5hQGWxF/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/bin/uautomizer-DQz5hQGWxF/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.02.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/bin/uautomizer-DQz5hQGWxF/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/bin/uautomizer-DQz5hQGWxF --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bc8487f898950b83c481f83a71342af68752fb6e7598d76df123761c32c89f72 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-53f42b1 [2021-11-20 06:41:51,852 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-20 06:41:51,854 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-20 06:41:51,883 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-20 06:41:51,884 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-20 06:41:51,885 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-20 06:41:51,887 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-20 06:41:51,890 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-20 06:41:51,892 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-20 06:41:51,893 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-20 06:41:51,895 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-20 06:41:51,896 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-20 06:41:51,897 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-20 06:41:51,898 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-20 06:41:51,900 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-20 06:41:51,901 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-20 06:41:51,903 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-20 06:41:51,904 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-20 06:41:51,906 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-20 06:41:51,908 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-20 06:41:51,910 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-20 06:41:51,912 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-20 06:41:51,914 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-20 06:41:51,915 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-20 06:41:51,918 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-20 06:41:51,919 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-20 06:41:51,919 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-20 06:41:51,921 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-20 06:41:51,921 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-20 06:41:51,922 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-20 06:41:51,923 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-20 06:41:51,924 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-20 06:41:51,925 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-20 06:41:51,926 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-20 06:41:51,927 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-20 06:41:51,928 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-20 06:41:51,929 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-20 06:41:51,929 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-20 06:41:51,930 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-20 06:41:51,931 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-20 06:41:51,932 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-20 06:41:51,934 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/bin/uautomizer-DQz5hQGWxF/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-20 06:41:51,972 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-20 06:41:51,972 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-20 06:41:51,973 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-20 06:41:51,973 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-20 06:41:51,974 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-20 06:41:51,975 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-20 06:41:51,975 INFO L138 SettingsManager]: * Use SBE=true [2021-11-20 06:41:51,976 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-20 06:41:51,976 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-20 06:41:51,976 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-20 06:41:51,977 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-20 06:41:51,978 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-20 06:41:51,978 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-20 06:41:51,978 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-20 06:41:51,979 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-20 06:41:51,979 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-20 06:41:51,979 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-20 06:41:51,980 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-20 06:41:51,980 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-20 06:41:51,980 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-20 06:41:51,980 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-20 06:41:51,981 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-20 06:41:51,981 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-20 06:41:51,981 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-20 06:41:51,982 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-20 06:41:51,982 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-20 06:41:51,982 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-20 06:41:51,982 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-20 06:41:51,983 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-20 06:41:51,983 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-20 06:41:51,983 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-20 06:41:51,984 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-20 06:41:51,985 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-20 06:41:51,985 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/bin/uautomizer-DQz5hQGWxF/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/bin/uautomizer-DQz5hQGWxF Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bc8487f898950b83c481f83a71342af68752fb6e7598d76df123761c32c89f72 [2021-11-20 06:41:52,275 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-20 06:41:52,297 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-20 06:41:52,299 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-20 06:41:52,301 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-20 06:41:52,302 INFO L275 PluginConnector]: CDTParser initialized [2021-11-20 06:41:52,303 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/bin/uautomizer-DQz5hQGWxF/../../sv-benchmarks/c/systemc/token_ring.02.cil-2.c [2021-11-20 06:41:52,369 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/bin/uautomizer-DQz5hQGWxF/data/a17d5dfbe/1569833e9c644be1a90f307f7f31a6f5/FLAGbd8a09264 [2021-11-20 06:41:52,852 INFO L306 CDTParser]: Found 1 translation units. [2021-11-20 06:41:52,853 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/sv-benchmarks/c/systemc/token_ring.02.cil-2.c [2021-11-20 06:41:52,863 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/bin/uautomizer-DQz5hQGWxF/data/a17d5dfbe/1569833e9c644be1a90f307f7f31a6f5/FLAGbd8a09264 [2021-11-20 06:41:53,223 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/bin/uautomizer-DQz5hQGWxF/data/a17d5dfbe/1569833e9c644be1a90f307f7f31a6f5 [2021-11-20 06:41:53,226 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-20 06:41:53,228 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-20 06:41:53,240 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-20 06:41:53,240 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-20 06:41:53,248 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-20 06:41:53,249 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 06:41:53" (1/1) ... [2021-11-20 06:41:53,250 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7066390c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:41:53, skipping insertion in model container [2021-11-20 06:41:53,250 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 06:41:53" (1/1) ... [2021-11-20 06:41:53,257 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-20 06:41:53,295 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-20 06:41:53,426 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/sv-benchmarks/c/systemc/token_ring.02.cil-2.c[671,684] [2021-11-20 06:41:53,482 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-20 06:41:53,493 INFO L203 MainTranslator]: Completed pre-run [2021-11-20 06:41:53,505 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/sv-benchmarks/c/systemc/token_ring.02.cil-2.c[671,684] [2021-11-20 06:41:53,546 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-20 06:41:53,563 INFO L208 MainTranslator]: Completed translation [2021-11-20 06:41:53,564 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:41:53 WrapperNode [2021-11-20 06:41:53,564 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-20 06:41:53,565 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-20 06:41:53,565 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-20 06:41:53,566 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-20 06:41:53,573 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:41:53" (1/1) ... [2021-11-20 06:41:53,582 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:41:53" (1/1) ... [2021-11-20 06:41:53,631 INFO L137 Inliner]: procedures = 32, calls = 38, calls flagged for inlining = 33, calls inlined = 50, statements flattened = 606 [2021-11-20 06:41:53,631 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-20 06:41:53,632 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-20 06:41:53,632 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-20 06:41:53,633 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-20 06:41:53,650 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:41:53" (1/1) ... [2021-11-20 06:41:53,651 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:41:53" (1/1) ... [2021-11-20 06:41:53,655 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:41:53" (1/1) ... [2021-11-20 06:41:53,655 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:41:53" (1/1) ... [2021-11-20 06:41:53,677 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:41:53" (1/1) ... [2021-11-20 06:41:53,711 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:41:53" (1/1) ... [2021-11-20 06:41:53,714 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:41:53" (1/1) ... [2021-11-20 06:41:53,719 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-20 06:41:53,724 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-20 06:41:53,724 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-20 06:41:53,730 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-20 06:41:53,731 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:41:53" (1/1) ... [2021-11-20 06:41:53,753 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 06:41:53,767 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 06:41:53,789 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 06:41:53,820 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-20 06:41:53,890 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-11-20 06:41:53,891 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-20 06:41:53,891 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-20 06:41:53,891 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-20 06:41:53,997 INFO L236 CfgBuilder]: Building ICFG [2021-11-20 06:41:53,998 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-11-20 06:41:54,603 INFO L277 CfgBuilder]: Performing block encoding [2021-11-20 06:41:54,615 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-20 06:41:54,615 INFO L301 CfgBuilder]: Removed 5 assume(true) statements. [2021-11-20 06:41:54,618 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 06:41:54 BoogieIcfgContainer [2021-11-20 06:41:54,618 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-20 06:41:54,619 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-20 06:41:54,619 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-20 06:41:54,622 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-20 06:41:54,623 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 06:41:54,623 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 20.11 06:41:53" (1/3) ... [2021-11-20 06:41:54,625 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2db85ba4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 06:41:54, skipping insertion in model container [2021-11-20 06:41:54,625 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 06:41:54,625 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:41:53" (2/3) ... [2021-11-20 06:41:54,625 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2db85ba4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 06:41:54, skipping insertion in model container [2021-11-20 06:41:54,625 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 06:41:54,626 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 06:41:54" (3/3) ... [2021-11-20 06:41:54,627 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.02.cil-2.c [2021-11-20 06:41:54,671 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-20 06:41:54,672 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-20 06:41:54,672 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-20 06:41:54,672 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-20 06:41:54,672 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-20 06:41:54,672 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-20 06:41:54,672 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-20 06:41:54,673 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-20 06:41:54,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 238 states, 237 states have (on average 1.540084388185654) internal successors, (365), 237 states have internal predecessors, (365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:54,736 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 191 [2021-11-20 06:41:54,736 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:41:54,736 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:41:54,746 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:54,747 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:54,747 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-20 06:41:54,748 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 238 states, 237 states have (on average 1.540084388185654) internal successors, (365), 237 states have internal predecessors, (365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:54,759 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 191 [2021-11-20 06:41:54,759 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:41:54,760 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:41:54,765 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:54,765 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:54,772 INFO L791 eck$LassoCheckResult]: Stem: 227#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 151#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 153#L528true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 162#L236true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 180#L243true assume !(1 == ~m_i~0);~m_st~0 := 2; 110#L243-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 177#L248-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 16#L253-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 192#L356true assume !(0 == ~M_E~0); 68#L356-2true assume !(0 == ~T1_E~0); 134#L361-1true assume !(0 == ~T2_E~0); 132#L366-1true assume 0 == ~E_M~0;~E_M~0 := 1; 126#L371-1true assume !(0 == ~E_1~0); 49#L376-1true assume !(0 == ~E_2~0); 84#L381-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19#L178true assume 1 == ~m_pc~0; 232#L179true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 70#L189true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163#L190true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 118#L437true assume !(0 != activate_threads_~tmp~1#1); 29#L437-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57#L197true assume !(1 == ~t1_pc~0); 209#L197-2true is_transmit1_triggered_~__retres1~1#1 := 0; 211#L208true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 217#L209true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26#L445true assume !(0 != activate_threads_~tmp___0~0#1); 189#L445-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 210#L216true assume 1 == ~t2_pc~0; 15#L217true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 79#L227true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69#L228true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 154#L453true assume !(0 != activate_threads_~tmp___1~0#1); 125#L453-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 129#L394true assume !(1 == ~M_E~0); 205#L394-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 101#L399-1true assume !(1 == ~T2_E~0); 221#L404-1true assume !(1 == ~E_M~0); 38#L409-1true assume !(1 == ~E_1~0); 160#L414-1true assume !(1 == ~E_2~0); 103#L419-1true assume { :end_inline_reset_delta_events } true; 164#L565-2true [2021-11-20 06:41:54,774 INFO L793 eck$LassoCheckResult]: Loop: 164#L565-2true assume !false; 92#L566true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 124#L331true assume !true; 33#L346true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 108#L236-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 185#L356-3true assume !(0 == ~M_E~0); 148#L356-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 120#L361-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 172#L366-3true assume 0 == ~E_M~0;~E_M~0 := 1; 146#L371-3true assume 0 == ~E_1~0;~E_1~0 := 1; 85#L376-3true assume 0 == ~E_2~0;~E_2~0 := 1; 119#L381-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83#L178-12true assume !(1 == ~m_pc~0); 4#L178-14true is_master_triggered_~__retres1~0#1 := 0; 102#L189-4true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 144#L190-4true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 190#L437-12true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 91#L437-14true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 141#L197-12true assume !(1 == ~t1_pc~0); 179#L197-14true is_transmit1_triggered_~__retres1~1#1 := 0; 42#L208-4true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 216#L209-4true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3#L445-12true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50#L445-14true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40#L216-12true assume !(1 == ~t2_pc~0); 107#L216-14true is_transmit2_triggered_~__retres1~2#1 := 0; 64#L227-4true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22#L228-4true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 35#L453-12true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 184#L453-14true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 239#L394-3true assume 1 == ~M_E~0;~M_E~0 := 2; 213#L394-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 13#L399-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 233#L404-3true assume 1 == ~E_M~0;~E_M~0 := 2; 60#L409-3true assume 1 == ~E_1~0;~E_1~0 := 2; 183#L414-3true assume 1 == ~E_2~0;~E_2~0 := 2; 166#L419-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 139#L266-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 55#L283-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 37#L284-1true start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 159#L584true assume !(0 == start_simulation_~tmp~3#1); 105#L584-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 112#L266-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 130#L283-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 138#L284-2true stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 41#L539true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25#L546true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 149#L547true start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 95#L597true assume !(0 != start_simulation_~tmp___0~1#1); 164#L565-2true [2021-11-20 06:41:54,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:54,780 INFO L85 PathProgramCache]: Analyzing trace with hash 332551043, now seen corresponding path program 1 times [2021-11-20 06:41:54,790 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:54,791 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881124941] [2021-11-20 06:41:54,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:54,792 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:54,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:54,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:54,951 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:54,951 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [881124941] [2021-11-20 06:41:54,952 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [881124941] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:54,952 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:54,953 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 06:41:54,954 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [782287891] [2021-11-20 06:41:54,955 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:54,960 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:41:54,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:54,961 INFO L85 PathProgramCache]: Analyzing trace with hash -2092676298, now seen corresponding path program 1 times [2021-11-20 06:41:54,962 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:54,962 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [870510700] [2021-11-20 06:41:54,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:54,962 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:54,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:54,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:54,985 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:54,985 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [870510700] [2021-11-20 06:41:54,985 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [870510700] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:54,986 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:54,986 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-20 06:41:54,986 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1652452181] [2021-11-20 06:41:54,986 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:54,988 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 06:41:54,989 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:41:55,021 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 06:41:55,022 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 06:41:55,025 INFO L87 Difference]: Start difference. First operand has 238 states, 237 states have (on average 1.540084388185654) internal successors, (365), 237 states have internal predecessors, (365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:55,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:41:55,066 INFO L93 Difference]: Finished difference Result 236 states and 350 transitions. [2021-11-20 06:41:55,068 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 06:41:55,073 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 236 states and 350 transitions. [2021-11-20 06:41:55,079 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 187 [2021-11-20 06:41:55,086 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 236 states to 230 states and 344 transitions. [2021-11-20 06:41:55,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 230 [2021-11-20 06:41:55,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 230 [2021-11-20 06:41:55,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 230 states and 344 transitions. [2021-11-20 06:41:55,091 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 06:41:55,091 INFO L681 BuchiCegarLoop]: Abstraction has 230 states and 344 transitions. [2021-11-20 06:41:55,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 230 states and 344 transitions. [2021-11-20 06:41:55,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 230 to 230. [2021-11-20 06:41:55,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 230 states, 230 states have (on average 1.4956521739130435) internal successors, (344), 229 states have internal predecessors, (344), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:55,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 344 transitions. [2021-11-20 06:41:55,135 INFO L704 BuchiCegarLoop]: Abstraction has 230 states and 344 transitions. [2021-11-20 06:41:55,136 INFO L587 BuchiCegarLoop]: Abstraction has 230 states and 344 transitions. [2021-11-20 06:41:55,136 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-20 06:41:55,136 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 230 states and 344 transitions. [2021-11-20 06:41:55,138 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 187 [2021-11-20 06:41:55,139 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:41:55,139 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:41:55,141 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:55,141 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:55,142 INFO L791 eck$LassoCheckResult]: Stem: 712#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 687#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 688#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 690#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 696#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 647#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 648#L248-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 513#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 514#L356 assume !(0 == ~M_E~0); 605#L356-2 assume !(0 == ~T1_E~0); 606#L361-1 assume !(0 == ~T2_E~0); 671#L366-1 assume 0 == ~E_M~0;~E_M~0 := 1; 665#L371-1 assume !(0 == ~E_1~0); 580#L376-1 assume !(0 == ~E_2~0); 581#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 517#L178 assume 1 == ~m_pc~0; 518#L179 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 609#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 610#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 657#L437 assume !(0 != activate_threads_~tmp~1#1); 542#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 543#L197 assume !(1 == ~t1_pc~0); 589#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 588#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 710#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 535#L445 assume !(0 != activate_threads_~tmp___0~0#1); 536#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 706#L216 assume 1 == ~t2_pc~0; 510#L217 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 511#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 607#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 608#L453 assume !(0 != activate_threads_~tmp___1~0#1); 663#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 664#L394 assume !(1 == ~M_E~0); 669#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 637#L399-1 assume !(1 == ~T2_E~0); 638#L404-1 assume !(1 == ~E_M~0); 560#L409-1 assume !(1 == ~E_1~0); 561#L414-1 assume !(1 == ~E_2~0); 640#L419-1 assume { :end_inline_reset_delta_events } true; 633#L565-2 [2021-11-20 06:41:55,142 INFO L793 eck$LassoCheckResult]: Loop: 633#L565-2 assume !false; 629#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 521#L331 assume !false; 631#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 492#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 488#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 578#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 579#L298 assume !(0 != eval_~tmp~0#1); 550#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 551#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 644#L356-3 assume !(0 == ~M_E~0); 686#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 658#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 659#L366-3 assume 0 == ~E_M~0;~E_M~0 := 1; 683#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 621#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 622#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 620#L178-12 assume !(1 == ~m_pc~0); 485#L178-14 is_master_triggered_~__retres1~0#1 := 0; 486#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 639#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 682#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 627#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 628#L197-12 assume !(1 == ~t1_pc~0); 676#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 566#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 567#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 483#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 484#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 562#L216-12 assume 1 == ~t2_pc~0; 563#L217-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 600#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 526#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 527#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 555#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 705#L394-3 assume 1 == ~M_E~0;~M_E~0 := 2; 711#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 506#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 507#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 594#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 595#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 699#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 675#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 496#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 558#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 559#L584 assume !(0 == start_simulation_~tmp~3#1); 583#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 642#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 650#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 670#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 565#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 533#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 534#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 632#L597 assume !(0 != start_simulation_~tmp___0~1#1); 633#L565-2 [2021-11-20 06:41:55,143 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:55,143 INFO L85 PathProgramCache]: Analyzing trace with hash 726917829, now seen corresponding path program 1 times [2021-11-20 06:41:55,143 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:55,143 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [968608784] [2021-11-20 06:41:55,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:55,144 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:55,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:55,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:55,243 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:55,243 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [968608784] [2021-11-20 06:41:55,244 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [968608784] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:55,244 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:55,244 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 06:41:55,244 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1720377735] [2021-11-20 06:41:55,245 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:55,245 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:41:55,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:55,246 INFO L85 PathProgramCache]: Analyzing trace with hash 175779481, now seen corresponding path program 1 times [2021-11-20 06:41:55,246 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:55,246 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881296127] [2021-11-20 06:41:55,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:55,247 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:55,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:55,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:55,323 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:55,323 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [881296127] [2021-11-20 06:41:55,323 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [881296127] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:55,323 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:55,324 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-20 06:41:55,324 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1612529066] [2021-11-20 06:41:55,324 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:55,325 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 06:41:55,325 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:41:55,325 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 06:41:55,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 06:41:55,326 INFO L87 Difference]: Start difference. First operand 230 states and 344 transitions. cyclomatic complexity: 115 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:55,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:41:55,346 INFO L93 Difference]: Finished difference Result 230 states and 343 transitions. [2021-11-20 06:41:55,347 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 06:41:55,348 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 230 states and 343 transitions. [2021-11-20 06:41:55,350 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 187 [2021-11-20 06:41:55,353 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 230 states to 230 states and 343 transitions. [2021-11-20 06:41:55,354 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 230 [2021-11-20 06:41:55,354 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 230 [2021-11-20 06:41:55,354 INFO L73 IsDeterministic]: Start isDeterministic. Operand 230 states and 343 transitions. [2021-11-20 06:41:55,356 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 06:41:55,356 INFO L681 BuchiCegarLoop]: Abstraction has 230 states and 343 transitions. [2021-11-20 06:41:55,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 230 states and 343 transitions. [2021-11-20 06:41:55,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 230 to 230. [2021-11-20 06:41:55,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 230 states, 230 states have (on average 1.491304347826087) internal successors, (343), 229 states have internal predecessors, (343), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:55,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 343 transitions. [2021-11-20 06:41:55,368 INFO L704 BuchiCegarLoop]: Abstraction has 230 states and 343 transitions. [2021-11-20 06:41:55,369 INFO L587 BuchiCegarLoop]: Abstraction has 230 states and 343 transitions. [2021-11-20 06:41:55,369 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-20 06:41:55,369 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 230 states and 343 transitions. [2021-11-20 06:41:55,371 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 187 [2021-11-20 06:41:55,371 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:41:55,371 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:41:55,373 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:55,373 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:55,373 INFO L791 eck$LassoCheckResult]: Stem: 1181#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1156#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1157#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1159#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1165#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 1116#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1117#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 982#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 983#L356 assume !(0 == ~M_E~0); 1074#L356-2 assume !(0 == ~T1_E~0); 1075#L361-1 assume !(0 == ~T2_E~0); 1140#L366-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1134#L371-1 assume !(0 == ~E_1~0); 1049#L376-1 assume !(0 == ~E_2~0); 1050#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 986#L178 assume 1 == ~m_pc~0; 987#L179 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1078#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1079#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1126#L437 assume !(0 != activate_threads_~tmp~1#1); 1011#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1012#L197 assume !(1 == ~t1_pc~0); 1058#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1057#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1179#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1004#L445 assume !(0 != activate_threads_~tmp___0~0#1); 1005#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1175#L216 assume 1 == ~t2_pc~0; 979#L217 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 980#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1076#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1077#L453 assume !(0 != activate_threads_~tmp___1~0#1); 1132#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1133#L394 assume !(1 == ~M_E~0); 1138#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1106#L399-1 assume !(1 == ~T2_E~0); 1107#L404-1 assume !(1 == ~E_M~0); 1029#L409-1 assume !(1 == ~E_1~0); 1030#L414-1 assume !(1 == ~E_2~0); 1109#L419-1 assume { :end_inline_reset_delta_events } true; 1102#L565-2 [2021-11-20 06:41:55,374 INFO L793 eck$LassoCheckResult]: Loop: 1102#L565-2 assume !false; 1098#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 990#L331 assume !false; 1100#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 961#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 957#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1047#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1048#L298 assume !(0 != eval_~tmp~0#1); 1019#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1020#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1113#L356-3 assume !(0 == ~M_E~0); 1155#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1127#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1128#L366-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1152#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1090#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1091#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1089#L178-12 assume 1 == ~m_pc~0; 1059#L179-4 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 955#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1108#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1151#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1096#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1097#L197-12 assume !(1 == ~t1_pc~0); 1145#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 1035#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1036#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 952#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 953#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1031#L216-12 assume 1 == ~t2_pc~0; 1032#L217-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1069#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 995#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 996#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1024#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1174#L394-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1180#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 975#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 976#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1063#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1064#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1168#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1144#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 965#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1027#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1028#L584 assume !(0 == start_simulation_~tmp~3#1); 1052#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1111#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1119#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1139#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1034#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1002#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1003#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1101#L597 assume !(0 != start_simulation_~tmp___0~1#1); 1102#L565-2 [2021-11-20 06:41:55,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:55,374 INFO L85 PathProgramCache]: Analyzing trace with hash -1324066169, now seen corresponding path program 1 times [2021-11-20 06:41:55,375 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:55,375 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1401328044] [2021-11-20 06:41:55,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:55,375 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:55,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:55,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:55,422 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:55,422 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1401328044] [2021-11-20 06:41:55,423 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1401328044] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:55,423 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:55,423 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 06:41:55,423 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [352334414] [2021-11-20 06:41:55,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:55,424 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:41:55,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:55,425 INFO L85 PathProgramCache]: Analyzing trace with hash -949480488, now seen corresponding path program 1 times [2021-11-20 06:41:55,425 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:55,425 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [340904130] [2021-11-20 06:41:55,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:55,426 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:55,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:55,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:55,474 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:55,474 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [340904130] [2021-11-20 06:41:55,474 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [340904130] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:55,474 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:55,474 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-20 06:41:55,475 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [89300820] [2021-11-20 06:41:55,475 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:55,475 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 06:41:55,475 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:41:55,476 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 06:41:55,476 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 06:41:55,476 INFO L87 Difference]: Start difference. First operand 230 states and 343 transitions. cyclomatic complexity: 114 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:55,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:41:55,573 INFO L93 Difference]: Finished difference Result 372 states and 552 transitions. [2021-11-20 06:41:55,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 06:41:55,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 372 states and 552 transitions. [2021-11-20 06:41:55,579 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 322 [2021-11-20 06:41:55,583 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 372 states to 372 states and 552 transitions. [2021-11-20 06:41:55,583 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 372 [2021-11-20 06:41:55,584 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 372 [2021-11-20 06:41:55,584 INFO L73 IsDeterministic]: Start isDeterministic. Operand 372 states and 552 transitions. [2021-11-20 06:41:55,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 06:41:55,587 INFO L681 BuchiCegarLoop]: Abstraction has 372 states and 552 transitions. [2021-11-20 06:41:55,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 372 states and 552 transitions. [2021-11-20 06:41:55,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 372 to 371. [2021-11-20 06:41:55,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 371 states, 371 states have (on average 1.4851752021563343) internal successors, (551), 370 states have internal predecessors, (551), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:55,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 371 states to 371 states and 551 transitions. [2021-11-20 06:41:55,605 INFO L704 BuchiCegarLoop]: Abstraction has 371 states and 551 transitions. [2021-11-20 06:41:55,605 INFO L587 BuchiCegarLoop]: Abstraction has 371 states and 551 transitions. [2021-11-20 06:41:55,605 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-20 06:41:55,606 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 371 states and 551 transitions. [2021-11-20 06:41:55,609 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 322 [2021-11-20 06:41:55,609 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:41:55,609 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:41:55,611 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:55,611 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:55,611 INFO L791 eck$LassoCheckResult]: Stem: 1800#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1773#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1774#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1776#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1782#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 1730#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1731#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1596#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1597#L356 assume !(0 == ~M_E~0); 1688#L356-2 assume !(0 == ~T1_E~0); 1689#L361-1 assume !(0 == ~T2_E~0); 1756#L366-1 assume !(0 == ~E_M~0); 1749#L371-1 assume !(0 == ~E_1~0); 1663#L376-1 assume !(0 == ~E_2~0); 1664#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1600#L178 assume 1 == ~m_pc~0; 1601#L179 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1692#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1693#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1741#L437 assume !(0 != activate_threads_~tmp~1#1); 1625#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1626#L197 assume !(1 == ~t1_pc~0); 1672#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1671#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1798#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1618#L445 assume !(0 != activate_threads_~tmp___0~0#1); 1619#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1794#L216 assume 1 == ~t2_pc~0; 1593#L217 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1594#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1690#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1691#L453 assume !(0 != activate_threads_~tmp___1~0#1); 1747#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1748#L394 assume 1 == ~M_E~0;~M_E~0 := 2; 1753#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1720#L399-1 assume !(1 == ~T2_E~0); 1721#L404-1 assume !(1 == ~E_M~0); 1643#L409-1 assume !(1 == ~E_1~0); 1644#L414-1 assume !(1 == ~E_2~0); 1723#L419-1 assume { :end_inline_reset_delta_events } true; 1716#L565-2 [2021-11-20 06:41:55,611 INFO L793 eck$LassoCheckResult]: Loop: 1716#L565-2 assume !false; 1712#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1604#L331 assume !false; 1714#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1575#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1571#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1661#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1662#L298 assume !(0 != eval_~tmp~0#1); 1633#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1634#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1727#L356-3 assume !(0 == ~M_E~0); 1772#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1742#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1743#L366-3 assume !(0 == ~E_M~0); 1769#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1704#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1705#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1703#L178-12 assume !(1 == ~m_pc~0); 1568#L178-14 is_master_triggered_~__retres1~0#1 := 0; 1569#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1722#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1768#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1710#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1711#L197-12 assume !(1 == ~t1_pc~0); 1762#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 1649#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1650#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1566#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1567#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1646#L216-12 assume !(1 == ~t2_pc~0); 1648#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 1683#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1609#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1610#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1638#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1791#L394-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1799#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1589#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1590#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1677#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1678#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1785#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1760#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1579#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1641#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1642#L584 assume !(0 == start_simulation_~tmp~3#1); 1666#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1725#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1733#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1755#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1645#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1613#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1614#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1715#L597 assume !(0 != start_simulation_~tmp___0~1#1); 1716#L565-2 [2021-11-20 06:41:55,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:55,612 INFO L85 PathProgramCache]: Analyzing trace with hash -1712870137, now seen corresponding path program 1 times [2021-11-20 06:41:55,612 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:55,612 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1242494191] [2021-11-20 06:41:55,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:55,613 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:55,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:55,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:55,646 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:55,647 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1242494191] [2021-11-20 06:41:55,647 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1242494191] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:55,647 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:55,647 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-20 06:41:55,647 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1033633556] [2021-11-20 06:41:55,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:55,648 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:41:55,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:55,649 INFO L85 PathProgramCache]: Analyzing trace with hash -1458177828, now seen corresponding path program 1 times [2021-11-20 06:41:55,649 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:55,649 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [382806992] [2021-11-20 06:41:55,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:55,650 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:55,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:55,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:55,718 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:55,719 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [382806992] [2021-11-20 06:41:55,719 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [382806992] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:55,719 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:55,719 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-20 06:41:55,720 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1518927509] [2021-11-20 06:41:55,720 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:55,720 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 06:41:55,721 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:41:55,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 06:41:55,724 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 06:41:55,724 INFO L87 Difference]: Start difference. First operand 371 states and 551 transitions. cyclomatic complexity: 182 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:55,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:41:55,777 INFO L93 Difference]: Finished difference Result 668 states and 973 transitions. [2021-11-20 06:41:55,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 06:41:55,778 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 668 states and 973 transitions. [2021-11-20 06:41:55,787 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 618 [2021-11-20 06:41:55,794 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 668 states to 668 states and 973 transitions. [2021-11-20 06:41:55,794 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 668 [2021-11-20 06:41:55,795 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 668 [2021-11-20 06:41:55,796 INFO L73 IsDeterministic]: Start isDeterministic. Operand 668 states and 973 transitions. [2021-11-20 06:41:55,797 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 06:41:55,797 INFO L681 BuchiCegarLoop]: Abstraction has 668 states and 973 transitions. [2021-11-20 06:41:55,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 668 states and 973 transitions. [2021-11-20 06:41:55,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 668 to 628. [2021-11-20 06:41:55,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 628 states, 628 states have (on average 1.463375796178344) internal successors, (919), 627 states have internal predecessors, (919), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:55,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 628 states to 628 states and 919 transitions. [2021-11-20 06:41:55,849 INFO L704 BuchiCegarLoop]: Abstraction has 628 states and 919 transitions. [2021-11-20 06:41:55,850 INFO L587 BuchiCegarLoop]: Abstraction has 628 states and 919 transitions. [2021-11-20 06:41:55,850 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-20 06:41:55,850 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 628 states and 919 transitions. [2021-11-20 06:41:55,855 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 578 [2021-11-20 06:41:55,856 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:41:55,856 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:41:55,860 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:55,861 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:55,862 INFO L791 eck$LassoCheckResult]: Stem: 2901#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2845#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2846#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2848#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2856#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 2795#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2796#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2644#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2645#L356 assume !(0 == ~M_E~0); 2738#L356-2 assume !(0 == ~T1_E~0); 2739#L361-1 assume !(0 == ~T2_E~0); 2821#L366-1 assume !(0 == ~E_M~0); 2813#L371-1 assume !(0 == ~E_1~0); 2710#L376-1 assume !(0 == ~E_2~0); 2711#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2648#L178 assume !(1 == ~m_pc~0); 2649#L178-2 is_master_triggered_~__retres1~0#1 := 0; 2743#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2744#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2802#L437 assume !(0 != activate_threads_~tmp~1#1); 2670#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2671#L197 assume !(1 == ~t1_pc~0); 2719#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2718#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2894#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2666#L445 assume !(0 != activate_threads_~tmp___0~0#1); 2667#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2874#L216 assume 1 == ~t2_pc~0; 2641#L217 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2642#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2740#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2741#L453 assume !(0 != activate_threads_~tmp___1~0#1); 2811#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2812#L394 assume 1 == ~M_E~0;~M_E~0 := 2; 2817#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3169#L399-1 assume !(1 == ~T2_E~0); 3168#L404-1 assume !(1 == ~E_M~0); 2897#L409-1 assume !(1 == ~E_1~0); 3167#L414-1 assume !(1 == ~E_2~0); 3166#L419-1 assume { :end_inline_reset_delta_events } true; 2974#L565-2 [2021-11-20 06:41:55,863 INFO L793 eck$LassoCheckResult]: Loop: 2974#L565-2 assume !false; 2975#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2953#L331 assume !false; 2954#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2946#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2945#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2708#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2709#L298 assume !(0 != eval_~tmp~0#1); 2678#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2679#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2791#L356-3 assume !(0 == ~M_E~0); 3150#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3211#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3210#L366-3 assume !(0 == ~E_M~0); 3209#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3208#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3207#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3206#L178-12 assume !(1 == ~m_pc~0); 3205#L178-14 is_master_triggered_~__retres1~0#1 := 0; 3204#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3203#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3202#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3201#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3200#L197-12 assume 1 == ~t1_pc~0; 2843#L198-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2695#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2696#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2614#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2615#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2691#L216-12 assume 1 == ~t2_pc~0; 2692#L217-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3194#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3191#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3190#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3189#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3188#L394-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2909#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3187#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3186#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2904#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3185#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3184#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3181#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3180#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3179#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3178#L584 assume !(0 == start_simulation_~tmp~3#1); 2713#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3176#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3174#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3173#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 3172#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3171#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3170#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 3165#L597 assume !(0 != start_simulation_~tmp___0~1#1); 2974#L565-2 [2021-11-20 06:41:55,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:55,864 INFO L85 PathProgramCache]: Analyzing trace with hash 524493128, now seen corresponding path program 1 times [2021-11-20 06:41:55,865 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:55,865 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319696046] [2021-11-20 06:41:55,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:55,865 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:55,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:55,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:55,946 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:55,947 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [319696046] [2021-11-20 06:41:55,947 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [319696046] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:55,953 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:55,953 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 06:41:55,953 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2007160777] [2021-11-20 06:41:55,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:55,954 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:41:55,954 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:55,955 INFO L85 PathProgramCache]: Analyzing trace with hash -1924070118, now seen corresponding path program 1 times [2021-11-20 06:41:55,955 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:55,955 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1550228779] [2021-11-20 06:41:55,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:55,956 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:55,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:56,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:56,012 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:56,012 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1550228779] [2021-11-20 06:41:56,012 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1550228779] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:56,012 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:56,013 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-20 06:41:56,013 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1455105557] [2021-11-20 06:41:56,013 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:56,013 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 06:41:56,014 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:41:56,014 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 06:41:56,015 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 06:41:56,015 INFO L87 Difference]: Start difference. First operand 628 states and 919 transitions. cyclomatic complexity: 295 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:56,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:41:56,116 INFO L93 Difference]: Finished difference Result 1421 states and 2040 transitions. [2021-11-20 06:41:56,117 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 06:41:56,119 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1421 states and 2040 transitions. [2021-11-20 06:41:56,136 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1316 [2021-11-20 06:41:56,151 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1421 states to 1421 states and 2040 transitions. [2021-11-20 06:41:56,151 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1421 [2021-11-20 06:41:56,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1421 [2021-11-20 06:41:56,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1421 states and 2040 transitions. [2021-11-20 06:41:56,156 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 06:41:56,156 INFO L681 BuchiCegarLoop]: Abstraction has 1421 states and 2040 transitions. [2021-11-20 06:41:56,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1421 states and 2040 transitions. [2021-11-20 06:41:56,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1421 to 1138. [2021-11-20 06:41:56,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1138 states, 1138 states have (on average 1.4507908611599296) internal successors, (1651), 1137 states have internal predecessors, (1651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:56,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1138 states to 1138 states and 1651 transitions. [2021-11-20 06:41:56,190 INFO L704 BuchiCegarLoop]: Abstraction has 1138 states and 1651 transitions. [2021-11-20 06:41:56,190 INFO L587 BuchiCegarLoop]: Abstraction has 1138 states and 1651 transitions. [2021-11-20 06:41:56,190 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-20 06:41:56,191 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1138 states and 1651 transitions. [2021-11-20 06:41:56,199 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1087 [2021-11-20 06:41:56,199 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:41:56,199 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:41:56,203 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:56,203 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:56,204 INFO L791 eck$LassoCheckResult]: Stem: 4958#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 4898#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4899#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4901#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4911#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 4849#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4850#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4701#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4702#L356 assume !(0 == ~M_E~0); 4796#L356-2 assume !(0 == ~T1_E~0); 4797#L361-1 assume !(0 == ~T2_E~0); 4876#L366-1 assume !(0 == ~E_M~0); 4867#L371-1 assume !(0 == ~E_1~0); 4768#L376-1 assume !(0 == ~E_2~0); 4769#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4707#L178 assume !(1 == ~m_pc~0); 4708#L178-2 is_master_triggered_~__retres1~0#1 := 0; 4800#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4801#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4856#L437 assume !(0 != activate_threads_~tmp~1#1); 4729#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4730#L197 assume !(1 == ~t1_pc~0); 4777#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4776#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4949#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4723#L445 assume !(0 != activate_threads_~tmp___0~0#1); 4724#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4926#L216 assume !(1 == ~t2_pc~0); 4705#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4706#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4798#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4799#L453 assume !(0 != activate_threads_~tmp___1~0#1); 4865#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4866#L394 assume 1 == ~M_E~0;~M_E~0 := 2; 4871#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4833#L399-1 assume !(1 == ~T2_E~0); 4834#L404-1 assume !(1 == ~E_M~0); 4748#L409-1 assume !(1 == ~E_1~0); 4749#L414-1 assume !(1 == ~E_2~0); 4836#L419-1 assume { :end_inline_reset_delta_events } true; 4829#L565-2 [2021-11-20 06:41:56,205 INFO L793 eck$LassoCheckResult]: Loop: 4829#L565-2 assume !false; 4824#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4710#L331 assume !false; 4827#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4684#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4680#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4939#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4883#L298 assume !(0 != eval_~tmp~0#1); 4884#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4841#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4842#L356-3 assume !(0 == ~M_E~0); 4896#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4860#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4861#L366-3 assume !(0 == ~E_M~0); 4892#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4815#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4816#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4814#L178-12 assume !(1 == ~m_pc~0); 4677#L178-14 is_master_triggered_~__retres1~0#1 := 0; 4678#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4835#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4890#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4822#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4823#L197-12 assume !(1 == ~t1_pc~0); 4885#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 4897#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4950#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4951#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5798#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5797#L216-12 assume !(1 == ~t2_pc~0); 5564#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 5796#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5795#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4742#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4743#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4923#L394-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4967#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5793#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5792#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4962#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5791#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5790#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5787#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5786#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5785#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 5784#L584 assume !(0 == start_simulation_~tmp~3#1); 4771#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4846#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4847#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5773#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 5772#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4721#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4722#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 4828#L597 assume !(0 != start_simulation_~tmp___0~1#1); 4829#L565-2 [2021-11-20 06:41:56,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:56,207 INFO L85 PathProgramCache]: Analyzing trace with hash -754831607, now seen corresponding path program 1 times [2021-11-20 06:41:56,207 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:56,207 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [755675960] [2021-11-20 06:41:56,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:56,208 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:56,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:56,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:56,262 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:56,263 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [755675960] [2021-11-20 06:41:56,263 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [755675960] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:56,264 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:56,264 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-20 06:41:56,264 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1437461716] [2021-11-20 06:41:56,265 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:56,265 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:41:56,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:56,270 INFO L85 PathProgramCache]: Analyzing trace with hash -1458177828, now seen corresponding path program 2 times [2021-11-20 06:41:56,272 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:56,272 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [838230847] [2021-11-20 06:41:56,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:56,274 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:56,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:56,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:56,317 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:56,318 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [838230847] [2021-11-20 06:41:56,325 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [838230847] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:56,326 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:56,326 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-20 06:41:56,326 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1883697055] [2021-11-20 06:41:56,326 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:56,327 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 06:41:56,327 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:41:56,328 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 06:41:56,329 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 06:41:56,329 INFO L87 Difference]: Start difference. First operand 1138 states and 1651 transitions. cyclomatic complexity: 517 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:56,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:41:56,392 INFO L93 Difference]: Finished difference Result 1671 states and 2418 transitions. [2021-11-20 06:41:56,392 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 06:41:56,397 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1671 states and 2418 transitions. [2021-11-20 06:41:56,413 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1621 [2021-11-20 06:41:56,429 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1671 states to 1671 states and 2418 transitions. [2021-11-20 06:41:56,429 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1671 [2021-11-20 06:41:56,433 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1671 [2021-11-20 06:41:56,433 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1671 states and 2418 transitions. [2021-11-20 06:41:56,436 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 06:41:56,436 INFO L681 BuchiCegarLoop]: Abstraction has 1671 states and 2418 transitions. [2021-11-20 06:41:56,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1671 states and 2418 transitions. [2021-11-20 06:41:56,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1671 to 1201. [2021-11-20 06:41:56,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1201 states, 1201 states have (on average 1.4487926727726894) internal successors, (1740), 1200 states have internal predecessors, (1740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:56,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1201 states to 1201 states and 1740 transitions. [2021-11-20 06:41:56,470 INFO L704 BuchiCegarLoop]: Abstraction has 1201 states and 1740 transitions. [2021-11-20 06:41:56,471 INFO L587 BuchiCegarLoop]: Abstraction has 1201 states and 1740 transitions. [2021-11-20 06:41:56,471 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-20 06:41:56,471 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1201 states and 1740 transitions. [2021-11-20 06:41:56,479 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1156 [2021-11-20 06:41:56,479 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:41:56,480 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:41:56,483 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:56,483 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:56,484 INFO L791 eck$LassoCheckResult]: Stem: 7749#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 7706#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 7707#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7709#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7716#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 7659#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7660#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7519#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7520#L356 assume !(0 == ~M_E~0); 7612#L356-2 assume !(0 == ~T1_E~0); 7613#L361-1 assume !(0 == ~T2_E~0); 7689#L366-1 assume !(0 == ~E_M~0); 7681#L371-1 assume !(0 == ~E_1~0); 7583#L376-1 assume !(0 == ~E_2~0); 7584#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7525#L178 assume !(1 == ~m_pc~0); 7526#L178-2 is_master_triggered_~__retres1~0#1 := 0; 7616#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7617#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7671#L437 assume !(0 != activate_threads_~tmp~1#1); 7547#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7548#L197 assume !(1 == ~t1_pc~0); 7593#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7592#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7746#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7541#L445 assume !(0 != activate_threads_~tmp___0~0#1); 7542#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7732#L216 assume !(1 == ~t2_pc~0); 7523#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7524#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7614#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7615#L453 assume !(0 != activate_threads_~tmp___1~0#1); 7679#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7680#L394 assume !(1 == ~M_E~0); 7687#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7648#L399-1 assume !(1 == ~T2_E~0); 7649#L404-1 assume !(1 == ~E_M~0); 7565#L409-1 assume !(1 == ~E_1~0); 7566#L414-1 assume !(1 == ~E_2~0); 7651#L419-1 assume { :end_inline_reset_delta_events } true; 7644#L565-2 [2021-11-20 06:41:56,484 INFO L793 eck$LassoCheckResult]: Loop: 7644#L565-2 assume !false; 7640#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7528#L331 assume !false; 7642#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7502#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7498#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7581#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7582#L298 assume !(0 != eval_~tmp~0#1); 7555#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7556#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7656#L356-3 assume !(0 == ~M_E~0); 7705#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7672#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7673#L366-3 assume !(0 == ~E_M~0); 7702#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7631#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7632#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7630#L178-12 assume !(1 == ~m_pc~0); 7495#L178-14 is_master_triggered_~__retres1~0#1 := 0; 7496#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7650#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7700#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7638#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7639#L197-12 assume 1 == ~t1_pc~0; 7696#L198-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7570#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7571#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7493#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7494#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7585#L216-12 assume !(1 == ~t2_pc~0); 8646#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 8645#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8644#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8640#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8638#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8636#L394-3 assume !(1 == ~M_E~0); 8290#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8633#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7753#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7600#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7601#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7719#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7720#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7808#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7804#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 7799#L584 assume !(0 == start_simulation_~tmp~3#1); 7587#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7653#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7663#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7688#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 7569#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7539#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7540#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 7643#L597 assume !(0 != start_simulation_~tmp___0~1#1); 7644#L565-2 [2021-11-20 06:41:56,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:56,485 INFO L85 PathProgramCache]: Analyzing trace with hash 1020175755, now seen corresponding path program 1 times [2021-11-20 06:41:56,486 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:56,486 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514082302] [2021-11-20 06:41:56,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:56,487 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:56,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:56,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:56,550 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:56,550 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514082302] [2021-11-20 06:41:56,550 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1514082302] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:56,551 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:56,551 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 06:41:56,551 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1138095062] [2021-11-20 06:41:56,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:56,552 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:41:56,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:56,553 INFO L85 PathProgramCache]: Analyzing trace with hash -1375650595, now seen corresponding path program 1 times [2021-11-20 06:41:56,553 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:56,553 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [38008052] [2021-11-20 06:41:56,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:56,554 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:56,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:56,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:56,613 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:56,613 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [38008052] [2021-11-20 06:41:56,613 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [38008052] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:56,613 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:56,614 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-20 06:41:56,614 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1392909048] [2021-11-20 06:41:56,614 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:56,615 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 06:41:56,615 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:41:56,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 06:41:56,615 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 06:41:56,616 INFO L87 Difference]: Start difference. First operand 1201 states and 1740 transitions. cyclomatic complexity: 541 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:56,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:41:56,685 INFO L93 Difference]: Finished difference Result 1960 states and 2805 transitions. [2021-11-20 06:41:56,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 06:41:56,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1960 states and 2805 transitions. [2021-11-20 06:41:56,705 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1882 [2021-11-20 06:41:56,723 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1960 states to 1960 states and 2805 transitions. [2021-11-20 06:41:56,723 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1960 [2021-11-20 06:41:56,726 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1960 [2021-11-20 06:41:56,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1960 states and 2805 transitions. [2021-11-20 06:41:56,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 06:41:56,731 INFO L681 BuchiCegarLoop]: Abstraction has 1960 states and 2805 transitions. [2021-11-20 06:41:56,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1960 states and 2805 transitions. [2021-11-20 06:41:56,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1960 to 1443. [2021-11-20 06:41:56,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1443 states, 1443 states have (on average 1.4317394317394316) internal successors, (2066), 1442 states have internal predecessors, (2066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:56,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1443 states to 1443 states and 2066 transitions. [2021-11-20 06:41:56,767 INFO L704 BuchiCegarLoop]: Abstraction has 1443 states and 2066 transitions. [2021-11-20 06:41:56,768 INFO L587 BuchiCegarLoop]: Abstraction has 1443 states and 2066 transitions. [2021-11-20 06:41:56,768 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-20 06:41:56,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1443 states and 2066 transitions. [2021-11-20 06:41:56,779 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1372 [2021-11-20 06:41:56,779 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:41:56,779 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:41:56,781 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:56,782 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:56,787 INFO L791 eck$LassoCheckResult]: Stem: 10944#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 10891#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10892#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10895#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10903#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 10839#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10840#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10692#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10693#L356 assume !(0 == ~M_E~0); 10786#L356-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10787#L361-1 assume !(0 == ~T2_E~0); 10963#L366-1 assume !(0 == ~E_M~0); 10962#L371-1 assume !(0 == ~E_1~0); 10756#L376-1 assume !(0 == ~E_2~0); 10757#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10698#L178 assume !(1 == ~m_pc~0); 10699#L178-2 is_master_triggered_~__retres1~0#1 := 0; 10857#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10904#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10849#L437 assume !(0 != activate_threads_~tmp~1#1); 10720#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10721#L197 assume !(1 == ~t1_pc~0); 10768#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10937#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10938#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10941#L445 assume !(0 != activate_threads_~tmp___0~0#1); 10921#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10922#L216 assume !(1 == ~t2_pc~0); 10954#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10800#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10801#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10896#L453 assume !(0 != activate_threads_~tmp___1~0#1); 10858#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10859#L394 assume !(1 == ~M_E~0); 10867#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10827#L399-1 assume !(1 == ~T2_E~0); 10828#L404-1 assume !(1 == ~E_M~0); 10738#L409-1 assume !(1 == ~E_1~0); 10739#L414-1 assume !(1 == ~E_2~0); 10830#L419-1 assume { :end_inline_reset_delta_events } true; 10831#L565-2 [2021-11-20 06:41:56,788 INFO L793 eck$LassoCheckResult]: Loop: 10831#L565-2 assume !false; 11540#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11534#L331 assume !false; 11531#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11527#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11514#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11513#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11500#L298 assume !(0 != eval_~tmp~0#1); 11496#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11492#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11489#L356-3 assume !(0 == ~M_E~0); 11450#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11449#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11448#L366-3 assume !(0 == ~E_M~0); 11447#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11446#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11445#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11444#L178-12 assume !(1 == ~m_pc~0); 11443#L178-14 is_master_triggered_~__retres1~0#1 := 0; 11442#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11441#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11440#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11439#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11438#L197-12 assume !(1 == ~t1_pc~0); 11436#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 11435#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11434#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11433#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11432#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11431#L216-12 assume !(1 == ~t2_pc~0); 11068#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 11430#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11429#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11428#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11427#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11426#L394-3 assume !(1 == ~M_E~0); 11331#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11418#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11410#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11406#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11403#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11398#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11393#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11390#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11387#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 10967#L584 assume !(0 == start_simulation_~tmp~3#1); 10969#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11581#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11575#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11571#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 11566#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11562#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11556#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 11553#L597 assume !(0 != start_simulation_~tmp___0~1#1); 10831#L565-2 [2021-11-20 06:41:56,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:56,788 INFO L85 PathProgramCache]: Analyzing trace with hash 318575881, now seen corresponding path program 1 times [2021-11-20 06:41:56,788 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:56,789 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [8789955] [2021-11-20 06:41:56,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:56,789 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:56,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:56,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:56,818 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:56,818 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [8789955] [2021-11-20 06:41:56,819 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [8789955] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:56,820 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:56,820 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 06:41:56,821 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2028578585] [2021-11-20 06:41:56,821 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:56,821 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:41:56,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:56,821 INFO L85 PathProgramCache]: Analyzing trace with hash 1147845726, now seen corresponding path program 1 times [2021-11-20 06:41:56,822 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:56,826 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390982442] [2021-11-20 06:41:56,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:56,828 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:56,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:56,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:56,875 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:56,877 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390982442] [2021-11-20 06:41:56,880 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1390982442] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:56,880 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:56,881 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-20 06:41:56,883 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1226437822] [2021-11-20 06:41:56,883 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:56,883 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 06:41:56,883 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:41:56,884 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 06:41:56,884 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 06:41:56,884 INFO L87 Difference]: Start difference. First operand 1443 states and 2066 transitions. cyclomatic complexity: 625 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:56,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:41:56,938 INFO L93 Difference]: Finished difference Result 1713 states and 2440 transitions. [2021-11-20 06:41:56,938 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 06:41:56,941 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1713 states and 2440 transitions. [2021-11-20 06:41:56,956 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1666 [2021-11-20 06:41:56,970 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1713 states to 1713 states and 2440 transitions. [2021-11-20 06:41:56,970 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1713 [2021-11-20 06:41:56,972 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1713 [2021-11-20 06:41:56,972 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1713 states and 2440 transitions. [2021-11-20 06:41:56,975 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 06:41:56,975 INFO L681 BuchiCegarLoop]: Abstraction has 1713 states and 2440 transitions. [2021-11-20 06:41:56,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1713 states and 2440 transitions. [2021-11-20 06:41:57,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1713 to 1201. [2021-11-20 06:41:57,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1201 states, 1201 states have (on average 1.4271440466278102) internal successors, (1714), 1200 states have internal predecessors, (1714), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:57,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1201 states to 1201 states and 1714 transitions. [2021-11-20 06:41:57,018 INFO L704 BuchiCegarLoop]: Abstraction has 1201 states and 1714 transitions. [2021-11-20 06:41:57,018 INFO L587 BuchiCegarLoop]: Abstraction has 1201 states and 1714 transitions. [2021-11-20 06:41:57,018 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-20 06:41:57,018 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1201 states and 1714 transitions. [2021-11-20 06:41:57,025 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1156 [2021-11-20 06:41:57,025 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:41:57,025 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:41:57,026 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:57,026 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:57,027 INFO L791 eck$LassoCheckResult]: Stem: 14088#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 14047#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 14048#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14050#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14056#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 14006#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14007#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13860#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13861#L356 assume !(0 == ~M_E~0); 13951#L356-2 assume !(0 == ~T1_E~0); 13952#L361-1 assume !(0 == ~T2_E~0); 14030#L366-1 assume !(0 == ~E_M~0); 14023#L371-1 assume !(0 == ~E_1~0); 13926#L376-1 assume !(0 == ~E_2~0); 13927#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13866#L178 assume !(1 == ~m_pc~0); 13867#L178-2 is_master_triggered_~__retres1~0#1 := 0; 13957#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13958#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14013#L437 assume !(0 != activate_threads_~tmp~1#1); 13888#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13889#L197 assume !(1 == ~t1_pc~0); 13935#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13934#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14085#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13884#L445 assume !(0 != activate_threads_~tmp___0~0#1); 13885#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14073#L216 assume !(1 == ~t2_pc~0); 13864#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13865#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13953#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13954#L453 assume !(0 != activate_threads_~tmp___1~0#1); 14021#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14022#L394 assume !(1 == ~M_E~0); 14027#L394-2 assume !(1 == ~T1_E~0); 13990#L399-1 assume !(1 == ~T2_E~0); 13991#L404-1 assume !(1 == ~E_M~0); 13906#L409-1 assume !(1 == ~E_1~0); 13907#L414-1 assume !(1 == ~E_2~0); 13993#L419-1 assume { :end_inline_reset_delta_events } true; 13994#L565-2 [2021-11-20 06:41:57,027 INFO L793 eck$LassoCheckResult]: Loop: 13994#L565-2 assume !false; 14559#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14548#L331 assume !false; 14544#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14534#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14529#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14525#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14520#L298 assume !(0 != eval_~tmp~0#1); 14514#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14508#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14503#L356-3 assume !(0 == ~M_E~0); 14496#L356-5 assume !(0 == ~T1_E~0); 14490#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14488#L366-3 assume !(0 == ~E_M~0); 14486#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14482#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14480#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14478#L178-12 assume !(1 == ~m_pc~0); 14475#L178-14 is_master_triggered_~__retres1~0#1 := 0; 14473#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14471#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14469#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14467#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14465#L197-12 assume !(1 == ~t1_pc~0); 14462#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 14460#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14458#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14456#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14454#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14452#L216-12 assume !(1 == ~t2_pc~0); 14432#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 14449#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14447#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14445#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14443#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14440#L394-3 assume !(1 == ~M_E~0); 14392#L394-5 assume !(1 == ~T1_E~0); 14437#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14435#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14433#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14430#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14427#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14154#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14148#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14140#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 14134#L584 assume !(0 == start_simulation_~tmp~3#1); 14135#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14599#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14595#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14591#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 14587#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14582#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14576#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 14572#L597 assume !(0 != start_simulation_~tmp___0~1#1); 13994#L565-2 [2021-11-20 06:41:57,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:57,027 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 1 times [2021-11-20 06:41:57,027 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:57,027 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1293392571] [2021-11-20 06:41:57,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:57,028 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:57,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:57,034 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:41:57,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:57,065 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:41:57,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:57,066 INFO L85 PathProgramCache]: Analyzing trace with hash -1743692258, now seen corresponding path program 1 times [2021-11-20 06:41:57,066 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:57,066 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814645817] [2021-11-20 06:41:57,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:57,067 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:57,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:57,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:57,094 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:57,094 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [814645817] [2021-11-20 06:41:57,094 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [814645817] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:57,095 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:57,095 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-20 06:41:57,095 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [149337151] [2021-11-20 06:41:57,095 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:57,095 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 06:41:57,095 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:41:57,096 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-20 06:41:57,096 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-20 06:41:57,096 INFO L87 Difference]: Start difference. First operand 1201 states and 1714 transitions. cyclomatic complexity: 515 Second operand has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:57,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:41:57,178 INFO L93 Difference]: Finished difference Result 2073 states and 2910 transitions. [2021-11-20 06:41:57,179 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-11-20 06:41:57,179 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2073 states and 2910 transitions. [2021-11-20 06:41:57,194 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2024 [2021-11-20 06:41:57,211 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2073 states to 2073 states and 2910 transitions. [2021-11-20 06:41:57,211 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2073 [2021-11-20 06:41:57,213 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2073 [2021-11-20 06:41:57,213 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2073 states and 2910 transitions. [2021-11-20 06:41:57,216 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 06:41:57,216 INFO L681 BuchiCegarLoop]: Abstraction has 2073 states and 2910 transitions. [2021-11-20 06:41:57,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2073 states and 2910 transitions. [2021-11-20 06:41:57,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2073 to 1225. [2021-11-20 06:41:57,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1225 states, 1225 states have (on average 1.4187755102040815) internal successors, (1738), 1224 states have internal predecessors, (1738), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:57,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1225 states to 1225 states and 1738 transitions. [2021-11-20 06:41:57,246 INFO L704 BuchiCegarLoop]: Abstraction has 1225 states and 1738 transitions. [2021-11-20 06:41:57,246 INFO L587 BuchiCegarLoop]: Abstraction has 1225 states and 1738 transitions. [2021-11-20 06:41:57,246 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-20 06:41:57,247 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1225 states and 1738 transitions. [2021-11-20 06:41:57,253 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1180 [2021-11-20 06:41:57,253 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:41:57,253 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:41:57,254 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:57,254 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:57,254 INFO L791 eck$LassoCheckResult]: Stem: 17392#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 17343#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 17344#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17346#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17353#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 17301#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17302#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17150#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17151#L356 assume !(0 == ~M_E~0); 17243#L356-2 assume !(0 == ~T1_E~0); 17244#L361-1 assume !(0 == ~T2_E~0); 17325#L366-1 assume !(0 == ~E_M~0); 17318#L371-1 assume !(0 == ~E_1~0); 17215#L376-1 assume !(0 == ~E_2~0); 17216#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17156#L178 assume !(1 == ~m_pc~0); 17157#L178-2 is_master_triggered_~__retres1~0#1 := 0; 17249#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17250#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17308#L437 assume !(0 != activate_threads_~tmp~1#1); 17178#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17179#L197 assume !(1 == ~t1_pc~0); 17225#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17224#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17388#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17174#L445 assume !(0 != activate_threads_~tmp___0~0#1); 17175#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17372#L216 assume !(1 == ~t2_pc~0); 17154#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17155#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17245#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17246#L453 assume !(0 != activate_threads_~tmp___1~0#1); 17316#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17317#L394 assume !(1 == ~M_E~0); 17322#L394-2 assume !(1 == ~T1_E~0); 17286#L399-1 assume !(1 == ~T2_E~0); 17287#L404-1 assume !(1 == ~E_M~0); 17197#L409-1 assume !(1 == ~E_1~0); 17198#L414-1 assume !(1 == ~E_2~0); 17289#L419-1 assume { :end_inline_reset_delta_events } true; 17290#L565-2 [2021-11-20 06:41:57,255 INFO L793 eck$LassoCheckResult]: Loop: 17290#L565-2 assume !false; 18302#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17159#L331 assume !false; 18028#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 18026#L266 assume !(0 == ~m_st~0); 18027#L270 assume !(0 == ~t1_st~0); 18025#L274 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 18022#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 18021#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 18020#L298 assume !(0 != eval_~tmp~0#1); 18019#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18018#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17371#L356-3 assume !(0 == ~M_E~0); 17342#L356-5 assume !(0 == ~T1_E~0); 17309#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17310#L366-3 assume !(0 == ~E_M~0); 17338#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17264#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17265#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17263#L178-12 assume !(1 == ~m_pc~0); 17126#L178-14 is_master_triggered_~__retres1~0#1 := 0; 17127#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17288#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17337#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17271#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17272#L197-12 assume !(1 == ~t1_pc~0); 17331#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 17202#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17203#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17986#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17217#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17200#L216-12 assume !(1 == ~t2_pc~0); 17201#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 18207#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18206#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17191#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17192#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18205#L394-3 assume !(1 == ~M_E~0); 17980#L394-5 assume !(1 == ~T1_E~0); 17146#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17147#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17232#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17233#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18202#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 17330#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 17137#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17195#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 17196#L584 assume !(0 == start_simulation_~tmp~3#1); 17351#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 18336#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 18308#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 18307#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 18306#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18305#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18304#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 18303#L597 assume !(0 != start_simulation_~tmp___0~1#1); 17290#L565-2 [2021-11-20 06:41:57,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:57,255 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 2 times [2021-11-20 06:41:57,255 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:57,256 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1082649394] [2021-11-20 06:41:57,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:57,256 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:57,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:57,262 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:41:57,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:57,274 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:41:57,275 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:57,275 INFO L85 PathProgramCache]: Analyzing trace with hash 1678104567, now seen corresponding path program 1 times [2021-11-20 06:41:57,275 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:57,275 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [321063853] [2021-11-20 06:41:57,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:57,276 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:57,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:57,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:57,334 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:57,334 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [321063853] [2021-11-20 06:41:57,334 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [321063853] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:57,334 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:57,334 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-20 06:41:57,335 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1552246791] [2021-11-20 06:41:57,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:57,335 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 06:41:57,335 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:41:57,336 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-20 06:41:57,336 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-20 06:41:57,336 INFO L87 Difference]: Start difference. First operand 1225 states and 1738 transitions. cyclomatic complexity: 515 Second operand has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:57,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:41:57,484 INFO L93 Difference]: Finished difference Result 2407 states and 3391 transitions. [2021-11-20 06:41:57,484 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-20 06:41:57,485 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2407 states and 3391 transitions. [2021-11-20 06:41:57,503 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2362 [2021-11-20 06:41:57,521 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2407 states to 2407 states and 3391 transitions. [2021-11-20 06:41:57,521 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2407 [2021-11-20 06:41:57,526 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2407 [2021-11-20 06:41:57,526 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2407 states and 3391 transitions. [2021-11-20 06:41:57,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 06:41:57,530 INFO L681 BuchiCegarLoop]: Abstraction has 2407 states and 3391 transitions. [2021-11-20 06:41:57,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2407 states and 3391 transitions. [2021-11-20 06:41:57,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2407 to 1273. [2021-11-20 06:41:57,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1273 states, 1273 states have (on average 1.3927729772191673) internal successors, (1773), 1272 states have internal predecessors, (1773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:57,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1273 states to 1273 states and 1773 transitions. [2021-11-20 06:41:57,590 INFO L704 BuchiCegarLoop]: Abstraction has 1273 states and 1773 transitions. [2021-11-20 06:41:57,590 INFO L587 BuchiCegarLoop]: Abstraction has 1273 states and 1773 transitions. [2021-11-20 06:41:57,590 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-20 06:41:57,590 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1273 states and 1773 transitions. [2021-11-20 06:41:57,595 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1228 [2021-11-20 06:41:57,595 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:41:57,595 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:41:57,596 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:57,596 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:57,596 INFO L791 eck$LassoCheckResult]: Stem: 21035#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 20988#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 20989#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20992#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20999#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 20941#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20942#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20795#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20796#L356 assume !(0 == ~M_E~0); 20887#L356-2 assume !(0 == ~T1_E~0); 20888#L361-1 assume !(0 == ~T2_E~0); 20967#L366-1 assume !(0 == ~E_M~0); 20961#L371-1 assume !(0 == ~E_1~0); 20859#L376-1 assume !(0 == ~E_2~0); 20860#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20801#L178 assume !(1 == ~m_pc~0); 20802#L178-2 is_master_triggered_~__retres1~0#1 := 0; 20891#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20892#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20950#L437 assume !(0 != activate_threads_~tmp~1#1); 20823#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20824#L197 assume !(1 == ~t1_pc~0); 20869#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20868#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21029#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20817#L445 assume !(0 != activate_threads_~tmp___0~0#1); 20818#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21015#L216 assume !(1 == ~t2_pc~0); 20799#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20800#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20889#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20890#L453 assume !(0 != activate_threads_~tmp___1~0#1); 20959#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20960#L394 assume !(1 == ~M_E~0); 20965#L394-2 assume !(1 == ~T1_E~0); 20928#L399-1 assume !(1 == ~T2_E~0); 20929#L404-1 assume !(1 == ~E_M~0); 20841#L409-1 assume !(1 == ~E_1~0); 20842#L414-1 assume !(1 == ~E_2~0); 20931#L419-1 assume { :end_inline_reset_delta_events } true; 20932#L565-2 [2021-11-20 06:41:57,596 INFO L793 eck$LassoCheckResult]: Loop: 20932#L565-2 assume !false; 21547#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21465#L331 assume !false; 21546#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 21544#L266 assume !(0 == ~m_st~0); 21545#L270 assume !(0 == ~t1_st~0); 21542#L274 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 21543#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 21538#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 21539#L298 assume !(0 != eval_~tmp~0#1); 21966#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21965#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21964#L356-3 assume !(0 == ~M_E~0); 21963#L356-5 assume !(0 == ~T1_E~0); 21962#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21961#L366-3 assume !(0 == ~E_M~0); 21960#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21959#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20951#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20906#L178-12 assume !(1 == ~m_pc~0); 20907#L178-14 is_master_triggered_~__retres1~0#1 := 0; 21537#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21536#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21535#L437-12 assume !(0 != activate_threads_~tmp~1#1); 21534#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21533#L197-12 assume !(1 == ~t1_pc~0); 21531#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 21530#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21529#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21528#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21527#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21525#L216-12 assume !(1 == ~t2_pc~0); 21342#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 21101#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21102#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21093#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21094#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21086#L394-3 assume !(1 == ~M_E~0); 21085#L394-5 assume !(1 == ~T1_E~0); 21418#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21416#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21414#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21412#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21073#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 21069#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 21065#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 21064#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 21059#L584 assume !(0 == start_simulation_~tmp~3#1); 21061#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 21555#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 21553#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 21552#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 21551#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21550#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21549#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 21548#L597 assume !(0 != start_simulation_~tmp___0~1#1); 20932#L565-2 [2021-11-20 06:41:57,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:57,597 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 3 times [2021-11-20 06:41:57,597 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:57,597 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [15486235] [2021-11-20 06:41:57,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:57,597 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:57,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:57,603 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:41:57,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:57,630 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:41:57,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:57,631 INFO L85 PathProgramCache]: Analyzing trace with hash 1605718009, now seen corresponding path program 1 times [2021-11-20 06:41:57,631 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:57,631 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1278362317] [2021-11-20 06:41:57,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:57,631 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:57,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:57,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:57,651 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:57,651 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1278362317] [2021-11-20 06:41:57,651 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1278362317] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:57,651 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:57,651 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 06:41:57,652 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1728505219] [2021-11-20 06:41:57,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:57,652 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 06:41:57,652 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:41:57,652 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 06:41:57,653 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 06:41:57,653 INFO L87 Difference]: Start difference. First operand 1273 states and 1773 transitions. cyclomatic complexity: 502 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:57,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:41:57,689 INFO L93 Difference]: Finished difference Result 1886 states and 2583 transitions. [2021-11-20 06:41:57,690 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 06:41:57,690 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1886 states and 2583 transitions. [2021-11-20 06:41:57,701 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1841 [2021-11-20 06:41:57,714 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1886 states to 1886 states and 2583 transitions. [2021-11-20 06:41:57,715 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1886 [2021-11-20 06:41:57,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1886 [2021-11-20 06:41:57,717 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1886 states and 2583 transitions. [2021-11-20 06:41:57,720 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 06:41:57,720 INFO L681 BuchiCegarLoop]: Abstraction has 1886 states and 2583 transitions. [2021-11-20 06:41:57,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1886 states and 2583 transitions. [2021-11-20 06:41:57,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1886 to 1824. [2021-11-20 06:41:57,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1824 states, 1824 states have (on average 1.3711622807017543) internal successors, (2501), 1823 states have internal predecessors, (2501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:57,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1824 states to 1824 states and 2501 transitions. [2021-11-20 06:41:57,758 INFO L704 BuchiCegarLoop]: Abstraction has 1824 states and 2501 transitions. [2021-11-20 06:41:57,758 INFO L587 BuchiCegarLoop]: Abstraction has 1824 states and 2501 transitions. [2021-11-20 06:41:57,758 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-20 06:41:57,758 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1824 states and 2501 transitions. [2021-11-20 06:41:57,765 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1779 [2021-11-20 06:41:57,765 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:41:57,765 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:41:57,766 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:57,766 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:57,766 INFO L791 eck$LassoCheckResult]: Stem: 24223#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 24158#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 24159#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24161#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24168#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 24110#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24111#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23960#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23961#L356 assume !(0 == ~M_E~0); 24053#L356-2 assume !(0 == ~T1_E~0); 24054#L361-1 assume !(0 == ~T2_E~0); 24136#L366-1 assume !(0 == ~E_M~0); 24129#L371-1 assume !(0 == ~E_1~0); 24024#L376-1 assume !(0 == ~E_2~0); 24025#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23966#L178 assume !(1 == ~m_pc~0); 23967#L178-2 is_master_triggered_~__retres1~0#1 := 0; 24057#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24058#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 24121#L437 assume !(0 != activate_threads_~tmp~1#1); 23988#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23989#L197 assume !(1 == ~t1_pc~0); 24034#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 24033#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24212#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 23982#L445 assume !(0 != activate_threads_~tmp___0~0#1); 23983#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24191#L216 assume !(1 == ~t2_pc~0); 23964#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23965#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24055#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 24056#L453 assume !(0 != activate_threads_~tmp___1~0#1); 24127#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24128#L394 assume !(1 == ~M_E~0); 24133#L394-2 assume !(1 == ~T1_E~0); 24096#L399-1 assume !(1 == ~T2_E~0); 24097#L404-1 assume !(1 == ~E_M~0); 24006#L409-1 assume !(1 == ~E_1~0); 24007#L414-1 assume !(1 == ~E_2~0); 24099#L419-1 assume { :end_inline_reset_delta_events } true; 24100#L565-2 assume !false; 24824#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24802#L331 [2021-11-20 06:41:57,766 INFO L793 eck$LassoCheckResult]: Loop: 24802#L331 assume !false; 24546#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 24547#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 24820#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 24818#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 24814#L298 assume 0 != eval_~tmp~0#1; 24811#L298-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 24808#L306 assume !(0 != eval_~tmp_ndt_1~0#1); 24806#L303 assume !(0 == ~t1_st~0); 24803#L317 assume !(0 == ~t2_st~0); 24802#L331 [2021-11-20 06:41:57,766 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:57,767 INFO L85 PathProgramCache]: Analyzing trace with hash 327016235, now seen corresponding path program 1 times [2021-11-20 06:41:57,767 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:57,767 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [940993915] [2021-11-20 06:41:57,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:57,767 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:57,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:57,772 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:41:57,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:57,783 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:41:57,784 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:57,784 INFO L85 PathProgramCache]: Analyzing trace with hash 698787991, now seen corresponding path program 1 times [2021-11-20 06:41:57,784 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:57,784 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [509780833] [2021-11-20 06:41:57,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:57,784 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:57,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:57,787 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:41:57,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:57,790 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:41:57,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:57,791 INFO L85 PathProgramCache]: Analyzing trace with hash 1780423489, now seen corresponding path program 1 times [2021-11-20 06:41:57,791 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:57,791 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1176673279] [2021-11-20 06:41:57,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:57,791 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:57,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:57,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:57,812 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:57,812 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1176673279] [2021-11-20 06:41:57,812 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1176673279] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:57,812 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:57,812 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 06:41:57,813 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [298367039] [2021-11-20 06:41:57,813 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:57,875 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:41:57,875 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 06:41:57,875 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 06:41:57,875 INFO L87 Difference]: Start difference. First operand 1824 states and 2501 transitions. cyclomatic complexity: 680 Second operand has 3 states, 3 states have (on average 17.333333333333332) internal successors, (52), 3 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:57,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:41:57,925 INFO L93 Difference]: Finished difference Result 3112 states and 4211 transitions. [2021-11-20 06:41:57,925 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 06:41:57,926 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3112 states and 4211 transitions. [2021-11-20 06:41:57,943 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3028 [2021-11-20 06:41:57,967 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3112 states to 3112 states and 4211 transitions. [2021-11-20 06:41:57,967 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3112 [2021-11-20 06:41:57,970 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3112 [2021-11-20 06:41:57,970 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3112 states and 4211 transitions. [2021-11-20 06:41:57,974 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 06:41:57,975 INFO L681 BuchiCegarLoop]: Abstraction has 3112 states and 4211 transitions. [2021-11-20 06:41:57,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3112 states and 4211 transitions. [2021-11-20 06:41:58,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3112 to 2965. [2021-11-20 06:41:58,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2965 states, 2965 states have (on average 1.3612141652613827) internal successors, (4036), 2964 states have internal predecessors, (4036), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:58,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2965 states to 2965 states and 4036 transitions. [2021-11-20 06:41:58,075 INFO L704 BuchiCegarLoop]: Abstraction has 2965 states and 4036 transitions. [2021-11-20 06:41:58,076 INFO L587 BuchiCegarLoop]: Abstraction has 2965 states and 4036 transitions. [2021-11-20 06:41:58,076 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-20 06:41:58,076 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2965 states and 4036 transitions. [2021-11-20 06:41:58,087 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2881 [2021-11-20 06:41:58,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:41:58,087 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:41:58,087 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:58,087 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:58,088 INFO L791 eck$LassoCheckResult]: Stem: 29192#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 29127#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 29128#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29130#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29142#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 29068#L243-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 29069#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29156#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29166#L356 assume !(0 == ~M_E~0); 29167#L356-2 assume !(0 == ~T1_E~0); 29105#L361-1 assume !(0 == ~T2_E~0); 29106#L366-1 assume !(0 == ~E_M~0); 29093#L371-1 assume !(0 == ~E_1~0); 29094#L376-1 assume !(0 == ~E_2~0); 29027#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29028#L178 assume !(1 == ~m_pc~0); 29089#L178-2 is_master_triggered_~__retres1~0#1 := 0; 29090#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29143#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 29144#L437 assume !(0 != activate_threads_~tmp~1#1); 28933#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28934#L197 assume !(1 == ~t1_pc~0); 28977#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28976#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29184#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 29185#L445 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28928#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29176#L216 assume !(1 == ~t2_pc~0); 29177#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29018#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29019#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 29131#L453 assume !(0 != activate_threads_~tmp___1~0#1); 29132#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29098#L394 assume !(1 == ~M_E~0); 29099#L394-2 assume !(1 == ~T1_E~0); 29053#L399-1 assume !(1 == ~T2_E~0); 29054#L404-1 assume !(1 == ~E_M~0); 28950#L409-1 assume !(1 == ~E_1~0); 28951#L414-1 assume !(1 == ~E_2~0); 29056#L419-1 assume { :end_inline_reset_delta_events } true; 29057#L565-2 assume !false; 30120#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30096#L331 [2021-11-20 06:41:58,088 INFO L793 eck$LassoCheckResult]: Loop: 30096#L331 assume !false; 30117#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 30114#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 30115#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 31497#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 31495#L298 assume 0 != eval_~tmp~0#1; 31492#L298-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 31489#L306 assume !(0 != eval_~tmp_ndt_1~0#1); 29194#L303 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 28996#L320 assume !(0 != eval_~tmp_ndt_2~0#1); 28997#L317 assume !(0 == ~t2_st~0); 30096#L331 [2021-11-20 06:41:58,088 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:58,088 INFO L85 PathProgramCache]: Analyzing trace with hash -1720071637, now seen corresponding path program 1 times [2021-11-20 06:41:58,089 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:58,089 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887910898] [2021-11-20 06:41:58,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:58,089 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:58,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:58,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:58,104 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:58,104 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1887910898] [2021-11-20 06:41:58,104 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1887910898] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:58,104 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:58,104 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 06:41:58,104 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1856745123] [2021-11-20 06:41:58,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:58,105 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 06:41:58,105 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:58,105 INFO L85 PathProgramCache]: Analyzing trace with hash 187484484, now seen corresponding path program 1 times [2021-11-20 06:41:58,105 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:58,105 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [629855693] [2021-11-20 06:41:58,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:58,106 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:58,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:58,109 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:41:58,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:58,112 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:41:58,191 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:41:58,191 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 06:41:58,191 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 06:41:58,191 INFO L87 Difference]: Start difference. First operand 2965 states and 4036 transitions. cyclomatic complexity: 1074 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:58,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:41:58,210 INFO L93 Difference]: Finished difference Result 2928 states and 3987 transitions. [2021-11-20 06:41:58,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 06:41:58,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2928 states and 3987 transitions. [2021-11-20 06:41:58,225 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2881 [2021-11-20 06:41:58,245 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2928 states to 2928 states and 3987 transitions. [2021-11-20 06:41:58,245 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2928 [2021-11-20 06:41:58,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2928 [2021-11-20 06:41:58,248 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2928 states and 3987 transitions. [2021-11-20 06:41:58,252 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 06:41:58,252 INFO L681 BuchiCegarLoop]: Abstraction has 2928 states and 3987 transitions. [2021-11-20 06:41:58,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2928 states and 3987 transitions. [2021-11-20 06:41:58,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2928 to 2928. [2021-11-20 06:41:58,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2928 states, 2928 states have (on average 1.3616803278688525) internal successors, (3987), 2927 states have internal predecessors, (3987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:58,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2928 states to 2928 states and 3987 transitions. [2021-11-20 06:41:58,309 INFO L704 BuchiCegarLoop]: Abstraction has 2928 states and 3987 transitions. [2021-11-20 06:41:58,309 INFO L587 BuchiCegarLoop]: Abstraction has 2928 states and 3987 transitions. [2021-11-20 06:41:58,309 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-20 06:41:58,309 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2928 states and 3987 transitions. [2021-11-20 06:41:58,320 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2881 [2021-11-20 06:41:58,320 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:41:58,320 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:41:58,321 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:58,321 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:58,321 INFO L791 eck$LassoCheckResult]: Stem: 35049#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 35001#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 35002#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35004#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35012#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 34957#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34958#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34802#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34803#L356 assume !(0 == ~M_E~0); 34896#L356-2 assume !(0 == ~T1_E~0); 34897#L361-1 assume !(0 == ~T2_E~0); 34983#L366-1 assume !(0 == ~E_M~0); 34975#L371-1 assume !(0 == ~E_1~0); 34866#L376-1 assume !(0 == ~E_2~0); 34867#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34808#L178 assume !(1 == ~m_pc~0); 34809#L178-2 is_master_triggered_~__retres1~0#1 := 0; 34902#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34903#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 34964#L437 assume !(0 != activate_threads_~tmp~1#1); 34830#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34831#L197 assume !(1 == ~t1_pc~0); 34875#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34874#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35042#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 34826#L445 assume !(0 != activate_threads_~tmp___0~0#1); 34827#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35031#L216 assume !(1 == ~t2_pc~0); 34806#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34807#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34898#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34899#L453 assume !(0 != activate_threads_~tmp___1~0#1); 34973#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34974#L394 assume !(1 == ~M_E~0); 34979#L394-2 assume !(1 == ~T1_E~0); 34941#L399-1 assume !(1 == ~T2_E~0); 34942#L404-1 assume !(1 == ~E_M~0); 34847#L409-1 assume !(1 == ~E_1~0); 34848#L414-1 assume !(1 == ~E_2~0); 34944#L419-1 assume { :end_inline_reset_delta_events } true; 34945#L565-2 assume !false; 37121#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36075#L331 [2021-11-20 06:41:58,321 INFO L793 eck$LassoCheckResult]: Loop: 36075#L331 assume !false; 37119#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 37117#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 37116#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 37115#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37114#L298 assume 0 != eval_~tmp~0#1; 37113#L298-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 34946#L306 assume !(0 != eval_~tmp_ndt_1~0#1); 34948#L303 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 36008#L320 assume !(0 != eval_~tmp_ndt_2~0#1); 36078#L317 assume !(0 == ~t2_st~0); 36075#L331 [2021-11-20 06:41:58,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:58,322 INFO L85 PathProgramCache]: Analyzing trace with hash 327016235, now seen corresponding path program 2 times [2021-11-20 06:41:58,322 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:58,322 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1890673314] [2021-11-20 06:41:58,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:58,322 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:58,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:58,328 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:41:58,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:58,368 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:41:58,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:58,369 INFO L85 PathProgramCache]: Analyzing trace with hash 187484484, now seen corresponding path program 2 times [2021-11-20 06:41:58,369 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:58,370 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [962627063] [2021-11-20 06:41:58,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:58,370 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:58,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:58,373 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:41:58,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:58,376 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:41:58,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:58,377 INFO L85 PathProgramCache]: Analyzing trace with hash -641553446, now seen corresponding path program 1 times [2021-11-20 06:41:58,377 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:58,377 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [13821380] [2021-11-20 06:41:58,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:58,378 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:58,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 06:41:58,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 06:41:58,399 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 06:41:58,399 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [13821380] [2021-11-20 06:41:58,399 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [13821380] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 06:41:58,399 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 06:41:58,399 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-20 06:41:58,400 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [827778308] [2021-11-20 06:41:58,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 06:41:58,477 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 06:41:58,477 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 06:41:58,477 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 06:41:58,477 INFO L87 Difference]: Start difference. First operand 2928 states and 3987 transitions. cyclomatic complexity: 1062 Second operand has 3 states, 2 states have (on average 26.5) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:58,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 06:41:58,534 INFO L93 Difference]: Finished difference Result 4987 states and 6732 transitions. [2021-11-20 06:41:58,535 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 06:41:58,535 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4987 states and 6732 transitions. [2021-11-20 06:41:58,562 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4936 [2021-11-20 06:41:58,591 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4987 states to 4987 states and 6732 transitions. [2021-11-20 06:41:58,591 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4987 [2021-11-20 06:41:58,596 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4987 [2021-11-20 06:41:58,597 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4987 states and 6732 transitions. [2021-11-20 06:41:58,603 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 06:41:58,603 INFO L681 BuchiCegarLoop]: Abstraction has 4987 states and 6732 transitions. [2021-11-20 06:41:58,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4987 states and 6732 transitions. [2021-11-20 06:41:58,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4987 to 4931. [2021-11-20 06:41:58,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4931 states, 4931 states have (on average 1.3538835935915636) internal successors, (6676), 4930 states have internal predecessors, (6676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 06:41:58,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4931 states to 4931 states and 6676 transitions. [2021-11-20 06:41:58,715 INFO L704 BuchiCegarLoop]: Abstraction has 4931 states and 6676 transitions. [2021-11-20 06:41:58,715 INFO L587 BuchiCegarLoop]: Abstraction has 4931 states and 6676 transitions. [2021-11-20 06:41:58,715 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-20 06:41:58,715 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4931 states and 6676 transitions. [2021-11-20 06:41:58,736 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4880 [2021-11-20 06:41:58,736 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 06:41:58,736 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 06:41:58,737 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:58,737 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 06:41:58,737 INFO L791 eck$LassoCheckResult]: Stem: 42992#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 42934#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 42935#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42937#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42947#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 42886#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42887#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42725#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42726#L356 assume !(0 == ~M_E~0); 42825#L356-2 assume !(0 == ~T1_E~0); 42826#L361-1 assume !(0 == ~T2_E~0); 42915#L366-1 assume !(0 == ~E_M~0); 42906#L371-1 assume !(0 == ~E_1~0); 42791#L376-1 assume !(0 == ~E_2~0); 42792#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42731#L178 assume !(1 == ~m_pc~0); 42732#L178-2 is_master_triggered_~__retres1~0#1 := 0; 42831#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42832#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 42896#L437 assume !(0 != activate_threads_~tmp~1#1); 42754#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42755#L197 assume !(1 == ~t1_pc~0); 42803#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42802#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42986#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 42750#L445 assume !(0 != activate_threads_~tmp___0~0#1); 42751#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42973#L216 assume !(1 == ~t2_pc~0); 42729#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 42730#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42827#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 42828#L453 assume !(0 != activate_threads_~tmp___1~0#1); 42904#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42905#L394 assume !(1 == ~M_E~0); 42910#L394-2 assume !(1 == ~T1_E~0); 42869#L399-1 assume !(1 == ~T2_E~0); 42870#L404-1 assume !(1 == ~E_M~0); 42772#L409-1 assume !(1 == ~E_1~0); 42773#L414-1 assume !(1 == ~E_2~0); 42872#L419-1 assume { :end_inline_reset_delta_events } true; 42873#L565-2 assume !false; 44466#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44305#L331 [2021-11-20 06:41:58,737 INFO L793 eck$LassoCheckResult]: Loop: 44305#L331 assume !false; 44464#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 44460#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 44455#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 44452#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44450#L298 assume 0 != eval_~tmp~0#1; 44448#L298-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 44445#L306 assume !(0 != eval_~tmp_ndt_1~0#1); 44442#L303 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 44312#L320 assume !(0 != eval_~tmp_ndt_2~0#1); 44313#L317 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 44198#L334 assume !(0 != eval_~tmp_ndt_3~0#1); 44305#L331 [2021-11-20 06:41:58,737 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:58,738 INFO L85 PathProgramCache]: Analyzing trace with hash 327016235, now seen corresponding path program 3 times [2021-11-20 06:41:58,738 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:58,738 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2012449249] [2021-11-20 06:41:58,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:58,738 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:58,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:58,744 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:41:58,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:58,753 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:41:58,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:58,753 INFO L85 PathProgramCache]: Analyzing trace with hash 1517048953, now seen corresponding path program 1 times [2021-11-20 06:41:58,753 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:58,754 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [785701610] [2021-11-20 06:41:58,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:58,754 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:58,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:58,757 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:41:58,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:58,760 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:41:58,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 06:41:58,761 INFO L85 PathProgramCache]: Analyzing trace with hash 1586676899, now seen corresponding path program 1 times [2021-11-20 06:41:58,761 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 06:41:58,761 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [540663588] [2021-11-20 06:41:58,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 06:41:58,761 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 06:41:58,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:58,767 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 06:41:58,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 06:41:58,777 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 06:41:59,643 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 20.11 06:41:59 BoogieIcfgContainer [2021-11-20 06:41:59,643 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-11-20 06:41:59,644 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-11-20 06:41:59,644 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-11-20 06:41:59,644 INFO L275 PluginConnector]: Witness Printer initialized [2021-11-20 06:41:59,645 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 06:41:54" (3/4) ... [2021-11-20 06:41:59,647 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-11-20 06:41:59,717 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/bin/uautomizer-DQz5hQGWxF/witness.graphml [2021-11-20 06:41:59,717 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-11-20 06:41:59,718 INFO L158 Benchmark]: Toolchain (without parser) took 6490.32ms. Allocated memory was 86.0MB in the beginning and 213.9MB in the end (delta: 127.9MB). Free memory was 43.1MB in the beginning and 116.6MB in the end (delta: -73.5MB). Peak memory consumption was 57.4MB. Max. memory is 16.1GB. [2021-11-20 06:41:59,719 INFO L158 Benchmark]: CDTParser took 0.26ms. Allocated memory is still 86.0MB. Free memory was 59.5MB in the beginning and 59.4MB in the end (delta: 44.7kB). There was no memory consumed. Max. memory is 16.1GB. [2021-11-20 06:41:59,719 INFO L158 Benchmark]: CACSL2BoogieTranslator took 324.25ms. Allocated memory is still 104.9MB. Free memory was 84.2MB in the beginning and 71.1MB in the end (delta: 13.1MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2021-11-20 06:41:59,720 INFO L158 Benchmark]: Boogie Procedure Inliner took 66.46ms. Allocated memory is still 104.9MB. Free memory was 71.1MB in the beginning and 68.1MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-11-20 06:41:59,720 INFO L158 Benchmark]: Boogie Preprocessor took 91.22ms. Allocated memory is still 104.9MB. Free memory was 68.1MB in the beginning and 65.5MB in the end (delta: 2.5MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-11-20 06:41:59,720 INFO L158 Benchmark]: RCFGBuilder took 893.73ms. Allocated memory is still 104.9MB. Free memory was 65.5MB in the beginning and 60.2MB in the end (delta: 5.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2021-11-20 06:41:59,721 INFO L158 Benchmark]: BuchiAutomizer took 5024.46ms. Allocated memory was 104.9MB in the beginning and 213.9MB in the end (delta: 109.1MB). Free memory was 59.9MB in the beginning and 119.8MB in the end (delta: -59.8MB). Peak memory consumption was 95.1MB. Max. memory is 16.1GB. [2021-11-20 06:41:59,721 INFO L158 Benchmark]: Witness Printer took 73.59ms. Allocated memory is still 213.9MB. Free memory was 119.8MB in the beginning and 116.6MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-11-20 06:41:59,724 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.26ms. Allocated memory is still 86.0MB. Free memory was 59.5MB in the beginning and 59.4MB in the end (delta: 44.7kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 324.25ms. Allocated memory is still 104.9MB. Free memory was 84.2MB in the beginning and 71.1MB in the end (delta: 13.1MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 66.46ms. Allocated memory is still 104.9MB. Free memory was 71.1MB in the beginning and 68.1MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 91.22ms. Allocated memory is still 104.9MB. Free memory was 68.1MB in the beginning and 65.5MB in the end (delta: 2.5MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 893.73ms. Allocated memory is still 104.9MB. Free memory was 65.5MB in the beginning and 60.2MB in the end (delta: 5.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * BuchiAutomizer took 5024.46ms. Allocated memory was 104.9MB in the beginning and 213.9MB in the end (delta: 109.1MB). Free memory was 59.9MB in the beginning and 119.8MB in the end (delta: -59.8MB). Peak memory consumption was 95.1MB. Max. memory is 16.1GB. * Witness Printer took 73.59ms. Allocated memory is still 213.9MB. Free memory was 119.8MB in the beginning and 116.6MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 14 terminating modules (14 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.14 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 4931 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.9s and 15 iterations. TraceHistogramMax:1. Analysis of lassos took 2.5s. Construction of modules took 0.3s. Büchi inclusion checks took 0.5s. Highest rank in rank-based complementation 0. Minimization of det autom 14. Minimization of nondet autom 0. Automata minimization 0.7s AutomataMinimizationTime, 14 MinimizatonAttempts, 4070 StatesRemovedByMinimization, 11 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had 4931 states and ocurred in iteration 14. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 6447 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 6447 mSDsluCounter, 10400 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 5216 mSDsCounter, 126 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 381 IncrementalHoareTripleChecker+Invalid, 507 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 126 mSolverCounterUnsat, 5184 mSDtfsCounter, 381 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc2 concLT0 SILN1 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 293]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, token=0, NULL=1, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6e34ff63=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2acc0b87=0, tmp_ndt_2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3f7cf242=0, E_1=2, __retres1=1, tmp_ndt_1=0, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@75497245=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4f63b0c9=0, m_st=0, NULL=0, __retres1=0, tmp___0=0, m_pc=0, \result=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@257b738d=0, \result=0, \result=0, __retres1=0, tmp___1=0, T2_E=2, tmp=0, t1_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5ae62812=0, E_2=2, tmp___0=0, T1_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5e88cf93=0, __retres1=0, M_E=2, t2_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5d32b035=0, t1_st=0, __retres1=0, local=0, t2_pc=0, E_M=2, kernel_st=1, t1_i=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 293]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int t2_st ; [L30] int m_i ; [L31] int t1_i ; [L32] int t2_i ; [L33] int M_E = 2; [L34] int T1_E = 2; [L35] int T2_E = 2; [L36] int E_M = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L43] int token ; [L45] int local ; [L610] int __retres1 ; [L614] CALL init_model() [L524] m_i = 1 [L525] t1_i = 1 [L526] t2_i = 1 [L614] RET init_model() [L615] CALL start_simulation() [L551] int kernel_st ; [L552] int tmp ; [L553] int tmp___0 ; [L557] kernel_st = 0 [L558] FCALL update_channels() [L559] CALL init_threads() [L243] COND TRUE m_i == 1 [L244] m_st = 0 [L248] COND TRUE t1_i == 1 [L249] t1_st = 0 [L253] COND TRUE t2_i == 1 [L254] t2_st = 0 [L559] RET init_threads() [L560] CALL fire_delta_events() [L356] COND FALSE !(M_E == 0) [L361] COND FALSE !(T1_E == 0) [L366] COND FALSE !(T2_E == 0) [L371] COND FALSE !(E_M == 0) [L376] COND FALSE !(E_1 == 0) [L381] COND FALSE !(E_2 == 0) [L560] RET fire_delta_events() [L561] CALL activate_threads() [L429] int tmp ; [L430] int tmp___0 ; [L431] int tmp___1 ; [L435] CALL, EXPR is_master_triggered() [L175] int __retres1 ; [L178] COND FALSE !(m_pc == 1) [L188] __retres1 = 0 [L190] return (__retres1); [L435] RET, EXPR is_master_triggered() [L435] tmp = is_master_triggered() [L437] COND FALSE !(\read(tmp)) [L443] CALL, EXPR is_transmit1_triggered() [L194] int __retres1 ; [L197] COND FALSE !(t1_pc == 1) [L207] __retres1 = 0 [L209] return (__retres1); [L443] RET, EXPR is_transmit1_triggered() [L443] tmp___0 = is_transmit1_triggered() [L445] COND FALSE !(\read(tmp___0)) [L451] CALL, EXPR is_transmit2_triggered() [L213] int __retres1 ; [L216] COND FALSE !(t2_pc == 1) [L226] __retres1 = 0 [L228] return (__retres1); [L451] RET, EXPR is_transmit2_triggered() [L451] tmp___1 = is_transmit2_triggered() [L453] COND FALSE !(\read(tmp___1)) [L561] RET activate_threads() [L562] CALL reset_delta_events() [L394] COND FALSE !(M_E == 1) [L399] COND FALSE !(T1_E == 1) [L404] COND FALSE !(T2_E == 1) [L409] COND FALSE !(E_M == 1) [L414] COND FALSE !(E_1 == 1) [L419] COND FALSE !(E_2 == 1) [L562] RET reset_delta_events() [L565] COND TRUE 1 [L568] kernel_st = 1 [L569] CALL eval() [L289] int tmp ; Loop: [L293] COND TRUE 1 [L296] CALL, EXPR exists_runnable_thread() [L263] int __retres1 ; [L266] COND TRUE m_st == 0 [L267] __retres1 = 1 [L284] return (__retres1); [L296] RET, EXPR exists_runnable_thread() [L296] tmp = exists_runnable_thread() [L298] COND TRUE \read(tmp) [L303] COND TRUE m_st == 0 [L304] int tmp_ndt_1; [L305] tmp_ndt_1 = __VERIFIER_nondet_int() [L306] COND FALSE !(\read(tmp_ndt_1)) [L317] COND TRUE t1_st == 0 [L318] int tmp_ndt_2; [L319] tmp_ndt_2 = __VERIFIER_nondet_int() [L320] COND FALSE !(\read(tmp_ndt_2)) [L331] COND TRUE t2_st == 0 [L332] int tmp_ndt_3; [L333] tmp_ndt_3 = __VERIFIER_nondet_int() [L334] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-11-20 06:41:59,811 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5c9d2fc5-d109-4554-aaf2-830f60986aeb/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)