./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 53f42b1a Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/bin/uautomizer-DQz5hQGWxF/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/bin/uautomizer-DQz5hQGWxF/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/bin/uautomizer-DQz5hQGWxF/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/bin/uautomizer-DQz5hQGWxF/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.03.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/bin/uautomizer-DQz5hQGWxF/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/bin/uautomizer-DQz5hQGWxF --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-53f42b1 [2021-11-20 07:39:30,018 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-20 07:39:30,022 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-20 07:39:30,082 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-20 07:39:30,083 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-20 07:39:30,084 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-20 07:39:30,086 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-20 07:39:30,090 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-20 07:39:30,093 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-20 07:39:30,095 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-20 07:39:30,096 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-20 07:39:30,098 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-20 07:39:30,099 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-20 07:39:30,101 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-20 07:39:30,108 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-20 07:39:30,111 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-20 07:39:30,117 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-20 07:39:30,126 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-20 07:39:30,128 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-20 07:39:30,134 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-20 07:39:30,143 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-20 07:39:30,144 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-20 07:39:30,146 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-20 07:39:30,149 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-20 07:39:30,154 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-20 07:39:30,161 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-20 07:39:30,162 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-20 07:39:30,163 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-20 07:39:30,165 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-20 07:39:30,167 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-20 07:39:30,168 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-20 07:39:30,169 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-20 07:39:30,172 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-20 07:39:30,174 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-20 07:39:30,176 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-20 07:39:30,176 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-20 07:39:30,177 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-20 07:39:30,177 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-20 07:39:30,178 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-20 07:39:30,179 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-20 07:39:30,180 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-20 07:39:30,181 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/bin/uautomizer-DQz5hQGWxF/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-20 07:39:30,250 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-20 07:39:30,253 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-20 07:39:30,253 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-20 07:39:30,254 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-20 07:39:30,255 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-20 07:39:30,256 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-20 07:39:30,256 INFO L138 SettingsManager]: * Use SBE=true [2021-11-20 07:39:30,256 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-20 07:39:30,257 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-20 07:39:30,257 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-20 07:39:30,258 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-20 07:39:30,259 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-20 07:39:30,259 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-20 07:39:30,259 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-20 07:39:30,259 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-20 07:39:30,260 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-20 07:39:30,260 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-20 07:39:30,260 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-20 07:39:30,260 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-20 07:39:30,261 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-20 07:39:30,261 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-20 07:39:30,261 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-20 07:39:30,262 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-20 07:39:30,262 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-20 07:39:30,262 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-20 07:39:30,262 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-20 07:39:30,264 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-20 07:39:30,264 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-20 07:39:30,265 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-20 07:39:30,265 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-20 07:39:30,265 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-20 07:39:30,266 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-20 07:39:30,268 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-20 07:39:30,268 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/bin/uautomizer-DQz5hQGWxF/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/bin/uautomizer-DQz5hQGWxF Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 [2021-11-20 07:39:30,568 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-20 07:39:30,616 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-20 07:39:30,619 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-20 07:39:30,620 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-20 07:39:30,622 INFO L275 PluginConnector]: CDTParser initialized [2021-11-20 07:39:30,623 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/bin/uautomizer-DQz5hQGWxF/../../sv-benchmarks/c/systemc/transmitter.03.cil.c [2021-11-20 07:39:30,703 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/bin/uautomizer-DQz5hQGWxF/data/315576f99/e3a614d341194c2ebd2fef85624ec995/FLAG15ff3815f [2021-11-20 07:39:31,379 INFO L306 CDTParser]: Found 1 translation units. [2021-11-20 07:39:31,381 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/sv-benchmarks/c/systemc/transmitter.03.cil.c [2021-11-20 07:39:31,394 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/bin/uautomizer-DQz5hQGWxF/data/315576f99/e3a614d341194c2ebd2fef85624ec995/FLAG15ff3815f [2021-11-20 07:39:31,709 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/bin/uautomizer-DQz5hQGWxF/data/315576f99/e3a614d341194c2ebd2fef85624ec995 [2021-11-20 07:39:31,712 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-20 07:39:31,714 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-20 07:39:31,716 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-20 07:39:31,716 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-20 07:39:31,720 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-20 07:39:31,721 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 07:39:31" (1/1) ... [2021-11-20 07:39:31,723 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@262dc0b6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:39:31, skipping insertion in model container [2021-11-20 07:39:31,723 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 07:39:31" (1/1) ... [2021-11-20 07:39:31,732 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-20 07:39:31,766 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-20 07:39:31,973 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/sv-benchmarks/c/systemc/transmitter.03.cil.c[706,719] [2021-11-20 07:39:32,055 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-20 07:39:32,067 INFO L203 MainTranslator]: Completed pre-run [2021-11-20 07:39:32,089 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/sv-benchmarks/c/systemc/transmitter.03.cil.c[706,719] [2021-11-20 07:39:32,172 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-20 07:39:32,207 INFO L208 MainTranslator]: Completed translation [2021-11-20 07:39:32,208 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:39:32 WrapperNode [2021-11-20 07:39:32,208 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-20 07:39:32,210 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-20 07:39:32,210 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-20 07:39:32,210 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-20 07:39:32,219 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:39:32" (1/1) ... [2021-11-20 07:39:32,231 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:39:32" (1/1) ... [2021-11-20 07:39:32,303 INFO L137 Inliner]: procedures = 34, calls = 39, calls flagged for inlining = 34, calls inlined = 56, statements flattened = 733 [2021-11-20 07:39:32,303 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-20 07:39:32,304 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-20 07:39:32,305 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-20 07:39:32,305 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-20 07:39:32,315 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:39:32" (1/1) ... [2021-11-20 07:39:32,316 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:39:32" (1/1) ... [2021-11-20 07:39:32,333 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:39:32" (1/1) ... [2021-11-20 07:39:32,346 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:39:32" (1/1) ... [2021-11-20 07:39:32,360 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:39:32" (1/1) ... [2021-11-20 07:39:32,398 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:39:32" (1/1) ... [2021-11-20 07:39:32,401 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:39:32" (1/1) ... [2021-11-20 07:39:32,407 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-20 07:39:32,416 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-20 07:39:32,416 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-20 07:39:32,416 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-20 07:39:32,420 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:39:32" (1/1) ... [2021-11-20 07:39:32,431 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 07:39:32,444 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 07:39:32,457 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 07:39:32,474 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-20 07:39:32,524 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-11-20 07:39:32,525 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-20 07:39:32,525 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-20 07:39:32,525 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-20 07:39:32,620 INFO L236 CfgBuilder]: Building ICFG [2021-11-20 07:39:32,622 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-11-20 07:39:33,505 INFO L277 CfgBuilder]: Performing block encoding [2021-11-20 07:39:33,527 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-20 07:39:33,530 INFO L301 CfgBuilder]: Removed 7 assume(true) statements. [2021-11-20 07:39:33,535 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 07:39:33 BoogieIcfgContainer [2021-11-20 07:39:33,536 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-20 07:39:33,538 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-20 07:39:33,538 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-20 07:39:33,542 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-20 07:39:33,543 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 07:39:33,544 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 20.11 07:39:31" (1/3) ... [2021-11-20 07:39:33,546 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@68f190d6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 07:39:33, skipping insertion in model container [2021-11-20 07:39:33,546 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 07:39:33,546 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:39:32" (2/3) ... [2021-11-20 07:39:33,547 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@68f190d6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 07:39:33, skipping insertion in model container [2021-11-20 07:39:33,547 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 07:39:33,547 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 07:39:33" (3/3) ... [2021-11-20 07:39:33,549 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.03.cil.c [2021-11-20 07:39:33,618 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-20 07:39:33,618 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-20 07:39:33,619 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-20 07:39:33,619 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-20 07:39:33,619 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-20 07:39:33,619 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-20 07:39:33,620 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-20 07:39:33,620 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-20 07:39:33,666 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 291 states, 290 states have (on average 1.5413793103448277) internal successors, (447), 290 states have internal predecessors, (447), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:33,750 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 234 [2021-11-20 07:39:33,753 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:33,753 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:33,771 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:33,771 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:33,771 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-20 07:39:33,773 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 291 states, 290 states have (on average 1.5413793103448277) internal successors, (447), 290 states have internal predecessors, (447), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:33,792 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 234 [2021-11-20 07:39:33,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:33,792 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:33,804 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:33,804 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:33,815 INFO L791 eck$LassoCheckResult]: Stem: 282#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 193#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 161#L615true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 113#L274true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 169#L281true assume !(1 == ~m_i~0);~m_st~0 := 2; 227#L281-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 34#L286-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 206#L291-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 221#L296-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15#L418true assume !(0 == ~M_E~0); 168#L418-2true assume !(0 == ~T1_E~0); 214#L423-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 224#L428-1true assume !(0 == ~T3_E~0); 211#L433-1true assume !(0 == ~E_1~0); 197#L438-1true assume !(0 == ~E_2~0); 127#L443-1true assume !(0 == ~E_3~0); 123#L448-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92#L197true assume !(1 == ~m_pc~0); 259#L197-2true is_master_triggered_~__retres1~0#1 := 0; 263#L208true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 271#L209true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 233#L510true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7#L510-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 260#L216true assume 1 == ~t1_pc~0; 26#L217true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 118#L227true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 110#L228true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8#L518true assume !(0 != activate_threads_~tmp___0~0#1); 135#L518-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 274#L235true assume !(1 == ~t2_pc~0); 203#L235-2true is_transmit2_triggered_~__retres1~2#1 := 0; 81#L246true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132#L247true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 245#L526true assume !(0 != activate_threads_~tmp___1~0#1); 255#L526-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72#L254true assume 1 == ~t3_pc~0; 19#L255true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 88#L265true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13#L266true activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 111#L534true assume !(0 != activate_threads_~tmp___2~0#1); 77#L534-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3#L461true assume !(1 == ~M_E~0); 35#L461-2true assume !(1 == ~T1_E~0); 222#L466-1true assume !(1 == ~T2_E~0); 267#L471-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 47#L476-1true assume !(1 == ~E_1~0); 272#L481-1true assume !(1 == ~E_2~0); 147#L486-1true assume !(1 == ~E_3~0); 55#L491-1true assume { :end_inline_reset_delta_events } true; 11#L652-2true [2021-11-20 07:39:33,830 INFO L793 eck$LassoCheckResult]: Loop: 11#L652-2true assume !false; 63#L653true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 172#L393true assume false; 264#L408true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 231#L274-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 290#L418-3true assume 0 == ~M_E~0;~M_E~0 := 1; 134#L418-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 155#L423-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 130#L428-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 91#L433-3true assume 0 == ~E_1~0;~E_1~0 := 1; 177#L438-3true assume !(0 == ~E_2~0); 184#L443-3true assume 0 == ~E_3~0;~E_3~0 := 1; 4#L448-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 186#L197-12true assume !(1 == ~m_pc~0); 229#L197-14true is_master_triggered_~__retres1~0#1 := 0; 69#L208-4true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 269#L209-4true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10#L510-12true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 106#L510-14true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68#L216-12true assume 1 == ~t1_pc~0; 284#L217-4true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 103#L227-4true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45#L228-4true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 74#L518-12true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33#L518-14true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 278#L235-12true assume 1 == ~t2_pc~0; 195#L236-4true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 246#L246-4true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 241#L247-4true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 286#L526-12true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 124#L526-14true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 236#L254-12true assume !(1 == ~t3_pc~0); 242#L254-14true is_transmit3_triggered_~__retres1~3#1 := 0; 126#L265-4true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 133#L266-4true activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 108#L534-12true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 148#L534-14true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70#L461-3true assume 1 == ~M_E~0;~M_E~0 := 2; 291#L461-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 139#L466-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 232#L471-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 65#L476-3true assume 1 == ~E_1~0;~E_1~0 := 2; 131#L481-3true assume 1 == ~E_2~0;~E_2~0 := 2; 87#L486-3true assume !(1 == ~E_3~0); 252#L491-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21#L309-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 36#L331-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 49#L332-1true start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 140#L671true assume !(0 == start_simulation_~tmp~3#1); 174#L671-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 292#L309-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 146#L331-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 112#L332-2true stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 219#L626true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 150#L633true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 244#L634true start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 159#L684true assume !(0 != start_simulation_~tmp___0~1#1); 11#L652-2true [2021-11-20 07:39:33,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:33,837 INFO L85 PathProgramCache]: Analyzing trace with hash -1773697160, now seen corresponding path program 1 times [2021-11-20 07:39:33,847 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:33,848 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209532532] [2021-11-20 07:39:33,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:33,849 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:33,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:34,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:34,038 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:34,038 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [209532532] [2021-11-20 07:39:34,039 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [209532532] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:34,039 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:34,040 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:34,042 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1715441693] [2021-11-20 07:39:34,043 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:34,047 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:39:34,048 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:34,049 INFO L85 PathProgramCache]: Analyzing trace with hash -1061159640, now seen corresponding path program 1 times [2021-11-20 07:39:34,049 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:34,049 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [957482158] [2021-11-20 07:39:34,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:34,050 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:34,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:34,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:34,076 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:34,077 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [957482158] [2021-11-20 07:39:34,077 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [957482158] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:34,077 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:34,077 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-20 07:39:34,078 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1533699212] [2021-11-20 07:39:34,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:34,080 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:39:34,081 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:39:34,114 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:39:34,114 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:39:34,118 INFO L87 Difference]: Start difference. First operand has 291 states, 290 states have (on average 1.5413793103448277) internal successors, (447), 290 states have internal predecessors, (447), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:34,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:39:34,190 INFO L93 Difference]: Finished difference Result 290 states and 430 transitions. [2021-11-20 07:39:34,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:39:34,197 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 290 states and 430 transitions. [2021-11-20 07:39:34,203 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2021-11-20 07:39:34,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 290 states to 284 states and 424 transitions. [2021-11-20 07:39:34,213 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 284 [2021-11-20 07:39:34,214 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 284 [2021-11-20 07:39:34,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 424 transitions. [2021-11-20 07:39:34,218 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:39:34,218 INFO L681 BuchiCegarLoop]: Abstraction has 284 states and 424 transitions. [2021-11-20 07:39:34,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 424 transitions. [2021-11-20 07:39:34,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 284. [2021-11-20 07:39:34,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284 states, 284 states have (on average 1.4929577464788732) internal successors, (424), 283 states have internal predecessors, (424), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:34,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 424 transitions. [2021-11-20 07:39:34,270 INFO L704 BuchiCegarLoop]: Abstraction has 284 states and 424 transitions. [2021-11-20 07:39:34,270 INFO L587 BuchiCegarLoop]: Abstraction has 284 states and 424 transitions. [2021-11-20 07:39:34,271 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-20 07:39:34,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 284 states and 424 transitions. [2021-11-20 07:39:34,275 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2021-11-20 07:39:34,295 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:34,296 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:34,298 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:34,298 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:34,299 INFO L791 eck$LassoCheckResult]: Stem: 873#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 840#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 810#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 771#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 772#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 818#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 657#L286-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 658#L291-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 850#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 614#L418 assume !(0 == ~M_E~0); 615#L418-2 assume !(0 == ~T1_E~0); 817#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 853#L428-1 assume !(0 == ~T3_E~0); 851#L433-1 assume !(0 == ~E_1~0); 843#L438-1 assume !(0 == ~E_2~0); 784#L443-1 assume !(0 == ~E_3~0); 779#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 745#L197 assume !(1 == ~m_pc~0); 742#L197-2 is_master_triggered_~__retres1~0#1 := 0; 741#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 868#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 861#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 598#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 599#L216 assume 1 == ~t1_pc~0; 642#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 643#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 768#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 600#L518 assume !(0 != activate_threads_~tmp___0~0#1); 601#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 790#L235 assume !(1 == ~t2_pc~0); 847#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 731#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 732#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 786#L526 assume !(0 != activate_threads_~tmp___1~0#1); 864#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 720#L254 assume 1 == ~t3_pc~0; 624#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 625#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 610#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 611#L534 assume !(0 != activate_threads_~tmp___2~0#1); 726#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 590#L461 assume !(1 == ~M_E~0); 591#L461-2 assume !(1 == ~T1_E~0); 659#L466-1 assume !(1 == ~T2_E~0); 856#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 680#L476-1 assume !(1 == ~E_1~0); 681#L481-1 assume !(1 == ~E_2~0); 803#L486-1 assume !(1 == ~E_3~0); 694#L491-1 assume { :end_inline_reset_delta_events } true; 608#L652-2 [2021-11-20 07:39:34,299 INFO L793 eck$LassoCheckResult]: Loop: 608#L652-2 assume !false; 609#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 707#L393 assume !false; 674#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 675#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 653#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 813#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 697#L346 assume !(0 != eval_~tmp~0#1); 698#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 859#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 860#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 787#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 788#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 785#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 743#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 744#L438-3 assume !(0 == ~E_2~0); 825#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 592#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 593#L197-12 assume !(1 == ~m_pc~0); 833#L197-14 is_master_triggered_~__retres1~0#1 := 0; 714#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 715#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 604#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 605#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 711#L216-12 assume 1 == ~t1_pc~0; 712#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 759#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 676#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 677#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 655#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 656#L235-12 assume !(1 == ~t2_pc~0); 729#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 730#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 862#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 863#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 781#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 782#L254-12 assume 1 == ~t3_pc~0; 633#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 634#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 783#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 763#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 764#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 716#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 717#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 794#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 795#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 708#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 709#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 736#L486-3 assume !(1 == ~E_3~0); 737#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 627#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 628#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 660#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 685#L671 assume !(0 == start_simulation_~tmp~3#1); 613#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 820#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 705#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 769#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 770#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 804#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 805#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 808#L684 assume !(0 != start_simulation_~tmp___0~1#1); 608#L652-2 [2021-11-20 07:39:34,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:34,301 INFO L85 PathProgramCache]: Analyzing trace with hash 1627783798, now seen corresponding path program 1 times [2021-11-20 07:39:34,301 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:34,301 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1875995876] [2021-11-20 07:39:34,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:34,302 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:34,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:34,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:34,352 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:34,352 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1875995876] [2021-11-20 07:39:34,352 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1875995876] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:34,353 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:34,353 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:34,353 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1896741567] [2021-11-20 07:39:34,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:34,354 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:39:34,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:34,355 INFO L85 PathProgramCache]: Analyzing trace with hash 1668488769, now seen corresponding path program 1 times [2021-11-20 07:39:34,356 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:34,356 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1668670462] [2021-11-20 07:39:34,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:34,357 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:34,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:34,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:34,463 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:34,463 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1668670462] [2021-11-20 07:39:34,463 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1668670462] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:34,464 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:34,464 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:34,464 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [299094155] [2021-11-20 07:39:34,464 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:34,465 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:39:34,465 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:39:34,465 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:39:34,466 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:39:34,466 INFO L87 Difference]: Start difference. First operand 284 states and 424 transitions. cyclomatic complexity: 141 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:34,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:39:34,481 INFO L93 Difference]: Finished difference Result 284 states and 423 transitions. [2021-11-20 07:39:34,482 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:39:34,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 284 states and 423 transitions. [2021-11-20 07:39:34,486 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2021-11-20 07:39:34,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 284 states to 284 states and 423 transitions. [2021-11-20 07:39:34,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 284 [2021-11-20 07:39:34,491 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 284 [2021-11-20 07:39:34,492 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 423 transitions. [2021-11-20 07:39:34,494 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:39:34,494 INFO L681 BuchiCegarLoop]: Abstraction has 284 states and 423 transitions. [2021-11-20 07:39:34,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 423 transitions. [2021-11-20 07:39:34,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 284. [2021-11-20 07:39:34,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284 states, 284 states have (on average 1.4894366197183098) internal successors, (423), 283 states have internal predecessors, (423), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:34,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 423 transitions. [2021-11-20 07:39:34,511 INFO L704 BuchiCegarLoop]: Abstraction has 284 states and 423 transitions. [2021-11-20 07:39:34,511 INFO L587 BuchiCegarLoop]: Abstraction has 284 states and 423 transitions. [2021-11-20 07:39:34,511 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-20 07:39:34,511 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 284 states and 423 transitions. [2021-11-20 07:39:34,514 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2021-11-20 07:39:34,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:34,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:34,516 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:34,516 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:34,517 INFO L791 eck$LassoCheckResult]: Stem: 1448#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 1415#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1385#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1346#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1347#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 1393#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1232#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1233#L291-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1425#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1192#L418 assume !(0 == ~M_E~0); 1193#L418-2 assume !(0 == ~T1_E~0); 1392#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1428#L428-1 assume !(0 == ~T3_E~0); 1426#L433-1 assume !(0 == ~E_1~0); 1418#L438-1 assume !(0 == ~E_2~0); 1359#L443-1 assume !(0 == ~E_3~0); 1354#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1320#L197 assume !(1 == ~m_pc~0); 1317#L197-2 is_master_triggered_~__retres1~0#1 := 0; 1316#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1443#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1436#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1173#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1174#L216 assume 1 == ~t1_pc~0; 1217#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1218#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1343#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1175#L518 assume !(0 != activate_threads_~tmp___0~0#1); 1176#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1365#L235 assume !(1 == ~t2_pc~0); 1424#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1306#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1307#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1361#L526 assume !(0 != activate_threads_~tmp___1~0#1); 1439#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1295#L254 assume 1 == ~t3_pc~0; 1199#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1200#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1185#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1186#L534 assume !(0 != activate_threads_~tmp___2~0#1); 1301#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1165#L461 assume !(1 == ~M_E~0); 1166#L461-2 assume !(1 == ~T1_E~0); 1234#L466-1 assume !(1 == ~T2_E~0); 1431#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1255#L476-1 assume !(1 == ~E_1~0); 1256#L481-1 assume !(1 == ~E_2~0); 1378#L486-1 assume !(1 == ~E_3~0); 1271#L491-1 assume { :end_inline_reset_delta_events } true; 1183#L652-2 [2021-11-20 07:39:34,517 INFO L793 eck$LassoCheckResult]: Loop: 1183#L652-2 assume !false; 1184#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1282#L393 assume !false; 1249#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1250#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1228#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1388#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1272#L346 assume !(0 != eval_~tmp~0#1); 1273#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1434#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1435#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1362#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1363#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1360#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1318#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1319#L438-3 assume !(0 == ~E_2~0); 1401#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1167#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1168#L197-12 assume !(1 == ~m_pc~0); 1408#L197-14 is_master_triggered_~__retres1~0#1 := 0; 1289#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1290#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1179#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1180#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1286#L216-12 assume 1 == ~t1_pc~0; 1287#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1334#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1251#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1252#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1230#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1231#L235-12 assume !(1 == ~t2_pc~0); 1304#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 1305#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1437#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1438#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1355#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1356#L254-12 assume 1 == ~t3_pc~0; 1208#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1209#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1358#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1338#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1339#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1291#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1292#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1369#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1370#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1283#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1284#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1311#L486-3 assume !(1 == ~E_3~0); 1312#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1202#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1203#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1235#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1260#L671 assume !(0 == start_simulation_~tmp~3#1); 1188#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1395#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1280#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1344#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1345#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1379#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1380#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1383#L684 assume !(0 != start_simulation_~tmp___0~1#1); 1183#L652-2 [2021-11-20 07:39:34,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:34,518 INFO L85 PathProgramCache]: Analyzing trace with hash -1769790220, now seen corresponding path program 1 times [2021-11-20 07:39:34,518 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:34,519 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1375568675] [2021-11-20 07:39:34,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:34,519 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:34,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:34,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:34,570 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:34,571 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1375568675] [2021-11-20 07:39:34,571 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1375568675] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:34,571 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:34,572 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:34,572 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1615274887] [2021-11-20 07:39:34,573 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:34,573 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:39:34,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:34,575 INFO L85 PathProgramCache]: Analyzing trace with hash 1668488769, now seen corresponding path program 2 times [2021-11-20 07:39:34,576 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:34,576 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791863736] [2021-11-20 07:39:34,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:34,577 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:34,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:34,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:34,680 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:34,680 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1791863736] [2021-11-20 07:39:34,680 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1791863736] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:34,681 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:34,681 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:34,681 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [69515422] [2021-11-20 07:39:34,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:34,681 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:39:34,682 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:39:34,682 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:39:34,682 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:39:34,683 INFO L87 Difference]: Start difference. First operand 284 states and 423 transitions. cyclomatic complexity: 140 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:34,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:39:34,696 INFO L93 Difference]: Finished difference Result 284 states and 422 transitions. [2021-11-20 07:39:34,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:39:34,697 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 284 states and 422 transitions. [2021-11-20 07:39:34,700 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2021-11-20 07:39:34,703 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 284 states to 284 states and 422 transitions. [2021-11-20 07:39:34,703 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 284 [2021-11-20 07:39:34,703 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 284 [2021-11-20 07:39:34,704 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 422 transitions. [2021-11-20 07:39:34,705 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:39:34,705 INFO L681 BuchiCegarLoop]: Abstraction has 284 states and 422 transitions. [2021-11-20 07:39:34,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 422 transitions. [2021-11-20 07:39:34,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 284. [2021-11-20 07:39:34,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284 states, 284 states have (on average 1.4859154929577465) internal successors, (422), 283 states have internal predecessors, (422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:34,716 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 422 transitions. [2021-11-20 07:39:34,716 INFO L704 BuchiCegarLoop]: Abstraction has 284 states and 422 transitions. [2021-11-20 07:39:34,716 INFO L587 BuchiCegarLoop]: Abstraction has 284 states and 422 transitions. [2021-11-20 07:39:34,716 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-20 07:39:34,716 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 284 states and 422 transitions. [2021-11-20 07:39:34,719 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2021-11-20 07:39:34,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:34,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:34,720 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:34,720 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:34,721 INFO L791 eck$LassoCheckResult]: Stem: 2023#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 1990#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1960#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1921#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1922#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 1968#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1807#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1808#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2000#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1769#L418 assume !(0 == ~M_E~0); 1770#L418-2 assume !(0 == ~T1_E~0); 1967#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2003#L428-1 assume !(0 == ~T3_E~0); 2001#L433-1 assume !(0 == ~E_1~0); 1993#L438-1 assume !(0 == ~E_2~0); 1934#L443-1 assume !(0 == ~E_3~0); 1929#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1895#L197 assume !(1 == ~m_pc~0); 1892#L197-2 is_master_triggered_~__retres1~0#1 := 0; 1891#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2019#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2011#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1748#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1749#L216 assume 1 == ~t1_pc~0; 1792#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1793#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1918#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1750#L518 assume !(0 != activate_threads_~tmp___0~0#1); 1751#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1941#L235 assume !(1 == ~t2_pc~0); 1999#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1882#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1883#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1936#L526 assume !(0 != activate_threads_~tmp___1~0#1); 2014#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1873#L254 assume 1 == ~t3_pc~0; 1774#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1775#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1760#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1761#L534 assume !(0 != activate_threads_~tmp___2~0#1); 1876#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1740#L461 assume !(1 == ~M_E~0); 1741#L461-2 assume !(1 == ~T1_E~0); 1809#L466-1 assume !(1 == ~T2_E~0); 2006#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1830#L476-1 assume !(1 == ~E_1~0); 1831#L481-1 assume !(1 == ~E_2~0); 1953#L486-1 assume !(1 == ~E_3~0); 1846#L491-1 assume { :end_inline_reset_delta_events } true; 1758#L652-2 [2021-11-20 07:39:34,721 INFO L793 eck$LassoCheckResult]: Loop: 1758#L652-2 assume !false; 1759#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1857#L393 assume !false; 1824#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1825#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1803#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1963#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1847#L346 assume !(0 != eval_~tmp~0#1); 1848#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2009#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2010#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1937#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1938#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1935#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1893#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1894#L438-3 assume !(0 == ~E_2~0); 1975#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1742#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1743#L197-12 assume 1 == ~m_pc~0; 1984#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1864#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1865#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1754#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1755#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1861#L216-12 assume 1 == ~t1_pc~0; 1862#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1909#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1826#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1827#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1805#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1806#L235-12 assume !(1 == ~t2_pc~0); 1879#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 1880#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2012#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2013#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1930#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1931#L254-12 assume 1 == ~t3_pc~0; 1783#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1784#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1933#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1913#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1914#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1866#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1867#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1944#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1945#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1858#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1859#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1886#L486-3 assume !(1 == ~E_3~0); 1887#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1780#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1781#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1810#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1835#L671 assume !(0 == start_simulation_~tmp~3#1); 1763#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1970#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1855#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1919#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1920#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1954#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1955#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1958#L684 assume !(0 != start_simulation_~tmp___0~1#1); 1758#L652-2 [2021-11-20 07:39:34,721 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:34,722 INFO L85 PathProgramCache]: Analyzing trace with hash -2017936714, now seen corresponding path program 1 times [2021-11-20 07:39:34,722 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:34,722 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [291651502] [2021-11-20 07:39:34,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:34,722 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:34,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:34,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:34,769 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:34,770 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [291651502] [2021-11-20 07:39:34,771 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [291651502] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:34,773 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:34,774 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-20 07:39:34,774 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [377034601] [2021-11-20 07:39:34,774 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:34,774 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:39:34,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:34,775 INFO L85 PathProgramCache]: Analyzing trace with hash -1351375838, now seen corresponding path program 1 times [2021-11-20 07:39:34,775 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:34,775 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [840461311] [2021-11-20 07:39:34,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:34,776 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:34,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:34,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:34,821 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:34,822 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [840461311] [2021-11-20 07:39:34,822 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [840461311] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:34,822 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:34,822 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:34,822 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1145352468] [2021-11-20 07:39:34,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:34,823 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:39:34,823 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:39:34,824 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:39:34,824 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:39:34,824 INFO L87 Difference]: Start difference. First operand 284 states and 422 transitions. cyclomatic complexity: 139 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:34,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:39:34,843 INFO L93 Difference]: Finished difference Result 284 states and 417 transitions. [2021-11-20 07:39:34,843 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:39:34,844 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 284 states and 417 transitions. [2021-11-20 07:39:34,847 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2021-11-20 07:39:34,850 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 284 states to 284 states and 417 transitions. [2021-11-20 07:39:34,850 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 284 [2021-11-20 07:39:34,851 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 284 [2021-11-20 07:39:34,851 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 417 transitions. [2021-11-20 07:39:34,852 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:39:34,852 INFO L681 BuchiCegarLoop]: Abstraction has 284 states and 417 transitions. [2021-11-20 07:39:34,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 417 transitions. [2021-11-20 07:39:34,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 284. [2021-11-20 07:39:34,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284 states, 284 states have (on average 1.4683098591549295) internal successors, (417), 283 states have internal predecessors, (417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:34,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 417 transitions. [2021-11-20 07:39:34,862 INFO L704 BuchiCegarLoop]: Abstraction has 284 states and 417 transitions. [2021-11-20 07:39:34,862 INFO L587 BuchiCegarLoop]: Abstraction has 284 states and 417 transitions. [2021-11-20 07:39:34,863 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-20 07:39:34,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 284 states and 417 transitions. [2021-11-20 07:39:34,865 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2021-11-20 07:39:34,865 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:34,865 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:34,866 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:34,866 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:34,867 INFO L791 eck$LassoCheckResult]: Stem: 2598#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 2565#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2535#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2496#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2497#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 2543#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2382#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2383#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2575#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2344#L418 assume !(0 == ~M_E~0); 2345#L418-2 assume !(0 == ~T1_E~0); 2542#L423-1 assume !(0 == ~T2_E~0); 2578#L428-1 assume !(0 == ~T3_E~0); 2576#L433-1 assume !(0 == ~E_1~0); 2568#L438-1 assume !(0 == ~E_2~0); 2509#L443-1 assume !(0 == ~E_3~0); 2504#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2470#L197 assume !(1 == ~m_pc~0); 2467#L197-2 is_master_triggered_~__retres1~0#1 := 0; 2466#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2593#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2586#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2323#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2324#L216 assume 1 == ~t1_pc~0; 2367#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2368#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2493#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2325#L518 assume !(0 != activate_threads_~tmp___0~0#1); 2326#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2514#L235 assume !(1 == ~t2_pc~0); 2572#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2456#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2457#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2511#L526 assume !(0 != activate_threads_~tmp___1~0#1); 2589#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2445#L254 assume 1 == ~t3_pc~0; 2349#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2350#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2335#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2336#L534 assume !(0 != activate_threads_~tmp___2~0#1); 2451#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2315#L461 assume !(1 == ~M_E~0); 2316#L461-2 assume !(1 == ~T1_E~0); 2384#L466-1 assume !(1 == ~T2_E~0); 2581#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2405#L476-1 assume !(1 == ~E_1~0); 2406#L481-1 assume !(1 == ~E_2~0); 2528#L486-1 assume !(1 == ~E_3~0); 2419#L491-1 assume { :end_inline_reset_delta_events } true; 2331#L652-2 [2021-11-20 07:39:34,867 INFO L793 eck$LassoCheckResult]: Loop: 2331#L652-2 assume !false; 2332#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2429#L393 assume !false; 2399#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2400#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2378#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2538#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2422#L346 assume !(0 != eval_~tmp~0#1); 2423#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2584#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2585#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2512#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2513#L423-3 assume !(0 == ~T2_E~0); 2510#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2468#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2469#L438-3 assume !(0 == ~E_2~0); 2550#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2317#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2318#L197-12 assume !(1 == ~m_pc~0); 2558#L197-14 is_master_triggered_~__retres1~0#1 := 0; 2439#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2440#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2329#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2330#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2436#L216-12 assume 1 == ~t1_pc~0; 2437#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2484#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2401#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2402#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2380#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2381#L235-12 assume !(1 == ~t2_pc~0); 2454#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 2455#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2587#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2588#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2505#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2506#L254-12 assume 1 == ~t3_pc~0; 2358#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2359#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2508#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2488#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2489#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2441#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2442#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2519#L466-3 assume !(1 == ~T2_E~0); 2520#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2433#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2434#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2462#L486-3 assume !(1 == ~E_3~0); 2463#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2355#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2356#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2385#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2410#L671 assume !(0 == start_simulation_~tmp~3#1); 2338#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2545#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2431#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2494#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 2495#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2529#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2530#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 2534#L684 assume !(0 != start_simulation_~tmp___0~1#1); 2331#L652-2 [2021-11-20 07:39:34,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:34,868 INFO L85 PathProgramCache]: Analyzing trace with hash 1247671284, now seen corresponding path program 1 times [2021-11-20 07:39:34,868 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:34,868 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [348787412] [2021-11-20 07:39:34,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:34,868 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:34,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:34,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:34,918 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:34,918 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [348787412] [2021-11-20 07:39:34,918 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [348787412] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:34,919 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:34,919 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-20 07:39:34,919 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1897989431] [2021-11-20 07:39:34,919 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:34,919 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:39:34,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:34,920 INFO L85 PathProgramCache]: Analyzing trace with hash -806736195, now seen corresponding path program 1 times [2021-11-20 07:39:34,920 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:34,921 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1916605665] [2021-11-20 07:39:34,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:34,921 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:34,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:34,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:34,980 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:34,980 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1916605665] [2021-11-20 07:39:34,980 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1916605665] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:34,980 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:34,980 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:34,981 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1871295448] [2021-11-20 07:39:34,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:34,981 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:39:34,981 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:39:34,982 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-20 07:39:34,982 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-20 07:39:34,982 INFO L87 Difference]: Start difference. First operand 284 states and 417 transitions. cyclomatic complexity: 134 Second operand has 5 states, 5 states have (on average 9.8) internal successors, (49), 5 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:35,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:39:35,183 INFO L93 Difference]: Finished difference Result 764 states and 1113 transitions. [2021-11-20 07:39:35,184 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-20 07:39:35,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 764 states and 1113 transitions. [2021-11-20 07:39:35,198 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 648 [2021-11-20 07:39:35,210 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 764 states to 764 states and 1113 transitions. [2021-11-20 07:39:35,210 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 764 [2021-11-20 07:39:35,212 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 764 [2021-11-20 07:39:35,212 INFO L73 IsDeterministic]: Start isDeterministic. Operand 764 states and 1113 transitions. [2021-11-20 07:39:35,214 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:39:35,214 INFO L681 BuchiCegarLoop]: Abstraction has 764 states and 1113 transitions. [2021-11-20 07:39:35,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 764 states and 1113 transitions. [2021-11-20 07:39:35,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 764 to 302. [2021-11-20 07:39:35,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 302 states, 302 states have (on average 1.4403973509933774) internal successors, (435), 301 states have internal predecessors, (435), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:35,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 302 states to 302 states and 435 transitions. [2021-11-20 07:39:35,230 INFO L704 BuchiCegarLoop]: Abstraction has 302 states and 435 transitions. [2021-11-20 07:39:35,230 INFO L587 BuchiCegarLoop]: Abstraction has 302 states and 435 transitions. [2021-11-20 07:39:35,230 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-20 07:39:35,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 302 states and 435 transitions. [2021-11-20 07:39:35,233 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 246 [2021-11-20 07:39:35,233 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:35,233 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:35,237 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:35,237 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:35,238 INFO L791 eck$LassoCheckResult]: Stem: 3677#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 3631#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3599#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3557#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3558#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 3607#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3443#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3444#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3642#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3403#L418 assume !(0 == ~M_E~0); 3404#L418-2 assume !(0 == ~T1_E~0); 3606#L423-1 assume !(0 == ~T2_E~0); 3645#L428-1 assume !(0 == ~T3_E~0); 3643#L433-1 assume !(0 == ~E_1~0); 3634#L438-1 assume !(0 == ~E_2~0); 3571#L443-1 assume !(0 == ~E_3~0); 3566#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3531#L197 assume !(1 == ~m_pc~0); 3528#L197-2 is_master_triggered_~__retres1~0#1 := 0; 3666#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3667#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3653#L510 assume !(0 != activate_threads_~tmp~1#1); 3384#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3385#L216 assume 1 == ~t1_pc~0; 3428#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3429#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3554#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3386#L518 assume !(0 != activate_threads_~tmp___0~0#1); 3387#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3577#L235 assume !(1 == ~t2_pc~0); 3638#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3517#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3518#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3573#L526 assume !(0 != activate_threads_~tmp___1~0#1); 3657#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3506#L254 assume 1 == ~t3_pc~0; 3410#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3411#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3396#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3397#L534 assume !(0 != activate_threads_~tmp___2~0#1); 3512#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3376#L461 assume !(1 == ~M_E~0); 3377#L461-2 assume !(1 == ~T1_E~0); 3445#L466-1 assume !(1 == ~T2_E~0); 3648#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3466#L476-1 assume !(1 == ~E_1~0); 3467#L481-1 assume !(1 == ~E_2~0); 3591#L486-1 assume !(1 == ~E_3~0); 3480#L491-1 assume { :end_inline_reset_delta_events } true; 3394#L652-2 [2021-11-20 07:39:35,241 INFO L793 eck$LassoCheckResult]: Loop: 3394#L652-2 assume !false; 3395#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3493#L393 assume !false; 3460#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3461#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3439#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3602#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3483#L346 assume !(0 != eval_~tmp~0#1); 3484#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3651#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3652#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3574#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3575#L423-3 assume !(0 == ~T2_E~0); 3572#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3529#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3530#L438-3 assume !(0 == ~E_2~0); 3615#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3378#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3379#L197-12 assume !(1 == ~m_pc~0); 3623#L197-14 is_master_triggered_~__retres1~0#1 := 0; 3500#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3501#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3390#L510-12 assume !(0 != activate_threads_~tmp~1#1); 3391#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3497#L216-12 assume 1 == ~t1_pc~0; 3498#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3545#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3462#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3463#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3441#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3442#L235-12 assume 1 == ~t2_pc~0; 3633#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3516#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3655#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3656#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3567#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3568#L254-12 assume 1 == ~t3_pc~0; 3419#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3420#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3570#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3549#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3550#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3502#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3503#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3581#L466-3 assume !(1 == ~T2_E~0); 3582#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3494#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3495#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3522#L486-3 assume !(1 == ~E_3~0); 3523#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3413#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3414#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3446#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3471#L671 assume !(0 == start_simulation_~tmp~3#1); 3399#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3609#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3491#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3555#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 3556#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3592#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3593#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 3597#L684 assume !(0 != start_simulation_~tmp___0~1#1); 3394#L652-2 [2021-11-20 07:39:35,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:35,243 INFO L85 PathProgramCache]: Analyzing trace with hash 738198194, now seen corresponding path program 1 times [2021-11-20 07:39:35,243 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:35,243 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1261473336] [2021-11-20 07:39:35,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:35,244 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:35,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:35,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:35,333 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:35,333 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1261473336] [2021-11-20 07:39:35,333 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1261473336] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:35,333 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:35,334 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:35,334 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1409740470] [2021-11-20 07:39:35,334 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:35,335 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:39:35,335 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:35,335 INFO L85 PathProgramCache]: Analyzing trace with hash 1197449180, now seen corresponding path program 1 times [2021-11-20 07:39:35,336 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:35,336 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [761109034] [2021-11-20 07:39:35,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:35,336 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:35,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:35,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:35,399 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:35,399 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [761109034] [2021-11-20 07:39:35,400 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [761109034] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:35,400 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:35,400 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:35,400 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1862003813] [2021-11-20 07:39:35,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:35,401 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:39:35,401 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:39:35,401 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 07:39:35,402 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 07:39:35,402 INFO L87 Difference]: Start difference. First operand 302 states and 435 transitions. cyclomatic complexity: 134 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:35,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:39:35,542 INFO L93 Difference]: Finished difference Result 716 states and 1012 transitions. [2021-11-20 07:39:35,542 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 07:39:35,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 716 states and 1012 transitions. [2021-11-20 07:39:35,551 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 628 [2021-11-20 07:39:35,558 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 716 states to 716 states and 1012 transitions. [2021-11-20 07:39:35,559 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 716 [2021-11-20 07:39:35,560 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 716 [2021-11-20 07:39:35,560 INFO L73 IsDeterministic]: Start isDeterministic. Operand 716 states and 1012 transitions. [2021-11-20 07:39:35,561 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:39:35,562 INFO L681 BuchiCegarLoop]: Abstraction has 716 states and 1012 transitions. [2021-11-20 07:39:35,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 716 states and 1012 transitions. [2021-11-20 07:39:35,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 716 to 662. [2021-11-20 07:39:35,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 662 states, 662 states have (on average 1.4244712990936557) internal successors, (943), 661 states have internal predecessors, (943), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:35,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 662 states to 662 states and 943 transitions. [2021-11-20 07:39:35,582 INFO L704 BuchiCegarLoop]: Abstraction has 662 states and 943 transitions. [2021-11-20 07:39:35,582 INFO L587 BuchiCegarLoop]: Abstraction has 662 states and 943 transitions. [2021-11-20 07:39:35,582 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-20 07:39:35,583 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 662 states and 943 transitions. [2021-11-20 07:39:35,588 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 606 [2021-11-20 07:39:35,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:35,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:35,590 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:35,590 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:35,590 INFO L791 eck$LassoCheckResult]: Stem: 4717#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 4664#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4632#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4584#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4585#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 4641#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4470#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4471#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4676#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4430#L418 assume !(0 == ~M_E~0); 4431#L418-2 assume !(0 == ~T1_E~0); 4640#L423-1 assume !(0 == ~T2_E~0); 4682#L428-1 assume !(0 == ~T3_E~0); 4680#L433-1 assume !(0 == ~E_1~0); 4668#L438-1 assume !(0 == ~E_2~0); 4601#L443-1 assume !(0 == ~E_3~0); 4595#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4556#L197 assume !(1 == ~m_pc~0); 4557#L197-2 is_master_triggered_~__retres1~0#1 := 0; 4708#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4710#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4689#L510 assume !(0 != activate_threads_~tmp~1#1); 4412#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4413#L216 assume !(1 == ~t1_pc~0); 4466#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4467#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4581#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4414#L518 assume !(0 != activate_threads_~tmp___0~0#1); 4415#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4608#L235 assume !(1 == ~t2_pc~0); 4672#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4546#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4547#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4604#L526 assume !(0 != activate_threads_~tmp___1~0#1); 4698#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4537#L254 assume 1 == ~t3_pc~0; 4438#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4439#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4424#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4425#L534 assume !(0 != activate_threads_~tmp___2~0#1); 4540#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4404#L461 assume !(1 == ~M_E~0); 4405#L461-2 assume !(1 == ~T1_E~0); 4472#L466-1 assume !(1 == ~T2_E~0); 4685#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4493#L476-1 assume !(1 == ~E_1~0); 4494#L481-1 assume !(1 == ~E_2~0); 4624#L486-1 assume !(1 == ~E_3~0); 4507#L491-1 assume { :end_inline_reset_delta_events } true; 4508#L652-2 [2021-11-20 07:39:35,590 INFO L793 eck$LassoCheckResult]: Loop: 4508#L652-2 assume !false; 4988#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4987#L393 assume !false; 4986#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4985#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4981#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4980#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4975#L346 assume !(0 != eval_~tmp~0#1); 4974#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4973#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4972#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4971#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4970#L423-3 assume !(0 == ~T2_E~0); 4969#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4968#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4967#L438-3 assume !(0 == ~E_2~0); 4966#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4965#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4964#L197-12 assume !(1 == ~m_pc~0); 4963#L197-14 is_master_triggered_~__retres1~0#1 := 0; 4962#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4961#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4960#L510-12 assume !(0 != activate_threads_~tmp~1#1); 4959#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4958#L216-12 assume !(1 == ~t1_pc~0); 4956#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 4954#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4952#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4950#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4947#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4945#L235-12 assume !(1 == ~t2_pc~0); 4942#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 4940#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4938#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4936#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4932#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4929#L254-12 assume 1 == ~t3_pc~0; 4925#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4922#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4918#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4915#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4912#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4909#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4907#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4905#L466-3 assume !(1 == ~T2_E~0); 4903#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4884#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4881#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4879#L486-3 assume !(1 == ~E_3~0); 4877#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4859#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4856#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4849#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 4612#L671 assume !(0 == start_simulation_~tmp~3#1); 4613#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4643#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4521#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4582#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 4583#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4625#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4626#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 4697#L684 assume !(0 != start_simulation_~tmp___0~1#1); 4508#L652-2 [2021-11-20 07:39:35,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:35,591 INFO L85 PathProgramCache]: Analyzing trace with hash 1376982673, now seen corresponding path program 1 times [2021-11-20 07:39:35,591 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:35,592 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100031703] [2021-11-20 07:39:35,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:35,592 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:35,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:35,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:35,631 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:35,631 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100031703] [2021-11-20 07:39:35,631 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2100031703] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:35,631 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:35,631 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:35,632 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2077988576] [2021-11-20 07:39:35,632 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:35,632 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:39:35,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:35,633 INFO L85 PathProgramCache]: Analyzing trace with hash -1655222822, now seen corresponding path program 1 times [2021-11-20 07:39:35,633 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:35,633 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1067220847] [2021-11-20 07:39:35,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:35,634 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:35,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:35,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:35,667 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:35,668 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1067220847] [2021-11-20 07:39:35,668 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1067220847] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:35,668 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:35,668 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:35,669 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1316961197] [2021-11-20 07:39:35,669 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:35,669 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:39:35,669 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:39:35,670 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 07:39:35,670 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 07:39:35,670 INFO L87 Difference]: Start difference. First operand 662 states and 943 transitions. cyclomatic complexity: 283 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:35,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:39:35,844 INFO L93 Difference]: Finished difference Result 1809 states and 2533 transitions. [2021-11-20 07:39:35,844 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 07:39:35,847 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1809 states and 2533 transitions. [2021-11-20 07:39:35,871 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1667 [2021-11-20 07:39:35,893 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1809 states to 1809 states and 2533 transitions. [2021-11-20 07:39:35,894 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1809 [2021-11-20 07:39:35,896 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1809 [2021-11-20 07:39:35,897 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1809 states and 2533 transitions. [2021-11-20 07:39:35,900 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:39:35,900 INFO L681 BuchiCegarLoop]: Abstraction has 1809 states and 2533 transitions. [2021-11-20 07:39:35,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1809 states and 2533 transitions. [2021-11-20 07:39:35,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1809 to 1726. [2021-11-20 07:39:35,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1726 states, 1726 states have (on average 1.4078794901506373) internal successors, (2430), 1725 states have internal predecessors, (2430), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:35,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1726 states to 1726 states and 2430 transitions. [2021-11-20 07:39:35,956 INFO L704 BuchiCegarLoop]: Abstraction has 1726 states and 2430 transitions. [2021-11-20 07:39:35,956 INFO L587 BuchiCegarLoop]: Abstraction has 1726 states and 2430 transitions. [2021-11-20 07:39:35,956 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-20 07:39:35,956 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1726 states and 2430 transitions. [2021-11-20 07:39:35,973 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1661 [2021-11-20 07:39:35,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:35,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:35,976 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:35,976 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:35,976 INFO L791 eck$LassoCheckResult]: Stem: 7202#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 7147#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 7114#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7061#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7062#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 7123#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6947#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6948#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7163#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6909#L418 assume !(0 == ~M_E~0); 6910#L418-2 assume !(0 == ~T1_E~0); 7122#L423-1 assume !(0 == ~T2_E~0); 7167#L428-1 assume !(0 == ~T3_E~0); 7165#L433-1 assume !(0 == ~E_1~0); 7150#L438-1 assume !(0 == ~E_2~0); 7080#L443-1 assume !(0 == ~E_3~0); 7074#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7033#L197 assume !(1 == ~m_pc~0); 7034#L197-2 is_master_triggered_~__retres1~0#1 := 0; 7195#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7196#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7176#L510 assume !(0 != activate_threads_~tmp~1#1); 6893#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6894#L216 assume !(1 == ~t1_pc~0); 6943#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6944#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7058#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6895#L518 assume !(0 != activate_threads_~tmp___0~0#1); 6896#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7086#L235 assume !(1 == ~t2_pc~0); 7159#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7022#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7023#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7083#L526 assume !(0 != activate_threads_~tmp___1~0#1); 7183#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7012#L254 assume !(1 == ~t3_pc~0); 6951#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6952#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6905#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6906#L534 assume !(0 != activate_threads_~tmp___2~0#1); 7017#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6885#L461 assume !(1 == ~M_E~0); 6886#L461-2 assume !(1 == ~T1_E~0); 6949#L466-1 assume !(1 == ~T2_E~0); 7170#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6972#L476-1 assume !(1 == ~E_1~0); 6973#L481-1 assume !(1 == ~E_2~0); 7102#L486-1 assume !(1 == ~E_3~0); 6985#L491-1 assume { :end_inline_reset_delta_events } true; 6986#L652-2 [2021-11-20 07:39:35,977 INFO L793 eck$LassoCheckResult]: Loop: 6986#L652-2 assume !false; 8329#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8327#L393 assume !false; 8325#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8323#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8320#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8313#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8314#L346 assume !(0 != eval_~tmp~0#1); 8476#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8473#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8470#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8467#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8464#L423-3 assume !(0 == ~T2_E~0); 8461#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8458#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8455#L438-3 assume !(0 == ~E_2~0); 8452#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8449#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8446#L197-12 assume !(1 == ~m_pc~0); 8443#L197-14 is_master_triggered_~__retres1~0#1 := 0; 8440#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8437#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8434#L510-12 assume !(0 != activate_threads_~tmp~1#1); 8431#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8428#L216-12 assume !(1 == ~t1_pc~0); 8427#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 8426#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8425#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8424#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8423#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8422#L235-12 assume !(1 == ~t2_pc~0); 8419#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 8417#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8415#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8413#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8411#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8409#L254-12 assume !(1 == ~t3_pc~0); 8407#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 8405#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8403#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8401#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8399#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8397#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8395#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8392#L466-3 assume !(1 == ~T2_E~0); 8390#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8388#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8386#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8384#L486-3 assume !(1 == ~E_3~0); 8382#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8378#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8374#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8372#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 8369#L671 assume !(0 == start_simulation_~tmp~3#1); 8367#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8363#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8362#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8360#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 8358#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8356#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8354#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 8352#L684 assume !(0 != start_simulation_~tmp___0~1#1); 6986#L652-2 [2021-11-20 07:39:35,977 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:35,978 INFO L85 PathProgramCache]: Analyzing trace with hash 372621552, now seen corresponding path program 1 times [2021-11-20 07:39:35,978 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:35,979 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100612921] [2021-11-20 07:39:35,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:35,980 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:35,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:36,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:36,046 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:36,047 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100612921] [2021-11-20 07:39:36,047 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2100612921] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:36,049 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:36,050 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:36,050 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1309961673] [2021-11-20 07:39:36,050 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:36,051 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:39:36,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:36,052 INFO L85 PathProgramCache]: Analyzing trace with hash -1016438343, now seen corresponding path program 1 times [2021-11-20 07:39:36,052 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:36,058 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1741322423] [2021-11-20 07:39:36,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:36,064 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:36,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:36,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:36,127 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:36,128 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1741322423] [2021-11-20 07:39:36,130 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1741322423] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:36,134 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:36,134 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:36,135 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [101484265] [2021-11-20 07:39:36,135 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:36,135 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:39:36,136 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:39:36,136 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 07:39:36,136 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 07:39:36,144 INFO L87 Difference]: Start difference. First operand 1726 states and 2430 transitions. cyclomatic complexity: 708 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:36,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:39:36,269 INFO L93 Difference]: Finished difference Result 3793 states and 5275 transitions. [2021-11-20 07:39:36,270 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 07:39:36,273 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3793 states and 5275 transitions. [2021-11-20 07:39:36,324 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3641 [2021-11-20 07:39:36,365 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3793 states to 3793 states and 5275 transitions. [2021-11-20 07:39:36,366 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3793 [2021-11-20 07:39:36,373 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3793 [2021-11-20 07:39:36,373 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3793 states and 5275 transitions. [2021-11-20 07:39:36,381 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:39:36,382 INFO L681 BuchiCegarLoop]: Abstraction has 3793 states and 5275 transitions. [2021-11-20 07:39:36,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3793 states and 5275 transitions. [2021-11-20 07:39:36,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3793 to 3793. [2021-11-20 07:39:36,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3793 states, 3793 states have (on average 1.3907197469021881) internal successors, (5275), 3792 states have internal predecessors, (5275), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:36,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3793 states to 3793 states and 5275 transitions. [2021-11-20 07:39:36,527 INFO L704 BuchiCegarLoop]: Abstraction has 3793 states and 5275 transitions. [2021-11-20 07:39:36,527 INFO L587 BuchiCegarLoop]: Abstraction has 3793 states and 5275 transitions. [2021-11-20 07:39:36,527 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-20 07:39:36,528 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3793 states and 5275 transitions. [2021-11-20 07:39:36,557 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3641 [2021-11-20 07:39:36,558 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:36,558 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:36,559 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:36,559 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:36,560 INFO L791 eck$LassoCheckResult]: Stem: 12777#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 12695#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12658#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12596#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12597#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 12668#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12476#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12477#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12712#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12438#L418 assume !(0 == ~M_E~0); 12439#L418-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12666#L423-1 assume !(0 == ~T2_E~0); 12724#L428-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12725#L433-1 assume !(0 == ~E_1~0); 12817#L438-1 assume !(0 == ~E_2~0); 12816#L443-1 assume !(0 == ~E_3~0); 12815#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12814#L197 assume !(1 == ~m_pc~0); 12813#L197-2 is_master_triggered_~__retres1~0#1 := 0; 12812#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12811#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 12810#L510 assume !(0 != activate_threads_~tmp~1#1); 12809#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12808#L216 assume !(1 == ~t1_pc~0); 12807#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12806#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12805#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12804#L518 assume !(0 != activate_threads_~tmp___0~0#1); 12803#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12802#L235 assume !(1 == ~t2_pc~0); 12801#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12799#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12798#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12797#L526 assume !(0 != activate_threads_~tmp___1~0#1); 12796#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12795#L254 assume !(1 == ~t3_pc~0); 12794#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12793#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12792#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12791#L534 assume !(0 != activate_threads_~tmp___2~0#1); 12790#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12789#L461 assume !(1 == ~M_E~0); 12788#L461-2 assume !(1 == ~T1_E~0); 12787#L466-1 assume !(1 == ~T2_E~0); 12786#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12501#L476-1 assume !(1 == ~E_1~0); 12502#L481-1 assume !(1 == ~E_2~0); 12770#L486-1 assume !(1 == ~E_3~0); 15601#L491-1 assume { :end_inline_reset_delta_events } true; 15598#L652-2 [2021-11-20 07:39:36,560 INFO L793 eck$LassoCheckResult]: Loop: 15598#L652-2 assume !false; 15596#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12601#L393 assume !false; 15595#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 15591#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 15586#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 15584#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15582#L346 assume !(0 != eval_~tmp~0#1); 15583#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16204#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16203#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16202#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12628#L423-3 assume !(0 == ~T2_E~0); 16173#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12625#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16185#L438-3 assume !(0 == ~E_2~0); 16183#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16181#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16174#L197-12 assume !(1 == ~m_pc~0); 16158#L197-14 is_master_triggered_~__retres1~0#1 := 0; 16157#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16156#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16155#L510-12 assume !(0 != activate_threads_~tmp~1#1); 16154#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15796#L216-12 assume !(1 == ~t1_pc~0); 15793#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 15790#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15787#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 15783#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15778#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15774#L235-12 assume !(1 == ~t2_pc~0); 15768#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 15765#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15762#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15759#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15755#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15752#L254-12 assume !(1 == ~t3_pc~0); 15749#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 15745#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15741#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15737#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15732#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15727#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15722#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15717#L466-3 assume !(1 == ~T2_E~0); 15712#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15709#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15705#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15701#L486-3 assume !(1 == ~E_3~0); 15698#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 15658#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 15650#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 15645#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 15639#L671 assume !(0 == start_simulation_~tmp~3#1); 15636#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 15629#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 15625#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 15621#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 15617#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15613#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15610#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 15600#L684 assume !(0 != start_simulation_~tmp___0~1#1); 15598#L652-2 [2021-11-20 07:39:36,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:36,561 INFO L85 PathProgramCache]: Analyzing trace with hash 1558457196, now seen corresponding path program 1 times [2021-11-20 07:39:36,561 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:36,561 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1912622237] [2021-11-20 07:39:36,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:36,562 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:36,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:36,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:36,584 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:36,584 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1912622237] [2021-11-20 07:39:36,584 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1912622237] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:36,584 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:36,585 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-20 07:39:36,585 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879419474] [2021-11-20 07:39:36,585 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:36,585 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:39:36,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:36,586 INFO L85 PathProgramCache]: Analyzing trace with hash -1016438343, now seen corresponding path program 2 times [2021-11-20 07:39:36,586 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:36,587 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111433192] [2021-11-20 07:39:36,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:36,587 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:36,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:36,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:36,615 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:36,615 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2111433192] [2021-11-20 07:39:36,615 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2111433192] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:36,615 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:36,615 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:36,616 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647051318] [2021-11-20 07:39:36,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:36,616 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:39:36,617 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:39:36,617 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:39:36,617 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:39:36,618 INFO L87 Difference]: Start difference. First operand 3793 states and 5275 transitions. cyclomatic complexity: 1490 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:36,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:39:36,673 INFO L93 Difference]: Finished difference Result 3758 states and 5182 transitions. [2021-11-20 07:39:36,674 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:39:36,675 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3758 states and 5182 transitions. [2021-11-20 07:39:36,717 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3641 [2021-11-20 07:39:36,757 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3758 states to 3758 states and 5182 transitions. [2021-11-20 07:39:36,757 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3758 [2021-11-20 07:39:36,764 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3758 [2021-11-20 07:39:36,765 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3758 states and 5182 transitions. [2021-11-20 07:39:36,771 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:39:36,772 INFO L681 BuchiCegarLoop]: Abstraction has 3758 states and 5182 transitions. [2021-11-20 07:39:36,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3758 states and 5182 transitions. [2021-11-20 07:39:36,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3758 to 2078. [2021-11-20 07:39:36,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2078 states, 2078 states have (on average 1.3753609239653513) internal successors, (2858), 2077 states have internal predecessors, (2858), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:36,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2078 states to 2078 states and 2858 transitions. [2021-11-20 07:39:36,838 INFO L704 BuchiCegarLoop]: Abstraction has 2078 states and 2858 transitions. [2021-11-20 07:39:36,838 INFO L587 BuchiCegarLoop]: Abstraction has 2078 states and 2858 transitions. [2021-11-20 07:39:36,838 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-20 07:39:36,838 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2078 states and 2858 transitions. [2021-11-20 07:39:36,854 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1980 [2021-11-20 07:39:36,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:36,854 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:36,857 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:36,857 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:36,857 INFO L791 eck$LassoCheckResult]: Stem: 20350#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 20263#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 20228#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20168#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20169#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 20238#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20034#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20035#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20282#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20000#L418 assume !(0 == ~M_E~0); 20001#L418-2 assume !(0 == ~T1_E~0); 20237#L423-1 assume !(0 == ~T2_E~0); 20288#L428-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20294#L433-1 assume !(0 == ~E_1~0); 20267#L438-1 assume !(0 == ~E_2~0); 20268#L443-1 assume !(0 == ~E_3~0); 20184#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20185#L197 assume !(1 == ~m_pc~0); 20330#L197-2 is_master_triggered_~__retres1~0#1 := 0; 20331#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20337#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 20301#L510 assume !(0 != activate_threads_~tmp~1#1); 20302#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20332#L216 assume !(1 == ~t1_pc~0); 20333#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20178#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20179#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 19982#L518 assume !(0 != activate_threads_~tmp___0~0#1); 19983#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20345#L235 assume !(1 == ~t2_pc~0); 20346#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20118#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20119#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20198#L526 assume !(0 != activate_threads_~tmp___1~0#1); 20367#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20106#L254 assume !(1 == ~t3_pc~0); 20107#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20130#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20131#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20366#L534 assume !(0 != activate_threads_~tmp___2~0#1); 20111#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19972#L461 assume !(1 == ~M_E~0); 19973#L461-2 assume !(1 == ~T1_E~0); 20036#L466-1 assume !(1 == ~T2_E~0); 20293#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20060#L476-1 assume !(1 == ~E_1~0); 20061#L481-1 assume !(1 == ~E_2~0); 20220#L486-1 assume !(1 == ~E_3~0); 20078#L491-1 assume { :end_inline_reset_delta_events } true; 20079#L652-2 [2021-11-20 07:39:36,858 INFO L793 eck$LassoCheckResult]: Loop: 20079#L652-2 assume !false; 21747#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21745#L393 assume !false; 21743#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21741#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21732#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21729#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21725#L346 assume !(0 != eval_~tmp~0#1); 21726#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21872#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21871#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21870#L418-5 assume !(0 == ~T1_E~0); 21869#L423-3 assume !(0 == ~T2_E~0); 21867#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21866#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21865#L438-3 assume !(0 == ~E_2~0); 21864#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21863#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21862#L197-12 assume !(1 == ~m_pc~0); 21861#L197-14 is_master_triggered_~__retres1~0#1 := 0; 21860#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21859#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 21858#L510-12 assume !(0 != activate_threads_~tmp~1#1); 21857#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21856#L216-12 assume !(1 == ~t1_pc~0); 21855#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 21854#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21853#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21852#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21851#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21850#L235-12 assume !(1 == ~t2_pc~0); 21848#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 21847#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21846#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21845#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21844#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21843#L254-12 assume !(1 == ~t3_pc~0); 21842#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 21841#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21840#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21839#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21838#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21837#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21836#L461-5 assume !(1 == ~T1_E~0); 21835#L466-3 assume !(1 == ~T2_E~0); 21833#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21831#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21829#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21827#L486-3 assume !(1 == ~E_3~0); 21825#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21821#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21817#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21815#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 21813#L671 assume !(0 == start_simulation_~tmp~3#1); 21811#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21805#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21803#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21801#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 21799#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21797#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21795#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 21793#L684 assume !(0 != start_simulation_~tmp___0~1#1); 20079#L652-2 [2021-11-20 07:39:36,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:36,859 INFO L85 PathProgramCache]: Analyzing trace with hash -286909970, now seen corresponding path program 1 times [2021-11-20 07:39:36,859 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:36,859 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529186474] [2021-11-20 07:39:36,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:36,860 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:36,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:36,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:36,899 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:36,899 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1529186474] [2021-11-20 07:39:36,900 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1529186474] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:36,900 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:36,900 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:36,900 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [652474164] [2021-11-20 07:39:36,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:36,902 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:39:36,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:36,903 INFO L85 PathProgramCache]: Analyzing trace with hash -439000899, now seen corresponding path program 1 times [2021-11-20 07:39:36,903 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:36,909 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1906029175] [2021-11-20 07:39:36,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:36,910 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:36,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:36,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:36,944 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:36,945 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1906029175] [2021-11-20 07:39:36,945 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1906029175] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:36,945 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:36,945 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:36,945 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2018587881] [2021-11-20 07:39:36,946 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:36,946 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:39:36,946 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:39:36,947 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 07:39:36,947 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 07:39:36,948 INFO L87 Difference]: Start difference. First operand 2078 states and 2858 transitions. cyclomatic complexity: 784 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:36,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:39:36,989 INFO L93 Difference]: Finished difference Result 1726 states and 2372 transitions. [2021-11-20 07:39:36,991 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:39:36,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1726 states and 2372 transitions. [2021-11-20 07:39:37,007 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1661 [2021-11-20 07:39:37,024 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1726 states to 1726 states and 2372 transitions. [2021-11-20 07:39:37,025 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1726 [2021-11-20 07:39:37,027 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1726 [2021-11-20 07:39:37,027 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1726 states and 2372 transitions. [2021-11-20 07:39:37,030 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:39:37,031 INFO L681 BuchiCegarLoop]: Abstraction has 1726 states and 2372 transitions. [2021-11-20 07:39:37,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1726 states and 2372 transitions. [2021-11-20 07:39:37,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1726 to 1726. [2021-11-20 07:39:37,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1726 states, 1726 states have (on average 1.3742757821552722) internal successors, (2372), 1725 states have internal predecessors, (2372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:37,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1726 states to 1726 states and 2372 transitions. [2021-11-20 07:39:37,150 INFO L704 BuchiCegarLoop]: Abstraction has 1726 states and 2372 transitions. [2021-11-20 07:39:37,150 INFO L587 BuchiCegarLoop]: Abstraction has 1726 states and 2372 transitions. [2021-11-20 07:39:37,150 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-20 07:39:37,150 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1726 states and 2372 transitions. [2021-11-20 07:39:37,160 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1661 [2021-11-20 07:39:37,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:37,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:37,161 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:37,162 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:37,162 INFO L791 eck$LassoCheckResult]: Stem: 24109#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 24052#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 24017#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23962#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23963#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 24027#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23848#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23849#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24066#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23810#L418 assume !(0 == ~M_E~0); 23811#L418-2 assume !(0 == ~T1_E~0); 24026#L423-1 assume !(0 == ~T2_E~0); 24072#L428-1 assume !(0 == ~T3_E~0); 24070#L433-1 assume !(0 == ~E_1~0); 24055#L438-1 assume !(0 == ~E_2~0); 23980#L443-1 assume !(0 == ~E_3~0); 23974#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23935#L197 assume !(1 == ~m_pc~0); 23936#L197-2 is_master_triggered_~__retres1~0#1 := 0; 24101#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24102#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 24081#L510 assume !(0 != activate_threads_~tmp~1#1); 23794#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23795#L216 assume !(1 == ~t1_pc~0); 23844#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23845#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23959#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 23796#L518 assume !(0 != activate_threads_~tmp___0~0#1); 23797#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23988#L235 assume !(1 == ~t2_pc~0); 24062#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23922#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23923#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 23985#L526 assume !(0 != activate_threads_~tmp___1~0#1); 24090#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23912#L254 assume !(1 == ~t3_pc~0); 23852#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23853#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23806#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23807#L534 assume !(0 != activate_threads_~tmp___2~0#1); 23917#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23786#L461 assume !(1 == ~M_E~0); 23787#L461-2 assume !(1 == ~T1_E~0); 23850#L466-1 assume !(1 == ~T2_E~0); 24075#L471-1 assume !(1 == ~T3_E~0); 23873#L476-1 assume !(1 == ~E_1~0); 23874#L481-1 assume !(1 == ~E_2~0); 24004#L486-1 assume !(1 == ~E_3~0); 23886#L491-1 assume { :end_inline_reset_delta_events } true; 23887#L652-2 [2021-11-20 07:39:37,162 INFO L793 eck$LassoCheckResult]: Loop: 23887#L652-2 assume !false; 25303#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23966#L393 assume !false; 25293#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 25289#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 24021#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 24022#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23890#L346 assume !(0 != eval_~tmp~0#1); 23891#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24079#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24080#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23986#L418-5 assume !(0 == ~T1_E~0); 23987#L423-3 assume !(0 == ~T2_E~0); 23984#L428-3 assume !(0 == ~T3_E~0); 23933#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23934#L438-3 assume !(0 == ~E_2~0); 24035#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23788#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23789#L197-12 assume !(1 == ~m_pc~0); 24042#L197-14 is_master_triggered_~__retres1~0#1 := 0; 23906#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23907#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 23800#L510-12 assume !(0 != activate_threads_~tmp~1#1); 23801#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23904#L216-12 assume !(1 == ~t1_pc~0); 23905#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 23950#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23869#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 23870#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23846#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23847#L235-12 assume !(1 == ~t2_pc~0); 23920#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 23921#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24087#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 24088#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23975#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23976#L254-12 assume !(1 == ~t3_pc~0); 24082#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 23978#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23979#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23954#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23955#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24005#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25428#L461-5 assume !(1 == ~T1_E~0); 25426#L466-3 assume !(1 == ~T2_E~0); 25424#L471-3 assume !(1 == ~T3_E~0); 25422#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25420#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25418#L486-3 assume !(1 == ~E_3~0); 25416#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 25412#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 25408#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 25406#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 25379#L671 assume !(0 == start_simulation_~tmp~3#1); 25376#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 25345#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 25340#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 25334#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 25329#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25320#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25315#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 25310#L684 assume !(0 != start_simulation_~tmp___0~1#1); 23887#L652-2 [2021-11-20 07:39:37,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:37,163 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 1 times [2021-11-20 07:39:37,163 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:37,163 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881632348] [2021-11-20 07:39:37,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:37,164 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:37,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:37,180 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 07:39:37,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:37,232 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 07:39:37,233 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:37,233 INFO L85 PathProgramCache]: Analyzing trace with hash -2042867519, now seen corresponding path program 1 times [2021-11-20 07:39:37,233 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:37,234 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [908193155] [2021-11-20 07:39:37,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:37,234 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:37,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:37,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:37,277 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:37,278 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [908193155] [2021-11-20 07:39:37,278 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [908193155] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:37,278 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:37,278 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:37,278 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1063745120] [2021-11-20 07:39:37,279 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:37,279 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:39:37,279 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:39:37,280 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:39:37,280 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:39:37,281 INFO L87 Difference]: Start difference. First operand 1726 states and 2372 transitions. cyclomatic complexity: 650 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:37,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:39:37,350 INFO L93 Difference]: Finished difference Result 2471 states and 3374 transitions. [2021-11-20 07:39:37,351 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:39:37,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2471 states and 3374 transitions. [2021-11-20 07:39:37,372 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2373 [2021-11-20 07:39:37,406 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2471 states to 2471 states and 3374 transitions. [2021-11-20 07:39:37,406 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2471 [2021-11-20 07:39:37,409 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2471 [2021-11-20 07:39:37,410 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2471 states and 3374 transitions. [2021-11-20 07:39:37,414 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:39:37,414 INFO L681 BuchiCegarLoop]: Abstraction has 2471 states and 3374 transitions. [2021-11-20 07:39:37,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2471 states and 3374 transitions. [2021-11-20 07:39:37,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2471 to 2467. [2021-11-20 07:39:37,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2467 states, 2467 states have (on average 1.3660316173490068) internal successors, (3370), 2466 states have internal predecessors, (3370), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:37,469 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2467 states to 2467 states and 3370 transitions. [2021-11-20 07:39:37,469 INFO L704 BuchiCegarLoop]: Abstraction has 2467 states and 3370 transitions. [2021-11-20 07:39:37,470 INFO L587 BuchiCegarLoop]: Abstraction has 2467 states and 3370 transitions. [2021-11-20 07:39:37,470 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-20 07:39:37,470 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2467 states and 3370 transitions. [2021-11-20 07:39:37,484 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2369 [2021-11-20 07:39:37,484 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:37,484 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:37,485 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:37,486 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:37,486 INFO L791 eck$LassoCheckResult]: Stem: 28344#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 28266#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 28229#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28172#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28173#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 28239#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28050#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28051#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28281#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28013#L418 assume !(0 == ~M_E~0); 28014#L418-2 assume !(0 == ~T1_E~0); 28238#L423-1 assume !(0 == ~T2_E~0); 28285#L428-1 assume !(0 == ~T3_E~0); 28283#L433-1 assume !(0 == ~E_1~0); 28269#L438-1 assume !(0 == ~E_2~0); 28191#L443-1 assume 0 == ~E_3~0;~E_3~0 := 1; 28184#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28185#L197 assume !(1 == ~m_pc~0); 28322#L197-2 is_master_triggered_~__retres1~0#1 := 0; 28323#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28333#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28334#L510 assume !(0 != activate_threads_~tmp~1#1); 27997#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27998#L216 assume !(1 == ~t1_pc~0); 28046#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28047#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28168#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28169#L518 assume !(0 != activate_threads_~tmp___0~0#1); 28199#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28200#L235 assume !(1 == ~t2_pc~0); 28276#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28277#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28366#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28360#L526 assume !(0 != activate_threads_~tmp___1~0#1); 28359#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28116#L254 assume !(1 == ~t3_pc~0); 28055#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 28056#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28009#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28010#L534 assume !(0 != activate_threads_~tmp___2~0#1); 28122#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27989#L461 assume !(1 == ~M_E~0); 27990#L461-2 assume !(1 == ~T1_E~0); 28052#L466-1 assume !(1 == ~T2_E~0); 28288#L471-1 assume !(1 == ~T3_E~0); 28076#L476-1 assume !(1 == ~E_1~0); 28077#L481-1 assume !(1 == ~E_2~0); 28216#L486-1 assume 1 == ~E_3~0;~E_3~0 := 2; 28090#L491-1 assume { :end_inline_reset_delta_events } true; 28005#L652-2 [2021-11-20 07:39:37,486 INFO L793 eck$LassoCheckResult]: Loop: 28005#L652-2 assume !false; 28006#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28101#L393 assume !false; 28070#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28071#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 28044#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 30206#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28093#L346 assume !(0 != eval_~tmp~0#1); 28094#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30374#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30362#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30360#L418-5 assume !(0 == ~T1_E~0); 30357#L423-3 assume !(0 == ~T2_E~0); 28194#L428-3 assume !(0 == ~T3_E~0); 28195#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28246#L438-3 assume !(0 == ~E_2~0); 28247#L443-3 assume !(0 == ~E_3~0); 27991#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27992#L197-12 assume !(1 == ~m_pc~0); 28257#L197-14 is_master_triggered_~__retres1~0#1 := 0; 28110#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28111#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28003#L510-12 assume !(0 != activate_threads_~tmp~1#1); 28004#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28108#L216-12 assume !(1 == ~t1_pc~0); 28109#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 28159#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28072#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28073#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28048#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28049#L235-12 assume 1 == ~t2_pc~0; 28268#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28127#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28305#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28306#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28348#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28298#L254-12 assume !(1 == ~t3_pc~0); 28299#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 28189#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28190#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28163#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28164#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28112#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28113#L461-5 assume !(1 == ~T1_E~0); 28205#L466-3 assume !(1 == ~T2_E~0); 28206#L471-3 assume !(1 == ~T3_E~0); 28295#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30353#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30350#L486-3 assume !(1 == ~E_3~0); 28140#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28315#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 28053#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28054#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 28080#L671 assume !(0 == start_simulation_~tmp~3#1); 28012#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28241#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 28103#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28170#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 28171#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28219#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28220#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 28228#L684 assume !(0 != start_simulation_~tmp___0~1#1); 28005#L652-2 [2021-11-20 07:39:37,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:37,487 INFO L85 PathProgramCache]: Analyzing trace with hash -1676515466, now seen corresponding path program 1 times [2021-11-20 07:39:37,487 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:37,487 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1938455190] [2021-11-20 07:39:37,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:37,488 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:37,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:37,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:37,526 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:37,526 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1938455190] [2021-11-20 07:39:37,526 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1938455190] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:37,526 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:37,527 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:37,527 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [222427315] [2021-11-20 07:39:37,527 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:37,527 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:39:37,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:37,528 INFO L85 PathProgramCache]: Analyzing trace with hash -1033569440, now seen corresponding path program 1 times [2021-11-20 07:39:37,528 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:37,528 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1281974591] [2021-11-20 07:39:37,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:37,531 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:37,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:37,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:37,574 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:37,574 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1281974591] [2021-11-20 07:39:37,574 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1281974591] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:37,575 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:37,575 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-20 07:39:37,575 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1025533868] [2021-11-20 07:39:37,575 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:37,576 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:39:37,576 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:39:37,576 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 07:39:37,577 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 07:39:37,577 INFO L87 Difference]: Start difference. First operand 2467 states and 3370 transitions. cyclomatic complexity: 907 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:37,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:39:37,715 INFO L93 Difference]: Finished difference Result 4256 states and 5869 transitions. [2021-11-20 07:39:37,716 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 07:39:37,717 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4256 states and 5869 transitions. [2021-11-20 07:39:37,750 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 3936 [2021-11-20 07:39:37,795 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4256 states to 4256 states and 5869 transitions. [2021-11-20 07:39:37,796 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4256 [2021-11-20 07:39:37,802 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4256 [2021-11-20 07:39:37,802 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4256 states and 5869 transitions. [2021-11-20 07:39:37,809 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:39:37,810 INFO L681 BuchiCegarLoop]: Abstraction has 4256 states and 5869 transitions. [2021-11-20 07:39:37,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4256 states and 5869 transitions. [2021-11-20 07:39:37,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4256 to 2279. [2021-11-20 07:39:37,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2279 states, 2279 states have (on average 1.3712154453707766) internal successors, (3125), 2278 states have internal predecessors, (3125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:37,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2279 states to 2279 states and 3125 transitions. [2021-11-20 07:39:37,888 INFO L704 BuchiCegarLoop]: Abstraction has 2279 states and 3125 transitions. [2021-11-20 07:39:37,889 INFO L587 BuchiCegarLoop]: Abstraction has 2279 states and 3125 transitions. [2021-11-20 07:39:37,889 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-20 07:39:37,889 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2279 states and 3125 transitions. [2021-11-20 07:39:37,902 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2214 [2021-11-20 07:39:37,902 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:37,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:37,908 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:37,908 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:37,908 INFO L791 eck$LassoCheckResult]: Stem: 35062#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 35003#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 34967#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34913#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34914#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 34976#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34785#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34786#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35017#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34752#L418 assume !(0 == ~M_E~0); 34753#L418-2 assume !(0 == ~T1_E~0); 34975#L423-1 assume !(0 == ~T2_E~0); 35023#L428-1 assume !(0 == ~T3_E~0); 35021#L433-1 assume !(0 == ~E_1~0); 35006#L438-1 assume !(0 == ~E_2~0); 34931#L443-1 assume !(0 == ~E_3~0); 34924#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34884#L197 assume !(1 == ~m_pc~0); 34885#L197-2 is_master_triggered_~__retres1~0#1 := 0; 35051#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35054#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 35032#L510 assume !(0 != activate_threads_~tmp~1#1); 34732#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34733#L216 assume !(1 == ~t1_pc~0); 34783#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34784#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34910#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 34734#L518 assume !(0 != activate_threads_~tmp___0~0#1); 34735#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34939#L235 assume !(1 == ~t2_pc~0); 35013#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34873#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34874#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 34933#L526 assume !(0 != activate_threads_~tmp___1~0#1); 35040#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34862#L254 assume !(1 == ~t3_pc~0); 34790#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34791#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34744#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34745#L534 assume !(0 != activate_threads_~tmp___2~0#1); 34867#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34724#L461 assume !(1 == ~M_E~0); 34725#L461-2 assume !(1 == ~T1_E~0); 34787#L466-1 assume !(1 == ~T2_E~0); 35026#L471-1 assume !(1 == ~T3_E~0); 34812#L476-1 assume !(1 == ~E_1~0); 34813#L481-1 assume !(1 == ~E_2~0); 34955#L486-1 assume !(1 == ~E_3~0); 34828#L491-1 assume { :end_inline_reset_delta_events } true; 34829#L652-2 [2021-11-20 07:39:37,909 INFO L793 eck$LassoCheckResult]: Loop: 34829#L652-2 assume !false; 34844#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34845#L393 assume !false; 34806#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 34807#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 34779#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 34971#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34830#L346 assume !(0 != eval_~tmp~0#1); 34832#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37000#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36999#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36998#L418-5 assume !(0 == ~T1_E~0); 36997#L423-3 assume !(0 == ~T2_E~0); 36996#L428-3 assume !(0 == ~T3_E~0); 36995#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36994#L438-3 assume !(0 == ~E_2~0); 36993#L443-3 assume !(0 == ~E_3~0); 36992#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36991#L197-12 assume !(1 == ~m_pc~0); 36989#L197-14 is_master_triggered_~__retres1~0#1 := 0; 36987#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36985#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 36983#L510-12 assume !(0 != activate_threads_~tmp~1#1); 36981#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36980#L216-12 assume !(1 == ~t1_pc~0); 36978#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 36976#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36975#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 36974#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36901#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36898#L235-12 assume !(1 == ~t2_pc~0); 36893#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 36891#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36888#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 36884#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36880#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36876#L254-12 assume !(1 == ~t3_pc~0); 36870#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 34928#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34929#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34905#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34906#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34956#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36859#L461-5 assume !(1 == ~T1_E~0); 36858#L466-3 assume !(1 == ~T2_E~0); 36853#L471-3 assume !(1 == ~T3_E~0); 36852#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36851#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36850#L486-3 assume !(1 == ~E_3~0); 36849#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 36847#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 34788#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 34789#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 34816#L671 assume !(0 == start_simulation_~tmp~3#1); 36603#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 36472#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 36470#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 36468#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 36466#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 36464#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36462#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 36460#L684 assume !(0 != start_simulation_~tmp___0~1#1); 34829#L652-2 [2021-11-20 07:39:37,911 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:37,912 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 2 times [2021-11-20 07:39:37,912 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:37,912 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [382681392] [2021-11-20 07:39:37,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:37,912 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:37,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:37,923 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 07:39:37,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:37,955 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 07:39:37,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:37,956 INFO L85 PathProgramCache]: Analyzing trace with hash -114594817, now seen corresponding path program 1 times [2021-11-20 07:39:37,957 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:37,957 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1102627324] [2021-11-20 07:39:37,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:37,957 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:37,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:37,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:38,000 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:38,000 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1102627324] [2021-11-20 07:39:38,000 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1102627324] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:38,000 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:38,001 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-20 07:39:38,001 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [209400529] [2021-11-20 07:39:38,001 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:38,001 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:39:38,002 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:39:38,002 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-20 07:39:38,002 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-20 07:39:38,002 INFO L87 Difference]: Start difference. First operand 2279 states and 3125 transitions. cyclomatic complexity: 850 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:38,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:39:38,116 INFO L93 Difference]: Finished difference Result 3900 states and 5296 transitions. [2021-11-20 07:39:38,117 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-11-20 07:39:38,118 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3900 states and 5296 transitions. [2021-11-20 07:39:38,189 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3820 [2021-11-20 07:39:38,217 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3900 states to 3900 states and 5296 transitions. [2021-11-20 07:39:38,217 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3900 [2021-11-20 07:39:38,223 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3900 [2021-11-20 07:39:38,223 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3900 states and 5296 transitions. [2021-11-20 07:39:38,230 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:39:38,231 INFO L681 BuchiCegarLoop]: Abstraction has 3900 states and 5296 transitions. [2021-11-20 07:39:38,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3900 states and 5296 transitions. [2021-11-20 07:39:38,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3900 to 2318. [2021-11-20 07:39:38,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2318 states, 2318 states have (on average 1.364969801553063) internal successors, (3164), 2317 states have internal predecessors, (3164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:38,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2318 states to 2318 states and 3164 transitions. [2021-11-20 07:39:38,308 INFO L704 BuchiCegarLoop]: Abstraction has 2318 states and 3164 transitions. [2021-11-20 07:39:38,309 INFO L587 BuchiCegarLoop]: Abstraction has 2318 states and 3164 transitions. [2021-11-20 07:39:38,309 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-20 07:39:38,309 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2318 states and 3164 transitions. [2021-11-20 07:39:38,323 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2253 [2021-11-20 07:39:38,323 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:38,323 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:38,325 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:38,325 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:38,325 INFO L791 eck$LassoCheckResult]: Stem: 41269#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 41199#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 41158#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41101#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41102#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 41168#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40981#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40982#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41213#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40943#L418 assume !(0 == ~M_E~0); 40944#L418-2 assume !(0 == ~T1_E~0); 41167#L423-1 assume !(0 == ~T2_E~0); 41221#L428-1 assume !(0 == ~T3_E~0); 41219#L433-1 assume !(0 == ~E_1~0); 41202#L438-1 assume !(0 == ~E_2~0); 41118#L443-1 assume !(0 == ~E_3~0); 41112#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41069#L197 assume !(1 == ~m_pc~0); 41070#L197-2 is_master_triggered_~__retres1~0#1 := 0; 41253#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41254#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 41233#L510 assume !(0 != activate_threads_~tmp~1#1); 40927#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40928#L216 assume !(1 == ~t1_pc~0); 40977#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40978#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41098#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 40929#L518 assume !(0 != activate_threads_~tmp___0~0#1); 40930#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41126#L235 assume !(1 == ~t2_pc~0); 41209#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41057#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41058#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 41123#L526 assume !(0 != activate_threads_~tmp___1~0#1); 41242#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41045#L254 assume !(1 == ~t3_pc~0); 40985#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40986#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40939#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 40940#L534 assume !(0 != activate_threads_~tmp___2~0#1); 41052#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40919#L461 assume !(1 == ~M_E~0); 40920#L461-2 assume !(1 == ~T1_E~0); 40983#L466-1 assume !(1 == ~T2_E~0); 41225#L471-1 assume !(1 == ~T3_E~0); 41006#L476-1 assume !(1 == ~E_1~0); 41007#L481-1 assume !(1 == ~E_2~0); 41143#L486-1 assume !(1 == ~E_3~0); 41019#L491-1 assume { :end_inline_reset_delta_events } true; 41020#L652-2 [2021-11-20 07:39:38,326 INFO L793 eck$LassoCheckResult]: Loop: 41020#L652-2 assume !false; 43047#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43046#L393 assume !false; 43045#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 43044#L309 assume !(0 == ~m_st~0); 43040#L313 assume !(0 == ~t1_st~0); 43041#L317 assume !(0 == ~t2_st~0); 43042#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 43043#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 43025#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 43026#L346 assume !(0 != eval_~tmp~0#1); 43036#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43126#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43125#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 43124#L418-5 assume !(0 == ~T1_E~0); 43123#L423-3 assume !(0 == ~T2_E~0); 43122#L428-3 assume !(0 == ~T3_E~0); 43121#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43120#L438-3 assume !(0 == ~E_2~0); 43119#L443-3 assume !(0 == ~E_3~0); 43118#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43117#L197-12 assume !(1 == ~m_pc~0); 43116#L197-14 is_master_triggered_~__retres1~0#1 := 0; 43115#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43114#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 43113#L510-12 assume !(0 != activate_threads_~tmp~1#1); 43112#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43111#L216-12 assume !(1 == ~t1_pc~0); 43110#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 43109#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43108#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 43107#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43106#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43105#L235-12 assume 1 == ~t2_pc~0; 43104#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43102#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43101#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 43100#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43099#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43098#L254-12 assume !(1 == ~t3_pc~0); 43097#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 43096#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43095#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 43094#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43093#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43092#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43091#L461-5 assume !(1 == ~T1_E~0); 43090#L466-3 assume !(1 == ~T2_E~0); 43089#L471-3 assume !(1 == ~T3_E~0); 43088#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 43087#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 43086#L486-3 assume !(1 == ~E_3~0); 43085#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 43083#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 43080#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 43078#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 43075#L671 assume !(0 == start_simulation_~tmp~3#1); 43071#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 43067#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 43064#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 43062#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 43059#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43058#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43056#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 43054#L684 assume !(0 != start_simulation_~tmp___0~1#1); 41020#L652-2 [2021-11-20 07:39:38,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:38,327 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 3 times [2021-11-20 07:39:38,327 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:38,328 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1520129687] [2021-11-20 07:39:38,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:38,328 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:38,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:38,339 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 07:39:38,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:38,373 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 07:39:38,376 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:38,376 INFO L85 PathProgramCache]: Analyzing trace with hash -1263888806, now seen corresponding path program 1 times [2021-11-20 07:39:38,377 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:38,377 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [68813993] [2021-11-20 07:39:38,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:38,378 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:38,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:38,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:38,409 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:38,409 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [68813993] [2021-11-20 07:39:38,410 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [68813993] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:38,410 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:38,410 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:38,410 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1790689596] [2021-11-20 07:39:38,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:38,412 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 07:39:38,412 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:39:38,412 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:39:38,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:39:38,413 INFO L87 Difference]: Start difference. First operand 2318 states and 3164 transitions. cyclomatic complexity: 850 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:38,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:39:38,487 INFO L93 Difference]: Finished difference Result 3602 states and 4851 transitions. [2021-11-20 07:39:38,488 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:39:38,489 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3602 states and 4851 transitions. [2021-11-20 07:39:38,519 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3535 [2021-11-20 07:39:38,556 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3602 states to 3602 states and 4851 transitions. [2021-11-20 07:39:38,556 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3602 [2021-11-20 07:39:38,561 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3602 [2021-11-20 07:39:38,561 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3602 states and 4851 transitions. [2021-11-20 07:39:38,569 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:39:38,569 INFO L681 BuchiCegarLoop]: Abstraction has 3602 states and 4851 transitions. [2021-11-20 07:39:38,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3602 states and 4851 transitions. [2021-11-20 07:39:38,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3602 to 3416. [2021-11-20 07:39:38,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3416 states, 3416 states have (on average 1.349824355971897) internal successors, (4611), 3415 states have internal predecessors, (4611), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:38,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3416 states to 3416 states and 4611 transitions. [2021-11-20 07:39:38,672 INFO L704 BuchiCegarLoop]: Abstraction has 3416 states and 4611 transitions. [2021-11-20 07:39:38,672 INFO L587 BuchiCegarLoop]: Abstraction has 3416 states and 4611 transitions. [2021-11-20 07:39:38,672 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-20 07:39:38,672 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3416 states and 4611 transitions. [2021-11-20 07:39:38,694 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3349 [2021-11-20 07:39:38,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:38,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:38,695 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:38,696 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:38,696 INFO L791 eck$LassoCheckResult]: Stem: 47194#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 47129#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 47092#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47033#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47034#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 47102#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46906#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46907#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47145#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46869#L418 assume !(0 == ~M_E~0); 46870#L418-2 assume !(0 == ~T1_E~0); 47101#L423-1 assume !(0 == ~T2_E~0); 47153#L428-1 assume !(0 == ~T3_E~0); 47151#L433-1 assume !(0 == ~E_1~0); 47133#L438-1 assume !(0 == ~E_2~0); 47051#L443-1 assume !(0 == ~E_3~0); 47046#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47002#L197 assume !(1 == ~m_pc~0); 47003#L197-2 is_master_triggered_~__retres1~0#1 := 0; 47184#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47185#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 47165#L510 assume !(0 != activate_threads_~tmp~1#1); 46853#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46854#L216 assume !(1 == ~t1_pc~0); 46902#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46903#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47030#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 46855#L518 assume !(0 != activate_threads_~tmp___0~0#1); 46856#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47058#L235 assume !(1 == ~t2_pc~0); 47141#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46990#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46991#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 47055#L526 assume !(0 != activate_threads_~tmp___1~0#1); 47174#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46978#L254 assume !(1 == ~t3_pc~0); 46911#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46912#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46865#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 46866#L534 assume !(0 != activate_threads_~tmp___2~0#1); 46985#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46845#L461 assume !(1 == ~M_E~0); 46846#L461-2 assume !(1 == ~T1_E~0); 46908#L466-1 assume !(1 == ~T2_E~0); 47159#L471-1 assume !(1 == ~T3_E~0); 46933#L476-1 assume !(1 == ~E_1~0); 46934#L481-1 assume !(1 == ~E_2~0); 47079#L486-1 assume !(1 == ~E_3~0); 46947#L491-1 assume { :end_inline_reset_delta_events } true; 46948#L652-2 assume !false; 49296#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49294#L393 [2021-11-20 07:39:38,697 INFO L793 eck$LassoCheckResult]: Loop: 49294#L393 assume !false; 49291#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 49289#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 49287#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 48608#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 48609#L346 assume 0 != eval_~tmp~0#1; 48591#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 48580#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 48581#L351 assume !(0 == ~t1_st~0); 49303#L365 assume !(0 == ~t2_st~0); 49298#L379 assume !(0 == ~t3_st~0); 49294#L393 [2021-11-20 07:39:38,697 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:38,698 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 1 times [2021-11-20 07:39:38,698 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:38,698 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251875792] [2021-11-20 07:39:38,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:38,698 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:38,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:38,713 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 07:39:38,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:38,744 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 07:39:38,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:38,745 INFO L85 PathProgramCache]: Analyzing trace with hash 1064760425, now seen corresponding path program 1 times [2021-11-20 07:39:38,745 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:38,745 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [829026594] [2021-11-20 07:39:38,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:38,745 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:38,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:38,751 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 07:39:38,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:38,756 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 07:39:38,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:38,757 INFO L85 PathProgramCache]: Analyzing trace with hash -787959978, now seen corresponding path program 1 times [2021-11-20 07:39:38,757 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:38,758 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [289967425] [2021-11-20 07:39:38,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:38,758 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:38,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:38,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:38,794 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:38,794 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [289967425] [2021-11-20 07:39:38,794 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [289967425] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:38,795 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:38,795 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:38,795 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2140980304] [2021-11-20 07:39:38,795 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:38,913 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:39:38,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:39:38,914 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:39:38,914 INFO L87 Difference]: Start difference. First operand 3416 states and 4611 transitions. cyclomatic complexity: 1202 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:39,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:39:39,022 INFO L93 Difference]: Finished difference Result 6131 states and 8182 transitions. [2021-11-20 07:39:39,022 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:39:39,023 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6131 states and 8182 transitions. [2021-11-20 07:39:39,066 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 5763 [2021-11-20 07:39:39,093 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6131 states to 6131 states and 8182 transitions. [2021-11-20 07:39:39,094 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6131 [2021-11-20 07:39:39,101 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6131 [2021-11-20 07:39:39,103 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6131 states and 8182 transitions. [2021-11-20 07:39:39,113 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:39:39,113 INFO L681 BuchiCegarLoop]: Abstraction has 6131 states and 8182 transitions. [2021-11-20 07:39:39,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6131 states and 8182 transitions. [2021-11-20 07:39:39,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6131 to 5959. [2021-11-20 07:39:39,252 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5959 states, 5959 states have (on average 1.336465849974828) internal successors, (7964), 5958 states have internal predecessors, (7964), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:39,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5959 states to 5959 states and 7964 transitions. [2021-11-20 07:39:39,270 INFO L704 BuchiCegarLoop]: Abstraction has 5959 states and 7964 transitions. [2021-11-20 07:39:39,270 INFO L587 BuchiCegarLoop]: Abstraction has 5959 states and 7964 transitions. [2021-11-20 07:39:39,270 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-20 07:39:39,270 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5959 states and 7964 transitions. [2021-11-20 07:39:39,304 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 5591 [2021-11-20 07:39:39,304 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:39,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:39,305 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:39,305 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:39,306 INFO L791 eck$LassoCheckResult]: Stem: 56809#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 56705#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 56665#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56591#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56592#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 56678#L281-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 56458#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56459#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56739#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 56740#L418 assume !(0 == ~M_E~0); 56676#L418-2 assume !(0 == ~T1_E~0); 56677#L423-1 assume !(0 == ~T2_E~0); 56743#L428-1 assume !(0 == ~T3_E~0); 56744#L433-1 assume !(0 == ~E_1~0); 56709#L438-1 assume !(0 == ~E_2~0); 56710#L443-1 assume !(0 == ~E_3~0); 56609#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56610#L197 assume !(1 == ~m_pc~0); 56782#L197-2 is_master_triggered_~__retres1~0#1 := 0; 56783#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56796#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 56797#L510 assume !(0 != activate_threads_~tmp~1#1); 56408#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56409#L216 assume !(1 == ~t1_pc~0); 56454#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56455#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56585#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 56586#L518 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 56411#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56801#L235 assume !(1 == ~t2_pc~0); 56802#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 56544#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56545#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 56765#L526 assume !(0 != activate_threads_~tmp___1~0#1); 56766#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56528#L254 assume !(1 == ~t3_pc~0); 56529#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 56554#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56555#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 56587#L534 assume !(0 != activate_threads_~tmp___2~0#1); 56588#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56400#L461 assume !(1 == ~M_E~0); 56401#L461-2 assume !(1 == ~T1_E~0); 56741#L466-1 assume !(1 == ~T2_E~0); 56742#L471-1 assume !(1 == ~T3_E~0); 56486#L476-1 assume !(1 == ~E_1~0); 56487#L481-1 assume !(1 == ~E_2~0); 56647#L486-1 assume !(1 == ~E_3~0); 56648#L491-1 assume { :end_inline_reset_delta_events } true; 57322#L652-2 assume !false; 57323#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57349#L393 [2021-11-20 07:39:39,306 INFO L793 eck$LassoCheckResult]: Loop: 57349#L393 assume !false; 57346#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 57347#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 57342#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 57343#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 57341#L346 assume 0 != eval_~tmp~0#1; 57288#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 57289#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 57337#L351 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 56955#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 56956#L365 assume !(0 == ~t2_st~0); 57352#L379 assume !(0 == ~t3_st~0); 57349#L393 [2021-11-20 07:39:39,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:39,307 INFO L85 PathProgramCache]: Analyzing trace with hash 1149359284, now seen corresponding path program 1 times [2021-11-20 07:39:39,307 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:39,307 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [533672592] [2021-11-20 07:39:39,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:39,308 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:39,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:39,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:39,335 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:39,335 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [533672592] [2021-11-20 07:39:39,336 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [533672592] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:39,336 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:39,336 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:39,336 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1732736986] [2021-11-20 07:39:39,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:39,337 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 07:39:39,337 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:39,337 INFO L85 PathProgramCache]: Analyzing trace with hash -1356201070, now seen corresponding path program 1 times [2021-11-20 07:39:39,338 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:39,339 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1788443732] [2021-11-20 07:39:39,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:39,339 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:39,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:39,344 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 07:39:39,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:39,354 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 07:39:39,507 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:39:39,507 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:39:39,507 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:39:39,508 INFO L87 Difference]: Start difference. First operand 5959 states and 7964 transitions. cyclomatic complexity: 2016 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:39,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:39:39,538 INFO L93 Difference]: Finished difference Result 5058 states and 6784 transitions. [2021-11-20 07:39:39,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:39:39,539 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5058 states and 6784 transitions. [2021-11-20 07:39:39,570 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 4981 [2021-11-20 07:39:39,592 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5058 states to 5058 states and 6784 transitions. [2021-11-20 07:39:39,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5058 [2021-11-20 07:39:39,599 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5058 [2021-11-20 07:39:39,599 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5058 states and 6784 transitions. [2021-11-20 07:39:39,604 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:39:39,605 INFO L681 BuchiCegarLoop]: Abstraction has 5058 states and 6784 transitions. [2021-11-20 07:39:39,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5058 states and 6784 transitions. [2021-11-20 07:39:39,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5058 to 5058. [2021-11-20 07:39:39,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5058 states, 5058 states have (on average 1.3412415974693555) internal successors, (6784), 5057 states have internal predecessors, (6784), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:39,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5058 states to 5058 states and 6784 transitions. [2021-11-20 07:39:39,690 INFO L704 BuchiCegarLoop]: Abstraction has 5058 states and 6784 transitions. [2021-11-20 07:39:39,690 INFO L587 BuchiCegarLoop]: Abstraction has 5058 states and 6784 transitions. [2021-11-20 07:39:39,690 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-20 07:39:39,690 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5058 states and 6784 transitions. [2021-11-20 07:39:39,715 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 4981 [2021-11-20 07:39:39,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:39,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:39,716 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:39,716 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:39,716 INFO L791 eck$LassoCheckResult]: Stem: 67755#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 67687#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 67652#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67596#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67597#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 67663#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67480#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 67481#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67702#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67451#L418 assume !(0 == ~M_E~0); 67452#L418-2 assume !(0 == ~T1_E~0); 67662#L423-1 assume !(0 == ~T2_E~0); 67709#L428-1 assume !(0 == ~T3_E~0); 67707#L433-1 assume !(0 == ~E_1~0); 67692#L438-1 assume !(0 == ~E_2~0); 67617#L443-1 assume !(0 == ~E_3~0); 67609#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67569#L197 assume !(1 == ~m_pc~0); 67570#L197-2 is_master_triggered_~__retres1~0#1 := 0; 67747#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67750#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 67721#L510 assume !(0 != activate_threads_~tmp~1#1); 67431#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67432#L216 assume !(1 == ~t1_pc~0); 67478#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 67479#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67593#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 67433#L518 assume !(0 != activate_threads_~tmp___0~0#1); 67434#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67623#L235 assume !(1 == ~t2_pc~0); 67699#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 67560#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67561#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 67619#L526 assume !(0 != activate_threads_~tmp___1~0#1); 67732#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67548#L254 assume !(1 == ~t3_pc~0); 67485#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 67486#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67443#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 67444#L534 assume !(0 != activate_threads_~tmp___2~0#1); 67553#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67423#L461 assume !(1 == ~M_E~0); 67424#L461-2 assume !(1 == ~T1_E~0); 67482#L466-1 assume !(1 == ~T2_E~0); 67715#L471-1 assume !(1 == ~T3_E~0); 67506#L476-1 assume !(1 == ~E_1~0); 67507#L481-1 assume !(1 == ~E_2~0); 67638#L486-1 assume !(1 == ~E_3~0); 67521#L491-1 assume { :end_inline_reset_delta_events } true; 67522#L652-2 assume !false; 72241#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 71204#L393 [2021-11-20 07:39:39,717 INFO L793 eck$LassoCheckResult]: Loop: 71204#L393 assume !false; 72238#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 72236#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 71349#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 71348#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 71346#L346 assume 0 != eval_~tmp~0#1; 71344#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 71342#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 71341#L351 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 71339#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 71220#L365 assume !(0 == ~t2_st~0); 71209#L379 assume !(0 == ~t3_st~0); 71204#L393 [2021-11-20 07:39:39,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:39,718 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 2 times [2021-11-20 07:39:39,718 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:39,718 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006435796] [2021-11-20 07:39:39,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:39,718 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:39,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:39,726 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 07:39:39,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:39,764 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 07:39:39,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:39,765 INFO L85 PathProgramCache]: Analyzing trace with hash -1356201070, now seen corresponding path program 2 times [2021-11-20 07:39:39,765 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:39,765 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089220384] [2021-11-20 07:39:39,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:39,765 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:39,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:39,769 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 07:39:39,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:39,774 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 07:39:39,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:39,775 INFO L85 PathProgramCache]: Analyzing trace with hash 1339008581, now seen corresponding path program 1 times [2021-11-20 07:39:39,775 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:39,775 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [221998955] [2021-11-20 07:39:39,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:39,776 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:39,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:39,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:39,806 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:39,807 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [221998955] [2021-11-20 07:39:39,807 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [221998955] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:39,807 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:39,807 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 07:39:39,807 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074353347] [2021-11-20 07:39:39,808 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:39,929 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:39:39,930 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:39:39,930 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:39:39,930 INFO L87 Difference]: Start difference. First operand 5058 states and 6784 transitions. cyclomatic complexity: 1733 Second operand has 3 states, 3 states have (on average 21.0) internal successors, (63), 3 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:40,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:39:40,020 INFO L93 Difference]: Finished difference Result 8623 states and 11451 transitions. [2021-11-20 07:39:40,020 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:39:40,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8623 states and 11451 transitions. [2021-11-20 07:39:40,077 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 8521 [2021-11-20 07:39:40,118 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8623 states to 8623 states and 11451 transitions. [2021-11-20 07:39:40,118 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8623 [2021-11-20 07:39:40,129 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8623 [2021-11-20 07:39:40,129 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8623 states and 11451 transitions. [2021-11-20 07:39:40,138 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:39:40,138 INFO L681 BuchiCegarLoop]: Abstraction has 8623 states and 11451 transitions. [2021-11-20 07:39:40,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8623 states and 11451 transitions. [2021-11-20 07:39:40,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8623 to 8323. [2021-11-20 07:39:40,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8323 states, 8323 states have (on average 1.3349753694581281) internal successors, (11111), 8322 states have internal predecessors, (11111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:40,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8323 states to 8323 states and 11111 transitions. [2021-11-20 07:39:40,294 INFO L704 BuchiCegarLoop]: Abstraction has 8323 states and 11111 transitions. [2021-11-20 07:39:40,294 INFO L587 BuchiCegarLoop]: Abstraction has 8323 states and 11111 transitions. [2021-11-20 07:39:40,294 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-20 07:39:40,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8323 states and 11111 transitions. [2021-11-20 07:39:40,334 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 8221 [2021-11-20 07:39:40,334 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:40,334 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:40,335 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:40,335 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:40,336 INFO L791 eck$LassoCheckResult]: Stem: 81493#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 81402#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 81361#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 81296#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 81297#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 81371#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 81169#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81170#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81421#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81136#L418 assume !(0 == ~M_E~0); 81137#L418-2 assume !(0 == ~T1_E~0); 81370#L423-1 assume !(0 == ~T2_E~0); 81429#L428-1 assume !(0 == ~T3_E~0); 81427#L433-1 assume !(0 == ~E_1~0); 81407#L438-1 assume !(0 == ~E_2~0); 81315#L443-1 assume !(0 == ~E_3~0); 81308#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81261#L197 assume !(1 == ~m_pc~0); 81262#L197-2 is_master_triggered_~__retres1~0#1 := 0; 81476#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81479#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 81443#L510 assume !(0 != activate_threads_~tmp~1#1); 81120#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81121#L216 assume !(1 == ~t1_pc~0); 81165#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 81166#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81293#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 81122#L518 assume !(0 != activate_threads_~tmp___0~0#1); 81123#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81327#L235 assume !(1 == ~t2_pc~0); 81416#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 81248#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81249#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 81323#L526 assume !(0 != activate_threads_~tmp___1~0#1); 81457#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81237#L254 assume !(1 == ~t3_pc~0); 81174#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 81175#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81132#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 81133#L534 assume !(0 != activate_threads_~tmp___2~0#1); 81243#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81112#L461 assume !(1 == ~M_E~0); 81113#L461-2 assume !(1 == ~T1_E~0); 81171#L466-1 assume !(1 == ~T2_E~0); 81436#L471-1 assume !(1 == ~T3_E~0); 81196#L476-1 assume !(1 == ~E_1~0); 81197#L481-1 assume !(1 == ~E_2~0); 81345#L486-1 assume !(1 == ~E_3~0); 81209#L491-1 assume { :end_inline_reset_delta_events } true; 81210#L652-2 assume !false; 82226#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 82227#L393 [2021-11-20 07:39:40,336 INFO L793 eck$LassoCheckResult]: Loop: 82227#L393 assume !false; 86596#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 86595#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 86594#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 86593#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 86592#L346 assume 0 != eval_~tmp~0#1; 86591#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 86590#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 86589#L351 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 86588#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 86587#L365 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 82456#L382 assume !(0 != eval_~tmp_ndt_3~0#1); 86586#L379 assume !(0 == ~t3_st~0); 82227#L393 [2021-11-20 07:39:40,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:40,337 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 3 times [2021-11-20 07:39:40,337 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:40,337 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [551355337] [2021-11-20 07:39:40,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:40,338 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:40,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:40,346 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 07:39:40,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:40,361 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 07:39:40,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:40,362 INFO L85 PathProgramCache]: Analyzing trace with hash 907313168, now seen corresponding path program 1 times [2021-11-20 07:39:40,362 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:40,362 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806134142] [2021-11-20 07:39:40,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:40,363 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:40,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:40,367 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 07:39:40,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:40,372 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 07:39:40,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:40,373 INFO L85 PathProgramCache]: Analyzing trace with hash -1440533571, now seen corresponding path program 1 times [2021-11-20 07:39:40,373 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:40,373 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574125986] [2021-11-20 07:39:40,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:40,373 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:40,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 07:39:40,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 07:39:40,402 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 07:39:40,402 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [574125986] [2021-11-20 07:39:40,403 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [574125986] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 07:39:40,403 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 07:39:40,403 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-20 07:39:40,403 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [169916152] [2021-11-20 07:39:40,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 07:39:40,551 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 07:39:40,551 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 07:39:40,551 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 07:39:40,551 INFO L87 Difference]: Start difference. First operand 8323 states and 11111 transitions. cyclomatic complexity: 2795 Second operand has 3 states, 2 states have (on average 32.0) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:40,716 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 07:39:40,716 INFO L93 Difference]: Finished difference Result 13454 states and 17930 transitions. [2021-11-20 07:39:40,717 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 07:39:40,717 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13454 states and 17930 transitions. [2021-11-20 07:39:40,799 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 13332 [2021-11-20 07:39:40,860 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13454 states to 13454 states and 17930 transitions. [2021-11-20 07:39:40,860 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13454 [2021-11-20 07:39:40,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13454 [2021-11-20 07:39:40,891 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13454 states and 17930 transitions. [2021-11-20 07:39:40,902 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 07:39:40,903 INFO L681 BuchiCegarLoop]: Abstraction has 13454 states and 17930 transitions. [2021-11-20 07:39:40,915 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13454 states and 17930 transitions. [2021-11-20 07:39:41,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13454 to 13454. [2021-11-20 07:39:41,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13454 states, 13454 states have (on average 1.3326891630741786) internal successors, (17930), 13453 states have internal predecessors, (17930), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 07:39:41,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13454 states to 13454 states and 17930 transitions. [2021-11-20 07:39:41,246 INFO L704 BuchiCegarLoop]: Abstraction has 13454 states and 17930 transitions. [2021-11-20 07:39:41,247 INFO L587 BuchiCegarLoop]: Abstraction has 13454 states and 17930 transitions. [2021-11-20 07:39:41,247 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-20 07:39:41,247 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13454 states and 17930 transitions. [2021-11-20 07:39:41,321 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 13332 [2021-11-20 07:39:41,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 07:39:41,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 07:39:41,322 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:41,322 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 07:39:41,323 INFO L791 eck$LassoCheckResult]: Stem: 103244#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 103175#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 103133#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 103076#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 103077#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 103143#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 102955#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 102956#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 103191#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 102923#L418 assume !(0 == ~M_E~0); 102924#L418-2 assume !(0 == ~T1_E~0); 103142#L423-1 assume !(0 == ~T2_E~0); 103198#L428-1 assume !(0 == ~T3_E~0); 103196#L433-1 assume !(0 == ~E_1~0); 103178#L438-1 assume !(0 == ~E_2~0); 103098#L443-1 assume !(0 == ~E_3~0); 103088#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103044#L197 assume !(1 == ~m_pc~0); 103045#L197-2 is_master_triggered_~__retres1~0#1 := 0; 103233#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103236#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 103211#L510 assume !(0 != activate_threads_~tmp~1#1); 102905#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102906#L216 assume !(1 == ~t1_pc~0); 102953#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 102954#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103073#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 102907#L518 assume !(0 != activate_threads_~tmp___0~0#1); 102908#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103105#L235 assume !(1 == ~t2_pc~0); 103186#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 103031#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103032#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 103101#L526 assume !(0 != activate_threads_~tmp___1~0#1); 103222#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103022#L254 assume !(1 == ~t3_pc~0); 102960#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 102961#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102917#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 102918#L534 assume !(0 != activate_threads_~tmp___2~0#1); 103026#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102897#L461 assume !(1 == ~M_E~0); 102898#L461-2 assume !(1 == ~T1_E~0); 102957#L466-1 assume !(1 == ~T2_E~0); 103203#L471-1 assume !(1 == ~T3_E~0); 102981#L476-1 assume !(1 == ~E_1~0); 102982#L481-1 assume !(1 == ~E_2~0); 103118#L486-1 assume !(1 == ~E_3~0); 102997#L491-1 assume { :end_inline_reset_delta_events } true; 102913#L652-2 assume !false; 102914#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 103006#L393 [2021-11-20 07:39:41,323 INFO L793 eck$LassoCheckResult]: Loop: 103006#L393 assume !false; 116300#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 116298#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 116296#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 116294#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 116292#L346 assume 0 != eval_~tmp~0#1; 116291#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 103193#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 103194#L351 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 113111#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 113112#L365 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 115828#L382 assume !(0 != eval_~tmp_ndt_3~0#1); 115827#L379 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 107048#L396 assume !(0 != eval_~tmp_ndt_4~0#1); 103006#L393 [2021-11-20 07:39:41,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:41,324 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 4 times [2021-11-20 07:39:41,324 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:41,324 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970726166] [2021-11-20 07:39:41,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:41,325 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:41,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:41,332 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 07:39:41,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:41,346 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 07:39:41,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:41,347 INFO L85 PathProgramCache]: Analyzing trace with hash -1938063381, now seen corresponding path program 1 times [2021-11-20 07:39:41,347 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:41,347 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771215138] [2021-11-20 07:39:41,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:41,348 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:41,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:41,352 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 07:39:41,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:41,356 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 07:39:41,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 07:39:41,357 INFO L85 PathProgramCache]: Analyzing trace with hash -1706868258, now seen corresponding path program 1 times [2021-11-20 07:39:41,357 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 07:39:41,358 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [103468455] [2021-11-20 07:39:41,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 07:39:41,358 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 07:39:41,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:41,366 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 07:39:41,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 07:39:41,385 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 07:39:42,775 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 20.11 07:39:42 BoogieIcfgContainer [2021-11-20 07:39:42,775 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-11-20 07:39:42,776 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-11-20 07:39:42,776 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-11-20 07:39:42,776 INFO L275 PluginConnector]: Witness Printer initialized [2021-11-20 07:39:42,777 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 07:39:33" (3/4) ... [2021-11-20 07:39:42,780 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-11-20 07:39:42,873 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/bin/uautomizer-DQz5hQGWxF/witness.graphml [2021-11-20 07:39:42,873 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-11-20 07:39:42,874 INFO L158 Benchmark]: Toolchain (without parser) took 11160.03ms. Allocated memory was 102.8MB in the beginning and 425.7MB in the end (delta: 323.0MB). Free memory was 72.4MB in the beginning and 232.1MB in the end (delta: -159.7MB). Peak memory consumption was 163.6MB. Max. memory is 16.1GB. [2021-11-20 07:39:42,875 INFO L158 Benchmark]: CDTParser took 0.32ms. Allocated memory is still 102.8MB. Free memory was 58.9MB in the beginning and 58.8MB in the end (delta: 84.1kB). There was no memory consumed. Max. memory is 16.1GB. [2021-11-20 07:39:42,876 INFO L158 Benchmark]: CACSL2BoogieTranslator took 493.13ms. Allocated memory is still 102.8MB. Free memory was 72.1MB in the beginning and 74.3MB in the end (delta: -2.2MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2021-11-20 07:39:42,876 INFO L158 Benchmark]: Boogie Procedure Inliner took 93.72ms. Allocated memory is still 102.8MB. Free memory was 74.3MB in the beginning and 71.1MB in the end (delta: 3.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-11-20 07:39:42,877 INFO L158 Benchmark]: Boogie Preprocessor took 110.48ms. Allocated memory is still 102.8MB. Free memory was 71.1MB in the beginning and 68.3MB in the end (delta: 2.8MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-11-20 07:39:42,878 INFO L158 Benchmark]: RCFGBuilder took 1120.83ms. Allocated memory was 102.8MB in the beginning and 123.7MB in the end (delta: 21.0MB). Free memory was 68.0MB in the beginning and 90.3MB in the end (delta: -22.4MB). Peak memory consumption was 27.7MB. Max. memory is 16.1GB. [2021-11-20 07:39:42,878 INFO L158 Benchmark]: BuchiAutomizer took 9237.54ms. Allocated memory was 123.7MB in the beginning and 425.7MB in the end (delta: 302.0MB). Free memory was 90.3MB in the beginning and 236.1MB in the end (delta: -145.8MB). Peak memory consumption was 168.2MB. Max. memory is 16.1GB. [2021-11-20 07:39:42,879 INFO L158 Benchmark]: Witness Printer took 97.35ms. Allocated memory is still 425.7MB. Free memory was 236.1MB in the beginning and 232.1MB in the end (delta: 4.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-11-20 07:39:42,881 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.32ms. Allocated memory is still 102.8MB. Free memory was 58.9MB in the beginning and 58.8MB in the end (delta: 84.1kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 493.13ms. Allocated memory is still 102.8MB. Free memory was 72.1MB in the beginning and 74.3MB in the end (delta: -2.2MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 93.72ms. Allocated memory is still 102.8MB. Free memory was 74.3MB in the beginning and 71.1MB in the end (delta: 3.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 110.48ms. Allocated memory is still 102.8MB. Free memory was 71.1MB in the beginning and 68.3MB in the end (delta: 2.8MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 1120.83ms. Allocated memory was 102.8MB in the beginning and 123.7MB in the end (delta: 21.0MB). Free memory was 68.0MB in the beginning and 90.3MB in the end (delta: -22.4MB). Peak memory consumption was 27.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 9237.54ms. Allocated memory was 123.7MB in the beginning and 425.7MB in the end (delta: 302.0MB). Free memory was 90.3MB in the beginning and 236.1MB in the end (delta: -145.8MB). Peak memory consumption was 168.2MB. Max. memory is 16.1GB. * Witness Printer took 97.35ms. Allocated memory is still 425.7MB. Free memory was 236.1MB in the beginning and 232.1MB in the end (delta: 4.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 18 terminating modules (18 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.18 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 13454 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 9.1s and 19 iterations. TraceHistogramMax:1. Analysis of lassos took 4.0s. Construction of modules took 0.7s. Büchi inclusion checks took 1.0s. Highest rank in rank-based complementation 0. Minimization of det autom 18. Minimization of nondet autom 0. Automata minimization 1.5s AutomataMinimizationTime, 18 MinimizatonAttempts, 6500 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 0.9s Buchi closure took 0.1s. Biggest automaton had 13454 states and ocurred in iteration 18. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 9878 SdHoareTripleChecker+Valid, 0.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 9878 mSDsluCounter, 15530 SdHoareTripleChecker+Invalid, 0.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 7038 mSDsCounter, 188 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 483 IncrementalHoareTripleChecker+Invalid, 671 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 188 mSolverCounterUnsat, 8492 mSDtfsCounter, 483 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc3 concLT0 SILN1 SILU0 SILI11 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 341]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, t3_st=0, NULL=1, tmp=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@536e4ad3=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5966edfd=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5bdf87e1=0, tmp_ndt_2=0, E_3=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@48c3fa37=0, E_1=2, tmp_ndt_1=0, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2646a56=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@dec67e4=0, m_st=0, NULL=0, t3_pc=0, __retres1=0, tmp___0=0, tmp___2=0, m_pc=0, \result=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2f5ca848=0, \result=0, \result=0, tmp___1=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@12d82553=0, tmp=0, t1_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4e85df2c=0, E_2=2, tmp___0=0, T1_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4ba81ba3=0, __retres1=0, M_E=2, __retres1=1, t2_i=1, \result=0, t3_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2ae2f340=0, t1_st=0, __retres1=0, t2_pc=0, __retres1=0, tmp_ndt_4=0, kernel_st=1, T3_E=2, t1_i=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 341]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int M_E = 2; [L38] int T1_E = 2; [L39] int T2_E = 2; [L40] int T3_E = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L697] int __retres1 ; [L701] CALL init_model() [L610] m_i = 1 [L611] t1_i = 1 [L612] t2_i = 1 [L613] t3_i = 1 [L701] RET init_model() [L702] CALL start_simulation() [L638] int kernel_st ; [L639] int tmp ; [L640] int tmp___0 ; [L644] kernel_st = 0 [L645] FCALL update_channels() [L646] CALL init_threads() [L281] COND TRUE m_i == 1 [L282] m_st = 0 [L286] COND TRUE t1_i == 1 [L287] t1_st = 0 [L291] COND TRUE t2_i == 1 [L292] t2_st = 0 [L296] COND TRUE t3_i == 1 [L297] t3_st = 0 [L646] RET init_threads() [L647] CALL fire_delta_events() [L418] COND FALSE !(M_E == 0) [L423] COND FALSE !(T1_E == 0) [L428] COND FALSE !(T2_E == 0) [L433] COND FALSE !(T3_E == 0) [L438] COND FALSE !(E_1 == 0) [L443] COND FALSE !(E_2 == 0) [L448] COND FALSE !(E_3 == 0) [L647] RET fire_delta_events() [L648] CALL activate_threads() [L501] int tmp ; [L502] int tmp___0 ; [L503] int tmp___1 ; [L504] int tmp___2 ; [L508] CALL, EXPR is_master_triggered() [L194] int __retres1 ; [L197] COND FALSE !(m_pc == 1) [L207] __retres1 = 0 [L209] return (__retres1); [L508] RET, EXPR is_master_triggered() [L508] tmp = is_master_triggered() [L510] COND FALSE !(\read(tmp)) [L516] CALL, EXPR is_transmit1_triggered() [L213] int __retres1 ; [L216] COND FALSE !(t1_pc == 1) [L226] __retres1 = 0 [L228] return (__retres1); [L516] RET, EXPR is_transmit1_triggered() [L516] tmp___0 = is_transmit1_triggered() [L518] COND FALSE !(\read(tmp___0)) [L524] CALL, EXPR is_transmit2_triggered() [L232] int __retres1 ; [L235] COND FALSE !(t2_pc == 1) [L245] __retres1 = 0 [L247] return (__retres1); [L524] RET, EXPR is_transmit2_triggered() [L524] tmp___1 = is_transmit2_triggered() [L526] COND FALSE !(\read(tmp___1)) [L532] CALL, EXPR is_transmit3_triggered() [L251] int __retres1 ; [L254] COND FALSE !(t3_pc == 1) [L264] __retres1 = 0 [L266] return (__retres1); [L532] RET, EXPR is_transmit3_triggered() [L532] tmp___2 = is_transmit3_triggered() [L534] COND FALSE !(\read(tmp___2)) [L648] RET activate_threads() [L649] CALL reset_delta_events() [L461] COND FALSE !(M_E == 1) [L466] COND FALSE !(T1_E == 1) [L471] COND FALSE !(T2_E == 1) [L476] COND FALSE !(T3_E == 1) [L481] COND FALSE !(E_1 == 1) [L486] COND FALSE !(E_2 == 1) [L491] COND FALSE !(E_3 == 1) [L649] RET reset_delta_events() [L652] COND TRUE 1 [L655] kernel_st = 1 [L656] CALL eval() [L337] int tmp ; Loop: [L341] COND TRUE 1 [L344] CALL, EXPR exists_runnable_thread() [L306] int __retres1 ; [L309] COND TRUE m_st == 0 [L310] __retres1 = 1 [L332] return (__retres1); [L344] RET, EXPR exists_runnable_thread() [L344] tmp = exists_runnable_thread() [L346] COND TRUE \read(tmp) [L351] COND TRUE m_st == 0 [L352] int tmp_ndt_1; [L353] tmp_ndt_1 = __VERIFIER_nondet_int() [L354] COND FALSE !(\read(tmp_ndt_1)) [L365] COND TRUE t1_st == 0 [L366] int tmp_ndt_2; [L367] tmp_ndt_2 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp_ndt_2)) [L379] COND TRUE t2_st == 0 [L380] int tmp_ndt_3; [L381] tmp_ndt_3 = __VERIFIER_nondet_int() [L382] COND FALSE !(\read(tmp_ndt_3)) [L393] COND TRUE t3_st == 0 [L394] int tmp_ndt_4; [L395] tmp_ndt_4 = __VERIFIER_nondet_int() [L396] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-11-20 07:39:42,959 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2ceae5f1-2155-4f26-a39d-0f6e1bdd6cca/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)