./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.08.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 53f42b1a Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/bin/uautomizer-DQz5hQGWxF/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/bin/uautomizer-DQz5hQGWxF/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/bin/uautomizer-DQz5hQGWxF/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/bin/uautomizer-DQz5hQGWxF/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.08.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/bin/uautomizer-DQz5hQGWxF/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/bin/uautomizer-DQz5hQGWxF --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d0fbb3eaba725aed5c3b8bf09c66f0f1daed4feeee0b9a3792dc033de334e501 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-53f42b1 [2021-11-20 05:51:54,286 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-20 05:51:54,288 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-20 05:51:54,328 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-20 05:51:54,329 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-20 05:51:54,330 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-20 05:51:54,336 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-20 05:51:54,340 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-20 05:51:54,344 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-20 05:51:54,347 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-20 05:51:54,349 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-20 05:51:54,352 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-20 05:51:54,352 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-20 05:51:54,359 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-20 05:51:54,361 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-20 05:51:54,364 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-20 05:51:54,367 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-20 05:51:54,368 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-20 05:51:54,374 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-20 05:51:54,377 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-20 05:51:54,383 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-20 05:51:54,385 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-20 05:51:54,389 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-20 05:51:54,390 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-20 05:51:54,396 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-20 05:51:54,396 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-20 05:51:54,397 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-20 05:51:54,399 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-20 05:51:54,400 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-20 05:51:54,401 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-20 05:51:54,402 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-20 05:51:54,404 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-20 05:51:54,406 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-20 05:51:54,407 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-20 05:51:54,409 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-20 05:51:54,409 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-20 05:51:54,410 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-20 05:51:54,410 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-20 05:51:54,411 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-20 05:51:54,412 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-20 05:51:54,413 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-20 05:51:54,413 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/bin/uautomizer-DQz5hQGWxF/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-20 05:51:54,467 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-20 05:51:54,469 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-20 05:51:54,470 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-20 05:51:54,470 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-20 05:51:54,472 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-20 05:51:54,472 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-20 05:51:54,472 INFO L138 SettingsManager]: * Use SBE=true [2021-11-20 05:51:54,473 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-20 05:51:54,473 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-20 05:51:54,473 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-20 05:51:54,474 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-20 05:51:54,474 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-20 05:51:54,475 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-20 05:51:54,475 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-20 05:51:54,475 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-20 05:51:54,475 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-20 05:51:54,476 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-20 05:51:54,476 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-20 05:51:54,476 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-20 05:51:54,476 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-20 05:51:54,477 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-20 05:51:54,477 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-20 05:51:54,477 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-20 05:51:54,477 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-20 05:51:54,478 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-20 05:51:54,478 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-20 05:51:54,479 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-20 05:51:54,480 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-20 05:51:54,480 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-20 05:51:54,480 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-20 05:51:54,480 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-20 05:51:54,481 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-20 05:51:54,482 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-20 05:51:54,482 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/bin/uautomizer-DQz5hQGWxF/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/bin/uautomizer-DQz5hQGWxF Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d0fbb3eaba725aed5c3b8bf09c66f0f1daed4feeee0b9a3792dc033de334e501 [2021-11-20 05:51:54,765 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-20 05:51:54,790 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-20 05:51:54,793 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-20 05:51:54,794 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-20 05:51:54,796 INFO L275 PluginConnector]: CDTParser initialized [2021-11-20 05:51:54,797 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/bin/uautomizer-DQz5hQGWxF/../../sv-benchmarks/c/systemc/transmitter.08.cil.c [2021-11-20 05:51:54,880 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/bin/uautomizer-DQz5hQGWxF/data/8b7f7fb9c/653e064e001044afb847c52049cd51e6/FLAGc936f3bdf [2021-11-20 05:51:55,429 INFO L306 CDTParser]: Found 1 translation units. [2021-11-20 05:51:55,432 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/sv-benchmarks/c/systemc/transmitter.08.cil.c [2021-11-20 05:51:55,452 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/bin/uautomizer-DQz5hQGWxF/data/8b7f7fb9c/653e064e001044afb847c52049cd51e6/FLAGc936f3bdf [2021-11-20 05:51:55,757 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/bin/uautomizer-DQz5hQGWxF/data/8b7f7fb9c/653e064e001044afb847c52049cd51e6 [2021-11-20 05:51:55,759 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-20 05:51:55,760 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-20 05:51:55,765 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-20 05:51:55,765 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-20 05:51:55,782 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-20 05:51:55,783 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 05:51:55" (1/1) ... [2021-11-20 05:51:55,784 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@b5de13b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:51:55, skipping insertion in model container [2021-11-20 05:51:55,784 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 05:51:55" (1/1) ... [2021-11-20 05:51:55,791 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-20 05:51:55,844 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-20 05:51:56,038 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/sv-benchmarks/c/systemc/transmitter.08.cil.c[706,719] [2021-11-20 05:51:56,150 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-20 05:51:56,161 INFO L203 MainTranslator]: Completed pre-run [2021-11-20 05:51:56,173 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/sv-benchmarks/c/systemc/transmitter.08.cil.c[706,719] [2021-11-20 05:51:56,257 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-20 05:51:56,281 INFO L208 MainTranslator]: Completed translation [2021-11-20 05:51:56,282 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:51:56 WrapperNode [2021-11-20 05:51:56,283 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-20 05:51:56,284 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-20 05:51:56,284 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-20 05:51:56,284 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-20 05:51:56,292 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:51:56" (1/1) ... [2021-11-20 05:51:56,319 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:51:56" (1/1) ... [2021-11-20 05:51:56,415 INFO L137 Inliner]: procedures = 44, calls = 54, calls flagged for inlining = 49, calls inlined = 146, statements flattened = 2198 [2021-11-20 05:51:56,416 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-20 05:51:56,416 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-20 05:51:56,417 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-20 05:51:56,417 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-20 05:51:56,435 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:51:56" (1/1) ... [2021-11-20 05:51:56,436 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:51:56" (1/1) ... [2021-11-20 05:51:56,443 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:51:56" (1/1) ... [2021-11-20 05:51:56,446 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:51:56" (1/1) ... [2021-11-20 05:51:56,487 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:51:56" (1/1) ... [2021-11-20 05:51:56,545 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:51:56" (1/1) ... [2021-11-20 05:51:56,550 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:51:56" (1/1) ... [2021-11-20 05:51:56,567 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-20 05:51:56,568 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-20 05:51:56,568 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-20 05:51:56,568 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-20 05:51:56,570 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:51:56" (1/1) ... [2021-11-20 05:51:56,577 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:51:56,588 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:51:56,613 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 05:51:56,640 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eaf73d9c-23e5-4ae5-b3ca-2d327cf0c864/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-20 05:51:56,672 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-11-20 05:51:56,672 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-20 05:51:56,672 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-20 05:51:56,673 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-20 05:51:56,815 INFO L236 CfgBuilder]: Building ICFG [2021-11-20 05:51:56,816 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-11-20 05:51:57,975 INFO L277 CfgBuilder]: Performing block encoding [2021-11-20 05:51:57,995 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-20 05:51:57,996 INFO L301 CfgBuilder]: Removed 12 assume(true) statements. [2021-11-20 05:51:57,999 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 05:51:57 BoogieIcfgContainer [2021-11-20 05:51:57,999 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-20 05:51:58,000 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-20 05:51:58,001 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-20 05:51:58,004 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-20 05:51:58,005 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 05:51:58,005 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 20.11 05:51:55" (1/3) ... [2021-11-20 05:51:58,006 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@12e0ddc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 05:51:58, skipping insertion in model container [2021-11-20 05:51:58,006 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 05:51:58,007 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:51:56" (2/3) ... [2021-11-20 05:51:58,007 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@12e0ddc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 05:51:58, skipping insertion in model container [2021-11-20 05:51:58,007 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 05:51:58,007 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 05:51:57" (3/3) ... [2021-11-20 05:51:58,008 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.08.cil.c [2021-11-20 05:51:58,054 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-20 05:51:58,055 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-20 05:51:58,055 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-20 05:51:58,055 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-20 05:51:58,055 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-20 05:51:58,056 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-20 05:51:58,056 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-20 05:51:58,056 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-20 05:51:58,109 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 931 states, 930 states have (on average 1.5182795698924731) internal successors, (1412), 930 states have internal predecessors, (1412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:51:58,205 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 814 [2021-11-20 05:51:58,205 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:51:58,205 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:51:58,228 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:51:58,229 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:51:58,229 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-20 05:51:58,232 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 931 states, 930 states have (on average 1.5182795698924731) internal successors, (1412), 930 states have internal predecessors, (1412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:51:58,247 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 814 [2021-11-20 05:51:58,247 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:51:58,247 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:51:58,258 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:51:58,258 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:51:58,274 INFO L791 eck$LassoCheckResult]: Stem: 422#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 841#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 848#L1235true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47#L574true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 671#L581true assume !(1 == ~m_i~0);~m_st~0 := 2; 193#L581-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 808#L586-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 664#L591-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 637#L596-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 232#L601-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 672#L606-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 405#L611-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 752#L616-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 287#L621-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 697#L838true assume !(0 == ~M_E~0); 413#L838-2true assume !(0 == ~T1_E~0); 28#L843-1true assume !(0 == ~T2_E~0); 86#L848-1true assume !(0 == ~T3_E~0); 426#L853-1true assume !(0 == ~T4_E~0); 278#L858-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 3#L863-1true assume !(0 == ~T6_E~0); 745#L868-1true assume !(0 == ~T7_E~0); 864#L873-1true assume !(0 == ~T8_E~0); 740#L878-1true assume !(0 == ~E_1~0); 706#L883-1true assume !(0 == ~E_2~0); 778#L888-1true assume !(0 == ~E_3~0); 383#L893-1true assume !(0 == ~E_4~0); 779#L898-1true assume 0 == ~E_5~0;~E_5~0 := 1; 913#L903-1true assume !(0 == ~E_6~0); 704#L908-1true assume !(0 == ~E_7~0); 496#L913-1true assume !(0 == ~E_8~0); 34#L918-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 513#L402true assume !(1 == ~m_pc~0); 262#L402-2true is_master_triggered_~__retres1~0#1 := 0; 98#L413true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 920#L414true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 236#L1035true assume !(0 != activate_threads_~tmp~1#1); 271#L1035-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 693#L421true assume 1 == ~t1_pc~0; 807#L422true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 883#L432true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 264#L433true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 308#L1043true assume !(0 != activate_threads_~tmp___0~0#1); 767#L1043-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 896#L440true assume 1 == ~t2_pc~0; 21#L441true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 103#L451true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 865#L452true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 816#L1051true assume !(0 != activate_threads_~tmp___1~0#1); 515#L1051-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 211#L459true assume !(1 == ~t3_pc~0); 686#L459-2true is_transmit3_triggered_~__retres1~3#1 := 0; 763#L470true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 446#L471true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 94#L1059true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 921#L1059-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100#L478true assume 1 == ~t4_pc~0; 387#L479true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 662#L489true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 809#L490true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 196#L1067true assume !(0 != activate_threads_~tmp___3~0#1); 56#L1067-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 423#L497true assume !(1 == ~t5_pc~0); 354#L497-2true is_transmit5_triggered_~__retres1~5#1 := 0; 450#L508true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 245#L509true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 768#L1075true assume !(0 != activate_threads_~tmp___4~0#1); 678#L1075-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 875#L516true assume 1 == ~t6_pc~0; 876#L517true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 404#L527true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 844#L528true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 122#L1083true assume !(0 != activate_threads_~tmp___5~0#1); 462#L1083-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 400#L535true assume !(1 == ~t7_pc~0); 783#L535-2true is_transmit7_triggered_~__retres1~7#1 := 0; 461#L546true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 589#L547true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 489#L1091true assume !(0 != activate_threads_~tmp___6~0#1); 482#L1091-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 673#L554true assume 1 == ~t8_pc~0; 430#L555true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 810#L565true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 535#L566true activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 171#L1099true assume !(0 != activate_threads_~tmp___7~0#1); 490#L1099-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9#L931true assume !(1 == ~M_E~0); 726#L931-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 805#L936-1true assume !(1 == ~T2_E~0); 891#L941-1true assume !(1 == ~T3_E~0); 272#L946-1true assume !(1 == ~T4_E~0); 689#L951-1true assume !(1 == ~T5_E~0); 131#L956-1true assume !(1 == ~T6_E~0); 877#L961-1true assume !(1 == ~T7_E~0); 384#L966-1true assume !(1 == ~T8_E~0); 484#L971-1true assume 1 == ~E_1~0;~E_1~0 := 2; 829#L976-1true assume !(1 == ~E_2~0); 455#L981-1true assume !(1 == ~E_3~0); 275#L986-1true assume !(1 == ~E_4~0); 148#L991-1true assume !(1 == ~E_5~0); 854#L996-1true assume !(1 == ~E_6~0); 757#L1001-1true assume !(1 == ~E_7~0); 421#L1006-1true assume !(1 == ~E_8~0); 690#L1011-1true assume { :end_inline_reset_delta_events } true; 39#L1272-2true [2021-11-20 05:51:58,286 INFO L793 eck$LassoCheckResult]: Loop: 39#L1272-2true assume !false; 417#L1273true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40#L813true assume false; 424#L828true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 552#L574-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 642#L838-3true assume !(0 == ~M_E~0); 467#L838-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 789#L843-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 345#L848-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 385#L853-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 571#L858-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 444#L863-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 434#L868-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 453#L873-3true assume !(0 == ~T8_E~0); 160#L878-3true assume 0 == ~E_1~0;~E_1~0 := 1; 22#L883-3true assume 0 == ~E_2~0;~E_2~0 := 1; 657#L888-3true assume 0 == ~E_3~0;~E_3~0 := 1; 23#L893-3true assume 0 == ~E_4~0;~E_4~0 := 1; 289#L898-3true assume 0 == ~E_5~0;~E_5~0 := 1; 592#L903-3true assume 0 == ~E_6~0;~E_6~0 := 1; 777#L908-3true assume 0 == ~E_7~0;~E_7~0 := 1; 297#L913-3true assume !(0 == ~E_8~0); 43#L918-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 885#L402-27true assume 1 == ~m_pc~0; 17#L403-9true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 835#L413-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 292#L414-9true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 732#L1035-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 623#L1035-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 659#L421-27true assume !(1 == ~t1_pc~0); 156#L421-29true is_transmit1_triggered_~__retres1~1#1 := 0; 815#L432-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 318#L433-9true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 758#L1043-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 881#L1043-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 401#L440-27true assume 1 == ~t2_pc~0; 859#L441-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 929#L451-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 207#L452-9true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 325#L1051-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 411#L1051-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 150#L459-27true assume 1 == ~t3_pc~0; 458#L460-9true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 831#L470-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 189#L471-9true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 399#L1059-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 743#L1059-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 878#L478-27true assume !(1 == ~t4_pc~0); 143#L478-29true is_transmit4_triggered_~__retres1~4#1 := 0; 406#L489-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 886#L490-9true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 541#L1067-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 744#L1067-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 593#L497-27true assume !(1 == ~t5_pc~0); 240#L497-29true is_transmit5_triggered_~__retres1~5#1 := 0; 165#L508-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 341#L509-9true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 134#L1075-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 665#L1075-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 293#L516-27true assume 1 == ~t6_pc~0; 337#L517-9true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 200#L527-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 294#L528-9true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 415#L1083-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 755#L1083-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 246#L535-27true assume !(1 == ~t7_pc~0); 521#L535-29true is_transmit7_triggered_~__retres1~7#1 := 0; 926#L546-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 554#L547-9true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 825#L1091-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 220#L1091-29true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 766#L554-27true assume !(1 == ~t8_pc~0); 30#L554-29true is_transmit8_triggered_~__retres1~8#1 := 0; 102#L565-9true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 309#L566-9true activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 329#L1099-27true assume !(0 != activate_threads_~tmp___7~0#1); 158#L1099-29true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 517#L931-3true assume 1 == ~M_E~0;~M_E~0 := 2; 92#L931-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 218#L936-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 304#L941-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 519#L946-3true assume !(1 == ~T4_E~0); 169#L951-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 502#L956-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 364#L961-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 225#L966-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 710#L971-3true assume 1 == ~E_1~0;~E_1~0 := 2; 403#L976-3true assume 1 == ~E_2~0;~E_2~0 := 2; 38#L981-3true assume 1 == ~E_3~0;~E_3~0 := 2; 159#L986-3true assume !(1 == ~E_4~0); 33#L991-3true assume 1 == ~E_5~0;~E_5~0 := 2; 470#L996-3true assume 1 == ~E_6~0;~E_6~0 := 2; 596#L1001-3true assume 1 == ~E_7~0;~E_7~0 := 2; 213#L1006-3true assume 1 == ~E_8~0;~E_8~0 := 2; 504#L1011-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 54#L634-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 307#L681-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 228#L682-1true start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 773#L1291true assume !(0 == start_simulation_~tmp~3#1); 741#L1291-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 285#L634-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5#L681-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 564#L682-2true stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 714#L1246true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 258#L1253true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 438#L1254true start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 542#L1304true assume !(0 != start_simulation_~tmp___0~1#1); 39#L1272-2true [2021-11-20 05:51:58,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:51:58,295 INFO L85 PathProgramCache]: Analyzing trace with hash -1897256038, now seen corresponding path program 1 times [2021-11-20 05:51:58,305 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:51:58,305 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1013594799] [2021-11-20 05:51:58,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:51:58,307 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:51:58,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:51:58,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:51:58,546 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:51:58,547 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1013594799] [2021-11-20 05:51:58,549 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1013594799] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:51:58,550 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:51:58,551 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:51:58,555 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1403475709] [2021-11-20 05:51:58,558 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:51:58,563 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:51:58,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:51:58,567 INFO L85 PathProgramCache]: Analyzing trace with hash -650170989, now seen corresponding path program 1 times [2021-11-20 05:51:58,568 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:51:58,568 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [915941190] [2021-11-20 05:51:58,568 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:51:58,569 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:51:58,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:51:58,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:51:58,638 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:51:58,638 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [915941190] [2021-11-20 05:51:58,638 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [915941190] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:51:58,638 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:51:58,639 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-20 05:51:58,639 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1467850527] [2021-11-20 05:51:58,639 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:51:58,640 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:51:58,641 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:51:58,677 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:51:58,678 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:51:58,682 INFO L87 Difference]: Start difference. First operand has 931 states, 930 states have (on average 1.5182795698924731) internal successors, (1412), 930 states have internal predecessors, (1412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:51:58,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:51:58,773 INFO L93 Difference]: Finished difference Result 930 states and 1385 transitions. [2021-11-20 05:51:58,774 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:51:58,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 930 states and 1385 transitions. [2021-11-20 05:51:58,793 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-11-20 05:51:58,811 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 930 states to 924 states and 1379 transitions. [2021-11-20 05:51:58,813 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2021-11-20 05:51:58,815 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2021-11-20 05:51:58,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1379 transitions. [2021-11-20 05:51:58,826 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:51:58,826 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1379 transitions. [2021-11-20 05:51:58,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1379 transitions. [2021-11-20 05:51:58,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2021-11-20 05:51:58,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4924242424242424) internal successors, (1379), 923 states have internal predecessors, (1379), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:51:58,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1379 transitions. [2021-11-20 05:51:58,919 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1379 transitions. [2021-11-20 05:51:58,919 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1379 transitions. [2021-11-20 05:51:58,919 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-20 05:51:58,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1379 transitions. [2021-11-20 05:51:58,929 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-11-20 05:51:58,929 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:51:58,929 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:51:58,935 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:51:58,935 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:51:58,936 INFO L791 eck$LassoCheckResult]: Stem: 2546#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2789#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1961#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1962#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 2233#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2234#L586-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2731#L591-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2721#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2301#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2302#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2526#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2527#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2383#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2384#L838 assume !(0 == ~M_E~0); 2533#L838-2 assume !(0 == ~T1_E~0); 1923#L843-1 assume !(0 == ~T2_E~0); 1924#L848-1 assume !(0 == ~T3_E~0); 2043#L853-1 assume !(0 == ~T4_E~0); 2369#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1870#L863-1 assume !(0 == ~T6_E~0); 1871#L868-1 assume !(0 == ~T7_E~0); 2763#L873-1 assume !(0 == ~T8_E~0); 2761#L878-1 assume !(0 == ~E_1~0); 2750#L883-1 assume !(0 == ~E_2~0); 2751#L888-1 assume !(0 == ~E_3~0); 2498#L893-1 assume !(0 == ~E_4~0); 2499#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2775#L903-1 assume !(0 == ~E_6~0); 2749#L908-1 assume !(0 == ~E_7~0); 2623#L913-1 assume !(0 == ~E_8~0); 1937#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1938#L402 assume !(1 == ~m_pc~0); 2146#L402-2 is_master_triggered_~__retres1~0#1 := 0; 2064#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2065#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2307#L1035 assume !(0 != activate_threads_~tmp~1#1); 2308#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2360#L421 assume 1 == ~t1_pc~0; 2745#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2764#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2352#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2353#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 2411#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2772#L440 assume 1 == ~t2_pc~0; 1907#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1908#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2074#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2783#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 2637#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2261#L459 assume !(1 == ~t3_pc~0); 2262#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2744#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2568#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2058#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2059#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2068#L478 assume 1 == ~t4_pc~0; 2069#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2503#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2730#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2239#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1982#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1983#L497 assume !(1 == ~t5_pc~0); 2029#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2030#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2321#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2322#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 2737#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2738#L516 assume 1 == ~t6_pc~0; 2792#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2524#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2525#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2113#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 2114#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2515#L535 assume !(1 == ~t7_pc~0); 2516#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2585#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2586#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2614#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 2604#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2605#L554 assume 1 == ~t8_pc~0; 2554#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1899#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2655#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2201#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 2202#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1883#L931 assume !(1 == ~M_E~0); 1884#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2758#L936-1 assume !(1 == ~T2_E~0); 2781#L941-1 assume !(1 == ~T3_E~0); 2361#L946-1 assume !(1 == ~T4_E~0); 2362#L951-1 assume !(1 == ~T5_E~0); 2128#L956-1 assume !(1 == ~T6_E~0); 2129#L961-1 assume !(1 == ~T7_E~0); 2500#L966-1 assume !(1 == ~T8_E~0); 2501#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2607#L976-1 assume !(1 == ~E_2~0); 2577#L981-1 assume !(1 == ~E_3~0); 2366#L986-1 assume !(1 == ~E_4~0); 2158#L991-1 assume !(1 == ~E_5~0); 2159#L996-1 assume !(1 == ~E_6~0); 2768#L1001-1 assume !(1 == ~E_7~0); 2544#L1006-1 assume !(1 == ~E_8~0); 2545#L1011-1 assume { :end_inline_reset_delta_events } true; 1946#L1272-2 [2021-11-20 05:51:58,938 INFO L793 eck$LassoCheckResult]: Loop: 1946#L1272-2 assume !false; 1947#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1948#L813 assume !false; 1949#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2695#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1951#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2495#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2505#L696 assume !(0 != eval_~tmp~0#1); 2548#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2549#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2670#L838-3 assume !(0 == ~M_E~0); 2590#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2591#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2453#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2454#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2502#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2565#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2557#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2558#L873-3 assume !(0 == ~T8_E~0); 2181#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1910#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1911#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1912#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1913#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2387#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2696#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2400#L913-3 assume !(0 == ~E_8~0); 1953#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1954#L402-27 assume 1 == ~m_pc~0; 1900#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1901#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2390#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2391#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2709#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2710#L421-27 assume !(1 == ~t1_pc~0); 2173#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2174#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2423#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2424#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2769#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2518#L440-27 assume 1 == ~t2_pc~0; 2519#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2692#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2257#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2258#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2432#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2161#L459-27 assume !(1 == ~t3_pc~0); 2162#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2580#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2225#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2226#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2514#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2762#L478-27 assume 1 == ~t4_pc~0; 2784#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2152#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2528#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2660#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2661#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2697#L497-27 assume 1 == ~t5_pc~0; 2698#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2190#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2191#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2134#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2135#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2392#L516-27 assume 1 == ~t6_pc~0; 2393#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2247#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2248#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2395#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2535#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2324#L535-27 assume 1 == ~t7_pc~0; 2325#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2641#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2671#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2672#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2278#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2279#L554-27 assume !(1 == ~t8_pc~0); 1927#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1928#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2073#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2412#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 2178#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2179#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2054#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2055#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2275#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2407#L946-3 assume !(1 == ~T4_E~0); 2196#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2197#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2476#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2285#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2286#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2523#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1944#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1945#L986-3 assume !(1 == ~E_4~0); 1935#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1936#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2595#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2266#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2267#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1977#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1979#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2293#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2294#L1291 assume !(0 == start_simulation_~tmp~3#1); 2473#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2379#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1874#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1875#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 2679#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2343#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2344#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2560#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1946#L1272-2 [2021-11-20 05:51:58,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:51:58,939 INFO L85 PathProgramCache]: Analyzing trace with hash 500214492, now seen corresponding path program 1 times [2021-11-20 05:51:58,939 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:51:58,940 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1594876780] [2021-11-20 05:51:58,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:51:58,940 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:51:58,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:51:59,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:51:59,049 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:51:59,050 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1594876780] [2021-11-20 05:51:59,051 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1594876780] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:51:59,051 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:51:59,051 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:51:59,051 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [103431817] [2021-11-20 05:51:59,052 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:51:59,053 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:51:59,054 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:51:59,060 INFO L85 PathProgramCache]: Analyzing trace with hash 1268138686, now seen corresponding path program 1 times [2021-11-20 05:51:59,060 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:51:59,060 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808740455] [2021-11-20 05:51:59,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:51:59,061 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:51:59,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:51:59,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:51:59,187 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:51:59,187 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808740455] [2021-11-20 05:51:59,188 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [808740455] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:51:59,189 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:51:59,189 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:51:59,189 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2068009622] [2021-11-20 05:51:59,189 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:51:59,190 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:51:59,190 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:51:59,216 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:51:59,216 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:51:59,216 INFO L87 Difference]: Start difference. First operand 924 states and 1379 transitions. cyclomatic complexity: 456 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:51:59,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:51:59,242 INFO L93 Difference]: Finished difference Result 924 states and 1378 transitions. [2021-11-20 05:51:59,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:51:59,243 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1378 transitions. [2021-11-20 05:51:59,252 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-11-20 05:51:59,261 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1378 transitions. [2021-11-20 05:51:59,261 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2021-11-20 05:51:59,264 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2021-11-20 05:51:59,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1378 transitions. [2021-11-20 05:51:59,266 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:51:59,266 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1378 transitions. [2021-11-20 05:51:59,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1378 transitions. [2021-11-20 05:51:59,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2021-11-20 05:51:59,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4913419913419914) internal successors, (1378), 923 states have internal predecessors, (1378), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:51:59,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1378 transitions. [2021-11-20 05:51:59,286 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1378 transitions. [2021-11-20 05:51:59,286 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1378 transitions. [2021-11-20 05:51:59,287 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-20 05:51:59,287 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1378 transitions. [2021-11-20 05:51:59,293 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-11-20 05:51:59,293 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:51:59,293 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:51:59,304 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:51:59,304 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:51:59,306 INFO L791 eck$LassoCheckResult]: Stem: 4401#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 4402#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4644#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3816#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3817#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 4088#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4089#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4586#L591-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4576#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4156#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4157#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4381#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4382#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4238#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4239#L838 assume !(0 == ~M_E~0); 4388#L838-2 assume !(0 == ~T1_E~0); 3778#L843-1 assume !(0 == ~T2_E~0); 3779#L848-1 assume !(0 == ~T3_E~0); 3898#L853-1 assume !(0 == ~T4_E~0); 4224#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3725#L863-1 assume !(0 == ~T6_E~0); 3726#L868-1 assume !(0 == ~T7_E~0); 4618#L873-1 assume !(0 == ~T8_E~0); 4616#L878-1 assume !(0 == ~E_1~0); 4605#L883-1 assume !(0 == ~E_2~0); 4606#L888-1 assume !(0 == ~E_3~0); 4353#L893-1 assume !(0 == ~E_4~0); 4354#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4630#L903-1 assume !(0 == ~E_6~0); 4604#L908-1 assume !(0 == ~E_7~0); 4478#L913-1 assume !(0 == ~E_8~0); 3792#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3793#L402 assume !(1 == ~m_pc~0); 4001#L402-2 is_master_triggered_~__retres1~0#1 := 0; 3919#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3920#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4162#L1035 assume !(0 != activate_threads_~tmp~1#1); 4163#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4215#L421 assume 1 == ~t1_pc~0; 4600#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4619#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4207#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4208#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 4266#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4627#L440 assume 1 == ~t2_pc~0; 3762#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3763#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3929#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4638#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 4492#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4116#L459 assume !(1 == ~t3_pc~0); 4117#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4599#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4423#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3913#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3914#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3923#L478 assume 1 == ~t4_pc~0; 3924#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4358#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4585#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4094#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 3837#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3838#L497 assume !(1 == ~t5_pc~0); 3884#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3885#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4176#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4177#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 4592#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4593#L516 assume 1 == ~t6_pc~0; 4647#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4379#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4380#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3968#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 3969#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4370#L535 assume !(1 == ~t7_pc~0); 4371#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4440#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4441#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4469#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 4459#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4460#L554 assume 1 == ~t8_pc~0; 4409#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3754#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4510#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4056#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 4057#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3738#L931 assume !(1 == ~M_E~0); 3739#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4613#L936-1 assume !(1 == ~T2_E~0); 4636#L941-1 assume !(1 == ~T3_E~0); 4216#L946-1 assume !(1 == ~T4_E~0); 4217#L951-1 assume !(1 == ~T5_E~0); 3983#L956-1 assume !(1 == ~T6_E~0); 3984#L961-1 assume !(1 == ~T7_E~0); 4355#L966-1 assume !(1 == ~T8_E~0); 4356#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4462#L976-1 assume !(1 == ~E_2~0); 4432#L981-1 assume !(1 == ~E_3~0); 4221#L986-1 assume !(1 == ~E_4~0); 4013#L991-1 assume !(1 == ~E_5~0); 4014#L996-1 assume !(1 == ~E_6~0); 4623#L1001-1 assume !(1 == ~E_7~0); 4399#L1006-1 assume !(1 == ~E_8~0); 4400#L1011-1 assume { :end_inline_reset_delta_events } true; 3801#L1272-2 [2021-11-20 05:51:59,307 INFO L793 eck$LassoCheckResult]: Loop: 3801#L1272-2 assume !false; 3802#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3803#L813 assume !false; 3804#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4550#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3806#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4350#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4360#L696 assume !(0 != eval_~tmp~0#1); 4403#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4404#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4525#L838-3 assume !(0 == ~M_E~0); 4445#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4446#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4308#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4309#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4357#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4420#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4412#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4413#L873-3 assume !(0 == ~T8_E~0); 4036#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3765#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3766#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3767#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3768#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4242#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4551#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4255#L913-3 assume !(0 == ~E_8~0); 3808#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3809#L402-27 assume 1 == ~m_pc~0; 3755#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3756#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4245#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4246#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4564#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4565#L421-27 assume !(1 == ~t1_pc~0); 4028#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 4029#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4278#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4279#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4624#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4373#L440-27 assume 1 == ~t2_pc~0; 4374#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4547#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4112#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4113#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4287#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4016#L459-27 assume !(1 == ~t3_pc~0); 4017#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 4435#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4080#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4081#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4369#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4617#L478-27 assume !(1 == ~t4_pc~0); 4006#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 4007#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4383#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4515#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4516#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4552#L497-27 assume 1 == ~t5_pc~0; 4553#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4045#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4046#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3989#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3990#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4247#L516-27 assume 1 == ~t6_pc~0; 4248#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4102#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4103#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4250#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4390#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4179#L535-27 assume 1 == ~t7_pc~0; 4180#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4496#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4526#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4527#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4133#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4134#L554-27 assume !(1 == ~t8_pc~0); 3782#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 3783#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3928#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4267#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 4033#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4034#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3909#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3910#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4130#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4262#L946-3 assume !(1 == ~T4_E~0); 4051#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4052#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4331#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4140#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4141#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4378#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3799#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3800#L986-3 assume !(1 == ~E_4~0); 3790#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3791#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4450#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4121#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4122#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3832#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3834#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4148#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 4149#L1291 assume !(0 == start_simulation_~tmp~3#1); 4328#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4234#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3729#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3730#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 4534#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4198#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4199#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 4415#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 3801#L1272-2 [2021-11-20 05:51:59,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:51:59,308 INFO L85 PathProgramCache]: Analyzing trace with hash -1888349538, now seen corresponding path program 1 times [2021-11-20 05:51:59,309 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:51:59,309 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [298179592] [2021-11-20 05:51:59,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:51:59,310 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:51:59,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:51:59,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:51:59,385 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:51:59,385 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [298179592] [2021-11-20 05:51:59,386 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [298179592] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:51:59,386 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:51:59,386 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:51:59,386 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [594861897] [2021-11-20 05:51:59,387 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:51:59,388 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:51:59,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:51:59,389 INFO L85 PathProgramCache]: Analyzing trace with hash -638345507, now seen corresponding path program 1 times [2021-11-20 05:51:59,389 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:51:59,389 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1583474508] [2021-11-20 05:51:59,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:51:59,390 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:51:59,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:51:59,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:51:59,475 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:51:59,476 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1583474508] [2021-11-20 05:51:59,477 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1583474508] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:51:59,477 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:51:59,477 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:51:59,477 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [475918392] [2021-11-20 05:51:59,477 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:51:59,478 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:51:59,478 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:51:59,479 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:51:59,479 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:51:59,479 INFO L87 Difference]: Start difference. First operand 924 states and 1378 transitions. cyclomatic complexity: 455 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:51:59,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:51:59,509 INFO L93 Difference]: Finished difference Result 924 states and 1377 transitions. [2021-11-20 05:51:59,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:51:59,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1377 transitions. [2021-11-20 05:51:59,521 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-11-20 05:51:59,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1377 transitions. [2021-11-20 05:51:59,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2021-11-20 05:51:59,531 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2021-11-20 05:51:59,531 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1377 transitions. [2021-11-20 05:51:59,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:51:59,533 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1377 transitions. [2021-11-20 05:51:59,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1377 transitions. [2021-11-20 05:51:59,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2021-11-20 05:51:59,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4902597402597402) internal successors, (1377), 923 states have internal predecessors, (1377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:51:59,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1377 transitions. [2021-11-20 05:51:59,554 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1377 transitions. [2021-11-20 05:51:59,554 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1377 transitions. [2021-11-20 05:51:59,555 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-20 05:51:59,555 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1377 transitions. [2021-11-20 05:51:59,564 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-11-20 05:51:59,564 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:51:59,564 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:51:59,566 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:51:59,566 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:51:59,567 INFO L791 eck$LassoCheckResult]: Stem: 6256#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 6257#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6499#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5671#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5672#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 5943#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5944#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6441#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6431#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6011#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6012#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6236#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6237#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6093#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6094#L838 assume !(0 == ~M_E~0); 6243#L838-2 assume !(0 == ~T1_E~0); 5633#L843-1 assume !(0 == ~T2_E~0); 5634#L848-1 assume !(0 == ~T3_E~0); 5753#L853-1 assume !(0 == ~T4_E~0); 6079#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5580#L863-1 assume !(0 == ~T6_E~0); 5581#L868-1 assume !(0 == ~T7_E~0); 6473#L873-1 assume !(0 == ~T8_E~0); 6471#L878-1 assume !(0 == ~E_1~0); 6460#L883-1 assume !(0 == ~E_2~0); 6461#L888-1 assume !(0 == ~E_3~0); 6208#L893-1 assume !(0 == ~E_4~0); 6209#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6485#L903-1 assume !(0 == ~E_6~0); 6459#L908-1 assume !(0 == ~E_7~0); 6333#L913-1 assume !(0 == ~E_8~0); 5647#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5648#L402 assume !(1 == ~m_pc~0); 5856#L402-2 is_master_triggered_~__retres1~0#1 := 0; 5774#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5775#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6017#L1035 assume !(0 != activate_threads_~tmp~1#1); 6018#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6070#L421 assume 1 == ~t1_pc~0; 6455#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6474#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6062#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6063#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 6121#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6482#L440 assume 1 == ~t2_pc~0; 5617#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5618#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5784#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6493#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 6347#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5971#L459 assume !(1 == ~t3_pc~0); 5972#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6454#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6278#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5768#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5769#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5778#L478 assume 1 == ~t4_pc~0; 5779#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6213#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6440#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5949#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 5692#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5693#L497 assume !(1 == ~t5_pc~0); 5739#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5740#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6031#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6032#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 6447#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6448#L516 assume 1 == ~t6_pc~0; 6502#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6234#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6235#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5823#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 5824#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6225#L535 assume !(1 == ~t7_pc~0); 6226#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6295#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6296#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6324#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 6314#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6315#L554 assume 1 == ~t8_pc~0; 6264#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5609#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6365#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5911#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 5912#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5593#L931 assume !(1 == ~M_E~0); 5594#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6468#L936-1 assume !(1 == ~T2_E~0); 6491#L941-1 assume !(1 == ~T3_E~0); 6071#L946-1 assume !(1 == ~T4_E~0); 6072#L951-1 assume !(1 == ~T5_E~0); 5838#L956-1 assume !(1 == ~T6_E~0); 5839#L961-1 assume !(1 == ~T7_E~0); 6210#L966-1 assume !(1 == ~T8_E~0); 6211#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6317#L976-1 assume !(1 == ~E_2~0); 6287#L981-1 assume !(1 == ~E_3~0); 6076#L986-1 assume !(1 == ~E_4~0); 5868#L991-1 assume !(1 == ~E_5~0); 5869#L996-1 assume !(1 == ~E_6~0); 6478#L1001-1 assume !(1 == ~E_7~0); 6254#L1006-1 assume !(1 == ~E_8~0); 6255#L1011-1 assume { :end_inline_reset_delta_events } true; 5656#L1272-2 [2021-11-20 05:51:59,567 INFO L793 eck$LassoCheckResult]: Loop: 5656#L1272-2 assume !false; 5657#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5658#L813 assume !false; 5659#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6405#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5661#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6205#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6215#L696 assume !(0 != eval_~tmp~0#1); 6258#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6259#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6380#L838-3 assume !(0 == ~M_E~0); 6300#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6301#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6163#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6164#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6212#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6275#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6267#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6268#L873-3 assume !(0 == ~T8_E~0); 5891#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5620#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5621#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5622#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5623#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6097#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6406#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6110#L913-3 assume !(0 == ~E_8~0); 5663#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5664#L402-27 assume 1 == ~m_pc~0; 5610#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5611#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6100#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6101#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6419#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6420#L421-27 assume !(1 == ~t1_pc~0); 5883#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 5884#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6133#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6134#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6479#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6228#L440-27 assume 1 == ~t2_pc~0; 6229#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6402#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5967#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5968#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6142#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5871#L459-27 assume !(1 == ~t3_pc~0); 5872#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 6290#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5935#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5936#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6224#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6472#L478-27 assume !(1 == ~t4_pc~0); 5861#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 5862#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6238#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6370#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6371#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6407#L497-27 assume 1 == ~t5_pc~0; 6408#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5900#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5901#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5844#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5845#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6102#L516-27 assume 1 == ~t6_pc~0; 6103#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5957#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5958#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6105#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6245#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6034#L535-27 assume 1 == ~t7_pc~0; 6035#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6351#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6381#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6382#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5988#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5989#L554-27 assume !(1 == ~t8_pc~0); 5637#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 5638#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5783#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6122#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 5888#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5889#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5764#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5765#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5985#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6117#L946-3 assume !(1 == ~T4_E~0); 5906#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5907#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6186#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5995#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5996#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6233#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5654#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5655#L986-3 assume !(1 == ~E_4~0); 5645#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5646#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6305#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5976#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5977#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 5687#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5689#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6003#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 6004#L1291 assume !(0 == start_simulation_~tmp~3#1); 6183#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6089#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5584#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5585#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 6389#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6053#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6054#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6270#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 5656#L1272-2 [2021-11-20 05:51:59,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:51:59,568 INFO L85 PathProgramCache]: Analyzing trace with hash 805546652, now seen corresponding path program 1 times [2021-11-20 05:51:59,568 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:51:59,569 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [298443638] [2021-11-20 05:51:59,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:51:59,569 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:51:59,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:51:59,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:51:59,630 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:51:59,630 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [298443638] [2021-11-20 05:51:59,631 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [298443638] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:51:59,631 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:51:59,632 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:51:59,635 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1400133841] [2021-11-20 05:51:59,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:51:59,636 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:51:59,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:51:59,636 INFO L85 PathProgramCache]: Analyzing trace with hash -638345507, now seen corresponding path program 2 times [2021-11-20 05:51:59,637 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:51:59,641 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1288030835] [2021-11-20 05:51:59,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:51:59,642 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:51:59,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:51:59,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:51:59,714 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:51:59,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1288030835] [2021-11-20 05:51:59,714 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1288030835] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:51:59,714 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:51:59,715 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:51:59,715 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143869615] [2021-11-20 05:51:59,715 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:51:59,716 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:51:59,716 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:51:59,717 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:51:59,718 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:51:59,718 INFO L87 Difference]: Start difference. First operand 924 states and 1377 transitions. cyclomatic complexity: 454 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:51:59,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:51:59,742 INFO L93 Difference]: Finished difference Result 924 states and 1376 transitions. [2021-11-20 05:51:59,743 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:51:59,744 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1376 transitions. [2021-11-20 05:51:59,752 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-11-20 05:51:59,760 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1376 transitions. [2021-11-20 05:51:59,761 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2021-11-20 05:51:59,762 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2021-11-20 05:51:59,762 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1376 transitions. [2021-11-20 05:51:59,763 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:51:59,763 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1376 transitions. [2021-11-20 05:51:59,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1376 transitions. [2021-11-20 05:51:59,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2021-11-20 05:51:59,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4891774891774892) internal successors, (1376), 923 states have internal predecessors, (1376), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:51:59,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1376 transitions. [2021-11-20 05:51:59,784 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1376 transitions. [2021-11-20 05:51:59,784 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1376 transitions. [2021-11-20 05:51:59,784 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-20 05:51:59,784 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1376 transitions. [2021-11-20 05:51:59,790 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-11-20 05:51:59,790 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:51:59,791 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:51:59,792 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:51:59,793 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:51:59,793 INFO L791 eck$LassoCheckResult]: Stem: 8111#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 8112#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8354#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7526#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7527#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 7798#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7799#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8296#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8286#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7866#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7867#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8091#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8092#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7948#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7949#L838 assume !(0 == ~M_E~0); 8098#L838-2 assume !(0 == ~T1_E~0); 7488#L843-1 assume !(0 == ~T2_E~0); 7489#L848-1 assume !(0 == ~T3_E~0); 7608#L853-1 assume !(0 == ~T4_E~0); 7934#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7435#L863-1 assume !(0 == ~T6_E~0); 7436#L868-1 assume !(0 == ~T7_E~0); 8328#L873-1 assume !(0 == ~T8_E~0); 8326#L878-1 assume !(0 == ~E_1~0); 8315#L883-1 assume !(0 == ~E_2~0); 8316#L888-1 assume !(0 == ~E_3~0); 8063#L893-1 assume !(0 == ~E_4~0); 8064#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 8340#L903-1 assume !(0 == ~E_6~0); 8314#L908-1 assume !(0 == ~E_7~0); 8188#L913-1 assume !(0 == ~E_8~0); 7502#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7503#L402 assume !(1 == ~m_pc~0); 7711#L402-2 is_master_triggered_~__retres1~0#1 := 0; 7629#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7630#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7872#L1035 assume !(0 != activate_threads_~tmp~1#1); 7873#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7925#L421 assume 1 == ~t1_pc~0; 8310#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8329#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7917#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7918#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 7976#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8337#L440 assume 1 == ~t2_pc~0; 7472#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7473#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7639#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8348#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 8202#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7826#L459 assume !(1 == ~t3_pc~0); 7827#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8309#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8133#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7623#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7624#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7633#L478 assume 1 == ~t4_pc~0; 7634#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8068#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8295#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7804#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 7547#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7548#L497 assume !(1 == ~t5_pc~0); 7594#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7595#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7886#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7887#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 8302#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8303#L516 assume 1 == ~t6_pc~0; 8357#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8089#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8090#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7678#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 7679#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8080#L535 assume !(1 == ~t7_pc~0); 8081#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8150#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8151#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8179#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 8169#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8170#L554 assume 1 == ~t8_pc~0; 8119#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7464#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8220#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7766#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 7767#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7448#L931 assume !(1 == ~M_E~0); 7449#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8323#L936-1 assume !(1 == ~T2_E~0); 8346#L941-1 assume !(1 == ~T3_E~0); 7926#L946-1 assume !(1 == ~T4_E~0); 7927#L951-1 assume !(1 == ~T5_E~0); 7693#L956-1 assume !(1 == ~T6_E~0); 7694#L961-1 assume !(1 == ~T7_E~0); 8065#L966-1 assume !(1 == ~T8_E~0); 8066#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 8172#L976-1 assume !(1 == ~E_2~0); 8142#L981-1 assume !(1 == ~E_3~0); 7931#L986-1 assume !(1 == ~E_4~0); 7723#L991-1 assume !(1 == ~E_5~0); 7724#L996-1 assume !(1 == ~E_6~0); 8333#L1001-1 assume !(1 == ~E_7~0); 8109#L1006-1 assume !(1 == ~E_8~0); 8110#L1011-1 assume { :end_inline_reset_delta_events } true; 7511#L1272-2 [2021-11-20 05:51:59,794 INFO L793 eck$LassoCheckResult]: Loop: 7511#L1272-2 assume !false; 7512#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7513#L813 assume !false; 7514#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8260#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7516#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8060#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8070#L696 assume !(0 != eval_~tmp~0#1); 8113#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8114#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8235#L838-3 assume !(0 == ~M_E~0); 8155#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8156#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8018#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8019#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8067#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8130#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8122#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8123#L873-3 assume !(0 == ~T8_E~0); 7746#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7475#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7476#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7477#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7478#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7952#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8261#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7965#L913-3 assume !(0 == ~E_8~0); 7518#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7519#L402-27 assume 1 == ~m_pc~0; 7465#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7466#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7955#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7956#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8274#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8275#L421-27 assume !(1 == ~t1_pc~0); 7738#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 7739#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7988#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7989#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8334#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8083#L440-27 assume 1 == ~t2_pc~0; 8084#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8257#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7822#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7823#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7997#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7726#L459-27 assume 1 == ~t3_pc~0; 7728#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8145#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7790#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7791#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8079#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8327#L478-27 assume !(1 == ~t4_pc~0); 7716#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 7717#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8093#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8225#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8226#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8262#L497-27 assume 1 == ~t5_pc~0; 8263#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7755#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7756#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7699#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7700#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7957#L516-27 assume 1 == ~t6_pc~0; 7958#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7812#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7813#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7960#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8100#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7889#L535-27 assume 1 == ~t7_pc~0; 7890#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8206#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8236#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8237#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7843#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7844#L554-27 assume !(1 == ~t8_pc~0); 7492#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 7493#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7638#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7977#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 7743#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7744#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7619#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7620#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7840#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7972#L946-3 assume !(1 == ~T4_E~0); 7761#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7762#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8041#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7850#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7851#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8088#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7509#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7510#L986-3 assume !(1 == ~E_4~0); 7500#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7501#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8160#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7831#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7832#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 7542#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7544#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7858#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 7859#L1291 assume !(0 == start_simulation_~tmp~3#1); 8038#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 7944#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7439#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7440#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 8244#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7908#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7909#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8125#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 7511#L1272-2 [2021-11-20 05:51:59,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:51:59,794 INFO L85 PathProgramCache]: Analyzing trace with hash 1862277854, now seen corresponding path program 1 times [2021-11-20 05:51:59,795 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:51:59,795 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [922449851] [2021-11-20 05:51:59,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:51:59,795 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:51:59,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:51:59,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:51:59,840 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:51:59,840 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [922449851] [2021-11-20 05:51:59,841 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [922449851] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:51:59,841 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:51:59,841 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:51:59,841 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1900519477] [2021-11-20 05:51:59,841 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:51:59,842 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:51:59,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:51:59,842 INFO L85 PathProgramCache]: Analyzing trace with hash 539629054, now seen corresponding path program 1 times [2021-11-20 05:51:59,843 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:51:59,843 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1651387195] [2021-11-20 05:51:59,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:51:59,843 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:51:59,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:51:59,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:51:59,887 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:51:59,887 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1651387195] [2021-11-20 05:51:59,888 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1651387195] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:51:59,888 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:51:59,888 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:51:59,888 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1419198952] [2021-11-20 05:51:59,888 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:51:59,889 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:51:59,889 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:51:59,889 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:51:59,890 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:51:59,890 INFO L87 Difference]: Start difference. First operand 924 states and 1376 transitions. cyclomatic complexity: 453 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:51:59,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:51:59,914 INFO L93 Difference]: Finished difference Result 924 states and 1375 transitions. [2021-11-20 05:51:59,914 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:51:59,916 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1375 transitions. [2021-11-20 05:51:59,924 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-11-20 05:51:59,932 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1375 transitions. [2021-11-20 05:51:59,933 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2021-11-20 05:51:59,934 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2021-11-20 05:51:59,934 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1375 transitions. [2021-11-20 05:51:59,935 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:51:59,936 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1375 transitions. [2021-11-20 05:51:59,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1375 transitions. [2021-11-20 05:51:59,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2021-11-20 05:51:59,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4880952380952381) internal successors, (1375), 923 states have internal predecessors, (1375), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:51:59,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1375 transitions. [2021-11-20 05:51:59,986 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1375 transitions. [2021-11-20 05:51:59,986 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1375 transitions. [2021-11-20 05:51:59,986 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-20 05:51:59,986 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1375 transitions. [2021-11-20 05:51:59,994 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-11-20 05:51:59,994 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:51:59,994 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:51:59,996 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:51:59,996 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:51:59,997 INFO L791 eck$LassoCheckResult]: Stem: 9966#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 9967#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10209#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9381#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9382#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 9653#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9654#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10151#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10141#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9721#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9722#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9946#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9947#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9803#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9804#L838 assume !(0 == ~M_E~0); 9953#L838-2 assume !(0 == ~T1_E~0); 9343#L843-1 assume !(0 == ~T2_E~0); 9344#L848-1 assume !(0 == ~T3_E~0); 9463#L853-1 assume !(0 == ~T4_E~0); 9789#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9290#L863-1 assume !(0 == ~T6_E~0); 9291#L868-1 assume !(0 == ~T7_E~0); 10183#L873-1 assume !(0 == ~T8_E~0); 10181#L878-1 assume !(0 == ~E_1~0); 10170#L883-1 assume !(0 == ~E_2~0); 10171#L888-1 assume !(0 == ~E_3~0); 9918#L893-1 assume !(0 == ~E_4~0); 9919#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10195#L903-1 assume !(0 == ~E_6~0); 10169#L908-1 assume !(0 == ~E_7~0); 10043#L913-1 assume !(0 == ~E_8~0); 9357#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9358#L402 assume !(1 == ~m_pc~0); 9566#L402-2 is_master_triggered_~__retres1~0#1 := 0; 9484#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9485#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9727#L1035 assume !(0 != activate_threads_~tmp~1#1); 9728#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9780#L421 assume 1 == ~t1_pc~0; 10165#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10184#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9772#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9773#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 9831#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10192#L440 assume 1 == ~t2_pc~0; 9327#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9328#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9494#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10203#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 10057#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9681#L459 assume !(1 == ~t3_pc~0); 9682#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10164#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9988#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9478#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9479#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9488#L478 assume 1 == ~t4_pc~0; 9489#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9923#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10150#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9659#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 9402#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9403#L497 assume !(1 == ~t5_pc~0); 9449#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9450#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9741#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9742#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 10157#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10158#L516 assume 1 == ~t6_pc~0; 10212#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9944#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9945#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9533#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 9534#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9935#L535 assume !(1 == ~t7_pc~0); 9936#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10005#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10006#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10034#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 10024#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10025#L554 assume 1 == ~t8_pc~0; 9974#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9319#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10075#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9621#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 9622#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9303#L931 assume !(1 == ~M_E~0); 9304#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10178#L936-1 assume !(1 == ~T2_E~0); 10201#L941-1 assume !(1 == ~T3_E~0); 9781#L946-1 assume !(1 == ~T4_E~0); 9782#L951-1 assume !(1 == ~T5_E~0); 9548#L956-1 assume !(1 == ~T6_E~0); 9549#L961-1 assume !(1 == ~T7_E~0); 9920#L966-1 assume !(1 == ~T8_E~0); 9921#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 10027#L976-1 assume !(1 == ~E_2~0); 9997#L981-1 assume !(1 == ~E_3~0); 9786#L986-1 assume !(1 == ~E_4~0); 9578#L991-1 assume !(1 == ~E_5~0); 9579#L996-1 assume !(1 == ~E_6~0); 10188#L1001-1 assume !(1 == ~E_7~0); 9964#L1006-1 assume !(1 == ~E_8~0); 9965#L1011-1 assume { :end_inline_reset_delta_events } true; 9366#L1272-2 [2021-11-20 05:51:59,997 INFO L793 eck$LassoCheckResult]: Loop: 9366#L1272-2 assume !false; 9367#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9368#L813 assume !false; 9369#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10115#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9371#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9915#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9925#L696 assume !(0 != eval_~tmp~0#1); 9968#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9969#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10090#L838-3 assume !(0 == ~M_E~0); 10010#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10011#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9873#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9874#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9922#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9985#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9977#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9978#L873-3 assume !(0 == ~T8_E~0); 9601#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9330#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9331#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9332#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9333#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9807#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10116#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9820#L913-3 assume !(0 == ~E_8~0); 9373#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9374#L402-27 assume 1 == ~m_pc~0; 9320#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9321#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9810#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9811#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10129#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10130#L421-27 assume !(1 == ~t1_pc~0); 9593#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 9594#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9843#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9844#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10189#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9938#L440-27 assume 1 == ~t2_pc~0; 9939#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10112#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9677#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9678#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9852#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9581#L459-27 assume !(1 == ~t3_pc~0); 9582#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 10000#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9645#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9646#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9934#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10182#L478-27 assume !(1 == ~t4_pc~0); 9571#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 9572#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9948#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10080#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10081#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10117#L497-27 assume 1 == ~t5_pc~0; 10118#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9610#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9611#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9554#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9555#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9812#L516-27 assume 1 == ~t6_pc~0; 9813#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9667#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9668#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9815#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9955#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9744#L535-27 assume 1 == ~t7_pc~0; 9745#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10061#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10091#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10092#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9698#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9699#L554-27 assume !(1 == ~t8_pc~0); 9347#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 9348#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9493#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9832#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 9598#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9599#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9474#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9475#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9695#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9827#L946-3 assume !(1 == ~T4_E~0); 9616#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9617#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9896#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9705#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9706#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9943#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9364#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9365#L986-3 assume !(1 == ~E_4~0); 9355#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9356#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10015#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9686#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9687#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9397#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9399#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9713#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 9714#L1291 assume !(0 == start_simulation_~tmp~3#1); 9893#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9799#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9294#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9295#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 10099#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9763#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9764#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 9980#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 9366#L1272-2 [2021-11-20 05:52:00,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:00,008 INFO L85 PathProgramCache]: Analyzing trace with hash 510892636, now seen corresponding path program 1 times [2021-11-20 05:52:00,008 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:00,008 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2492820] [2021-11-20 05:52:00,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:00,009 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:00,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:00,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:00,043 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:00,043 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2492820] [2021-11-20 05:52:00,043 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2492820] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:00,043 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:00,044 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:00,044 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205545821] [2021-11-20 05:52:00,044 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:00,044 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:52:00,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:00,047 INFO L85 PathProgramCache]: Analyzing trace with hash -638345507, now seen corresponding path program 3 times [2021-11-20 05:52:00,047 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:00,052 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2054600605] [2021-11-20 05:52:00,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:00,053 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:00,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:00,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:00,119 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:00,119 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2054600605] [2021-11-20 05:52:00,121 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2054600605] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:00,121 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:00,121 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:00,121 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1566867663] [2021-11-20 05:52:00,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:00,122 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:52:00,122 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:52:00,123 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:52:00,123 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:52:00,123 INFO L87 Difference]: Start difference. First operand 924 states and 1375 transitions. cyclomatic complexity: 452 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:00,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:52:00,155 INFO L93 Difference]: Finished difference Result 924 states and 1374 transitions. [2021-11-20 05:52:00,155 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:52:00,157 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1374 transitions. [2021-11-20 05:52:00,166 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-11-20 05:52:00,174 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1374 transitions. [2021-11-20 05:52:00,175 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2021-11-20 05:52:00,176 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2021-11-20 05:52:00,176 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1374 transitions. [2021-11-20 05:52:00,177 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:52:00,178 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1374 transitions. [2021-11-20 05:52:00,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1374 transitions. [2021-11-20 05:52:00,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2021-11-20 05:52:00,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4870129870129871) internal successors, (1374), 923 states have internal predecessors, (1374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:00,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1374 transitions. [2021-11-20 05:52:00,200 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1374 transitions. [2021-11-20 05:52:00,200 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1374 transitions. [2021-11-20 05:52:00,200 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-20 05:52:00,200 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1374 transitions. [2021-11-20 05:52:00,210 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-11-20 05:52:00,210 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:52:00,210 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:52:00,212 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:00,213 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:00,213 INFO L791 eck$LassoCheckResult]: Stem: 11821#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 11822#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 12064#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11236#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11237#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 11508#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11509#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12006#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11997#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11576#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11577#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11802#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11803#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11658#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11659#L838 assume !(0 == ~M_E~0); 11809#L838-2 assume !(0 == ~T1_E~0); 11198#L843-1 assume !(0 == ~T2_E~0); 11199#L848-1 assume !(0 == ~T3_E~0); 11318#L853-1 assume !(0 == ~T4_E~0); 11644#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11145#L863-1 assume !(0 == ~T6_E~0); 11146#L868-1 assume !(0 == ~T7_E~0); 12038#L873-1 assume !(0 == ~T8_E~0); 12036#L878-1 assume !(0 == ~E_1~0); 12025#L883-1 assume !(0 == ~E_2~0); 12026#L888-1 assume !(0 == ~E_3~0); 11773#L893-1 assume !(0 == ~E_4~0); 11774#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 12050#L903-1 assume !(0 == ~E_6~0); 12024#L908-1 assume !(0 == ~E_7~0); 11898#L913-1 assume !(0 == ~E_8~0); 11212#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11213#L402 assume !(1 == ~m_pc~0); 11421#L402-2 is_master_triggered_~__retres1~0#1 := 0; 11339#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11340#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11582#L1035 assume !(0 != activate_threads_~tmp~1#1); 11583#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11635#L421 assume 1 == ~t1_pc~0; 12020#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12039#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11627#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11628#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 11686#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12047#L440 assume 1 == ~t2_pc~0; 11182#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11183#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11349#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12058#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 11912#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11536#L459 assume !(1 == ~t3_pc~0); 11537#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12019#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11843#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11333#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11334#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11343#L478 assume 1 == ~t4_pc~0; 11344#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11778#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12005#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11514#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 11257#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11258#L497 assume !(1 == ~t5_pc~0); 11304#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11305#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11596#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11597#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 12012#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12013#L516 assume 1 == ~t6_pc~0; 12067#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11799#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11800#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11388#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 11389#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11790#L535 assume !(1 == ~t7_pc~0); 11791#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11860#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11861#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11889#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 11879#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11880#L554 assume 1 == ~t8_pc~0; 11829#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11174#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11930#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11476#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 11477#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11158#L931 assume !(1 == ~M_E~0); 11159#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12033#L936-1 assume !(1 == ~T2_E~0); 12056#L941-1 assume !(1 == ~T3_E~0); 11636#L946-1 assume !(1 == ~T4_E~0); 11637#L951-1 assume !(1 == ~T5_E~0); 11403#L956-1 assume !(1 == ~T6_E~0); 11404#L961-1 assume !(1 == ~T7_E~0); 11775#L966-1 assume !(1 == ~T8_E~0); 11776#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 11882#L976-1 assume !(1 == ~E_2~0); 11852#L981-1 assume !(1 == ~E_3~0); 11641#L986-1 assume !(1 == ~E_4~0); 11433#L991-1 assume !(1 == ~E_5~0); 11434#L996-1 assume !(1 == ~E_6~0); 12043#L1001-1 assume !(1 == ~E_7~0); 11819#L1006-1 assume !(1 == ~E_8~0); 11820#L1011-1 assume { :end_inline_reset_delta_events } true; 11221#L1272-2 [2021-11-20 05:52:00,213 INFO L793 eck$LassoCheckResult]: Loop: 11221#L1272-2 assume !false; 11222#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11223#L813 assume !false; 11224#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11970#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11226#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11770#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11780#L696 assume !(0 != eval_~tmp~0#1); 11823#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11824#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11945#L838-3 assume !(0 == ~M_E~0); 11865#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11866#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11728#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11729#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11777#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11840#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11832#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11833#L873-3 assume !(0 == ~T8_E~0); 11456#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11185#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11186#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11187#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11188#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11662#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11971#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11675#L913-3 assume !(0 == ~E_8~0); 11228#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11229#L402-27 assume 1 == ~m_pc~0; 11175#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11176#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11665#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11666#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11984#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11985#L421-27 assume !(1 == ~t1_pc~0); 11448#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 11449#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11698#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11699#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12044#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11793#L440-27 assume 1 == ~t2_pc~0; 11794#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11967#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11532#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11533#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11707#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11436#L459-27 assume !(1 == ~t3_pc~0); 11437#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 11855#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11500#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11501#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11789#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12037#L478-27 assume !(1 == ~t4_pc~0); 11426#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 11427#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11801#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11935#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11936#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11972#L497-27 assume 1 == ~t5_pc~0; 11973#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11465#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11466#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11409#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11410#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11667#L516-27 assume 1 == ~t6_pc~0; 11668#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11522#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11523#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11670#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11810#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11599#L535-27 assume 1 == ~t7_pc~0; 11600#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11916#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11946#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11947#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11553#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11554#L554-27 assume !(1 == ~t8_pc~0); 11202#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 11203#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11348#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11687#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 11453#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11454#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11329#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11330#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11550#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11682#L946-3 assume !(1 == ~T4_E~0); 11471#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11472#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11751#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11560#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11561#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11798#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11219#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11220#L986-3 assume !(1 == ~E_4~0); 11210#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11211#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11870#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11541#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11542#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11252#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11254#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11568#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 11569#L1291 assume !(0 == start_simulation_~tmp~3#1); 11748#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11654#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11149#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11150#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 11954#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11618#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11619#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 11835#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 11221#L1272-2 [2021-11-20 05:52:00,214 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:00,214 INFO L85 PathProgramCache]: Analyzing trace with hash 2129867550, now seen corresponding path program 1 times [2021-11-20 05:52:00,214 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:00,215 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985216585] [2021-11-20 05:52:00,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:00,215 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:00,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:00,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:00,244 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:00,244 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1985216585] [2021-11-20 05:52:00,244 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1985216585] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:00,244 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:00,245 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:00,245 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [233929422] [2021-11-20 05:52:00,245 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:00,245 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:52:00,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:00,246 INFO L85 PathProgramCache]: Analyzing trace with hash -638345507, now seen corresponding path program 4 times [2021-11-20 05:52:00,246 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:00,246 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1681237330] [2021-11-20 05:52:00,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:00,247 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:00,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:00,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:00,290 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:00,290 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1681237330] [2021-11-20 05:52:00,290 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1681237330] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:00,290 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:00,290 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:00,291 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [520349261] [2021-11-20 05:52:00,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:00,291 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:52:00,291 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:52:00,292 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:52:00,292 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:52:00,292 INFO L87 Difference]: Start difference. First operand 924 states and 1374 transitions. cyclomatic complexity: 451 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:00,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:52:00,318 INFO L93 Difference]: Finished difference Result 924 states and 1373 transitions. [2021-11-20 05:52:00,319 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:52:00,321 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1373 transitions. [2021-11-20 05:52:00,330 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-11-20 05:52:00,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1373 transitions. [2021-11-20 05:52:00,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2021-11-20 05:52:00,339 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2021-11-20 05:52:00,339 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1373 transitions. [2021-11-20 05:52:00,342 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:52:00,342 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1373 transitions. [2021-11-20 05:52:00,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1373 transitions. [2021-11-20 05:52:00,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2021-11-20 05:52:00,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4859307359307359) internal successors, (1373), 923 states have internal predecessors, (1373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:00,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1373 transitions. [2021-11-20 05:52:00,363 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1373 transitions. [2021-11-20 05:52:00,363 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1373 transitions. [2021-11-20 05:52:00,363 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-20 05:52:00,363 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1373 transitions. [2021-11-20 05:52:00,369 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-11-20 05:52:00,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:52:00,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:52:00,371 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:00,371 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:00,372 INFO L791 eck$LassoCheckResult]: Stem: 13676#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 13677#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 13919#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13091#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13092#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 13363#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13364#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13861#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13852#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13431#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13432#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13657#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13658#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13513#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13514#L838 assume !(0 == ~M_E~0); 13664#L838-2 assume !(0 == ~T1_E~0); 13053#L843-1 assume !(0 == ~T2_E~0); 13054#L848-1 assume !(0 == ~T3_E~0); 13173#L853-1 assume !(0 == ~T4_E~0); 13501#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13002#L863-1 assume !(0 == ~T6_E~0); 13003#L868-1 assume !(0 == ~T7_E~0); 13893#L873-1 assume !(0 == ~T8_E~0); 13891#L878-1 assume !(0 == ~E_1~0); 13880#L883-1 assume !(0 == ~E_2~0); 13881#L888-1 assume !(0 == ~E_3~0); 13628#L893-1 assume !(0 == ~E_4~0); 13629#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 13905#L903-1 assume !(0 == ~E_6~0); 13879#L908-1 assume !(0 == ~E_7~0); 13755#L913-1 assume !(0 == ~E_8~0); 13067#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13068#L402 assume !(1 == ~m_pc~0); 13280#L402-2 is_master_triggered_~__retres1~0#1 := 0; 13194#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13195#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13437#L1035 assume !(0 != activate_threads_~tmp~1#1); 13438#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13490#L421 assume 1 == ~t1_pc~0; 13875#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13897#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13482#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13483#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 13542#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13902#L440 assume 1 == ~t2_pc~0; 13037#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13038#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13204#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13913#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 13767#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13395#L459 assume !(1 == ~t3_pc~0); 13396#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13874#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13699#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13188#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13189#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13198#L478 assume 1 == ~t4_pc~0; 13199#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13633#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13860#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13369#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 13114#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13115#L497 assume !(1 == ~t5_pc~0); 13159#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13160#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13451#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13452#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 13868#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13869#L516 assume 1 == ~t6_pc~0; 13922#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13654#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13655#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13243#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 13244#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13645#L535 assume !(1 == ~t7_pc~0); 13646#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13715#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13716#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13744#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 13735#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13736#L554 assume 1 == ~t8_pc~0; 13685#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13029#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13785#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13334#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 13335#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13013#L931 assume !(1 == ~M_E~0); 13014#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13888#L936-1 assume !(1 == ~T2_E~0); 13911#L941-1 assume !(1 == ~T3_E~0); 13491#L946-1 assume !(1 == ~T4_E~0); 13492#L951-1 assume !(1 == ~T5_E~0); 13258#L956-1 assume !(1 == ~T6_E~0); 13259#L961-1 assume !(1 == ~T7_E~0); 13630#L966-1 assume !(1 == ~T8_E~0); 13631#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 13738#L976-1 assume !(1 == ~E_2~0); 13707#L981-1 assume !(1 == ~E_3~0); 13496#L986-1 assume !(1 == ~E_4~0); 13288#L991-1 assume !(1 == ~E_5~0); 13289#L996-1 assume !(1 == ~E_6~0); 13898#L1001-1 assume !(1 == ~E_7~0); 13674#L1006-1 assume !(1 == ~E_8~0); 13675#L1011-1 assume { :end_inline_reset_delta_events } true; 13076#L1272-2 [2021-11-20 05:52:00,372 INFO L793 eck$LassoCheckResult]: Loop: 13076#L1272-2 assume !false; 13077#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13078#L813 assume !false; 13079#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13825#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13081#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13627#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13635#L696 assume !(0 != eval_~tmp~0#1); 13678#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13679#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13802#L838-3 assume !(0 == ~M_E~0); 13720#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13721#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13584#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13585#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13632#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13695#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13687#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13688#L873-3 assume !(0 == ~T8_E~0); 13311#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13040#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13041#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13042#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13043#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13517#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13826#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13530#L913-3 assume !(0 == ~E_8~0); 13083#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13084#L402-27 assume 1 == ~m_pc~0; 13030#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13031#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13520#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13521#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13839#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13840#L421-27 assume 1 == ~t1_pc~0; 13750#L422-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13304#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13553#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13554#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13899#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13648#L440-27 assume 1 == ~t2_pc~0; 13649#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13821#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13387#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13388#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13562#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13291#L459-27 assume !(1 == ~t3_pc~0); 13292#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 13710#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13355#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13356#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13644#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13892#L478-27 assume !(1 == ~t4_pc~0); 13281#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 13282#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13656#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13790#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13791#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13827#L497-27 assume 1 == ~t5_pc~0; 13828#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13320#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13321#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13264#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13265#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13522#L516-27 assume 1 == ~t6_pc~0; 13523#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13374#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13375#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13525#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13665#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13454#L535-27 assume !(1 == ~t7_pc~0); 13456#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 13771#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13800#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13801#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13408#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13409#L554-27 assume !(1 == ~t8_pc~0); 13057#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 13058#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13203#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13541#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 13308#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13309#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13184#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13185#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13405#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13537#L946-3 assume !(1 == ~T4_E~0); 13326#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13327#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13606#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13415#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13416#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13653#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13074#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13075#L986-3 assume !(1 == ~E_4~0); 13065#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13066#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13725#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13393#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13394#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13107#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13109#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13423#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 13424#L1291 assume !(0 == start_simulation_~tmp~3#1); 13603#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13509#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13004#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13005#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 13809#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13473#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13474#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 13690#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 13076#L1272-2 [2021-11-20 05:52:00,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:00,373 INFO L85 PathProgramCache]: Analyzing trace with hash -1281590756, now seen corresponding path program 1 times [2021-11-20 05:52:00,373 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:00,373 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [313805837] [2021-11-20 05:52:00,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:00,373 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:00,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:00,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:00,420 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:00,420 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [313805837] [2021-11-20 05:52:00,421 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [313805837] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:00,421 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:00,421 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:00,421 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1873581431] [2021-11-20 05:52:00,421 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:00,422 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:52:00,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:00,422 INFO L85 PathProgramCache]: Analyzing trace with hash -1516707235, now seen corresponding path program 1 times [2021-11-20 05:52:00,423 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:00,423 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973041673] [2021-11-20 05:52:00,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:00,423 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:00,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:00,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:00,455 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:00,455 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [973041673] [2021-11-20 05:52:00,456 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [973041673] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:00,456 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:00,456 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:00,456 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1459039707] [2021-11-20 05:52:00,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:00,457 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:52:00,457 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:52:00,457 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:52:00,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:52:00,458 INFO L87 Difference]: Start difference. First operand 924 states and 1373 transitions. cyclomatic complexity: 450 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:00,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:52:00,482 INFO L93 Difference]: Finished difference Result 924 states and 1372 transitions. [2021-11-20 05:52:00,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:52:00,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1372 transitions. [2021-11-20 05:52:00,492 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-11-20 05:52:00,500 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1372 transitions. [2021-11-20 05:52:00,501 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2021-11-20 05:52:00,502 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2021-11-20 05:52:00,502 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1372 transitions. [2021-11-20 05:52:00,504 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:52:00,504 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1372 transitions. [2021-11-20 05:52:00,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1372 transitions. [2021-11-20 05:52:00,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2021-11-20 05:52:00,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4848484848484849) internal successors, (1372), 923 states have internal predecessors, (1372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:00,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1372 transitions. [2021-11-20 05:52:00,524 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1372 transitions. [2021-11-20 05:52:00,524 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1372 transitions. [2021-11-20 05:52:00,524 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-20 05:52:00,524 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1372 transitions. [2021-11-20 05:52:00,530 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-11-20 05:52:00,530 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:52:00,530 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:52:00,532 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:00,532 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:00,533 INFO L791 eck$LassoCheckResult]: Stem: 15531#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 15532#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 15774#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14946#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14947#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 15218#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15219#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15716#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15706#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15286#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15287#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15512#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 15513#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 15368#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15369#L838 assume !(0 == ~M_E~0); 15519#L838-2 assume !(0 == ~T1_E~0); 14908#L843-1 assume !(0 == ~T2_E~0); 14909#L848-1 assume !(0 == ~T3_E~0); 15028#L853-1 assume !(0 == ~T4_E~0); 15356#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14855#L863-1 assume !(0 == ~T6_E~0); 14856#L868-1 assume !(0 == ~T7_E~0); 15748#L873-1 assume !(0 == ~T8_E~0); 15746#L878-1 assume !(0 == ~E_1~0); 15735#L883-1 assume !(0 == ~E_2~0); 15736#L888-1 assume !(0 == ~E_3~0); 15483#L893-1 assume !(0 == ~E_4~0); 15484#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 15760#L903-1 assume !(0 == ~E_6~0); 15734#L908-1 assume !(0 == ~E_7~0); 15608#L913-1 assume !(0 == ~E_8~0); 14922#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14923#L402 assume !(1 == ~m_pc~0); 15133#L402-2 is_master_triggered_~__retres1~0#1 := 0; 15049#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15050#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15292#L1035 assume !(0 != activate_threads_~tmp~1#1); 15293#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15345#L421 assume 1 == ~t1_pc~0; 15730#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15752#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15337#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15338#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 15397#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15757#L440 assume 1 == ~t2_pc~0; 14892#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14893#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15059#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15768#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 15622#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15250#L459 assume !(1 == ~t3_pc~0); 15251#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15729#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15554#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15043#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15044#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15053#L478 assume 1 == ~t4_pc~0; 15054#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15488#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15715#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15224#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 14969#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14970#L497 assume !(1 == ~t5_pc~0); 15014#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15015#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15306#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15307#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 15723#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15724#L516 assume 1 == ~t6_pc~0; 15777#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15509#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15510#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15098#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 15099#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15500#L535 assume !(1 == ~t7_pc~0); 15501#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15570#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15571#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15599#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 15589#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15590#L554 assume 1 == ~t8_pc~0; 15540#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14884#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15640#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15189#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 15190#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14868#L931 assume !(1 == ~M_E~0); 14869#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15743#L936-1 assume !(1 == ~T2_E~0); 15766#L941-1 assume !(1 == ~T3_E~0); 15346#L946-1 assume !(1 == ~T4_E~0); 15347#L951-1 assume !(1 == ~T5_E~0); 15113#L956-1 assume !(1 == ~T6_E~0); 15114#L961-1 assume !(1 == ~T7_E~0); 15485#L966-1 assume !(1 == ~T8_E~0); 15486#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 15592#L976-1 assume !(1 == ~E_2~0); 15562#L981-1 assume !(1 == ~E_3~0); 15351#L986-1 assume !(1 == ~E_4~0); 15143#L991-1 assume !(1 == ~E_5~0); 15144#L996-1 assume !(1 == ~E_6~0); 15753#L1001-1 assume !(1 == ~E_7~0); 15529#L1006-1 assume !(1 == ~E_8~0); 15530#L1011-1 assume { :end_inline_reset_delta_events } true; 14931#L1272-2 [2021-11-20 05:52:00,533 INFO L793 eck$LassoCheckResult]: Loop: 14931#L1272-2 assume !false; 14932#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14933#L813 assume !false; 14934#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15680#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14936#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15480#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15490#L696 assume !(0 != eval_~tmp~0#1); 15533#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15534#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15657#L838-3 assume !(0 == ~M_E~0); 15575#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15576#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15438#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15439#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15487#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15550#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15542#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15543#L873-3 assume !(0 == ~T8_E~0); 15168#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14895#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14896#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14897#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14898#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15374#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15683#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15385#L913-3 assume !(0 == ~E_8~0); 14938#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14939#L402-27 assume 1 == ~m_pc~0; 14885#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14886#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15379#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15380#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15697#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15698#L421-27 assume 1 == ~t1_pc~0; 15605#L422-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15159#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15408#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15409#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15754#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15503#L440-27 assume 1 == ~t2_pc~0; 15504#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15676#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15242#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15243#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15417#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15146#L459-27 assume !(1 == ~t3_pc~0); 15147#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 15565#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15210#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15211#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15499#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15747#L478-27 assume !(1 == ~t4_pc~0); 15136#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 15137#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15511#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15645#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15646#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15681#L497-27 assume !(1 == ~t5_pc~0); 15298#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 15175#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15176#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15119#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15120#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15375#L516-27 assume 1 == ~t6_pc~0; 15376#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15225#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15226#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15378#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15520#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15309#L535-27 assume 1 == ~t7_pc~0; 15310#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15626#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15655#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15656#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15263#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15264#L554-27 assume !(1 == ~t8_pc~0); 14912#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 14913#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15058#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15396#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 15163#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15164#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15039#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15040#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15260#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15392#L946-3 assume !(1 == ~T4_E~0); 15181#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15182#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15461#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15270#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15271#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15508#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14929#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14930#L986-3 assume !(1 == ~E_4~0); 14920#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14921#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15580#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15248#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15249#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14962#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14964#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15278#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 15279#L1291 assume !(0 == start_simulation_~tmp~3#1); 15458#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15364#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14859#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14860#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 15664#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15328#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15329#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 15545#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 14931#L1272-2 [2021-11-20 05:52:00,534 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:00,534 INFO L85 PathProgramCache]: Analyzing trace with hash -1253090466, now seen corresponding path program 1 times [2021-11-20 05:52:00,534 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:00,535 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806640753] [2021-11-20 05:52:00,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:00,535 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:00,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:00,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:00,570 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:00,570 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1806640753] [2021-11-20 05:52:00,570 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1806640753] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:00,570 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:00,570 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:00,571 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [367650153] [2021-11-20 05:52:00,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:00,571 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:52:00,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:00,572 INFO L85 PathProgramCache]: Analyzing trace with hash 741608413, now seen corresponding path program 1 times [2021-11-20 05:52:00,572 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:00,572 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [573518257] [2021-11-20 05:52:00,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:00,573 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:00,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:00,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:00,604 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:00,604 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [573518257] [2021-11-20 05:52:00,604 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [573518257] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:00,605 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:00,605 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:00,605 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2029611830] [2021-11-20 05:52:00,605 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:00,606 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:52:00,606 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:52:00,606 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 05:52:00,606 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 05:52:00,607 INFO L87 Difference]: Start difference. First operand 924 states and 1372 transitions. cyclomatic complexity: 449 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:00,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:52:00,722 INFO L93 Difference]: Finished difference Result 1751 states and 2595 transitions. [2021-11-20 05:52:00,723 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 05:52:00,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1751 states and 2595 transitions. [2021-11-20 05:52:00,741 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1622 [2021-11-20 05:52:00,755 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1751 states to 1751 states and 2595 transitions. [2021-11-20 05:52:00,755 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1751 [2021-11-20 05:52:00,757 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1751 [2021-11-20 05:52:00,758 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1751 states and 2595 transitions. [2021-11-20 05:52:00,761 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:52:00,761 INFO L681 BuchiCegarLoop]: Abstraction has 1751 states and 2595 transitions. [2021-11-20 05:52:00,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1751 states and 2595 transitions. [2021-11-20 05:52:00,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1751 to 1751. [2021-11-20 05:52:00,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1751 states, 1751 states have (on average 1.4820102798400914) internal successors, (2595), 1750 states have internal predecessors, (2595), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:00,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1751 states to 1751 states and 2595 transitions. [2021-11-20 05:52:00,801 INFO L704 BuchiCegarLoop]: Abstraction has 1751 states and 2595 transitions. [2021-11-20 05:52:00,801 INFO L587 BuchiCegarLoop]: Abstraction has 1751 states and 2595 transitions. [2021-11-20 05:52:00,801 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-20 05:52:00,802 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1751 states and 2595 transitions. [2021-11-20 05:52:00,811 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1622 [2021-11-20 05:52:00,811 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:52:00,812 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:52:00,814 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:00,814 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:00,814 INFO L791 eck$LassoCheckResult]: Stem: 18222#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 18223#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 18480#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17632#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17633#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 17906#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17907#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18409#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18399#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17976#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17977#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18203#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18204#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 18058#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18059#L838 assume !(0 == ~M_E~0); 18210#L838-2 assume !(0 == ~T1_E~0); 17594#L843-1 assume !(0 == ~T2_E~0); 17595#L848-1 assume !(0 == ~T3_E~0); 17714#L853-1 assume !(0 == ~T4_E~0); 18046#L858-1 assume !(0 == ~T5_E~0); 17540#L863-1 assume !(0 == ~T6_E~0); 17541#L868-1 assume !(0 == ~T7_E~0); 18444#L873-1 assume !(0 == ~T8_E~0); 18442#L878-1 assume !(0 == ~E_1~0); 18429#L883-1 assume !(0 == ~E_2~0); 18430#L888-1 assume !(0 == ~E_3~0); 18174#L893-1 assume !(0 == ~E_4~0); 18175#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 18458#L903-1 assume !(0 == ~E_6~0); 18428#L908-1 assume !(0 == ~E_7~0); 18299#L913-1 assume !(0 == ~E_8~0); 17608#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17609#L402 assume !(1 == ~m_pc~0); 17822#L402-2 is_master_triggered_~__retres1~0#1 := 0; 17736#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17737#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17982#L1035 assume !(0 != activate_threads_~tmp~1#1); 17983#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18035#L421 assume 1 == ~t1_pc~0; 18424#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18448#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18027#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18028#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 18087#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18454#L440 assume 1 == ~t2_pc~0; 17577#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17578#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17746#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18469#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 18313#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17940#L459 assume !(1 == ~t3_pc~0); 17941#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 18422#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18245#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17730#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17731#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17740#L478 assume 1 == ~t4_pc~0; 17741#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18179#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18408#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17912#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 17655#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17656#L497 assume !(1 == ~t5_pc~0); 17700#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17701#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17996#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17997#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 18416#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18417#L516 assume 1 == ~t6_pc~0; 18483#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18200#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18201#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17785#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 17786#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18191#L535 assume !(1 == ~t7_pc~0); 18192#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18261#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18262#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18290#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 18281#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18282#L554 assume 1 == ~t8_pc~0; 18231#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17569#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18332#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17877#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 17878#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17553#L931 assume !(1 == ~M_E~0); 17554#L931-2 assume !(1 == ~T1_E~0); 18437#L936-1 assume !(1 == ~T2_E~0); 18467#L941-1 assume !(1 == ~T3_E~0); 18036#L946-1 assume !(1 == ~T4_E~0); 18037#L951-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18423#L956-1 assume !(1 == ~T6_E~0); 18976#L961-1 assume !(1 == ~T7_E~0); 18974#L966-1 assume !(1 == ~T8_E~0); 18972#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 18970#L976-1 assume !(1 == ~E_2~0); 18559#L981-1 assume !(1 == ~E_3~0); 18549#L986-1 assume !(1 == ~E_4~0); 18547#L991-1 assume !(1 == ~E_5~0); 18545#L996-1 assume !(1 == ~E_6~0); 18543#L1001-1 assume !(1 == ~E_7~0); 18530#L1006-1 assume !(1 == ~E_8~0); 18522#L1011-1 assume { :end_inline_reset_delta_events } true; 18514#L1272-2 [2021-11-20 05:52:00,815 INFO L793 eck$LassoCheckResult]: Loop: 18514#L1272-2 assume !false; 18509#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18506#L813 assume !false; 18505#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 18503#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 18495#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 18494#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18493#L696 assume !(0 != eval_~tmp~0#1); 18492#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18491#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18490#L838-3 assume !(0 == ~M_E~0); 18488#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18489#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19290#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19289#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19288#L858-3 assume !(0 == ~T5_E~0); 19287#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19286#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19285#L873-3 assume !(0 == ~T8_E~0); 19284#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19283#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19282#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19281#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19280#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19279#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19278#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19277#L913-3 assume !(0 == ~E_8~0); 19276#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19275#L402-27 assume 1 == ~m_pc~0; 19273#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19272#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19271#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19270#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19269#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19268#L421-27 assume 1 == ~t1_pc~0; 19266#L422-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19265#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19264#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19263#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19262#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19261#L440-27 assume 1 == ~t2_pc~0; 19259#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19258#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19257#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19256#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19255#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19254#L459-27 assume !(1 == ~t3_pc~0); 19252#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 19251#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19250#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19249#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19248#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19247#L478-27 assume 1 == ~t4_pc~0; 19245#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19244#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19243#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19242#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19241#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19240#L497-27 assume !(1 == ~t5_pc~0); 19238#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 19237#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19236#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19235#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19234#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19233#L516-27 assume !(1 == ~t6_pc~0); 19232#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 19230#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19229#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19228#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19227#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19226#L535-27 assume !(1 == ~t7_pc~0); 19224#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 19223#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19222#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19221#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19220#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19219#L554-27 assume 1 == ~t8_pc~0; 19217#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19216#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19215#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19214#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 19090#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19089#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19088#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17726#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19087#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19086#L946-3 assume !(1 == ~T4_E~0); 19085#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17869#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19083#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19080#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19078#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19076#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19074#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19072#L986-3 assume !(1 == ~E_4~0); 19070#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19067#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19065#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19063#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19061#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 18611#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 18601#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 18599#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 18598#L1291 assume !(0 == start_simulation_~tmp~3#1); 18595#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 18550#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 18548#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 18546#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 18544#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18542#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18529#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 18521#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 18514#L1272-2 [2021-11-20 05:52:00,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:00,816 INFO L85 PathProgramCache]: Analyzing trace with hash -378149536, now seen corresponding path program 1 times [2021-11-20 05:52:00,816 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:00,838 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [547613686] [2021-11-20 05:52:00,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:00,838 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:00,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:00,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:00,893 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:00,893 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [547613686] [2021-11-20 05:52:00,893 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [547613686] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:00,894 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:00,894 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:00,894 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1694434576] [2021-11-20 05:52:00,894 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:00,895 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:52:00,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:00,895 INFO L85 PathProgramCache]: Analyzing trace with hash 996333343, now seen corresponding path program 1 times [2021-11-20 05:52:00,895 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:00,896 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1191993312] [2021-11-20 05:52:00,896 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:00,896 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:00,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:00,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:00,947 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:00,947 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1191993312] [2021-11-20 05:52:00,948 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1191993312] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:00,948 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:00,948 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:00,948 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [258577529] [2021-11-20 05:52:00,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:00,949 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:52:00,949 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:52:00,949 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 05:52:00,950 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 05:52:00,950 INFO L87 Difference]: Start difference. First operand 1751 states and 2595 transitions. cyclomatic complexity: 846 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:01,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:52:01,153 INFO L93 Difference]: Finished difference Result 3261 states and 4828 transitions. [2021-11-20 05:52:01,154 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 05:52:01,155 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3261 states and 4828 transitions. [2021-11-20 05:52:01,181 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3114 [2021-11-20 05:52:01,209 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3261 states to 3261 states and 4828 transitions. [2021-11-20 05:52:01,209 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3261 [2021-11-20 05:52:01,215 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3261 [2021-11-20 05:52:01,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3261 states and 4828 transitions. [2021-11-20 05:52:01,220 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:52:01,220 INFO L681 BuchiCegarLoop]: Abstraction has 3261 states and 4828 transitions. [2021-11-20 05:52:01,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3261 states and 4828 transitions. [2021-11-20 05:52:01,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3261 to 3259. [2021-11-20 05:52:01,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3259 states, 3259 states have (on average 1.4808223381405339) internal successors, (4826), 3258 states have internal predecessors, (4826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:01,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3259 states to 3259 states and 4826 transitions. [2021-11-20 05:52:01,317 INFO L704 BuchiCegarLoop]: Abstraction has 3259 states and 4826 transitions. [2021-11-20 05:52:01,317 INFO L587 BuchiCegarLoop]: Abstraction has 3259 states and 4826 transitions. [2021-11-20 05:52:01,318 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-20 05:52:01,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3259 states and 4826 transitions. [2021-11-20 05:52:01,334 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3114 [2021-11-20 05:52:01,334 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:52:01,334 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:52:01,336 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:01,336 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:01,337 INFO L791 eck$LassoCheckResult]: Stem: 23272#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 23273#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 23577#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22654#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22655#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 22935#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22936#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23499#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23486#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23007#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23008#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23252#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 23253#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 23094#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23095#L838 assume !(0 == ~M_E~0); 23259#L838-2 assume !(0 == ~T1_E~0); 22616#L843-1 assume !(0 == ~T2_E~0); 22617#L848-1 assume !(0 == ~T3_E~0); 22736#L853-1 assume !(0 == ~T4_E~0); 23080#L858-1 assume !(0 == ~T5_E~0); 22562#L863-1 assume !(0 == ~T6_E~0); 22563#L868-1 assume !(0 == ~T7_E~0); 23540#L873-1 assume !(0 == ~T8_E~0); 23538#L878-1 assume !(0 == ~E_1~0); 23523#L883-1 assume !(0 == ~E_2~0); 23524#L888-1 assume !(0 == ~E_3~0); 23222#L893-1 assume !(0 == ~E_4~0); 23223#L898-1 assume !(0 == ~E_5~0); 23554#L903-1 assume !(0 == ~E_6~0); 23522#L908-1 assume !(0 == ~E_7~0); 23358#L913-1 assume !(0 == ~E_8~0); 22630#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22631#L402 assume !(1 == ~m_pc~0); 22841#L402-2 is_master_triggered_~__retres1~0#1 := 0; 22757#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22758#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23013#L1035 assume !(0 != activate_threads_~tmp~1#1); 23014#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23070#L421 assume 1 == ~t1_pc~0; 23518#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23541#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23059#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23060#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 23124#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23550#L440 assume 1 == ~t2_pc~0; 22599#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22600#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22767#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23565#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 23377#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22963#L459 assume !(1 == ~t3_pc~0); 22964#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23516#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23296#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22751#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22752#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22761#L478 assume 1 == ~t4_pc~0; 22762#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23227#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23498#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22941#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 22675#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22676#L497 assume !(1 == ~t5_pc~0); 22722#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 22723#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23027#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23028#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 23509#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23510#L516 assume 1 == ~t6_pc~0; 23590#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23250#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23251#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22807#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 22808#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23241#L535 assume !(1 == ~t7_pc~0); 23242#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 23313#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23314#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23348#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 23336#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23337#L554 assume 1 == ~t8_pc~0; 23280#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22591#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23399#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22900#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 22901#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22575#L931 assume !(1 == ~M_E~0); 22576#L931-2 assume !(1 == ~T1_E~0); 23533#L936-1 assume !(1 == ~T2_E~0); 23562#L941-1 assume !(1 == ~T3_E~0); 23071#L946-1 assume !(1 == ~T4_E~0); 23072#L951-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23819#L956-1 assume !(1 == ~T6_E~0); 23937#L961-1 assume !(1 == ~T7_E~0); 23935#L966-1 assume !(1 == ~T8_E~0); 23933#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 23931#L976-1 assume !(1 == ~E_2~0); 23929#L981-1 assume !(1 == ~E_3~0); 23927#L986-1 assume !(1 == ~E_4~0); 23677#L991-1 assume 1 == ~E_5~0;~E_5~0 := 2; 23663#L996-1 assume !(1 == ~E_6~0); 23661#L1001-1 assume !(1 == ~E_7~0); 23649#L1006-1 assume !(1 == ~E_8~0); 23640#L1011-1 assume { :end_inline_reset_delta_events } true; 23632#L1272-2 [2021-11-20 05:52:01,337 INFO L793 eck$LassoCheckResult]: Loop: 23632#L1272-2 assume !false; 23626#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23622#L813 assume !false; 23621#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 23619#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 23611#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 23610#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23608#L696 assume !(0 != eval_~tmp~0#1); 23607#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23606#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23605#L838-3 assume !(0 == ~M_E~0); 23603#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23604#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24851#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24850#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24849#L858-3 assume !(0 == ~T5_E~0); 24848#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24847#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24846#L873-3 assume !(0 == ~T8_E~0); 24845#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24844#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24843#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24842#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24841#L898-3 assume !(0 == ~E_5~0); 24840#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24839#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24838#L913-3 assume !(0 == ~E_8~0); 24837#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24836#L402-27 assume 1 == ~m_pc~0; 24834#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24833#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24832#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 24831#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24830#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24829#L421-27 assume 1 == ~t1_pc~0; 24827#L422-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24826#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24825#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24824#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24823#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24822#L440-27 assume 1 == ~t2_pc~0; 24820#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24819#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24818#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24817#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24816#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24815#L459-27 assume !(1 == ~t3_pc~0); 24813#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 24812#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24811#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24810#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24809#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24806#L478-27 assume 1 == ~t4_pc~0; 24807#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25745#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25744#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25743#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25742#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25741#L497-27 assume !(1 == ~t5_pc~0); 25739#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 25738#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25737#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25736#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25735#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25734#L516-27 assume 1 == ~t6_pc~0; 24788#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24787#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24786#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24785#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24784#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24781#L535-27 assume 1 == ~t7_pc~0; 24782#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25728#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25727#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23571#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22982#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22983#L554-27 assume !(1 == ~t8_pc~0); 22620#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 22621#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22766#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23125#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 22874#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22875#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22747#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22748#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24178#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23380#L946-3 assume !(1 == ~T4_E~0); 23381#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22895#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24104#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24089#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24087#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24085#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24069#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22876#L986-3 assume !(1 == ~E_4~0); 22877#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24029#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24022#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24017#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24012#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 24006#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 23994#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 23989#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 23983#L1291 assume !(0 == start_simulation_~tmp~3#1); 23981#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 23970#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 23678#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 23676#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 23662#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23650#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23648#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 23639#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 23632#L1272-2 [2021-11-20 05:52:01,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:01,338 INFO L85 PathProgramCache]: Analyzing trace with hash -352930976, now seen corresponding path program 1 times [2021-11-20 05:52:01,338 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:01,338 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [348694682] [2021-11-20 05:52:01,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:01,339 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:01,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:01,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:01,375 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:01,375 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [348694682] [2021-11-20 05:52:01,375 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [348694682] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:01,376 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:01,376 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:01,376 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1501589418] [2021-11-20 05:52:01,376 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:01,377 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:52:01,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:01,377 INFO L85 PathProgramCache]: Analyzing trace with hash -816537150, now seen corresponding path program 1 times [2021-11-20 05:52:01,377 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:01,378 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1232382323] [2021-11-20 05:52:01,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:01,378 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:01,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:01,434 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:01,434 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:01,435 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1232382323] [2021-11-20 05:52:01,435 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1232382323] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:01,435 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:01,435 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:01,435 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [395042917] [2021-11-20 05:52:01,435 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:01,436 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:52:01,436 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:52:01,437 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 05:52:01,437 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 05:52:01,437 INFO L87 Difference]: Start difference. First operand 3259 states and 4826 transitions. cyclomatic complexity: 1571 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:01,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:52:01,713 INFO L93 Difference]: Finished difference Result 9071 states and 13248 transitions. [2021-11-20 05:52:01,714 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 05:52:01,714 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9071 states and 13248 transitions. [2021-11-20 05:52:01,769 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8640 [2021-11-20 05:52:01,838 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9071 states to 9071 states and 13248 transitions. [2021-11-20 05:52:01,838 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9071 [2021-11-20 05:52:01,855 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9071 [2021-11-20 05:52:01,855 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9071 states and 13248 transitions. [2021-11-20 05:52:01,869 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:52:01,869 INFO L681 BuchiCegarLoop]: Abstraction has 9071 states and 13248 transitions. [2021-11-20 05:52:01,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9071 states and 13248 transitions. [2021-11-20 05:52:02,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9071 to 8575. [2021-11-20 05:52:02,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8575 states, 8575 states have (on average 1.4656559766763848) internal successors, (12568), 8574 states have internal predecessors, (12568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:02,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8575 states to 8575 states and 12568 transitions. [2021-11-20 05:52:02,149 INFO L704 BuchiCegarLoop]: Abstraction has 8575 states and 12568 transitions. [2021-11-20 05:52:02,150 INFO L587 BuchiCegarLoop]: Abstraction has 8575 states and 12568 transitions. [2021-11-20 05:52:02,150 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-20 05:52:02,150 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8575 states and 12568 transitions. [2021-11-20 05:52:02,205 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8412 [2021-11-20 05:52:02,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:52:02,206 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:52:02,208 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:02,208 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:02,209 INFO L791 eck$LassoCheckResult]: Stem: 35605#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 35606#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 35930#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34997#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34998#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 35270#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35271#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35828#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35815#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35341#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35342#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35580#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35581#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35428#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35429#L838 assume !(0 == ~M_E~0); 35589#L838-2 assume !(0 == ~T1_E~0); 34958#L843-1 assume !(0 == ~T2_E~0); 34959#L848-1 assume !(0 == ~T3_E~0); 35078#L853-1 assume !(0 == ~T4_E~0); 35414#L858-1 assume !(0 == ~T5_E~0); 34902#L863-1 assume !(0 == ~T6_E~0); 34903#L868-1 assume !(0 == ~T7_E~0); 35880#L873-1 assume !(0 == ~T8_E~0); 35877#L878-1 assume !(0 == ~E_1~0); 35851#L883-1 assume !(0 == ~E_2~0); 35852#L888-1 assume !(0 == ~E_3~0); 35553#L893-1 assume !(0 == ~E_4~0); 35554#L898-1 assume !(0 == ~E_5~0); 35903#L903-1 assume !(0 == ~E_6~0); 35850#L908-1 assume !(0 == ~E_7~0); 35691#L913-1 assume !(0 == ~E_8~0); 34973#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34974#L402 assume !(1 == ~m_pc~0); 35392#L402-2 is_master_triggered_~__retres1~0#1 := 0; 35100#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35101#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 35347#L1035 assume !(0 != activate_threads_~tmp~1#1); 35348#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35405#L421 assume !(1 == ~t1_pc~0); 35846#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35881#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35395#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 35396#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 35460#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35893#L440 assume 1 == ~t2_pc~0; 34941#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34942#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35110#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 35916#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 35710#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35301#L459 assume !(1 == ~t3_pc~0); 35302#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 35844#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35632#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 35093#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35094#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35104#L478 assume 1 == ~t4_pc~0; 35105#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35557#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35827#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35276#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 35017#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35018#L497 assume !(1 == ~t5_pc~0); 35064#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 35065#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35361#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35362#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 35836#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35837#L516 assume 1 == ~t6_pc~0; 35945#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35578#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35579#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35149#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 35150#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35569#L535 assume !(1 == ~t7_pc~0); 35570#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 35649#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35650#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35680#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 35670#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35671#L554 assume 1 == ~t8_pc~0; 35614#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34931#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35730#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35235#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 35236#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34915#L931 assume !(1 == ~M_E~0); 34916#L931-2 assume !(1 == ~T1_E~0); 35866#L936-1 assume !(1 == ~T2_E~0); 41500#L941-1 assume !(1 == ~T3_E~0); 41499#L946-1 assume !(1 == ~T4_E~0); 41498#L951-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41489#L956-1 assume !(1 == ~T6_E~0); 41467#L961-1 assume !(1 == ~T7_E~0); 41465#L966-1 assume !(1 == ~T8_E~0); 41439#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 41433#L976-1 assume !(1 == ~E_2~0); 41413#L981-1 assume !(1 == ~E_3~0); 41400#L986-1 assume !(1 == ~E_4~0); 41386#L991-1 assume 1 == ~E_5~0;~E_5~0 := 2; 35194#L996-1 assume !(1 == ~E_6~0); 42639#L1001-1 assume !(1 == ~E_7~0); 42637#L1006-1 assume !(1 == ~E_8~0); 42631#L1011-1 assume { :end_inline_reset_delta_events } true; 42630#L1272-2 [2021-11-20 05:52:02,209 INFO L793 eck$LassoCheckResult]: Loop: 42630#L1272-2 assume !false; 35595#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34984#L813 assume !false; 34985#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 35781#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 34987#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 35549#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 35559#L696 assume !(0 != eval_~tmp~0#1); 42611#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42610#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35819#L838-3 assume !(0 == ~M_E~0); 35820#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42609#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42862#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42861#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 42860#L858-3 assume !(0 == ~T5_E~0); 42859#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42858#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42857#L873-3 assume !(0 == ~T8_E~0); 42856#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42855#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42854#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42853#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42852#L898-3 assume !(0 == ~E_5~0); 42851#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42850#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42849#L913-3 assume !(0 == ~E_8~0); 42848#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42847#L402-27 assume !(1 == ~m_pc~0); 42846#L402-29 is_master_triggered_~__retres1~0#1 := 0; 42845#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42844#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 42843#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42842#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42841#L421-27 assume !(1 == ~t1_pc~0); 42840#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 42839#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42838#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 42837#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42836#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42835#L440-27 assume 1 == ~t2_pc~0; 42833#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42832#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42831#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 42830#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42829#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42828#L459-27 assume !(1 == ~t3_pc~0); 42826#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 42825#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42824#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 42823#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42822#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42821#L478-27 assume 1 == ~t4_pc~0; 42819#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42818#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42817#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 42816#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42815#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42814#L497-27 assume !(1 == ~t5_pc~0); 42812#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 42811#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42810#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42809#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42808#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42807#L516-27 assume 1 == ~t6_pc~0; 42805#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42804#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42803#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42802#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42801#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35363#L535-27 assume 1 == ~t7_pc~0; 35364#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35715#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35752#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35753#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35314#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35315#L554-27 assume !(1 == ~t8_pc~0); 34962#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 34963#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35109#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35459#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 35211#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35212#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35089#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35090#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35313#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35455#L946-3 assume !(1 == ~T4_E~0); 37199#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37198#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37197#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37196#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37195#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37194#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37193#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37192#L986-3 assume !(1 == ~E_4~0); 37191#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37190#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37189#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37188#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35699#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 35700#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 42740#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 42739#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 42735#L1291 assume !(0 == start_simulation_~tmp~3#1); 42732#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 35423#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 34906#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 34907#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 35760#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35384#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35385#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 35621#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 42630#L1272-2 [2021-11-20 05:52:02,210 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:02,210 INFO L85 PathProgramCache]: Analyzing trace with hash -1530905537, now seen corresponding path program 1 times [2021-11-20 05:52:02,210 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:02,210 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1878250188] [2021-11-20 05:52:02,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:02,210 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:02,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:02,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:02,245 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:02,245 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1878250188] [2021-11-20 05:52:02,245 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1878250188] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:02,245 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:02,245 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:02,246 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1493002009] [2021-11-20 05:52:02,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:02,246 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:52:02,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:02,247 INFO L85 PathProgramCache]: Analyzing trace with hash 1746371392, now seen corresponding path program 1 times [2021-11-20 05:52:02,247 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:02,247 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1062160210] [2021-11-20 05:52:02,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:02,247 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:02,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:02,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:02,281 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:02,282 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1062160210] [2021-11-20 05:52:02,282 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1062160210] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:02,282 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:02,282 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:02,282 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386500746] [2021-11-20 05:52:02,282 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:02,283 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:52:02,283 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:52:02,283 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 05:52:02,283 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 05:52:02,284 INFO L87 Difference]: Start difference. First operand 8575 states and 12568 transitions. cyclomatic complexity: 4001 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:02,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:52:02,690 INFO L93 Difference]: Finished difference Result 24202 states and 35119 transitions. [2021-11-20 05:52:02,691 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 05:52:02,691 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24202 states and 35119 transitions. [2021-11-20 05:52:02,829 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23412 [2021-11-20 05:52:03,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24202 states to 24202 states and 35119 transitions. [2021-11-20 05:52:03,033 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24202 [2021-11-20 05:52:03,045 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24202 [2021-11-20 05:52:03,045 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24202 states and 35119 transitions. [2021-11-20 05:52:03,068 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:52:03,068 INFO L681 BuchiCegarLoop]: Abstraction has 24202 states and 35119 transitions. [2021-11-20 05:52:03,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24202 states and 35119 transitions. [2021-11-20 05:52:03,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24202 to 23014. [2021-11-20 05:52:03,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23014 states, 23014 states have (on average 1.4559398626922744) internal successors, (33507), 23013 states have internal predecessors, (33507), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:03,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23014 states to 23014 states and 33507 transitions. [2021-11-20 05:52:03,876 INFO L704 BuchiCegarLoop]: Abstraction has 23014 states and 33507 transitions. [2021-11-20 05:52:03,876 INFO L587 BuchiCegarLoop]: Abstraction has 23014 states and 33507 transitions. [2021-11-20 05:52:03,876 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-20 05:52:03,876 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23014 states and 33507 transitions. [2021-11-20 05:52:04,057 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22812 [2021-11-20 05:52:04,058 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:52:04,058 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:52:04,060 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:04,060 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:04,061 INFO L791 eck$LassoCheckResult]: Stem: 68418#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 68419#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 68804#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67779#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67780#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 68055#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68056#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68686#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68664#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68131#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68132#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68396#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 68397#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68220#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68221#L838 assume !(0 == ~M_E~0); 68404#L838-2 assume !(0 == ~T1_E~0); 67740#L843-1 assume !(0 == ~T2_E~0); 67741#L848-1 assume !(0 == ~T3_E~0); 67859#L853-1 assume !(0 == ~T4_E~0); 68206#L858-1 assume !(0 == ~T5_E~0); 67689#L863-1 assume !(0 == ~T6_E~0); 67690#L868-1 assume !(0 == ~T7_E~0); 68745#L873-1 assume !(0 == ~T8_E~0); 68741#L878-1 assume !(0 == ~E_1~0); 68718#L883-1 assume !(0 == ~E_2~0); 68719#L888-1 assume !(0 == ~E_3~0); 68364#L893-1 assume !(0 == ~E_4~0); 68365#L898-1 assume !(0 == ~E_5~0); 68771#L903-1 assume !(0 == ~E_6~0); 68716#L908-1 assume !(0 == ~E_7~0); 68519#L913-1 assume !(0 == ~E_8~0); 67755#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67756#L402 assume !(1 == ~m_pc~0); 68181#L402-2 is_master_triggered_~__retres1~0#1 := 0; 67881#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67882#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68137#L1035 assume !(0 != activate_threads_~tmp~1#1); 68138#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68196#L421 assume !(1 == ~t1_pc~0); 68710#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68747#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68184#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68185#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 68252#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68765#L440 assume !(1 == ~t2_pc~0); 68840#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 67892#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67893#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68787#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 68538#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68084#L459 assume !(1 == ~t3_pc~0); 68085#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 68705#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68446#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 67874#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 67875#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67885#L478 assume 1 == ~t4_pc~0; 67886#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68369#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68685#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 68061#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 67799#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67800#L497 assume !(1 == ~t5_pc~0); 67845#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 67846#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68151#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 68152#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 68696#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68697#L516 assume 1 == ~t6_pc~0; 68823#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 68394#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68395#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67933#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 67934#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68385#L535 assume !(1 == ~t7_pc~0); 68386#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68470#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68471#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68509#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 68494#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68495#L554 assume 1 == ~t8_pc~0; 68428#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 67718#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68563#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68024#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 68025#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67702#L931 assume !(1 == ~M_E~0); 67703#L931-2 assume !(1 == ~T1_E~0); 68736#L936-1 assume !(1 == ~T2_E~0); 68782#L941-1 assume !(1 == ~T3_E~0); 68197#L946-1 assume !(1 == ~T4_E~0); 68198#L951-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 72330#L956-1 assume !(1 == ~T6_E~0); 68824#L961-1 assume !(1 == ~T7_E~0); 68825#L966-1 assume !(1 == ~T8_E~0); 68498#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 68499#L976-1 assume !(1 == ~E_2~0); 68459#L981-1 assume !(1 == ~E_3~0); 68460#L986-1 assume !(1 == ~E_4~0); 67978#L991-1 assume 1 == ~E_5~0;~E_5~0 := 2; 67979#L996-1 assume !(1 == ~E_6~0); 72743#L1001-1 assume !(1 == ~E_7~0); 72742#L1006-1 assume !(1 == ~E_8~0); 72740#L1011-1 assume { :end_inline_reset_delta_events } true; 72741#L1272-2 [2021-11-20 05:52:04,061 INFO L793 eck$LassoCheckResult]: Loop: 72741#L1272-2 assume !false; 72675#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 72672#L813 assume !false; 72657#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 72658#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 74940#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 74939#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 72523#L696 assume !(0 != eval_~tmp~0#1); 72525#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 74156#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 74142#L838-3 assume !(0 == ~M_E~0); 74143#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 74129#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 74130#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 74113#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 74114#L858-3 assume !(0 == ~T5_E~0); 74100#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 74094#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 74086#L873-3 assume !(0 == ~T8_E~0); 74087#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 74070#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 74071#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 74056#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 74057#L898-3 assume !(0 == ~E_5~0); 74041#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 74042#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 74025#L913-3 assume !(0 == ~E_8~0); 74026#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74009#L402-27 assume !(1 == ~m_pc~0); 74010#L402-29 is_master_triggered_~__retres1~0#1 := 0; 73993#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73994#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 73974#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 73975#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73958#L421-27 assume !(1 == ~t1_pc~0); 73959#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 73943#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73944#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 73924#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 73925#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73908#L440-27 assume !(1 == ~t2_pc~0); 73909#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 73895#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73896#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 73864#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 73865#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 73856#L459-27 assume !(1 == ~t3_pc~0); 73857#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 73849#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 73850#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 73843#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 73844#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 73835#L478-27 assume !(1 == ~t4_pc~0); 73837#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 73827#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73828#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 73820#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 73821#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73813#L497-27 assume 1 == ~t5_pc~0; 73815#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 73806#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 73807#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 73799#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 73800#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 73792#L516-27 assume 1 == ~t6_pc~0; 73793#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 73785#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 73786#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 73780#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 73781#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 73775#L535-27 assume !(1 == ~t7_pc~0); 73777#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 73769#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 73770#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 73763#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 73764#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 73756#L554-27 assume !(1 == ~t8_pc~0); 73757#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 73745#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 73746#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 73739#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 73740#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73732#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 73733#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 73261#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 73727#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 72949#L946-3 assume !(1 == ~T4_E~0); 72950#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 72937#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 72938#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 72929#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 72930#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 72919#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 72920#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 72911#L986-3 assume !(1 == ~E_4~0); 72912#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 72901#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 72902#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 72893#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 72894#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 72884#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 72873#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 72870#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 72868#L1291 assume !(0 == start_simulation_~tmp~3#1); 72866#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 72757#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 72755#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 72753#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 72750#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 72747#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 72748#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 76456#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 72741#L1272-2 [2021-11-20 05:52:04,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:04,062 INFO L85 PathProgramCache]: Analyzing trace with hash 857577566, now seen corresponding path program 1 times [2021-11-20 05:52:04,062 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:04,062 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702364562] [2021-11-20 05:52:04,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:04,062 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:04,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:04,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:04,120 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:04,120 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [702364562] [2021-11-20 05:52:04,120 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [702364562] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:04,120 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:04,121 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-20 05:52:04,121 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [320110595] [2021-11-20 05:52:04,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:04,121 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:52:04,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:04,122 INFO L85 PathProgramCache]: Analyzing trace with hash 1391123326, now seen corresponding path program 1 times [2021-11-20 05:52:04,122 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:04,122 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1964088564] [2021-11-20 05:52:04,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:04,122 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:04,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:04,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:04,179 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:04,179 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1964088564] [2021-11-20 05:52:04,179 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1964088564] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:04,179 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:04,180 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:04,180 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1811815641] [2021-11-20 05:52:04,180 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:04,181 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:52:04,181 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:52:04,181 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-20 05:52:04,182 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-20 05:52:04,182 INFO L87 Difference]: Start difference. First operand 23014 states and 33507 transitions. cyclomatic complexity: 10509 Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:04,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:52:04,988 INFO L93 Difference]: Finished difference Result 61183 states and 89474 transitions. [2021-11-20 05:52:04,989 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-20 05:52:04,990 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61183 states and 89474 transitions. [2021-11-20 05:52:05,481 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 60698 [2021-11-20 05:52:05,730 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61183 states to 61183 states and 89474 transitions. [2021-11-20 05:52:05,731 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61183 [2021-11-20 05:52:05,772 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61183 [2021-11-20 05:52:05,773 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61183 states and 89474 transitions. [2021-11-20 05:52:05,943 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:52:05,944 INFO L681 BuchiCegarLoop]: Abstraction has 61183 states and 89474 transitions. [2021-11-20 05:52:06,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61183 states and 89474 transitions. [2021-11-20 05:52:07,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61183 to 23839. [2021-11-20 05:52:07,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23839 states, 23839 states have (on average 1.4401610805822391) internal successors, (34332), 23838 states have internal predecessors, (34332), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:07,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23839 states to 23839 states and 34332 transitions. [2021-11-20 05:52:07,287 INFO L704 BuchiCegarLoop]: Abstraction has 23839 states and 34332 transitions. [2021-11-20 05:52:07,287 INFO L587 BuchiCegarLoop]: Abstraction has 23839 states and 34332 transitions. [2021-11-20 05:52:07,287 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-20 05:52:07,287 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23839 states and 34332 transitions. [2021-11-20 05:52:07,373 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23634 [2021-11-20 05:52:07,373 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:52:07,373 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:52:07,375 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:07,376 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:07,376 INFO L791 eck$LassoCheckResult]: Stem: 152603#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 152604#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 152943#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 151987#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 151988#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 152260#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 152261#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 152829#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 152816#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 152333#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 152334#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 152582#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 152583#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 152420#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 152421#L838 assume !(0 == ~M_E~0); 152590#L838-2 assume !(0 == ~T1_E~0); 151949#L843-1 assume !(0 == ~T2_E~0); 151950#L848-1 assume !(0 == ~T3_E~0); 152067#L853-1 assume !(0 == ~T4_E~0); 152406#L858-1 assume !(0 == ~T5_E~0); 151899#L863-1 assume !(0 == ~T6_E~0); 151900#L868-1 assume !(0 == ~T7_E~0); 152896#L873-1 assume !(0 == ~T8_E~0); 152891#L878-1 assume !(0 == ~E_1~0); 152864#L883-1 assume !(0 == ~E_2~0); 152865#L888-1 assume !(0 == ~E_3~0); 152553#L893-1 assume !(0 == ~E_4~0); 152554#L898-1 assume !(0 == ~E_5~0); 152919#L903-1 assume !(0 == ~E_6~0); 152862#L908-1 assume !(0 == ~E_7~0); 152697#L913-1 assume !(0 == ~E_8~0); 151963#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 151964#L402 assume !(1 == ~m_pc~0); 152384#L402-2 is_master_triggered_~__retres1~0#1 := 0; 152089#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 152090#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 152340#L1035 assume !(0 != activate_threads_~tmp~1#1); 152341#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 152396#L421 assume !(1 == ~t1_pc~0); 152854#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 152898#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 152387#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 152388#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 152450#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 152913#L440 assume !(1 == ~t2_pc~0); 152979#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 152099#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 152100#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 152931#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 152710#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 152289#L459 assume !(1 == ~t3_pc~0); 152290#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 152850#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152911#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 152082#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 152083#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 152093#L478 assume 1 == ~t4_pc~0; 152094#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 152557#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 152828#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 152266#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 152007#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 152008#L497 assume !(1 == ~t5_pc~0); 152053#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 152054#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 152355#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 152356#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 152841#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 152842#L516 assume 1 == ~t6_pc~0; 152967#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 152580#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 152581#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 152139#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 152140#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 152572#L535 assume !(1 == ~t7_pc~0); 152573#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 152653#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 152654#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 152685#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 152674#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 152675#L554 assume 1 == ~t8_pc~0; 152612#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 151928#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 152730#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 152228#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 152229#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 151912#L931 assume !(1 == ~M_E~0); 151913#L931-2 assume !(1 == ~T1_E~0); 152878#L936-1 assume !(1 == ~T2_E~0); 158250#L941-1 assume !(1 == ~T3_E~0); 158249#L946-1 assume !(1 == ~T4_E~0); 158247#L951-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 158248#L956-1 assume !(1 == ~T6_E~0); 152968#L961-1 assume !(1 == ~T7_E~0); 152969#L966-1 assume !(1 == ~T8_E~0); 152678#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 152679#L976-1 assume !(1 == ~E_2~0); 152644#L981-1 assume !(1 == ~E_3~0); 152645#L986-1 assume !(1 == ~E_4~0); 152185#L991-1 assume 1 == ~E_5~0;~E_5~0 := 2; 152186#L996-1 assume !(1 == ~E_6~0); 158815#L1001-1 assume !(1 == ~E_7~0); 158814#L1006-1 assume !(1 == ~E_8~0); 152851#L1011-1 assume { :end_inline_reset_delta_events } true; 152852#L1272-2 [2021-11-20 05:52:07,376 INFO L793 eck$LassoCheckResult]: Loop: 152852#L1272-2 assume !false; 160282#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 161905#L813 assume !false; 161904#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 159058#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 159050#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 159049#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 158879#L696 assume !(0 != eval_~tmp~0#1); 158881#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 161284#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 161283#L838-3 assume !(0 == ~M_E~0); 161281#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 161282#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 161277#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 161278#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 161273#L858-3 assume !(0 == ~T5_E~0); 161274#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 161259#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 161260#L873-3 assume !(0 == ~T8_E~0); 161255#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 161256#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 161251#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 161252#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 161247#L898-3 assume !(0 == ~E_5~0); 161248#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 161243#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 161244#L913-3 assume !(0 == ~E_8~0); 161184#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 161185#L402-27 assume !(1 == ~m_pc~0); 161180#L402-29 is_master_triggered_~__retres1~0#1 := 0; 161181#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 161176#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 161177#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 161172#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 161173#L421-27 assume !(1 == ~t1_pc~0); 161168#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 161169#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 161164#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 161165#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 161160#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 161161#L440-27 assume !(1 == ~t2_pc~0); 161157#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 161158#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 161153#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 161154#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 161149#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 161150#L459-27 assume 1 == ~t3_pc~0; 161142#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 161144#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 161134#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 161135#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 161128#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 161129#L478-27 assume !(1 == ~t4_pc~0); 161121#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 161120#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 161114#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 161111#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 161112#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 162693#L497-27 assume !(1 == ~t5_pc~0); 162691#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 162690#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 162689#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 162688#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 162687#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 162686#L516-27 assume 1 == ~t6_pc~0; 162684#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 162683#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 162682#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 162681#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 162680#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 162679#L535-27 assume 1 == ~t7_pc~0; 162678#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 162676#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 162675#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 162674#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 162672#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 160924#L554-27 assume 1 == ~t8_pc~0; 160926#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 160912#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 160913#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 160849#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 160850#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 160836#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 160837#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 160824#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 160825#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 160814#L946-3 assume !(1 == ~T4_E~0); 160815#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 160756#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 160757#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 160750#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 160751#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 160746#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 160747#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 160742#L986-3 assume !(1 == ~E_4~0); 160743#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 160739#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 160740#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 160735#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 160736#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 160732#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 160724#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 162615#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 162613#L1291 assume !(0 == start_simulation_~tmp~3#1); 162141#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 160515#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 160508#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 160501#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 160495#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 160367#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 160307#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 160295#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 152852#L1272-2 [2021-11-20 05:52:07,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:07,377 INFO L85 PathProgramCache]: Analyzing trace with hash 376497308, now seen corresponding path program 1 times [2021-11-20 05:52:07,378 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:07,378 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1731228188] [2021-11-20 05:52:07,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:07,378 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:07,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:07,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:07,420 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:07,420 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1731228188] [2021-11-20 05:52:07,421 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1731228188] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:07,421 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:07,421 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-20 05:52:07,421 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2115812578] [2021-11-20 05:52:07,421 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:07,424 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:52:07,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:07,424 INFO L85 PathProgramCache]: Analyzing trace with hash -1997704448, now seen corresponding path program 1 times [2021-11-20 05:52:07,425 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:07,425 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039863946] [2021-11-20 05:52:07,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:07,426 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:07,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:07,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:07,464 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:07,464 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2039863946] [2021-11-20 05:52:07,465 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2039863946] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:07,465 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:07,465 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:07,465 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1066342834] [2021-11-20 05:52:07,465 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:07,466 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:52:07,466 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:52:07,466 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:52:07,467 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:52:07,467 INFO L87 Difference]: Start difference. First operand 23839 states and 34332 transitions. cyclomatic complexity: 10509 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:07,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:52:07,792 INFO L93 Difference]: Finished difference Result 46050 states and 65986 transitions. [2021-11-20 05:52:07,792 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:52:07,793 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46050 states and 65986 transitions. [2021-11-20 05:52:08,131 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 45714 [2021-11-20 05:52:08,418 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46050 states to 46050 states and 65986 transitions. [2021-11-20 05:52:08,418 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46050 [2021-11-20 05:52:08,441 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46050 [2021-11-20 05:52:08,441 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46050 states and 65986 transitions. [2021-11-20 05:52:08,510 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:52:08,510 INFO L681 BuchiCegarLoop]: Abstraction has 46050 states and 65986 transitions. [2021-11-20 05:52:08,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46050 states and 65986 transitions. [2021-11-20 05:52:09,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46050 to 45978. [2021-11-20 05:52:09,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45978 states, 45978 states have (on average 1.433598677628431) internal successors, (65914), 45977 states have internal predecessors, (65914), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:09,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45978 states to 45978 states and 65914 transitions. [2021-11-20 05:52:09,451 INFO L704 BuchiCegarLoop]: Abstraction has 45978 states and 65914 transitions. [2021-11-20 05:52:09,451 INFO L587 BuchiCegarLoop]: Abstraction has 45978 states and 65914 transitions. [2021-11-20 05:52:09,451 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-20 05:52:09,452 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45978 states and 65914 transitions. [2021-11-20 05:52:09,604 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 45642 [2021-11-20 05:52:09,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:52:09,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:52:09,606 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:09,606 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:09,606 INFO L791 eck$LassoCheckResult]: Stem: 222501#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 222502#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 222864#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 221886#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 221887#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 222161#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 222162#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 222744#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 222726#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 222235#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 222236#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 222480#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 222481#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 222320#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 222321#L838 assume !(0 == ~M_E~0); 222487#L838-2 assume !(0 == ~T1_E~0); 221847#L843-1 assume !(0 == ~T2_E~0); 221848#L848-1 assume !(0 == ~T3_E~0); 221966#L853-1 assume !(0 == ~T4_E~0); 222308#L858-1 assume !(0 == ~T5_E~0); 221795#L863-1 assume !(0 == ~T6_E~0); 221796#L868-1 assume !(0 == ~T7_E~0); 222809#L873-1 assume !(0 == ~T8_E~0); 222806#L878-1 assume !(0 == ~E_1~0); 222781#L883-1 assume !(0 == ~E_2~0); 222782#L888-1 assume !(0 == ~E_3~0); 222451#L893-1 assume !(0 == ~E_4~0); 222452#L898-1 assume !(0 == ~E_5~0); 222837#L903-1 assume !(0 == ~E_6~0); 222779#L908-1 assume !(0 == ~E_7~0); 222593#L913-1 assume !(0 == ~E_8~0); 221861#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 221862#L402 assume !(1 == ~m_pc~0); 222286#L402-2 is_master_triggered_~__retres1~0#1 := 0; 221988#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 221989#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 222242#L1035 assume !(0 != activate_threads_~tmp~1#1); 222243#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 222297#L421 assume !(1 == ~t1_pc~0); 222771#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 222812#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 222289#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 222290#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 222354#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 222825#L440 assume !(1 == ~t2_pc~0); 222891#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 221997#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 221998#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 222848#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 222611#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 222195#L459 assume !(1 == ~t3_pc~0); 222196#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 222766#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 222530#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 221981#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 221982#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 221992#L478 assume !(1 == ~t4_pc~0); 221993#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 222674#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 222743#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 222167#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 221908#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 221909#L497 assume !(1 == ~t5_pc~0); 221952#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 221953#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 222256#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 222257#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 222757#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 222758#L516 assume 1 == ~t6_pc~0; 222883#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 222477#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 222478#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 222036#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 222037#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 222469#L535 assume !(1 == ~t7_pc~0); 222470#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 222548#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 222549#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 222580#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 222570#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 222571#L554 assume 1 == ~t8_pc~0; 222510#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 221824#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 222635#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 222128#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 222129#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 221808#L931 assume !(1 == ~M_E~0); 221809#L931-2 assume !(1 == ~T1_E~0); 222797#L936-1 assume !(1 == ~T2_E~0); 244448#L941-1 assume !(1 == ~T3_E~0); 244447#L946-1 assume !(1 == ~T4_E~0); 244443#L951-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 244444#L956-1 assume !(1 == ~T6_E~0); 262187#L961-1 assume !(1 == ~T7_E~0); 262186#L966-1 assume !(1 == ~T8_E~0); 262185#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 262184#L976-1 assume !(1 == ~E_2~0); 262183#L981-1 assume !(1 == ~E_3~0); 262182#L986-1 assume !(1 == ~E_4~0); 262180#L991-1 assume 1 == ~E_5~0;~E_5~0 := 2; 222083#L996-1 assume !(1 == ~E_6~0); 222817#L1001-1 assume !(1 == ~E_7~0); 222818#L1006-1 assume !(1 == ~E_8~0); 222767#L1011-1 assume { :end_inline_reset_delta_events } true; 222768#L1272-2 [2021-11-20 05:52:09,607 INFO L793 eck$LassoCheckResult]: Loop: 222768#L1272-2 assume !false; 260195#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 260192#L813 assume !false; 260191#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 240847#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 240838#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 240835#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 240833#L696 assume !(0 != eval_~tmp~0#1); 240834#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 260584#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 260582#L838-3 assume !(0 == ~M_E~0); 260580#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 260578#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 260576#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 260574#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 260572#L858-3 assume !(0 == ~T5_E~0); 260571#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 260570#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 260568#L873-3 assume !(0 == ~T8_E~0); 260566#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 260563#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 260561#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 260559#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 260557#L898-3 assume !(0 == ~E_5~0); 260555#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 260553#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 260551#L913-3 assume !(0 == ~E_8~0); 260549#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 260547#L402-27 assume !(1 == ~m_pc~0); 260544#L402-29 is_master_triggered_~__retres1~0#1 := 0; 260542#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 260540#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 260538#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 260536#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 260534#L421-27 assume !(1 == ~t1_pc~0); 260531#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 260529#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 260527#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 260525#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 260523#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 260521#L440-27 assume !(1 == ~t2_pc~0); 260518#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 260516#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 260514#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 260512#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 260510#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 260508#L459-27 assume !(1 == ~t3_pc~0); 260503#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 260501#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 260499#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 260497#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 260494#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 260493#L478-27 assume !(1 == ~t4_pc~0); 260492#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 260488#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 260486#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 260484#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 260480#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 260475#L497-27 assume 1 == ~t5_pc~0; 260287#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 260284#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 260282#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 260280#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 260278#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 260277#L516-27 assume !(1 == ~t6_pc~0); 260275#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 260272#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 260270#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 260269#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 260267#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 260265#L535-27 assume 1 == ~t7_pc~0; 260263#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 260260#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 260258#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 260256#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 260254#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 260253#L554-27 assume !(1 == ~t8_pc~0); 260251#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 260248#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 260247#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 260246#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 260245#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 260244#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 260243#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 244165#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 260242#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 260241#L946-3 assume !(1 == ~T4_E~0); 260240#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 244156#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 260239#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 260238#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 260237#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 260236#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 260235#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 260234#L986-3 assume !(1 == ~E_4~0); 260233#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 245009#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 260232#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 260231#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 260230#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 260229#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 260220#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 260219#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 260217#L1291 assume !(0 == start_simulation_~tmp~3#1); 260215#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 260206#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 260205#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 260204#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 260203#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 260202#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 260201#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 260200#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 222768#L1272-2 [2021-11-20 05:52:09,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:09,608 INFO L85 PathProgramCache]: Analyzing trace with hash 1809332027, now seen corresponding path program 1 times [2021-11-20 05:52:09,608 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:09,608 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [736375346] [2021-11-20 05:52:09,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:09,608 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:09,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:09,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:09,641 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:09,641 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [736375346] [2021-11-20 05:52:09,642 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [736375346] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:09,642 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:09,642 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:09,642 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [888402807] [2021-11-20 05:52:09,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:09,643 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:52:09,643 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:09,643 INFO L85 PathProgramCache]: Analyzing trace with hash 1363777404, now seen corresponding path program 1 times [2021-11-20 05:52:09,643 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:09,644 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123834940] [2021-11-20 05:52:09,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:09,644 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:09,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:09,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:09,672 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:09,673 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2123834940] [2021-11-20 05:52:09,673 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2123834940] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:09,673 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:09,673 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:09,673 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [567298792] [2021-11-20 05:52:09,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:09,674 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:52:09,674 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:52:09,674 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 05:52:09,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 05:52:09,675 INFO L87 Difference]: Start difference. First operand 45978 states and 65914 transitions. cyclomatic complexity: 19968 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:10,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:52:10,585 INFO L93 Difference]: Finished difference Result 128313 states and 182791 transitions. [2021-11-20 05:52:10,585 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 05:52:10,586 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128313 states and 182791 transitions. [2021-11-20 05:52:11,114 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 125082 [2021-11-20 05:52:11,747 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128313 states to 128313 states and 182791 transitions. [2021-11-20 05:52:11,747 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128313 [2021-11-20 05:52:11,857 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128313 [2021-11-20 05:52:11,857 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128313 states and 182791 transitions. [2021-11-20 05:52:12,043 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:52:12,044 INFO L681 BuchiCegarLoop]: Abstraction has 128313 states and 182791 transitions. [2021-11-20 05:52:12,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128313 states and 182791 transitions. [2021-11-20 05:52:13,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128313 to 124137. [2021-11-20 05:52:13,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124137 states, 124137 states have (on average 1.4286715483699461) internal successors, (177351), 124136 states have internal predecessors, (177351), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:14,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124137 states to 124137 states and 177351 transitions. [2021-11-20 05:52:14,078 INFO L704 BuchiCegarLoop]: Abstraction has 124137 states and 177351 transitions. [2021-11-20 05:52:14,078 INFO L587 BuchiCegarLoop]: Abstraction has 124137 states and 177351 transitions. [2021-11-20 05:52:14,078 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-20 05:52:14,079 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124137 states and 177351 transitions. [2021-11-20 05:52:14,795 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 123498 [2021-11-20 05:52:14,795 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:52:14,795 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:52:14,816 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:14,816 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:14,817 INFO L791 eck$LassoCheckResult]: Stem: 396798#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 396799#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 397147#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 396184#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 396185#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 396453#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 396454#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 397038#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 397021#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 396527#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 396528#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 396774#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 396775#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 396612#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 396613#L838 assume !(0 == ~M_E~0); 396782#L838-2 assume !(0 == ~T1_E~0); 396146#L843-1 assume !(0 == ~T2_E~0); 396147#L848-1 assume !(0 == ~T3_E~0); 396264#L853-1 assume !(0 == ~T4_E~0); 396598#L858-1 assume !(0 == ~T5_E~0); 396096#L863-1 assume !(0 == ~T6_E~0); 396097#L868-1 assume !(0 == ~T7_E~0); 397099#L873-1 assume !(0 == ~T8_E~0); 397097#L878-1 assume !(0 == ~E_1~0); 397072#L883-1 assume !(0 == ~E_2~0); 397073#L888-1 assume !(0 == ~E_3~0); 396744#L893-1 assume !(0 == ~E_4~0); 396745#L898-1 assume !(0 == ~E_5~0); 397120#L903-1 assume !(0 == ~E_6~0); 397071#L908-1 assume !(0 == ~E_7~0); 396889#L913-1 assume !(0 == ~E_8~0); 396160#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 396161#L402 assume !(1 == ~m_pc~0); 396577#L402-2 is_master_triggered_~__retres1~0#1 := 0; 396286#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 396287#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 396534#L1035 assume !(0 != activate_threads_~tmp~1#1); 396535#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 396588#L421 assume !(1 == ~t1_pc~0); 397062#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 397101#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 396580#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 396581#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 396643#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 397115#L440 assume !(1 == ~t2_pc~0); 397177#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 396296#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 396297#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 397133#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 396906#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 396482#L459 assume !(1 == ~t3_pc~0); 396483#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 397057#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 396825#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 396279#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 396280#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 396290#L478 assume !(1 == ~t4_pc~0); 396291#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 396964#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 397037#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 396459#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 396204#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 396205#L497 assume !(1 == ~t5_pc~0); 396250#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 396251#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 396548#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 396549#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 397049#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 397050#L516 assume !(1 == ~t6_pc~0); 396977#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 396772#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 396773#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 396336#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 396337#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 396764#L535 assume !(1 == ~t7_pc~0); 396765#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 396844#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 396845#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 396879#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 396868#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 396869#L554 assume 1 == ~t8_pc~0; 396806#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 396125#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 396931#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 396420#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 396421#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 396109#L931 assume !(1 == ~M_E~0); 396110#L931-2 assume !(1 == ~T1_E~0); 397086#L936-1 assume !(1 == ~T2_E~0); 397129#L941-1 assume !(1 == ~T3_E~0); 396589#L946-1 assume !(1 == ~T4_E~0); 396590#L951-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 412030#L956-1 assume !(1 == ~T6_E~0); 397168#L961-1 assume !(1 == ~T7_E~0); 397169#L966-1 assume !(1 == ~T8_E~0); 396871#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 396872#L976-1 assume !(1 == ~E_2~0); 396835#L981-1 assume !(1 == ~E_3~0); 396836#L986-1 assume !(1 == ~E_4~0); 396380#L991-1 assume 1 == ~E_5~0;~E_5~0 := 2; 396381#L996-1 assume !(1 == ~E_6~0); 412520#L1001-1 assume !(1 == ~E_7~0); 412519#L1006-1 assume !(1 == ~E_8~0); 412517#L1011-1 assume { :end_inline_reset_delta_events } true; 412518#L1272-2 [2021-11-20 05:52:14,817 INFO L793 eck$LassoCheckResult]: Loop: 412518#L1272-2 assume !false; 508351#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 508347#L813 assume !false; 508346#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 508344#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 508336#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 508335#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 508333#L696 assume !(0 != eval_~tmp~0#1); 508334#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 508479#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 508478#L838-3 assume !(0 == ~M_E~0); 508477#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 508476#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 508475#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 508474#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 508473#L858-3 assume !(0 == ~T5_E~0); 508472#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 508471#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 508470#L873-3 assume !(0 == ~T8_E~0); 508469#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 508468#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 508467#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 508466#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 508465#L898-3 assume !(0 == ~E_5~0); 508464#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 508463#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 508462#L913-3 assume !(0 == ~E_8~0); 508461#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 508460#L402-27 assume !(1 == ~m_pc~0); 508459#L402-29 is_master_triggered_~__retres1~0#1 := 0; 508458#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 508457#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 508456#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 508455#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 508454#L421-27 assume !(1 == ~t1_pc~0); 508453#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 508452#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 508451#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 508450#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 508449#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 508448#L440-27 assume !(1 == ~t2_pc~0); 508447#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 508446#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 508445#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 508444#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 508443#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 508442#L459-27 assume !(1 == ~t3_pc~0); 508439#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 508438#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 508437#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 508436#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 508434#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 508433#L478-27 assume !(1 == ~t4_pc~0); 508432#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 508431#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 508430#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 508429#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 508428#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 508427#L497-27 assume 1 == ~t5_pc~0; 508426#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 508424#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 508423#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 508422#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 508421#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 508420#L516-27 assume !(1 == ~t6_pc~0); 508419#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 508418#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 508417#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 508416#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 508415#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 508414#L535-27 assume 1 == ~t7_pc~0; 508413#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 508411#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 508410#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 508409#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 508408#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 508407#L554-27 assume !(1 == ~t8_pc~0); 508406#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 508404#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 508403#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 508402#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 508401#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 508400#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 508399#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 412623#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 508398#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 508397#L946-3 assume !(1 == ~T4_E~0); 508396#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 502425#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 508395#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 508394#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 508393#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 508392#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 508391#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 508390#L986-3 assume !(1 == ~E_4~0); 508389#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 502414#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 508388#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 508387#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 508386#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 508385#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 508376#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 508375#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 508373#L1291 assume !(0 == start_simulation_~tmp~3#1); 508371#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 508362#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 508361#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 508360#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 508359#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 508358#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 508357#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 508356#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 412518#L1272-2 [2021-11-20 05:52:14,818 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:14,818 INFO L85 PathProgramCache]: Analyzing trace with hash 44515418, now seen corresponding path program 1 times [2021-11-20 05:52:14,818 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:14,818 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [964800704] [2021-11-20 05:52:14,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:14,819 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:14,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:14,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:14,895 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:14,895 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [964800704] [2021-11-20 05:52:14,895 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [964800704] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:14,895 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:14,896 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-20 05:52:14,896 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1236863451] [2021-11-20 05:52:14,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:14,896 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:52:14,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:14,899 INFO L85 PathProgramCache]: Analyzing trace with hash 1363777404, now seen corresponding path program 2 times [2021-11-20 05:52:14,899 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:14,899 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1212619831] [2021-11-20 05:52:14,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:14,900 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:14,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:14,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:14,937 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:14,938 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1212619831] [2021-11-20 05:52:14,938 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1212619831] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:14,938 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:14,938 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:14,938 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [582779093] [2021-11-20 05:52:14,938 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:14,939 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:52:14,939 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:52:14,939 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:52:14,940 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:52:14,940 INFO L87 Difference]: Start difference. First operand 124137 states and 177351 transitions. cyclomatic complexity: 53278 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:15,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:52:15,783 INFO L93 Difference]: Finished difference Result 246500 states and 350020 transitions. [2021-11-20 05:52:15,784 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:52:15,784 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 246500 states and 350020 transitions. [2021-11-20 05:52:17,428 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 244934 [2021-11-20 05:52:18,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 246500 states to 246500 states and 350020 transitions. [2021-11-20 05:52:18,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 246500 [2021-11-20 05:52:18,553 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 246500 [2021-11-20 05:52:18,553 INFO L73 IsDeterministic]: Start isDeterministic. Operand 246500 states and 350020 transitions. [2021-11-20 05:52:18,614 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:52:18,614 INFO L681 BuchiCegarLoop]: Abstraction has 246500 states and 350020 transitions. [2021-11-20 05:52:18,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246500 states and 350020 transitions. [2021-11-20 05:52:21,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246500 to 245636. [2021-11-20 05:52:21,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 245636 states, 245636 states have (on average 1.4205572473090264) internal successors, (348940), 245635 states have internal predecessors, (348940), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:21,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245636 states to 245636 states and 348940 transitions. [2021-11-20 05:52:21,817 INFO L704 BuchiCegarLoop]: Abstraction has 245636 states and 348940 transitions. [2021-11-20 05:52:21,817 INFO L587 BuchiCegarLoop]: Abstraction has 245636 states and 348940 transitions. [2021-11-20 05:52:21,817 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-20 05:52:21,817 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 245636 states and 348940 transitions. [2021-11-20 05:52:23,615 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 244502 [2021-11-20 05:52:23,615 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:52:23,615 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:52:23,616 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:23,616 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:23,617 INFO L791 eck$LassoCheckResult]: Stem: 767456#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 767457#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 767846#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 766828#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 766829#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 767100#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 767101#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 767713#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 767699#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 767178#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 767179#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 767435#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 767436#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 767268#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 767269#L838 assume !(0 == ~M_E~0); 767445#L838-2 assume !(0 == ~T1_E~0); 766790#L843-1 assume !(0 == ~T2_E~0); 766791#L848-1 assume !(0 == ~T3_E~0); 766908#L853-1 assume !(0 == ~T4_E~0); 767256#L858-1 assume !(0 == ~T5_E~0); 766742#L863-1 assume !(0 == ~T6_E~0); 766743#L868-1 assume !(0 == ~T7_E~0); 767784#L873-1 assume !(0 == ~T8_E~0); 767781#L878-1 assume !(0 == ~E_1~0); 767751#L883-1 assume !(0 == ~E_2~0); 767752#L888-1 assume !(0 == ~E_3~0); 767405#L893-1 assume !(0 == ~E_4~0); 767406#L898-1 assume !(0 == ~E_5~0); 767806#L903-1 assume !(0 == ~E_6~0); 767748#L908-1 assume !(0 == ~E_7~0); 767555#L913-1 assume !(0 == ~E_8~0); 766804#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 766805#L402 assume !(1 == ~m_pc~0); 767229#L402-2 is_master_triggered_~__retres1~0#1 := 0; 766930#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 766931#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 767185#L1035 assume !(0 != activate_threads_~tmp~1#1); 767186#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 767242#L421 assume !(1 == ~t1_pc~0); 767740#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 767787#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 767232#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 767233#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 767302#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 767799#L440 assume !(1 == ~t2_pc~0); 767868#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 766940#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 766941#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 767827#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 767574#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 767137#L459 assume !(1 == ~t3_pc~0); 767138#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 767734#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 767483#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 766923#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 766924#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 766934#L478 assume !(1 == ~t4_pc~0); 766935#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 767632#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 767712#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 767106#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 766850#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 766851#L497 assume !(1 == ~t5_pc~0); 766894#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 766895#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 767199#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 767200#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 767727#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 767728#L516 assume !(1 == ~t6_pc~0); 767646#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 767432#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 767433#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 766980#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 766981#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 767424#L535 assume !(1 == ~t7_pc~0); 767425#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 767504#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 767505#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 767542#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 767532#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 767533#L554 assume !(1 == ~t8_pc~0); 766768#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 766769#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 767598#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 767071#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 767072#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 766753#L931 assume !(1 == ~M_E~0); 766754#L931-2 assume !(1 == ~T1_E~0); 767767#L936-1 assume !(1 == ~T2_E~0); 767825#L941-1 assume !(1 == ~T3_E~0); 767243#L946-1 assume !(1 == ~T4_E~0); 767244#L951-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 791447#L956-1 assume !(1 == ~T6_E~0); 767860#L961-1 assume !(1 == ~T7_E~0); 767861#L966-1 assume !(1 == ~T8_E~0); 767535#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 767536#L976-1 assume !(1 == ~E_2~0); 767493#L981-1 assume !(1 == ~E_3~0); 767494#L986-1 assume !(1 == ~E_4~0); 791438#L991-1 assume 1 == ~E_5~0;~E_5~0 := 2; 791437#L996-1 assume !(1 == ~E_6~0); 791436#L1001-1 assume !(1 == ~E_7~0); 791435#L1006-1 assume !(1 == ~E_8~0); 791433#L1011-1 assume { :end_inline_reset_delta_events } true; 791434#L1272-2 [2021-11-20 05:52:23,617 INFO L793 eck$LassoCheckResult]: Loop: 791434#L1272-2 assume !false; 878977#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 878972#L813 assume !false; 878970#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 878578#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 878233#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 878231#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 878228#L696 assume !(0 != eval_~tmp~0#1); 878229#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1002872#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1002871#L838-3 assume !(0 == ~M_E~0); 1002870#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1002869#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1002868#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1002867#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1002866#L858-3 assume !(0 == ~T5_E~0); 1002865#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1002864#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1002863#L873-3 assume !(0 == ~T8_E~0); 1002862#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1002861#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1002860#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1002859#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1002858#L898-3 assume !(0 == ~E_5~0); 1002857#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1002856#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1002855#L913-3 assume !(0 == ~E_8~0); 1002854#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1002853#L402-27 assume !(1 == ~m_pc~0); 1002851#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1002849#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1002847#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1002844#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1002842#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1002840#L421-27 assume !(1 == ~t1_pc~0); 1002838#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1002836#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1002834#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1002833#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1002831#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1002829#L440-27 assume !(1 == ~t2_pc~0); 1002827#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1002825#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1002823#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1002820#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1002818#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1002816#L459-27 assume 1 == ~t3_pc~0; 1002814#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1002815#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1002873#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1002803#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1002801#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1002799#L478-27 assume !(1 == ~t4_pc~0); 1002796#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1002794#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1002792#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1002790#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 999590#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 791619#L497-27 assume !(1 == ~t5_pc~0); 791616#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 791613#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 791614#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 980236#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 980234#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 980232#L516-27 assume !(1 == ~t6_pc~0); 980230#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 980228#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 980226#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 980224#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 980222#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 980220#L535-27 assume 1 == ~t7_pc~0; 980218#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 980215#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 980213#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 980211#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 980209#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 980207#L554-27 assume !(1 == ~t8_pc~0); 980205#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 980203#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 980200#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 980198#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 980196#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 980194#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 979599#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 791563#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 979591#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 978790#L946-3 assume !(1 == ~T4_E~0); 791551#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 791547#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 791545#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 791541#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 791537#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 791534#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 791531#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 791528#L986-3 assume !(1 == ~E_4~0); 791525#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 791520#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 791518#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 791516#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 791513#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 791514#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 884905#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 884904#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 884893#L1291 assume !(0 == start_simulation_~tmp~3#1); 884890#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 884711#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 884709#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 884707#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 884705#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 884703#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 884701#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 884699#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 791434#L1272-2 [2021-11-20 05:52:23,617 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:23,618 INFO L85 PathProgramCache]: Analyzing trace with hash -1545879559, now seen corresponding path program 1 times [2021-11-20 05:52:23,618 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:23,618 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1262980364] [2021-11-20 05:52:23,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:23,618 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:23,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:23,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:23,656 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:23,656 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1262980364] [2021-11-20 05:52:23,656 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1262980364] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:23,657 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:23,657 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:23,657 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [167695599] [2021-11-20 05:52:23,657 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:23,658 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:52:23,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:23,658 INFO L85 PathProgramCache]: Analyzing trace with hash 1965280958, now seen corresponding path program 1 times [2021-11-20 05:52:23,658 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:23,659 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [236733743] [2021-11-20 05:52:23,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:23,659 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:23,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:23,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:23,690 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:23,690 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [236733743] [2021-11-20 05:52:23,691 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [236733743] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:23,691 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:23,691 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:23,691 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1352377702] [2021-11-20 05:52:23,691 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:23,692 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:52:23,692 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:52:23,692 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 05:52:23,692 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 05:52:23,693 INFO L87 Difference]: Start difference. First operand 245636 states and 348940 transitions. cyclomatic complexity: 103432 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:24,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:52:24,095 INFO L93 Difference]: Finished difference Result 122861 states and 173605 transitions. [2021-11-20 05:52:24,096 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:52:24,096 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122861 states and 173605 transitions. [2021-11-20 05:52:25,365 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 122251 [2021-11-20 05:52:25,678 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122861 states to 122861 states and 173605 transitions. [2021-11-20 05:52:25,678 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122861 [2021-11-20 05:52:25,745 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122861 [2021-11-20 05:52:25,745 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122861 states and 173605 transitions. [2021-11-20 05:52:25,792 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:52:25,793 INFO L681 BuchiCegarLoop]: Abstraction has 122861 states and 173605 transitions. [2021-11-20 05:52:25,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122861 states and 173605 transitions. [2021-11-20 05:52:26,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122861 to 63233. [2021-11-20 05:52:26,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63233 states, 63233 states have (on average 1.4103711669539638) internal successors, (89182), 63232 states have internal predecessors, (89182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:27,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63233 states to 63233 states and 89182 transitions. [2021-11-20 05:52:27,197 INFO L704 BuchiCegarLoop]: Abstraction has 63233 states and 89182 transitions. [2021-11-20 05:52:27,197 INFO L587 BuchiCegarLoop]: Abstraction has 63233 states and 89182 transitions. [2021-11-20 05:52:27,197 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-20 05:52:27,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63233 states and 89182 transitions. [2021-11-20 05:52:27,359 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 62875 [2021-11-20 05:52:27,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:52:27,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:52:27,360 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:27,361 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:27,361 INFO L791 eck$LassoCheckResult]: Stem: 1135965#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1135966#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1136338#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1135337#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1135338#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1135609#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1135610#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1136223#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1136203#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1135684#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1135685#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1135941#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1135942#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1135778#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1135779#L838 assume !(0 == ~M_E~0); 1135952#L838-2 assume !(0 == ~T1_E~0); 1135299#L843-1 assume !(0 == ~T2_E~0); 1135300#L848-1 assume !(0 == ~T3_E~0); 1135418#L853-1 assume !(0 == ~T4_E~0); 1135766#L858-1 assume !(0 == ~T5_E~0); 1135249#L863-1 assume !(0 == ~T6_E~0); 1135250#L868-1 assume !(0 == ~T7_E~0); 1136283#L873-1 assume !(0 == ~T8_E~0); 1136279#L878-1 assume !(0 == ~E_1~0); 1136257#L883-1 assume !(0 == ~E_2~0); 1136258#L888-1 assume !(0 == ~E_3~0); 1135912#L893-1 assume !(0 == ~E_4~0); 1135913#L898-1 assume !(0 == ~E_5~0); 1136309#L903-1 assume !(0 == ~E_6~0); 1136253#L908-1 assume !(0 == ~E_7~0); 1136062#L913-1 assume !(0 == ~E_8~0); 1135313#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1135314#L402 assume !(1 == ~m_pc~0); 1135739#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1135442#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1135443#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1135692#L1035 assume !(0 != activate_threads_~tmp~1#1); 1135693#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1135754#L421 assume !(1 == ~t1_pc~0); 1136245#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1136287#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1135743#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1135744#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1135810#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1136297#L440 assume !(1 == ~t2_pc~0); 1136359#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1135452#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1135453#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1136326#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1136078#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1135644#L459 assume !(1 == ~t3_pc~0); 1135645#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1136242#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1135992#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1135435#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1135436#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1135446#L478 assume !(1 == ~t4_pc~0); 1135447#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1136140#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1136222#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1135615#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1135359#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1135360#L497 assume !(1 == ~t5_pc~0); 1135402#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1135403#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1135708#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1135709#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1136236#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1136237#L516 assume !(1 == ~t6_pc~0); 1136154#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1135938#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1135939#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1135491#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1135492#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1135930#L535 assume !(1 == ~t7_pc~0); 1135931#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1136010#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1136011#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1136047#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1136038#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1136039#L554 assume !(1 == ~t8_pc~0); 1135275#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1135276#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1136098#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1135578#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1135579#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1135260#L931 assume !(1 == ~M_E~0); 1135261#L931-2 assume !(1 == ~T1_E~0); 1136268#L936-1 assume !(1 == ~T2_E~0); 1136323#L941-1 assume !(1 == ~T3_E~0); 1135755#L946-1 assume !(1 == ~T4_E~0); 1135756#L951-1 assume !(1 == ~T5_E~0); 1135507#L956-1 assume !(1 == ~T6_E~0); 1135508#L961-1 assume !(1 == ~T7_E~0); 1135914#L966-1 assume !(1 == ~T8_E~0); 1135915#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1136041#L976-1 assume !(1 == ~E_2~0); 1136002#L981-1 assume !(1 == ~E_3~0); 1135760#L986-1 assume !(1 == ~E_4~0); 1135536#L991-1 assume !(1 == ~E_5~0); 1135537#L996-1 assume !(1 == ~E_6~0); 1136291#L1001-1 assume !(1 == ~E_7~0); 1135963#L1006-1 assume !(1 == ~E_8~0); 1135964#L1011-1 assume { :end_inline_reset_delta_events } true; 1136243#L1272-2 [2021-11-20 05:52:27,362 INFO L793 eck$LassoCheckResult]: Loop: 1136243#L1272-2 assume !false; 1195454#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1191836#L813 assume !false; 1195450#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1195447#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1195438#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1195436#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1195433#L696 assume !(0 != eval_~tmp~0#1); 1195434#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1197861#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1197859#L838-3 assume !(0 == ~M_E~0); 1195839#L838-5 assume !(0 == ~T1_E~0); 1195838#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1195837#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1195836#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1195835#L858-3 assume !(0 == ~T5_E~0); 1195834#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1195833#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1195832#L873-3 assume !(0 == ~T8_E~0); 1195831#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1195830#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1195829#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1195828#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1195827#L898-3 assume !(0 == ~E_5~0); 1195826#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1195825#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1195824#L913-3 assume !(0 == ~E_8~0); 1195823#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1195822#L402-27 assume !(1 == ~m_pc~0); 1195821#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1195819#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1195817#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1195815#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1195813#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1195811#L421-27 assume !(1 == ~t1_pc~0); 1195809#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1195807#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1195805#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1195803#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1195801#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1195799#L440-27 assume !(1 == ~t2_pc~0); 1195795#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1195792#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1195789#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1195786#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1195783#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1195781#L459-27 assume 1 == ~t3_pc~0; 1195778#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1195774#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1195769#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1195764#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1195760#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1195756#L478-27 assume !(1 == ~t4_pc~0); 1195753#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1195750#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1195747#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1195744#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1195741#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1195738#L497-27 assume !(1 == ~t5_pc~0); 1195734#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1195731#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1195727#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1195723#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1195719#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1195715#L516-27 assume !(1 == ~t6_pc~0); 1195711#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1195707#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1195702#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1195697#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1195692#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1195687#L535-27 assume !(1 == ~t7_pc~0); 1195682#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1195678#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1195672#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1195668#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1195664#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1195660#L554-27 assume !(1 == ~t8_pc~0); 1195656#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1195653#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1195650#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1195646#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1195641#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1195636#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1195631#L931-5 assume !(1 == ~T1_E~0); 1195626#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1195622#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1195618#L946-3 assume !(1 == ~T4_E~0); 1195613#L951-3 assume !(1 == ~T5_E~0); 1195609#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1195605#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1195601#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1195597#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1195593#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1195588#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1195584#L986-3 assume !(1 == ~E_4~0); 1195581#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1195526#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1195524#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1195522#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1195521#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1195520#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1195509#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1195507#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1195504#L1291 assume !(0 == start_simulation_~tmp~3#1); 1195501#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1195489#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1195477#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1195469#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1195462#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1195461#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1195459#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1195457#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1136243#L1272-2 [2021-11-20 05:52:27,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:27,363 INFO L85 PathProgramCache]: Analyzing trace with hash -2130838531, now seen corresponding path program 1 times [2021-11-20 05:52:27,363 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:27,363 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1073803190] [2021-11-20 05:52:27,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:27,363 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:27,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:27,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:27,399 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:27,399 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1073803190] [2021-11-20 05:52:27,400 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1073803190] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:27,400 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:27,400 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:27,400 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1219339227] [2021-11-20 05:52:27,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:27,401 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:52:27,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:27,401 INFO L85 PathProgramCache]: Analyzing trace with hash 29376163, now seen corresponding path program 1 times [2021-11-20 05:52:27,401 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:27,402 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [647401215] [2021-11-20 05:52:27,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:27,402 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:27,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:27,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:27,430 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:27,430 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [647401215] [2021-11-20 05:52:27,431 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [647401215] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:27,431 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:27,431 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:27,431 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1223504426] [2021-11-20 05:52:27,431 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:27,432 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:52:27,432 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:52:27,432 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 05:52:27,432 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 05:52:27,433 INFO L87 Difference]: Start difference. First operand 63233 states and 89182 transitions. cyclomatic complexity: 25981 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:27,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:52:27,875 INFO L93 Difference]: Finished difference Result 133866 states and 188018 transitions. [2021-11-20 05:52:27,877 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 05:52:27,878 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 133866 states and 188018 transitions. [2021-11-20 05:52:28,416 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 133138 [2021-11-20 05:52:29,330 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 133866 states to 133866 states and 188018 transitions. [2021-11-20 05:52:29,330 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 133866 [2021-11-20 05:52:29,385 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 133866 [2021-11-20 05:52:29,385 INFO L73 IsDeterministic]: Start isDeterministic. Operand 133866 states and 188018 transitions. [2021-11-20 05:52:29,444 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:52:29,444 INFO L681 BuchiCegarLoop]: Abstraction has 133866 states and 188018 transitions. [2021-11-20 05:52:29,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133866 states and 188018 transitions. [2021-11-20 05:52:30,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133866 to 71947. [2021-11-20 05:52:30,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71947 states, 71947 states have (on average 1.4048952701294009) internal successors, (101078), 71946 states have internal predecessors, (101078), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:30,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71947 states to 71947 states and 101078 transitions. [2021-11-20 05:52:30,476 INFO L704 BuchiCegarLoop]: Abstraction has 71947 states and 101078 transitions. [2021-11-20 05:52:30,476 INFO L587 BuchiCegarLoop]: Abstraction has 71947 states and 101078 transitions. [2021-11-20 05:52:30,476 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-20 05:52:30,477 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71947 states and 101078 transitions. [2021-11-20 05:52:30,710 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 71511 [2021-11-20 05:52:30,710 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:52:30,711 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:52:30,713 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:30,713 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:30,713 INFO L791 eck$LassoCheckResult]: Stem: 1333057#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1333058#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1333426#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1332444#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1332445#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1332714#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1332715#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1333312#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1333295#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1332788#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1332789#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1333034#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1333035#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1332875#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1332876#L838 assume !(0 == ~M_E~0); 1333041#L838-2 assume !(0 == ~T1_E~0); 1332406#L843-1 assume !(0 == ~T2_E~0); 1332407#L848-1 assume !(0 == ~T3_E~0); 1332524#L853-1 assume !(0 == ~T4_E~0); 1332861#L858-1 assume !(0 == ~T5_E~0); 1332356#L863-1 assume !(0 == ~T6_E~0); 1332357#L868-1 assume !(0 == ~T7_E~0); 1333374#L873-1 assume !(0 == ~T8_E~0); 1333371#L878-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1333347#L883-1 assume !(0 == ~E_2~0); 1333348#L888-1 assume !(0 == ~E_3~0); 1333005#L893-1 assume !(0 == ~E_4~0); 1333006#L898-1 assume !(0 == ~E_5~0); 1333507#L903-1 assume !(0 == ~E_6~0); 1333346#L908-1 assume !(0 == ~E_7~0); 1333153#L913-1 assume !(0 == ~E_8~0); 1332420#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1332421#L402 assume !(1 == ~m_pc~0); 1332838#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1332839#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1333502#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1333501#L1035 assume !(0 != activate_threads_~tmp~1#1); 1332850#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1332851#L421 assume !(1 == ~t1_pc~0); 1333376#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1333377#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1332842#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1332843#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1333387#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1333388#L440 assume !(1 == ~t2_pc~0); 1333461#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1333462#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1333441#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1333442#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1333500#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1332745#L459 assume !(1 == ~t3_pc~0); 1332746#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1333499#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1333497#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1333494#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1333493#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1332550#L478 assume !(1 == ~t4_pc~0); 1332551#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1333310#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1333311#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1332720#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1332721#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1333059#L497 assume !(1 == ~t5_pc~0); 1333060#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1333095#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1332809#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1332810#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1333326#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1333327#L516 assume !(1 == ~t6_pc~0); 1333246#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1333247#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1333430#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1332595#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1332596#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1333110#L535 assume !(1 == ~t7_pc~0); 1333278#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1333108#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1333109#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1333488#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1333487#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1333319#L554 assume !(1 == ~t8_pc~0); 1332382#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1332383#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1333192#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1333193#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1333485#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1332368#L931 assume !(1 == ~M_E~0); 1332369#L931-2 assume !(1 == ~T1_E~0); 1333406#L936-1 assume !(1 == ~T2_E~0); 1333407#L941-1 assume !(1 == ~T3_E~0); 1333460#L946-1 assume !(1 == ~T4_E~0); 1333335#L951-1 assume !(1 == ~T5_E~0); 1332613#L956-1 assume !(1 == ~T6_E~0); 1332614#L961-1 assume !(1 == ~T7_E~0); 1333452#L966-1 assume !(1 == ~T8_E~0); 1333481#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1333134#L976-1 assume !(1 == ~E_2~0); 1333100#L981-1 assume !(1 == ~E_3~0); 1332858#L986-1 assume !(1 == ~E_4~0); 1332642#L991-1 assume !(1 == ~E_5~0); 1332643#L996-1 assume !(1 == ~E_6~0); 1333382#L1001-1 assume !(1 == ~E_7~0); 1333055#L1006-1 assume !(1 == ~E_8~0); 1333056#L1011-1 assume { :end_inline_reset_delta_events } true; 1333336#L1272-2 [2021-11-20 05:52:30,714 INFO L793 eck$LassoCheckResult]: Loop: 1333336#L1272-2 assume !false; 1366534#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1365893#L813 assume !false; 1366526#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1366521#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1366510#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1366506#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1366343#L696 assume !(0 != eval_~tmp~0#1); 1366344#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1366955#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1366950#L838-3 assume !(0 == ~M_E~0); 1366945#L838-5 assume !(0 == ~T1_E~0); 1366938#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1366932#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1366926#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1366920#L858-3 assume !(0 == ~T5_E~0); 1366914#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1366909#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1366903#L873-3 assume !(0 == ~T8_E~0); 1366896#L878-3 assume !(0 == ~E_1~0); 1366897#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1367291#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1367289#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1367287#L898-3 assume !(0 == ~E_5~0); 1367285#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1367283#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1367281#L913-3 assume !(0 == ~E_8~0); 1367279#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1367277#L402-27 assume !(1 == ~m_pc~0); 1367275#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1367273#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1367271#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1367269#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1367267#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1367265#L421-27 assume !(1 == ~t1_pc~0); 1367263#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1367261#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1367258#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1367255#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1367252#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1367248#L440-27 assume !(1 == ~t2_pc~0); 1367244#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1367240#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1367236#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1367233#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1367230#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1367227#L459-27 assume 1 == ~t3_pc~0; 1367223#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1367219#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1367215#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1367211#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1367208#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1367204#L478-27 assume !(1 == ~t4_pc~0); 1367201#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1367198#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1367194#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1367189#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1367184#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1367179#L497-27 assume !(1 == ~t5_pc~0); 1367173#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1367168#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1367163#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1367158#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1367153#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1367147#L516-27 assume !(1 == ~t6_pc~0); 1367142#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1367137#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1367132#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1367126#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1367121#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1367116#L535-27 assume !(1 == ~t7_pc~0); 1367110#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1367105#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1367100#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1367097#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1367090#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1367085#L554-27 assume !(1 == ~t8_pc~0); 1366964#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1366962#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1366960#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1366958#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1366954#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1366949#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1366944#L931-5 assume !(1 == ~T1_E~0); 1366937#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1366931#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1366925#L946-3 assume !(1 == ~T4_E~0); 1366919#L951-3 assume !(1 == ~T5_E~0); 1366913#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1366908#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1366902#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1366818#L971-3 assume !(1 == ~E_1~0); 1366813#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1366808#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1366803#L986-3 assume !(1 == ~E_4~0); 1366798#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1366794#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1366790#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1366786#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1366783#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1366630#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1366617#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1366612#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1366608#L1291 assume !(0 == start_simulation_~tmp~3#1); 1366605#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1366569#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1366565#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1366560#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1366556#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1366552#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1366548#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1366544#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1333336#L1272-2 [2021-11-20 05:52:30,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:30,715 INFO L85 PathProgramCache]: Analyzing trace with hash -1073000453, now seen corresponding path program 1 times [2021-11-20 05:52:30,715 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:30,716 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [42831574] [2021-11-20 05:52:30,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:30,716 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:30,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:30,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:30,752 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:30,752 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [42831574] [2021-11-20 05:52:30,752 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [42831574] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:30,752 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:30,753 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:30,753 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1410920021] [2021-11-20 05:52:30,753 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:30,753 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:52:30,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:30,754 INFO L85 PathProgramCache]: Analyzing trace with hash -431431001, now seen corresponding path program 1 times [2021-11-20 05:52:30,754 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:30,754 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1182504304] [2021-11-20 05:52:30,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:30,755 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:30,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:30,785 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:30,785 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:30,785 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1182504304] [2021-11-20 05:52:30,785 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1182504304] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:30,786 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:30,786 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:30,786 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1070451968] [2021-11-20 05:52:30,786 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:30,787 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:52:30,787 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:52:30,787 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 05:52:30,787 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 05:52:30,787 INFO L87 Difference]: Start difference. First operand 71947 states and 101078 transitions. cyclomatic complexity: 29163 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:31,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:52:31,787 INFO L93 Difference]: Finished difference Result 82849 states and 116398 transitions. [2021-11-20 05:52:31,788 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 05:52:31,790 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82849 states and 116398 transitions. [2021-11-20 05:52:32,172 INFO L131 ngComponentsAnalysis]: Automaton has 36 accepting balls. 82395 [2021-11-20 05:52:32,370 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82849 states to 82849 states and 116398 transitions. [2021-11-20 05:52:32,370 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82849 [2021-11-20 05:52:32,416 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82849 [2021-11-20 05:52:32,416 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82849 states and 116398 transitions. [2021-11-20 05:52:32,454 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:52:32,454 INFO L681 BuchiCegarLoop]: Abstraction has 82849 states and 116398 transitions. [2021-11-20 05:52:32,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82849 states and 116398 transitions. [2021-11-20 05:52:33,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82849 to 63233. [2021-11-20 05:52:33,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63233 states, 63233 states have (on average 1.401135483054734) internal successors, (88598), 63232 states have internal predecessors, (88598), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:33,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63233 states to 63233 states and 88598 transitions. [2021-11-20 05:52:33,852 INFO L704 BuchiCegarLoop]: Abstraction has 63233 states and 88598 transitions. [2021-11-20 05:52:33,852 INFO L587 BuchiCegarLoop]: Abstraction has 63233 states and 88598 transitions. [2021-11-20 05:52:33,852 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-20 05:52:33,853 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63233 states and 88598 transitions. [2021-11-20 05:52:34,027 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 62875 [2021-11-20 05:52:34,028 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:52:34,028 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:52:34,030 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:34,030 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:34,030 INFO L791 eck$LassoCheckResult]: Stem: 1487854#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1487855#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1488175#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1487250#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1487251#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1487519#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1487520#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1488076#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1488066#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1487591#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1487592#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1487833#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1487834#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1487676#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1487677#L838 assume !(0 == ~M_E~0); 1487843#L838-2 assume !(0 == ~T1_E~0); 1487212#L843-1 assume !(0 == ~T2_E~0); 1487213#L848-1 assume !(0 == ~T3_E~0); 1487330#L853-1 assume !(0 == ~T4_E~0); 1487664#L858-1 assume !(0 == ~T5_E~0); 1487164#L863-1 assume !(0 == ~T6_E~0); 1487165#L868-1 assume !(0 == ~T7_E~0); 1488132#L873-1 assume !(0 == ~T8_E~0); 1488130#L878-1 assume !(0 == ~E_1~0); 1488105#L883-1 assume !(0 == ~E_2~0); 1488106#L888-1 assume !(0 == ~E_3~0); 1487805#L893-1 assume !(0 == ~E_4~0); 1487806#L898-1 assume !(0 == ~E_5~0); 1488150#L903-1 assume !(0 == ~E_6~0); 1488103#L908-1 assume !(0 == ~E_7~0); 1487943#L913-1 assume !(0 == ~E_8~0); 1487226#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1487227#L402 assume !(1 == ~m_pc~0); 1487642#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1487354#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1487355#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1487600#L1035 assume !(0 != activate_threads_~tmp~1#1); 1487601#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1487653#L421 assume !(1 == ~t1_pc~0); 1488096#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1488134#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1487645#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1487646#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1487704#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1488143#L440 assume !(1 == ~t2_pc~0); 1488191#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1487364#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1487365#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1488162#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1487957#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1487552#L459 assume !(1 == ~t3_pc~0); 1487553#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1488094#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1487882#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1487347#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1487348#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1487358#L478 assume !(1 == ~t4_pc~0); 1487359#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1488007#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1488075#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1487525#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1487272#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1487273#L497 assume !(1 == ~t5_pc~0); 1487316#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1487317#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1487614#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1487615#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1488086#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1488087#L516 assume !(1 == ~t6_pc~0); 1488022#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1487830#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1487831#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1487402#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1487403#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1487822#L535 assume !(1 == ~t7_pc~0); 1487823#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1487899#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1487900#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1487931#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1487921#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1487922#L554 assume !(1 == ~t8_pc~0); 1487188#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1487189#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1487977#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1487490#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1487491#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1487174#L931 assume !(1 == ~M_E~0); 1487175#L931-2 assume !(1 == ~T1_E~0); 1488119#L936-1 assume !(1 == ~T2_E~0); 1488159#L941-1 assume !(1 == ~T3_E~0); 1487654#L946-1 assume !(1 == ~T4_E~0); 1487655#L951-1 assume !(1 == ~T5_E~0); 1487419#L956-1 assume !(1 == ~T6_E~0); 1487420#L961-1 assume !(1 == ~T7_E~0); 1487807#L966-1 assume !(1 == ~T8_E~0); 1487808#L971-1 assume !(1 == ~E_1~0); 1487924#L976-1 assume !(1 == ~E_2~0); 1487891#L981-1 assume !(1 == ~E_3~0); 1487659#L986-1 assume !(1 == ~E_4~0); 1487447#L991-1 assume !(1 == ~E_5~0); 1487448#L996-1 assume !(1 == ~E_6~0); 1488137#L1001-1 assume !(1 == ~E_7~0); 1487852#L1006-1 assume !(1 == ~E_8~0); 1487853#L1011-1 assume { :end_inline_reset_delta_events } true; 1488095#L1272-2 [2021-11-20 05:52:34,031 INFO L793 eck$LassoCheckResult]: Loop: 1488095#L1272-2 assume !false; 1522512#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1509611#L813 assume !false; 1509612#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1509603#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1509596#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1509589#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1509590#L696 assume !(0 != eval_~tmp~0#1); 1509916#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1509914#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1509912#L838-3 assume !(0 == ~M_E~0); 1509910#L838-5 assume !(0 == ~T1_E~0); 1509908#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1509906#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1509904#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1509901#L858-3 assume !(0 == ~T5_E~0); 1509899#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1509897#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1509896#L873-3 assume !(0 == ~T8_E~0); 1509895#L878-3 assume !(0 == ~E_1~0); 1509894#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1509893#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1509892#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1509891#L898-3 assume !(0 == ~E_5~0); 1509889#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1509888#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1509885#L913-3 assume !(0 == ~E_8~0); 1509882#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1509881#L402-27 assume !(1 == ~m_pc~0); 1509880#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1509879#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1509877#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1509875#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1509873#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1509871#L421-27 assume !(1 == ~t1_pc~0); 1509869#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1509867#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1509865#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1509863#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1509861#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1509859#L440-27 assume !(1 == ~t2_pc~0); 1509857#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1509855#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1509853#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1509851#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1509849#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1509847#L459-27 assume !(1 == ~t3_pc~0); 1509845#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1523304#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1509837#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1509838#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 1509828#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1509829#L478-27 assume !(1 == ~t4_pc~0); 1509822#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1509823#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1509815#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1509816#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1509809#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1509810#L497-27 assume 1 == ~t5_pc~0; 1509803#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1509802#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1509795#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1509796#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1509788#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1509789#L516-27 assume !(1 == ~t6_pc~0); 1509783#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1509784#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1509777#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1509778#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1509772#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1509773#L535-27 assume 1 == ~t7_pc~0; 1509766#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1509765#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1509758#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1509759#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1509751#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1509752#L554-27 assume !(1 == ~t8_pc~0); 1509745#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1509746#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1509739#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1509740#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1509733#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1509734#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1509727#L931-5 assume !(1 == ~T1_E~0); 1509728#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1509721#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1509722#L946-3 assume !(1 == ~T4_E~0); 1509715#L951-3 assume !(1 == ~T5_E~0); 1509716#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1509709#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1509710#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1509703#L971-3 assume !(1 == ~E_1~0); 1509704#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1509697#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1509698#L986-3 assume !(1 == ~E_4~0); 1509691#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1509692#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1509685#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1509686#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1509679#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1509680#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1522641#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1522640#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1522638#L1291 assume !(0 == start_simulation_~tmp~3#1); 1509656#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1509657#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1522518#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1522517#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1522516#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1522515#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1522514#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1522513#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1488095#L1272-2 [2021-11-20 05:52:34,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:34,032 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 1 times [2021-11-20 05:52:34,032 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:34,032 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [721836669] [2021-11-20 05:52:34,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:34,033 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:34,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:52:34,047 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-20 05:52:34,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-20 05:52:34,121 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-20 05:52:34,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:34,122 INFO L85 PathProgramCache]: Analyzing trace with hash 1122579846, now seen corresponding path program 1 times [2021-11-20 05:52:34,122 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:34,122 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281419538] [2021-11-20 05:52:34,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:34,122 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:34,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:34,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:34,156 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:34,156 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [281419538] [2021-11-20 05:52:34,156 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [281419538] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:34,156 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:34,157 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:34,157 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1766997368] [2021-11-20 05:52:34,157 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:34,157 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:52:34,157 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:52:34,158 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:52:34,158 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:52:34,158 INFO L87 Difference]: Start difference. First operand 63233 states and 88598 transitions. cyclomatic complexity: 25397 Second operand has 3 states, 3 states have (on average 37.333333333333336) internal successors, (112), 3 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:34,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:52:34,387 INFO L93 Difference]: Finished difference Result 71983 states and 100751 transitions. [2021-11-20 05:52:34,387 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:52:34,387 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71983 states and 100751 transitions. [2021-11-20 05:52:34,671 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 71547 [2021-11-20 05:52:34,830 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71983 states to 71983 states and 100751 transitions. [2021-11-20 05:52:34,830 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 71983 [2021-11-20 05:52:34,867 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 71983 [2021-11-20 05:52:34,867 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71983 states and 100751 transitions. [2021-11-20 05:52:34,897 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:52:34,897 INFO L681 BuchiCegarLoop]: Abstraction has 71983 states and 100751 transitions. [2021-11-20 05:52:34,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71983 states and 100751 transitions. [2021-11-20 05:52:36,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71983 to 71983. [2021-11-20 05:52:36,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71983 states, 71983 states have (on average 1.3996499173415946) internal successors, (100751), 71982 states have internal predecessors, (100751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:36,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71983 states to 71983 states and 100751 transitions. [2021-11-20 05:52:36,216 INFO L704 BuchiCegarLoop]: Abstraction has 71983 states and 100751 transitions. [2021-11-20 05:52:36,216 INFO L587 BuchiCegarLoop]: Abstraction has 71983 states and 100751 transitions. [2021-11-20 05:52:36,216 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-20 05:52:36,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71983 states and 100751 transitions. [2021-11-20 05:52:36,414 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 71547 [2021-11-20 05:52:36,414 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:52:36,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:52:36,416 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:36,416 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:52:36,417 INFO L791 eck$LassoCheckResult]: Stem: 1623086#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1623087#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1623475#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1622471#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1622472#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1622741#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1622742#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1623350#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1623335#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1622817#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1622818#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1623064#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1623065#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1622906#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1622907#L838 assume !(0 == ~M_E~0); 1623075#L838-2 assume !(0 == ~T1_E~0); 1622433#L843-1 assume !(0 == ~T2_E~0); 1622434#L848-1 assume !(0 == ~T3_E~0); 1622551#L853-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1622893#L858-1 assume !(0 == ~T5_E~0); 1622894#L863-1 assume !(0 == ~T6_E~0); 1623421#L868-1 assume !(0 == ~T7_E~0); 1623422#L873-1 assume !(0 == ~T8_E~0); 1623417#L878-1 assume !(0 == ~E_1~0); 1623418#L883-1 assume !(0 == ~E_2~0); 1623450#L888-1 assume !(0 == ~E_3~0); 1623451#L893-1 assume !(0 == ~E_4~0); 1623448#L898-1 assume !(0 == ~E_5~0); 1623449#L903-1 assume !(0 == ~E_6~0); 1623391#L908-1 assume !(0 == ~E_7~0); 1623190#L913-1 assume !(0 == ~E_8~0); 1622447#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1622448#L402 assume !(1 == ~m_pc~0); 1622868#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1622869#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1623550#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1623549#L1035 assume !(0 != activate_threads_~tmp~1#1); 1622881#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1622882#L421 assume !(1 == ~t1_pc~0); 1623426#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1623427#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1622872#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1622873#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1623437#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1623438#L440 assume !(1 == ~t2_pc~0); 1623511#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1623512#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1623491#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1623492#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1623548#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1622777#L459 assume !(1 == ~t3_pc~0); 1622778#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1623546#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1623544#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1623542#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1623541#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1622577#L478 assume !(1 == ~t4_pc~0); 1622578#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1623348#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1623349#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1622747#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1622748#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1623088#L497 assume !(1 == ~t5_pc~0); 1623089#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1623124#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1622840#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1622841#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1623369#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1623370#L516 assume !(1 == ~t6_pc~0); 1623281#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1623282#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1623479#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1622622#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1622623#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1623140#L535 assume !(1 == ~t7_pc~0); 1623315#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1623138#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1623139#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1623536#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1623535#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1623358#L554 assume !(1 == ~t8_pc~0); 1622410#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1622411#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1623231#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1622713#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1622714#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1622396#L931 assume !(1 == ~M_E~0); 1622397#L931-2 assume !(1 == ~T1_E~0); 1623406#L936-1 assume !(1 == ~T2_E~0); 1623459#L941-1 assume !(1 == ~T3_E~0); 1622883#L946-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1622884#L951-1 assume !(1 == ~T5_E~0); 1622639#L956-1 assume !(1 == ~T6_E~0); 1622640#L961-1 assume !(1 == ~T7_E~0); 1623040#L966-1 assume !(1 == ~T8_E~0); 1623041#L971-1 assume !(1 == ~E_1~0); 1623171#L976-1 assume !(1 == ~E_2~0); 1623130#L981-1 assume !(1 == ~E_3~0); 1622888#L986-1 assume !(1 == ~E_4~0); 1622667#L991-1 assume !(1 == ~E_5~0); 1622668#L996-1 assume !(1 == ~E_6~0); 1623431#L1001-1 assume !(1 == ~E_7~0); 1623084#L1006-1 assume !(1 == ~E_8~0); 1623085#L1011-1 assume { :end_inline_reset_delta_events } true; 1623379#L1272-2 [2021-11-20 05:52:36,417 INFO L793 eck$LassoCheckResult]: Loop: 1623379#L1272-2 assume !false; 1645376#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1645368#L813 assume !false; 1645362#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1645300#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1645291#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1645289#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1645286#L696 assume !(0 != eval_~tmp~0#1); 1645287#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1647181#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1647176#L838-3 assume !(0 == ~M_E~0); 1647172#L838-5 assume !(0 == ~T1_E~0); 1647168#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1647164#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1647160#L853-3 assume !(0 == ~T4_E~0); 1647155#L858-3 assume !(0 == ~T5_E~0); 1647150#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1647146#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1647141#L873-3 assume !(0 == ~T8_E~0); 1647134#L878-3 assume !(0 == ~E_1~0); 1647129#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1647124#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1647119#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1647113#L898-3 assume !(0 == ~E_5~0); 1647107#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1647101#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1647095#L913-3 assume !(0 == ~E_8~0); 1647091#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1647086#L402-27 assume !(1 == ~m_pc~0); 1647081#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1647076#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1647070#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1647065#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1647059#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1647053#L421-27 assume !(1 == ~t1_pc~0); 1647046#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1647040#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1647035#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1647030#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1647025#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1647020#L440-27 assume !(1 == ~t2_pc~0); 1647015#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1647010#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1647005#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1647000#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1646994#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1646989#L459-27 assume 1 == ~t3_pc~0; 1646981#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1646974#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1646967#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1646960#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1646954#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1646948#L478-27 assume !(1 == ~t4_pc~0); 1646238#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1646234#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1646230#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1646226#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1646222#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1646218#L497-27 assume 1 == ~t5_pc~0; 1646213#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1646208#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1646202#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1646198#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1646194#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1646190#L516-27 assume !(1 == ~t6_pc~0); 1646186#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1646182#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1646178#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1646174#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1646169#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1646164#L535-27 assume !(1 == ~t7_pc~0); 1646157#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1646151#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1646143#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1646137#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1646131#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1646124#L554-27 assume !(1 == ~t8_pc~0); 1646117#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1646110#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1646103#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1646096#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1646089#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1646083#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1646077#L931-5 assume !(1 == ~T1_E~0); 1646070#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1646063#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1646057#L946-3 assume !(1 == ~T4_E~0); 1645986#L951-3 assume !(1 == ~T5_E~0); 1645983#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1645981#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1645979#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1645977#L971-3 assume !(1 == ~E_1~0); 1645975#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1645973#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1645971#L986-3 assume !(1 == ~E_4~0); 1645969#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1645967#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1645965#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1645963#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1645961#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1645959#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1645876#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1645818#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1645811#L1291 assume !(0 == start_simulation_~tmp~3#1); 1645807#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1645664#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1645663#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1645662#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1645661#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1645406#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1645405#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1645393#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1623379#L1272-2 [2021-11-20 05:52:36,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:36,418 INFO L85 PathProgramCache]: Analyzing trace with hash 1518911875, now seen corresponding path program 1 times [2021-11-20 05:52:36,418 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:36,419 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [996028920] [2021-11-20 05:52:36,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:36,419 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:36,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:36,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:36,452 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:36,452 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [996028920] [2021-11-20 05:52:36,452 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [996028920] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:36,452 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:36,453 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:36,453 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [914454106] [2021-11-20 05:52:36,453 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:36,453 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:52:36,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:52:36,454 INFO L85 PathProgramCache]: Analyzing trace with hash 1854331782, now seen corresponding path program 1 times [2021-11-20 05:52:36,454 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:52:36,454 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1419541487] [2021-11-20 05:52:36,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:52:36,455 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:52:36,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:52:36,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:52:36,488 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:52:36,488 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1419541487] [2021-11-20 05:52:36,488 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1419541487] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:52:36,488 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:52:36,488 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:52:36,488 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1441337047] [2021-11-20 05:52:36,489 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:52:36,489 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:52:36,489 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:52:36,490 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 05:52:36,490 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 05:52:36,490 INFO L87 Difference]: Start difference. First operand 71983 states and 100751 transitions. cyclomatic complexity: 28800 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:36,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:52:36,849 INFO L93 Difference]: Finished difference Result 126369 states and 176849 transitions. [2021-11-20 05:52:36,849 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 05:52:36,850 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 126369 states and 176849 transitions. [2021-11-20 05:52:38,210 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 125750 [2021-11-20 05:52:38,569 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 126369 states to 126369 states and 176849 transitions. [2021-11-20 05:52:38,569 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 126369 [2021-11-20 05:52:38,642 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 126369 [2021-11-20 05:52:38,642 INFO L73 IsDeterministic]: Start isDeterministic. Operand 126369 states and 176849 transitions. [2021-11-20 05:52:38,709 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:52:38,709 INFO L681 BuchiCegarLoop]: Abstraction has 126369 states and 176849 transitions. [2021-11-20 05:52:38,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126369 states and 176849 transitions. [2021-11-20 05:52:39,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126369 to 63233. [2021-11-20 05:52:39,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63233 states, 63233 states have (on average 1.3994116995872408) internal successors, (88489), 63232 states have internal predecessors, (88489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:52:39,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63233 states to 63233 states and 88489 transitions. [2021-11-20 05:52:39,703 INFO L704 BuchiCegarLoop]: Abstraction has 63233 states and 88489 transitions. [2021-11-20 05:52:39,703 INFO L587 BuchiCegarLoop]: Abstraction has 63233 states and 88489 transitions. [2021-11-20 05:52:39,703 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-20 05:52:39,703 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63233 states and 88489 transitions.