./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.10.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 53f42b1a Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/bin/uautomizer-DQz5hQGWxF/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/bin/uautomizer-DQz5hQGWxF/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/bin/uautomizer-DQz5hQGWxF/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/bin/uautomizer-DQz5hQGWxF/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.10.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/bin/uautomizer-DQz5hQGWxF/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/bin/uautomizer-DQz5hQGWxF --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c68befe0cb772d649d152823cc17c89d77797d55cc04257d4beaaad2b518a7a0 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-53f42b1 [2021-11-20 05:32:24,800 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-20 05:32:24,803 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-20 05:32:24,856 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-20 05:32:24,857 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-20 05:32:24,861 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-20 05:32:24,863 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-20 05:32:24,866 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-20 05:32:24,869 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-20 05:32:24,875 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-20 05:32:24,876 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-20 05:32:24,877 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-20 05:32:24,878 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-20 05:32:24,880 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-20 05:32:24,882 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-20 05:32:24,887 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-20 05:32:24,889 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-20 05:32:24,890 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-20 05:32:24,892 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-20 05:32:24,900 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-20 05:32:24,902 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-20 05:32:24,904 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-20 05:32:24,907 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-20 05:32:24,908 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-20 05:32:24,917 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-20 05:32:24,917 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-20 05:32:24,918 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-20 05:32:24,919 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-20 05:32:24,920 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-20 05:32:24,922 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-20 05:32:24,922 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-20 05:32:24,923 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-20 05:32:24,925 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-20 05:32:24,926 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-20 05:32:24,927 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-20 05:32:24,928 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-20 05:32:24,928 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-20 05:32:24,929 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-20 05:32:24,929 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-20 05:32:24,930 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-20 05:32:24,931 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-20 05:32:24,932 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/bin/uautomizer-DQz5hQGWxF/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-20 05:32:24,978 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-20 05:32:24,978 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-20 05:32:24,979 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-20 05:32:24,979 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-20 05:32:24,980 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-20 05:32:24,981 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-20 05:32:24,981 INFO L138 SettingsManager]: * Use SBE=true [2021-11-20 05:32:24,981 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-20 05:32:24,981 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-20 05:32:24,982 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-20 05:32:24,983 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-20 05:32:24,983 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-20 05:32:24,983 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-20 05:32:24,983 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-20 05:32:24,984 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-20 05:32:24,984 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-20 05:32:24,984 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-20 05:32:24,984 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-20 05:32:24,984 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-20 05:32:24,985 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-20 05:32:24,985 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-20 05:32:24,985 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-20 05:32:24,985 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-20 05:32:24,986 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-20 05:32:24,986 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-20 05:32:24,986 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-20 05:32:24,987 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-20 05:32:24,988 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-20 05:32:24,988 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-20 05:32:24,988 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-20 05:32:24,988 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-20 05:32:24,989 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-20 05:32:24,990 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-20 05:32:24,990 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/bin/uautomizer-DQz5hQGWxF/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/bin/uautomizer-DQz5hQGWxF Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c68befe0cb772d649d152823cc17c89d77797d55cc04257d4beaaad2b518a7a0 [2021-11-20 05:32:25,250 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-20 05:32:25,271 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-20 05:32:25,274 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-20 05:32:25,275 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-20 05:32:25,276 INFO L275 PluginConnector]: CDTParser initialized [2021-11-20 05:32:25,278 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/bin/uautomizer-DQz5hQGWxF/../../sv-benchmarks/c/systemc/transmitter.10.cil.c [2021-11-20 05:32:25,357 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/bin/uautomizer-DQz5hQGWxF/data/d248cae57/50bd2b8a5f984aafb65a0cafa640f805/FLAGeb0da5933 [2021-11-20 05:32:25,836 INFO L306 CDTParser]: Found 1 translation units. [2021-11-20 05:32:25,837 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/sv-benchmarks/c/systemc/transmitter.10.cil.c [2021-11-20 05:32:25,850 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/bin/uautomizer-DQz5hQGWxF/data/d248cae57/50bd2b8a5f984aafb65a0cafa640f805/FLAGeb0da5933 [2021-11-20 05:32:26,181 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/bin/uautomizer-DQz5hQGWxF/data/d248cae57/50bd2b8a5f984aafb65a0cafa640f805 [2021-11-20 05:32:26,185 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-20 05:32:26,188 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-20 05:32:26,191 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-20 05:32:26,192 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-20 05:32:26,195 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-20 05:32:26,195 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 05:32:26" (1/1) ... [2021-11-20 05:32:26,197 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@47ec83e9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:32:26, skipping insertion in model container [2021-11-20 05:32:26,198 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 05:32:26" (1/1) ... [2021-11-20 05:32:26,205 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-20 05:32:26,271 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-20 05:32:26,500 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/sv-benchmarks/c/systemc/transmitter.10.cil.c[706,719] [2021-11-20 05:32:26,614 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-20 05:32:26,624 INFO L203 MainTranslator]: Completed pre-run [2021-11-20 05:32:26,635 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/sv-benchmarks/c/systemc/transmitter.10.cil.c[706,719] [2021-11-20 05:32:26,691 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-20 05:32:26,722 INFO L208 MainTranslator]: Completed translation [2021-11-20 05:32:26,723 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:32:26 WrapperNode [2021-11-20 05:32:26,723 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-20 05:32:26,724 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-20 05:32:26,724 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-20 05:32:26,724 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-20 05:32:26,735 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:32:26" (1/1) ... [2021-11-20 05:32:26,768 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:32:26" (1/1) ... [2021-11-20 05:32:26,863 INFO L137 Inliner]: procedures = 48, calls = 60, calls flagged for inlining = 55, calls inlined = 196, statements flattened = 2994 [2021-11-20 05:32:26,863 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-20 05:32:26,864 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-20 05:32:26,864 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-20 05:32:26,864 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-20 05:32:26,872 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:32:26" (1/1) ... [2021-11-20 05:32:26,872 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:32:26" (1/1) ... [2021-11-20 05:32:26,887 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:32:26" (1/1) ... [2021-11-20 05:32:26,887 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:32:26" (1/1) ... [2021-11-20 05:32:26,925 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:32:26" (1/1) ... [2021-11-20 05:32:26,969 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:32:26" (1/1) ... [2021-11-20 05:32:26,976 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:32:26" (1/1) ... [2021-11-20 05:32:26,992 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-20 05:32:26,993 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-20 05:32:26,994 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-20 05:32:26,994 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-20 05:32:26,995 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:32:26" (1/1) ... [2021-11-20 05:32:27,002 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-20 05:32:27,018 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/bin/uautomizer-DQz5hQGWxF/z3 [2021-11-20 05:32:27,031 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-20 05:32:27,060 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2af80219-14ef-4c80-a9fd-67a4a0499d83/bin/uautomizer-DQz5hQGWxF/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-20 05:32:27,084 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-11-20 05:32:27,085 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-20 05:32:27,085 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-20 05:32:27,085 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-20 05:32:27,193 INFO L236 CfgBuilder]: Building ICFG [2021-11-20 05:32:27,195 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-11-20 05:32:28,668 INFO L277 CfgBuilder]: Performing block encoding [2021-11-20 05:32:28,693 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-20 05:32:28,693 INFO L301 CfgBuilder]: Removed 14 assume(true) statements. [2021-11-20 05:32:28,697 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 05:32:28 BoogieIcfgContainer [2021-11-20 05:32:28,698 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-20 05:32:28,699 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-20 05:32:28,699 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-20 05:32:28,702 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-20 05:32:28,703 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 05:32:28,703 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 20.11 05:32:26" (1/3) ... [2021-11-20 05:32:28,705 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3735204a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 05:32:28, skipping insertion in model container [2021-11-20 05:32:28,705 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 05:32:28,705 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:32:26" (2/3) ... [2021-11-20 05:32:28,705 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3735204a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 05:32:28, skipping insertion in model container [2021-11-20 05:32:28,706 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-20 05:32:28,706 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 05:32:28" (3/3) ... [2021-11-20 05:32:28,707 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.10.cil.c [2021-11-20 05:32:28,752 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-20 05:32:28,752 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-20 05:32:28,753 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-20 05:32:28,753 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-20 05:32:28,753 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-20 05:32:28,753 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-20 05:32:28,753 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-20 05:32:28,753 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-20 05:32:28,794 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1285 states, 1284 states have (on average 1.5093457943925233) internal successors, (1938), 1284 states have internal predecessors, (1938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:28,911 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1144 [2021-11-20 05:32:28,911 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:32:28,911 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:32:28,933 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:28,934 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:28,934 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-20 05:32:28,937 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1285 states, 1284 states have (on average 1.5093457943925233) internal successors, (1938), 1284 states have internal predecessors, (1938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:28,956 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1144 [2021-11-20 05:32:28,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:32:28,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:32:28,960 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:28,961 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:28,970 INFO L791 eck$LassoCheckResult]: Stem: 617#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 1166#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1096#L1483true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1051#L694true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1270#L701true assume !(1 == ~m_i~0);~m_st~0 := 2; 1144#L701-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1164#L706-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 284#L711-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 132#L716-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1186#L721-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 878#L726-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1069#L731-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 850#L736-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 924#L741-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1224#L746-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 159#L751-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 792#L1006true assume !(0 == ~M_E~0); 83#L1006-2true assume !(0 == ~T1_E~0); 978#L1011-1true assume !(0 == ~T2_E~0); 1017#L1016-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1169#L1021-1true assume !(0 == ~T4_E~0); 25#L1026-1true assume !(0 == ~T5_E~0); 1237#L1031-1true assume !(0 == ~T6_E~0); 562#L1036-1true assume !(0 == ~T7_E~0); 559#L1041-1true assume !(0 == ~T8_E~0); 896#L1046-1true assume !(0 == ~T9_E~0); 178#L1051-1true assume !(0 == ~T10_E~0); 702#L1056-1true assume 0 == ~E_1~0;~E_1~0 := 1; 748#L1061-1true assume !(0 == ~E_2~0); 134#L1066-1true assume !(0 == ~E_3~0); 1061#L1071-1true assume !(0 == ~E_4~0); 680#L1076-1true assume !(0 == ~E_5~0); 88#L1081-1true assume !(0 == ~E_6~0); 271#L1086-1true assume !(0 == ~E_7~0); 1075#L1091-1true assume !(0 == ~E_8~0); 951#L1096-1true assume 0 == ~E_9~0;~E_9~0 := 1; 1170#L1101-1true assume !(0 == ~E_10~0); 308#L1106-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1086#L484true assume !(1 == ~m_pc~0); 371#L484-2true is_master_triggered_~__retres1~0#1 := 0; 495#L495true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 879#L496true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 795#L1245true assume !(0 != activate_threads_~tmp~1#1); 1206#L1245-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 554#L503true assume 1 == ~t1_pc~0; 566#L504true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 734#L514true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 694#L515true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 384#L1253true assume !(0 != activate_threads_~tmp___0~0#1); 40#L1253-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 900#L522true assume !(1 == ~t2_pc~0); 522#L522-2true is_transmit2_triggered_~__retres1~2#1 := 0; 141#L533true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 424#L534true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 880#L1261true assume !(0 != activate_threads_~tmp___1~0#1); 1197#L1261-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1040#L541true assume 1 == ~t3_pc~0; 483#L542true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 825#L552true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 238#L553true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 591#L1269true assume !(0 != activate_threads_~tmp___2~0#1); 525#L1269-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 964#L560true assume !(1 == ~t4_pc~0); 1067#L560-2true is_transmit4_triggered_~__retres1~4#1 := 0; 463#L571true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 447#L572true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24#L1277true assume !(0 != activate_threads_~tmp___3~0#1); 888#L1277-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 166#L579true assume 1 == ~t5_pc~0; 3#L580true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55#L590true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 453#L591true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1015#L1285true assume !(0 != activate_threads_~tmp___4~0#1); 1090#L1285-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1263#L598true assume 1 == ~t6_pc~0; 220#L599true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 409#L609true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1185#L610true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 833#L1293true assume !(0 != activate_threads_~tmp___5~0#1); 598#L1293-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 548#L617true assume !(1 == ~t7_pc~0); 459#L617-2true is_transmit7_triggered_~__retres1~7#1 := 0; 1180#L628true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 372#L629true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 902#L1301true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 327#L1301-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 595#L636true assume 1 == ~t8_pc~0; 445#L637true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 782#L647true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 309#L648true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 605#L1309true assume !(0 != activate_threads_~tmp___7~0#1); 415#L1309-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 684#L655true assume !(1 == ~t9_pc~0); 761#L655-2true is_transmit9_triggered_~__retres1~9#1 := 0; 1121#L666true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 196#L667true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1019#L1317true assume !(0 != activate_threads_~tmp___8~0#1); 618#L1317-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 961#L674true assume 1 == ~t10_pc~0; 78#L675true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1046#L685true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1203#L686true activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1284#L1325true assume !(0 != activate_threads_~tmp___9~0#1); 408#L1325-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 890#L1119true assume !(1 == ~M_E~0); 123#L1119-2true assume !(1 == ~T1_E~0); 354#L1124-1true assume !(1 == ~T2_E~0); 36#L1129-1true assume !(1 == ~T3_E~0); 533#L1134-1true assume !(1 == ~T4_E~0); 197#L1139-1true assume !(1 == ~T5_E~0); 325#L1144-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1244#L1149-1true assume !(1 == ~T7_E~0); 120#L1154-1true assume !(1 == ~T8_E~0); 169#L1159-1true assume !(1 == ~T9_E~0); 1213#L1164-1true assume !(1 == ~T10_E~0); 426#L1169-1true assume !(1 == ~E_1~0); 347#L1174-1true assume !(1 == ~E_2~0); 227#L1179-1true assume !(1 == ~E_3~0); 162#L1184-1true assume 1 == ~E_4~0;~E_4~0 := 2; 193#L1189-1true assume !(1 == ~E_5~0); 260#L1194-1true assume !(1 == ~E_6~0); 1257#L1199-1true assume !(1 == ~E_7~0); 233#L1204-1true assume !(1 == ~E_8~0); 1119#L1209-1true assume !(1 == ~E_9~0); 615#L1214-1true assume !(1 == ~E_10~0); 1211#L1219-1true assume { :end_inline_reset_delta_events } true; 18#L1520-2true [2021-11-20 05:32:28,974 INFO L793 eck$LassoCheckResult]: Loop: 18#L1520-2true assume !false; 1267#L1521true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 164#L981true assume !true; 322#L996true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1260#L694-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 321#L1006-3true assume 0 == ~M_E~0;~M_E~0 := 1; 959#L1006-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 731#L1011-3true assume !(0 == ~T2_E~0); 968#L1016-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 777#L1021-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 464#L1026-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1139#L1031-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 698#L1036-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1207#L1041-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 769#L1046-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1085#L1051-3true assume !(0 == ~T10_E~0); 699#L1056-3true assume 0 == ~E_1~0;~E_1~0 := 1; 175#L1061-3true assume 0 == ~E_2~0;~E_2~0 := 1; 177#L1066-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1227#L1071-3true assume 0 == ~E_4~0;~E_4~0 := 1; 992#L1076-3true assume 0 == ~E_5~0;~E_5~0 := 1; 67#L1081-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1140#L1086-3true assume 0 == ~E_7~0;~E_7~0 := 1; 91#L1091-3true assume !(0 == ~E_8~0); 1052#L1096-3true assume 0 == ~E_9~0;~E_9~0 := 1; 928#L1101-3true assume 0 == ~E_10~0;~E_10~0 := 1; 985#L1106-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 480#L484-33true assume 1 == ~m_pc~0; 1177#L485-11true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 418#L495-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 943#L496-11true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21#L1245-33true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 632#L1245-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 265#L503-33true assume !(1 == ~t1_pc~0); 895#L503-35true is_transmit1_triggered_~__retres1~1#1 := 0; 600#L514-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 530#L515-11true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 216#L1253-33true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 645#L1253-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 506#L522-33true assume 1 == ~t2_pc~0; 631#L523-11true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 85#L533-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 608#L534-11true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 804#L1261-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 521#L1261-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 875#L541-33true assume !(1 == ~t3_pc~0); 288#L541-35true is_transmit3_triggered_~__retres1~3#1 := 0; 20#L552-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 973#L553-11true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 500#L1269-33true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 932#L1269-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 693#L560-33true assume !(1 == ~t4_pc~0); 988#L560-35true is_transmit4_triggered_~__retres1~4#1 := 0; 57#L571-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189#L572-11true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1074#L1277-33true assume !(0 != activate_threads_~tmp___3~0#1); 672#L1277-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16#L579-33true assume 1 == ~t5_pc~0; 460#L580-11true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1033#L590-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1047#L591-11true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 549#L1285-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 569#L1285-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1035#L598-33true assume 1 == ~t6_pc~0; 1249#L599-11true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 278#L609-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 753#L610-11true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 192#L1293-33true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 901#L1293-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1155#L617-33true assume 1 == ~t7_pc~0; 918#L618-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 776#L628-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1002#L629-11true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1123#L1301-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 994#L1301-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50#L636-33true assume !(1 == ~t8_pc~0); 1010#L636-35true is_transmit8_triggered_~__retres1~8#1 := 0; 664#L647-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1165#L648-11true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1055#L1309-33true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 652#L1309-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1255#L655-33true assume 1 == ~t9_pc~0; 1171#L656-11true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 247#L666-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 487#L667-11true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 750#L1317-33true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1000#L1317-35true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 346#L674-33true assume !(1 == ~t10_pc~0); 1029#L674-35true is_transmit10_triggered_~__retres1~10#1 := 0; 1066#L685-11true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 202#L686-11true activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 512#L1325-33true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1060#L1325-35true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1093#L1119-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1101#L1119-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1261#L1124-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1150#L1129-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 214#L1134-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 497#L1139-3true assume !(1 == ~T5_E~0); 342#L1144-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 450#L1149-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1248#L1154-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 708#L1159-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1230#L1164-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1005#L1169-3true assume 1 == ~E_1~0;~E_1~0 := 2; 277#L1174-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1083#L1179-3true assume !(1 == ~E_3~0); 835#L1184-3true assume 1 == ~E_4~0;~E_4~0 := 2; 80#L1189-3true assume 1 == ~E_5~0;~E_5~0 := 2; 840#L1194-3true assume 1 == ~E_6~0;~E_6~0 := 2; 244#L1199-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1266#L1204-3true assume 1 == ~E_8~0;~E_8~0 := 2; 438#L1209-3true assume 1 == ~E_9~0;~E_9~0 := 2; 27#L1214-3true assume 1 == ~E_10~0;~E_10~0 := 2; 937#L1219-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 607#L764-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 945#L821-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 254#L822-1true start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 306#L1539true assume !(0 == start_simulation_~tmp~3#1); 501#L1539-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 428#L764-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 863#L821-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 386#L822-2true stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 250#L1494true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 739#L1501true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 903#L1502true start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 307#L1552true assume !(0 != start_simulation_~tmp___0~1#1); 18#L1520-2true [2021-11-20 05:32:28,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:28,981 INFO L85 PathProgramCache]: Analyzing trace with hash 1310232617, now seen corresponding path program 1 times [2021-11-20 05:32:28,989 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:28,990 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1273108138] [2021-11-20 05:32:28,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:28,991 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:29,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:29,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:29,221 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:29,221 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1273108138] [2021-11-20 05:32:29,222 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1273108138] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:29,222 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:29,222 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:29,224 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1987523159] [2021-11-20 05:32:29,225 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:29,229 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:32:29,230 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:29,231 INFO L85 PathProgramCache]: Analyzing trace with hash 1452797615, now seen corresponding path program 1 times [2021-11-20 05:32:29,231 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:29,231 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1563786335] [2021-11-20 05:32:29,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:29,232 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:29,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:29,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:29,293 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:29,293 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1563786335] [2021-11-20 05:32:29,293 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1563786335] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:29,294 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:29,294 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-20 05:32:29,294 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2109970932] [2021-11-20 05:32:29,294 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:29,296 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:32:29,297 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:32:29,345 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:32:29,345 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:32:29,350 INFO L87 Difference]: Start difference. First operand has 1285 states, 1284 states have (on average 1.5093457943925233) internal successors, (1938), 1284 states have internal predecessors, (1938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:29,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:32:29,439 INFO L93 Difference]: Finished difference Result 1284 states and 1907 transitions. [2021-11-20 05:32:29,440 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:32:29,447 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1284 states and 1907 transitions. [2021-11-20 05:32:29,461 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-11-20 05:32:29,479 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1284 states to 1278 states and 1901 transitions. [2021-11-20 05:32:29,480 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2021-11-20 05:32:29,483 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2021-11-20 05:32:29,484 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1901 transitions. [2021-11-20 05:32:29,494 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:32:29,495 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1901 transitions. [2021-11-20 05:32:29,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1901 transitions. [2021-11-20 05:32:29,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2021-11-20 05:32:29,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4874804381846636) internal successors, (1901), 1277 states have internal predecessors, (1901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:29,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1901 transitions. [2021-11-20 05:32:29,602 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1901 transitions. [2021-11-20 05:32:29,602 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1901 transitions. [2021-11-20 05:32:29,602 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-20 05:32:29,603 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1901 transitions. [2021-11-20 05:32:29,611 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-11-20 05:32:29,612 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:32:29,612 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:32:29,615 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:29,615 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:29,616 INFO L791 eck$LassoCheckResult]: Stem: 3560#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 3561#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3835#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3823#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3824#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 3844#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3845#L706-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3128#L711-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2846#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2847#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3753#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3754#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3739#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3740#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3775#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 2900#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2901#L1006 assume !(0 == ~M_E~0); 2749#L1006-2 assume !(0 == ~T1_E~0); 2750#L1011-1 assume !(0 == ~T2_E~0); 3797#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3812#L1021-1 assume !(0 == ~T4_E~0); 2631#L1026-1 assume !(0 == ~T5_E~0); 2632#L1031-1 assume !(0 == ~T6_E~0); 3505#L1036-1 assume !(0 == ~T7_E~0); 3501#L1041-1 assume !(0 == ~T8_E~0); 3502#L1046-1 assume !(0 == ~T9_E~0); 2931#L1051-1 assume !(0 == ~T10_E~0); 2932#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 3634#L1061-1 assume !(0 == ~E_2~0); 2850#L1066-1 assume !(0 == ~E_3~0); 2851#L1071-1 assume !(0 == ~E_4~0); 3613#L1076-1 assume !(0 == ~E_5~0); 2760#L1081-1 assume !(0 == ~E_6~0); 2761#L1086-1 assume !(0 == ~E_7~0); 3103#L1091-1 assume !(0 == ~E_8~0); 3790#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 3791#L1101-1 assume !(0 == ~E_10~0); 3165#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3166#L484 assume !(1 == ~m_pc~0); 2809#L484-2 is_master_triggered_~__retres1~0#1 := 0; 2808#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3424#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3708#L1245 assume !(0 != activate_threads_~tmp~1#1); 3709#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3493#L503 assume 1 == ~t1_pc~0; 3494#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3511#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3626#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3279#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 2659#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2660#L522 assume !(1 == ~t2_pc~0); 3460#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2863#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2864#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3334#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 3755#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3820#L541 assume 1 == ~t3_pc~0; 3409#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3225#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3040#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3041#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 3463#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3464#L560 assume !(1 == ~t4_pc~0); 2743#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2742#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3368#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2627#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 2628#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2914#L579 assume 1 == ~t5_pc~0; 2578#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2579#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2687#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3371#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 3811#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3832#L598 assume 1 == ~t6_pc~0; 3008#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3009#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3311#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3731#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 3542#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3484#L617 assume !(1 == ~t7_pc~0); 2981#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2980#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3266#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3267#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3202#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3203#L636 assume 1 == ~t8_pc~0; 3365#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3366#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3167#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3168#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 3318#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3319#L655 assume !(1 == ~t9_pc~0); 3348#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3349#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2960#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2961#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 3562#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3563#L674 assume 1 == ~t10_pc~0; 2736#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2737#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3822#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3853#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 3308#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3309#L1119 assume !(1 == ~M_E~0); 2832#L1119-2 assume !(1 == ~T1_E~0); 2833#L1124-1 assume !(1 == ~T2_E~0); 2651#L1129-1 assume !(1 == ~T3_E~0); 2652#L1134-1 assume !(1 == ~T4_E~0); 2965#L1139-1 assume !(1 == ~T5_E~0); 2966#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3198#L1149-1 assume !(1 == ~T7_E~0); 2827#L1154-1 assume !(1 == ~T8_E~0); 2828#L1159-1 assume !(1 == ~T9_E~0); 2915#L1164-1 assume !(1 == ~T10_E~0); 3337#L1169-1 assume !(1 == ~E_1~0); 3235#L1174-1 assume !(1 == ~E_2~0); 3022#L1179-1 assume !(1 == ~E_3~0); 2904#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2905#L1189-1 assume !(1 == ~E_5~0); 2958#L1194-1 assume !(1 == ~E_6~0); 3081#L1199-1 assume !(1 == ~E_7~0); 3032#L1204-1 assume !(1 == ~E_8~0); 3033#L1209-1 assume !(1 == ~E_9~0); 3556#L1214-1 assume !(1 == ~E_10~0); 3557#L1219-1 assume { :end_inline_reset_delta_events } true; 2615#L1520-2 [2021-11-20 05:32:29,617 INFO L793 eck$LassoCheckResult]: Loop: 2615#L1520-2 assume !false; 2616#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2719#L981 assume !false; 2911#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3583#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2601#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3701#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3751#L836 assume !(0 != eval_~tmp~0#1); 3193#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3194#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3189#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3190#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3660#L1011-3 assume !(0 == ~T2_E~0); 3661#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3700#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3383#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3384#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3628#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3629#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3691#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3692#L1051-3 assume !(0 == ~T10_E~0); 3630#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2928#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2929#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2930#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3801#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2713#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2714#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2768#L1091-3 assume !(0 == ~E_8~0); 2769#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3776#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3777#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3403#L484-33 assume 1 == ~m_pc~0; 3404#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3323#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3324#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2621#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2622#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3093#L503-33 assume !(1 == ~t1_pc~0); 3094#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 3544#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3473#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3000#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3001#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3440#L522-33 assume 1 == ~t2_pc~0; 3441#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2756#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2757#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3550#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3458#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3459#L541-33 assume 1 == ~t3_pc~0; 2780#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2619#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2620#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3430#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3431#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3625#L560-33 assume 1 == ~t4_pc~0; 3330#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2691#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2692#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2948#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 3607#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2607#L579-33 assume 1 == ~t5_pc~0; 2608#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2856#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3816#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3485#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3486#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3510#L598-33 assume !(1 == ~t6_pc~0); 3283#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 3114#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3115#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2955#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2956#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3765#L617-33 assume 1 == ~t7_pc~0; 3771#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2748#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3699#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3806#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3802#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2679#L636-33 assume !(1 == ~t8_pc~0); 2680#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 3599#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3600#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3825#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3588#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3589#L655-33 assume 1 == ~t9_pc~0; 3849#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3055#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3056#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3414#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3678#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3234#L674-33 assume 1 == ~t10_pc~0; 3109#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3110#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2971#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2972#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3449#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3826#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3833#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3836#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3847#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2993#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2994#L1139-3 assume !(1 == ~T5_E~0); 3227#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3228#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3370#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3640#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3641#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3807#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3112#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3113#L1179-3 assume !(1 == ~E_3~0); 3732#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2739#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2740#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3053#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3054#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3357#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2633#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2634#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3547#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2716#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3070#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3071#L1539 assume !(0 == start_simulation_~tmp~3#1); 3163#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3339#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3146#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3278#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 3062#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3063#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3667#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3164#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 2615#L1520-2 [2021-11-20 05:32:29,617 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:29,618 INFO L85 PathProgramCache]: Analyzing trace with hash -934325781, now seen corresponding path program 1 times [2021-11-20 05:32:29,618 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:29,618 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039819642] [2021-11-20 05:32:29,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:29,619 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:29,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:29,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:29,712 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:29,712 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1039819642] [2021-11-20 05:32:29,713 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1039819642] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:29,713 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:29,713 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:29,713 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1263436119] [2021-11-20 05:32:29,713 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:29,714 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:32:29,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:29,714 INFO L85 PathProgramCache]: Analyzing trace with hash -1410939798, now seen corresponding path program 1 times [2021-11-20 05:32:29,715 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:29,715 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [141083049] [2021-11-20 05:32:29,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:29,715 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:29,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:29,839 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:29,840 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:29,840 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [141083049] [2021-11-20 05:32:29,840 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [141083049] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:29,840 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:29,841 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:29,841 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [616438131] [2021-11-20 05:32:29,841 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:29,842 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:32:29,842 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:32:29,842 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:32:29,842 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:32:29,843 INFO L87 Difference]: Start difference. First operand 1278 states and 1901 transitions. cyclomatic complexity: 624 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:29,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:32:29,875 INFO L93 Difference]: Finished difference Result 1278 states and 1900 transitions. [2021-11-20 05:32:29,875 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:32:29,876 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1900 transitions. [2021-11-20 05:32:29,889 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-11-20 05:32:29,903 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1900 transitions. [2021-11-20 05:32:29,903 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2021-11-20 05:32:29,905 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2021-11-20 05:32:29,905 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1900 transitions. [2021-11-20 05:32:29,908 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:32:29,908 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1900 transitions. [2021-11-20 05:32:29,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1900 transitions. [2021-11-20 05:32:29,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2021-11-20 05:32:29,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.486697965571205) internal successors, (1900), 1277 states have internal predecessors, (1900), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:29,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1900 transitions. [2021-11-20 05:32:29,937 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1900 transitions. [2021-11-20 05:32:29,937 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1900 transitions. [2021-11-20 05:32:29,937 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-20 05:32:29,937 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1900 transitions. [2021-11-20 05:32:29,945 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-11-20 05:32:29,945 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:32:29,945 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:32:29,948 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:29,948 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:29,949 INFO L791 eck$LassoCheckResult]: Stem: 6123#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 6124#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6398#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6386#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6387#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 6407#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6408#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5691#L711-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5411#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5412#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6316#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6317#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6302#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6303#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6338#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5463#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5464#L1006 assume !(0 == ~M_E~0); 5315#L1006-2 assume !(0 == ~T1_E~0); 5316#L1011-1 assume !(0 == ~T2_E~0); 6360#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6375#L1021-1 assume !(0 == ~T4_E~0); 5194#L1026-1 assume !(0 == ~T5_E~0); 5195#L1031-1 assume !(0 == ~T6_E~0); 6070#L1036-1 assume !(0 == ~T7_E~0); 6064#L1041-1 assume !(0 == ~T8_E~0); 6065#L1046-1 assume !(0 == ~T9_E~0); 5494#L1051-1 assume !(0 == ~T10_E~0); 5495#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6197#L1061-1 assume !(0 == ~E_2~0); 5413#L1066-1 assume !(0 == ~E_3~0); 5414#L1071-1 assume !(0 == ~E_4~0); 6176#L1076-1 assume !(0 == ~E_5~0); 5323#L1081-1 assume !(0 == ~E_6~0); 5324#L1086-1 assume !(0 == ~E_7~0); 5667#L1091-1 assume !(0 == ~E_8~0); 6353#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 6354#L1101-1 assume !(0 == ~E_10~0); 5728#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5729#L484 assume !(1 == ~m_pc~0); 5372#L484-2 is_master_triggered_~__retres1~0#1 := 0; 5371#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5987#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6271#L1245 assume !(0 != activate_threads_~tmp~1#1); 6272#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6056#L503 assume 1 == ~t1_pc~0; 6057#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6075#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6189#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5842#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 5224#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5225#L522 assume !(1 == ~t2_pc~0); 6023#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5427#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5428#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5897#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 6318#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6383#L541 assume 1 == ~t3_pc~0; 5974#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5788#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5603#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5604#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 6030#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6031#L560 assume !(1 == ~t4_pc~0); 5306#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5305#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5931#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5190#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 5191#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5477#L579 assume 1 == ~t5_pc~0; 5141#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5142#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5250#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5934#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 6374#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6395#L598 assume 1 == ~t6_pc~0; 5573#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5574#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5876#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6294#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 6105#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6047#L617 assume !(1 == ~t7_pc~0); 5544#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5543#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5829#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5830#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5766#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5767#L636 assume 1 == ~t8_pc~0; 5928#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5929#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5730#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5731#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 5883#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5884#L655 assume !(1 == ~t9_pc~0); 5913#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5914#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5523#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5524#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 6125#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6126#L674 assume 1 == ~t10_pc~0; 5299#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5300#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6385#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6416#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 5871#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5872#L1119 assume !(1 == ~M_E~0); 5395#L1119-2 assume !(1 == ~T1_E~0); 5396#L1124-1 assume !(1 == ~T2_E~0); 5214#L1129-1 assume !(1 == ~T3_E~0); 5215#L1134-1 assume !(1 == ~T4_E~0); 5528#L1139-1 assume !(1 == ~T5_E~0); 5529#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5761#L1149-1 assume !(1 == ~T7_E~0); 5390#L1154-1 assume !(1 == ~T8_E~0); 5391#L1159-1 assume !(1 == ~T9_E~0); 5478#L1164-1 assume !(1 == ~T10_E~0); 5900#L1169-1 assume !(1 == ~E_1~0); 5798#L1174-1 assume !(1 == ~E_2~0); 5587#L1179-1 assume !(1 == ~E_3~0); 5467#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5468#L1189-1 assume !(1 == ~E_5~0); 5522#L1194-1 assume !(1 == ~E_6~0); 5644#L1199-1 assume !(1 == ~E_7~0); 5595#L1204-1 assume !(1 == ~E_8~0); 5596#L1209-1 assume !(1 == ~E_9~0); 6119#L1214-1 assume !(1 == ~E_10~0); 6120#L1219-1 assume { :end_inline_reset_delta_events } true; 5178#L1520-2 [2021-11-20 05:32:29,949 INFO L793 eck$LassoCheckResult]: Loop: 5178#L1520-2 assume !false; 5179#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5279#L981 assume !false; 5474#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6146#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5164#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6264#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6314#L836 assume !(0 != eval_~tmp~0#1); 5759#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5760#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5752#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5753#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6223#L1011-3 assume !(0 == ~T2_E~0); 6224#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6263#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5946#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5947#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6191#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6192#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6252#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6253#L1051-3 assume !(0 == ~T10_E~0); 6193#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5489#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5490#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5493#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6364#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5276#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5277#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5329#L1091-3 assume !(0 == ~E_8~0); 5330#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6339#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6340#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5966#L484-33 assume !(1 == ~m_pc~0); 5968#L484-35 is_master_triggered_~__retres1~0#1 := 0; 5886#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5887#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5184#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5185#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5653#L503-33 assume !(1 == ~t1_pc~0); 5654#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 6107#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6033#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5561#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5562#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6003#L522-33 assume 1 == ~t2_pc~0; 6004#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5317#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5318#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6112#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6021#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6022#L541-33 assume !(1 == ~t3_pc~0); 5344#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 5182#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5183#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5993#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5994#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6188#L560-33 assume 1 == ~t4_pc~0; 5893#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5254#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5255#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5513#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 6170#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5173#L579-33 assume 1 == ~t5_pc~0; 5174#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5420#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6379#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6048#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6049#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6074#L598-33 assume !(1 == ~t6_pc~0); 5851#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 5677#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5678#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5518#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5519#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6328#L617-33 assume 1 == ~t7_pc~0; 6334#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5311#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6262#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6369#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6365#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5242#L636-33 assume !(1 == ~t8_pc~0); 5243#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 6162#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6163#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6388#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6153#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6154#L655-33 assume 1 == ~t9_pc~0; 6412#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5618#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5619#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5977#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6241#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5797#L674-33 assume 1 == ~t10_pc~0; 5672#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5673#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5534#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5535#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6012#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6389#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6396#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6399#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6410#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5559#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5560#L1139-3 assume !(1 == ~T5_E~0); 5790#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5791#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5933#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6203#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6204#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6370#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5675#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5676#L1179-3 assume !(1 == ~E_3~0); 6295#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5302#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5303#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5616#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5617#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5920#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5196#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5197#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6111#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5282#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5633#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 5634#L1539 assume !(0 == start_simulation_~tmp~3#1); 5726#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5902#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5709#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5841#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 5625#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5626#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6230#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 5727#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 5178#L1520-2 [2021-11-20 05:32:29,950 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:29,950 INFO L85 PathProgramCache]: Analyzing trace with hash 158309421, now seen corresponding path program 1 times [2021-11-20 05:32:29,950 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:29,951 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [341729075] [2021-11-20 05:32:29,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:29,951 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:29,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:30,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:30,013 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:30,013 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [341729075] [2021-11-20 05:32:30,013 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [341729075] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:30,014 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:30,014 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:30,014 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [803761064] [2021-11-20 05:32:30,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:30,015 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:32:30,015 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:30,019 INFO L85 PathProgramCache]: Analyzing trace with hash -103858072, now seen corresponding path program 1 times [2021-11-20 05:32:30,019 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:30,020 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [502177420] [2021-11-20 05:32:30,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:30,020 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:30,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:30,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:30,111 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:30,111 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [502177420] [2021-11-20 05:32:30,111 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [502177420] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:30,111 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:30,112 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:30,112 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [334255136] [2021-11-20 05:32:30,113 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:30,113 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:32:30,113 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:32:30,114 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:32:30,114 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:32:30,115 INFO L87 Difference]: Start difference. First operand 1278 states and 1900 transitions. cyclomatic complexity: 623 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:30,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:32:30,166 INFO L93 Difference]: Finished difference Result 1278 states and 1899 transitions. [2021-11-20 05:32:30,167 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:32:30,168 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1899 transitions. [2021-11-20 05:32:30,178 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-11-20 05:32:30,189 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1899 transitions. [2021-11-20 05:32:30,189 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2021-11-20 05:32:30,190 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2021-11-20 05:32:30,190 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1899 transitions. [2021-11-20 05:32:30,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:32:30,193 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1899 transitions. [2021-11-20 05:32:30,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1899 transitions. [2021-11-20 05:32:30,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2021-11-20 05:32:30,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4859154929577465) internal successors, (1899), 1277 states have internal predecessors, (1899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:30,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1899 transitions. [2021-11-20 05:32:30,222 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1899 transitions. [2021-11-20 05:32:30,222 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1899 transitions. [2021-11-20 05:32:30,222 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-20 05:32:30,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1899 transitions. [2021-11-20 05:32:30,230 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-11-20 05:32:30,231 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:32:30,231 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:32:30,233 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:30,233 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:30,234 INFO L791 eck$LassoCheckResult]: Stem: 8685#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 8686#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 8961#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8949#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8950#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 8970#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8971#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8254#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7972#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7973#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8879#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8880#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8865#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8866#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8901#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8024#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8025#L1006 assume !(0 == ~M_E~0); 7875#L1006-2 assume !(0 == ~T1_E~0); 7876#L1011-1 assume !(0 == ~T2_E~0); 8923#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8938#L1021-1 assume !(0 == ~T4_E~0); 7755#L1026-1 assume !(0 == ~T5_E~0); 7756#L1031-1 assume !(0 == ~T6_E~0); 8631#L1036-1 assume !(0 == ~T7_E~0); 8627#L1041-1 assume !(0 == ~T8_E~0); 8628#L1046-1 assume !(0 == ~T9_E~0); 8057#L1051-1 assume !(0 == ~T10_E~0); 8058#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8760#L1061-1 assume !(0 == ~E_2~0); 7976#L1066-1 assume !(0 == ~E_3~0); 7977#L1071-1 assume !(0 == ~E_4~0); 8739#L1076-1 assume !(0 == ~E_5~0); 7886#L1081-1 assume !(0 == ~E_6~0); 7887#L1086-1 assume !(0 == ~E_7~0); 8229#L1091-1 assume !(0 == ~E_8~0); 8915#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 8916#L1101-1 assume !(0 == ~E_10~0); 8291#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8292#L484 assume !(1 == ~m_pc~0); 7935#L484-2 is_master_triggered_~__retres1~0#1 := 0; 7934#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8550#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8834#L1245 assume !(0 != activate_threads_~tmp~1#1); 8835#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8619#L503 assume 1 == ~t1_pc~0; 8620#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8636#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8752#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8402#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 7785#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7786#L522 assume !(1 == ~t2_pc~0); 8586#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7989#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7990#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8460#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 8881#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8946#L541 assume 1 == ~t3_pc~0; 8535#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8351#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8166#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8167#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 8589#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8590#L560 assume !(1 == ~t4_pc~0); 7867#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7866#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8494#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7753#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 7754#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8038#L579 assume 1 == ~t5_pc~0; 7704#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7705#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7813#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8497#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 8936#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8958#L598 assume 1 == ~t6_pc~0; 8134#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8135#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8436#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8857#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 8668#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8610#L617 assume !(1 == ~t7_pc~0); 8107#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8106#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8392#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8393#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8328#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8329#L636 assume 1 == ~t8_pc~0; 8491#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8492#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8293#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8294#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 8444#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8445#L655 assume !(1 == ~t9_pc~0); 8472#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 8473#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8086#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8087#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 8687#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8688#L674 assume 1 == ~t10_pc~0; 7862#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7863#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8948#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8979#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 8434#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8435#L1119 assume !(1 == ~M_E~0); 7958#L1119-2 assume !(1 == ~T1_E~0); 7959#L1124-1 assume !(1 == ~T2_E~0); 7777#L1129-1 assume !(1 == ~T3_E~0); 7778#L1134-1 assume !(1 == ~T4_E~0); 8088#L1139-1 assume !(1 == ~T5_E~0); 8089#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8324#L1149-1 assume !(1 == ~T7_E~0); 7953#L1154-1 assume !(1 == ~T8_E~0); 7954#L1159-1 assume !(1 == ~T9_E~0); 8041#L1164-1 assume !(1 == ~T10_E~0); 8463#L1169-1 assume !(1 == ~E_1~0); 8361#L1174-1 assume !(1 == ~E_2~0); 8148#L1179-1 assume !(1 == ~E_3~0); 8030#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8031#L1189-1 assume !(1 == ~E_5~0); 8083#L1194-1 assume !(1 == ~E_6~0); 8207#L1199-1 assume !(1 == ~E_7~0); 8158#L1204-1 assume !(1 == ~E_8~0); 8159#L1209-1 assume !(1 == ~E_9~0); 8682#L1214-1 assume !(1 == ~E_10~0); 8683#L1219-1 assume { :end_inline_reset_delta_events } true; 7741#L1520-2 [2021-11-20 05:32:30,234 INFO L793 eck$LassoCheckResult]: Loop: 7741#L1520-2 assume !false; 7742#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7842#L981 assume !false; 8034#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8709#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 7727#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8827#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8877#L836 assume !(0 != eval_~tmp~0#1); 8319#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8320#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8315#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8316#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8786#L1011-3 assume !(0 == ~T2_E~0); 8787#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8826#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8507#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8508#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8754#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8755#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8815#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8816#L1051-3 assume !(0 == ~T10_E~0); 8756#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8052#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8053#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8056#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8927#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7839#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7840#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7892#L1091-3 assume !(0 == ~E_8~0); 7893#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8902#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8903#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8529#L484-33 assume 1 == ~m_pc~0; 8530#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8449#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8450#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7747#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7748#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8216#L503-33 assume !(1 == ~t1_pc~0); 8217#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 8670#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8597#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8126#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8127#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8566#L522-33 assume 1 == ~t2_pc~0; 8567#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7880#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7881#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8675#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8584#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8585#L541-33 assume 1 == ~t3_pc~0; 7906#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7745#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7746#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8556#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8557#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8751#L560-33 assume 1 == ~t4_pc~0; 8456#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7817#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7818#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8076#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 8733#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7736#L579-33 assume 1 == ~t5_pc~0; 7737#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7983#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8942#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8611#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8612#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8640#L598-33 assume 1 == ~t6_pc~0; 8944#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8240#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8241#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8081#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8082#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8891#L617-33 assume 1 == ~t7_pc~0; 8897#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7874#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8825#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8932#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8928#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7805#L636-33 assume !(1 == ~t8_pc~0); 7806#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 8725#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8726#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8951#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8716#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8717#L655-33 assume !(1 == ~t9_pc~0); 8976#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 8183#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8184#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8540#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8804#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8360#L674-33 assume 1 == ~t10_pc~0; 8235#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8236#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8097#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8098#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8575#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8952#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8959#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8963#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8973#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8122#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8123#L1139-3 assume !(1 == ~T5_E~0); 8353#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8354#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8496#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8766#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8767#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8934#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8238#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8239#L1179-3 assume !(1 == ~E_3~0); 8858#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7868#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7869#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8179#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8180#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8483#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7759#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7760#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8674#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 7845#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8196#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 8197#L1539 assume !(0 == start_simulation_~tmp~3#1); 8289#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8465#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8272#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8405#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 8188#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8189#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8793#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 8290#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 7741#L1520-2 [2021-11-20 05:32:30,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:30,235 INFO L85 PathProgramCache]: Analyzing trace with hash 1440481707, now seen corresponding path program 1 times [2021-11-20 05:32:30,235 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:30,235 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131752892] [2021-11-20 05:32:30,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:30,236 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:30,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:30,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:30,272 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:30,273 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [131752892] [2021-11-20 05:32:30,273 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [131752892] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:30,273 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:30,273 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:30,273 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [420858309] [2021-11-20 05:32:30,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:30,274 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:32:30,275 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:30,275 INFO L85 PathProgramCache]: Analyzing trace with hash 871104042, now seen corresponding path program 1 times [2021-11-20 05:32:30,275 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:30,275 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1852633790] [2021-11-20 05:32:30,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:30,276 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:30,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:30,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:30,324 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:30,324 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1852633790] [2021-11-20 05:32:30,324 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1852633790] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:30,325 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:30,325 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:30,325 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1533208819] [2021-11-20 05:32:30,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:30,326 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:32:30,326 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:32:30,326 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:32:30,326 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:32:30,327 INFO L87 Difference]: Start difference. First operand 1278 states and 1899 transitions. cyclomatic complexity: 622 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:30,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:32:30,353 INFO L93 Difference]: Finished difference Result 1278 states and 1898 transitions. [2021-11-20 05:32:30,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:32:30,355 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1898 transitions. [2021-11-20 05:32:30,365 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-11-20 05:32:30,376 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1898 transitions. [2021-11-20 05:32:30,376 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2021-11-20 05:32:30,378 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2021-11-20 05:32:30,378 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1898 transitions. [2021-11-20 05:32:30,380 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:32:30,380 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1898 transitions. [2021-11-20 05:32:30,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1898 transitions. [2021-11-20 05:32:30,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2021-11-20 05:32:30,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4851330203442878) internal successors, (1898), 1277 states have internal predecessors, (1898), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:30,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1898 transitions. [2021-11-20 05:32:30,409 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1898 transitions. [2021-11-20 05:32:30,409 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1898 transitions. [2021-11-20 05:32:30,410 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-20 05:32:30,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1898 transitions. [2021-11-20 05:32:30,417 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-11-20 05:32:30,418 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:32:30,418 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:32:30,420 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:30,420 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:30,421 INFO L791 eck$LassoCheckResult]: Stem: 11248#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 11249#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 11524#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11512#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11513#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 11533#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11534#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10817#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10535#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10536#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11442#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11443#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11428#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11429#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11464#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10587#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10588#L1006 assume !(0 == ~M_E~0); 10438#L1006-2 assume !(0 == ~T1_E~0); 10439#L1011-1 assume !(0 == ~T2_E~0); 11486#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11501#L1021-1 assume !(0 == ~T4_E~0); 10318#L1026-1 assume !(0 == ~T5_E~0); 10319#L1031-1 assume !(0 == ~T6_E~0); 11194#L1036-1 assume !(0 == ~T7_E~0); 11190#L1041-1 assume !(0 == ~T8_E~0); 11191#L1046-1 assume !(0 == ~T9_E~0); 10620#L1051-1 assume !(0 == ~T10_E~0); 10621#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 11323#L1061-1 assume !(0 == ~E_2~0); 10539#L1066-1 assume !(0 == ~E_3~0); 10540#L1071-1 assume !(0 == ~E_4~0); 11302#L1076-1 assume !(0 == ~E_5~0); 10449#L1081-1 assume !(0 == ~E_6~0); 10450#L1086-1 assume !(0 == ~E_7~0); 10792#L1091-1 assume !(0 == ~E_8~0); 11478#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 11479#L1101-1 assume !(0 == ~E_10~0); 10854#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10855#L484 assume !(1 == ~m_pc~0); 10498#L484-2 is_master_triggered_~__retres1~0#1 := 0; 10497#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11113#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11397#L1245 assume !(0 != activate_threads_~tmp~1#1); 11398#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11182#L503 assume 1 == ~t1_pc~0; 11183#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11199#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11315#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10965#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 10348#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10349#L522 assume !(1 == ~t2_pc~0); 11149#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10552#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10553#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11023#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 11444#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11509#L541 assume 1 == ~t3_pc~0; 11098#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10914#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10729#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10730#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 11152#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11153#L560 assume !(1 == ~t4_pc~0); 10430#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10429#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11057#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10316#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 10317#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10601#L579 assume 1 == ~t5_pc~0; 10267#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10268#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10376#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11060#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 11499#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11521#L598 assume 1 == ~t6_pc~0; 10697#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10698#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10999#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11420#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 11231#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11173#L617 assume !(1 == ~t7_pc~0); 10670#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10669#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10955#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10956#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10891#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10892#L636 assume 1 == ~t8_pc~0; 11054#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11055#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10856#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10857#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 11007#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11008#L655 assume !(1 == ~t9_pc~0); 11035#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 11036#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10649#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10650#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 11250#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11251#L674 assume 1 == ~t10_pc~0; 10425#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10426#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11511#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11542#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 10997#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10998#L1119 assume !(1 == ~M_E~0); 10521#L1119-2 assume !(1 == ~T1_E~0); 10522#L1124-1 assume !(1 == ~T2_E~0); 10340#L1129-1 assume !(1 == ~T3_E~0); 10341#L1134-1 assume !(1 == ~T4_E~0); 10652#L1139-1 assume !(1 == ~T5_E~0); 10653#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10887#L1149-1 assume !(1 == ~T7_E~0); 10516#L1154-1 assume !(1 == ~T8_E~0); 10517#L1159-1 assume !(1 == ~T9_E~0); 10604#L1164-1 assume !(1 == ~T10_E~0); 11026#L1169-1 assume !(1 == ~E_1~0); 10924#L1174-1 assume !(1 == ~E_2~0); 10711#L1179-1 assume !(1 == ~E_3~0); 10593#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10594#L1189-1 assume !(1 == ~E_5~0); 10646#L1194-1 assume !(1 == ~E_6~0); 10770#L1199-1 assume !(1 == ~E_7~0); 10721#L1204-1 assume !(1 == ~E_8~0); 10722#L1209-1 assume !(1 == ~E_9~0); 11245#L1214-1 assume !(1 == ~E_10~0); 11246#L1219-1 assume { :end_inline_reset_delta_events } true; 10304#L1520-2 [2021-11-20 05:32:30,421 INFO L793 eck$LassoCheckResult]: Loop: 10304#L1520-2 assume !false; 10305#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10405#L981 assume !false; 10597#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11272#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10290#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11390#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11440#L836 assume !(0 != eval_~tmp~0#1); 10882#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10883#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10878#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10879#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11349#L1011-3 assume !(0 == ~T2_E~0); 11350#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11389#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11070#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11071#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11317#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11318#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11378#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11379#L1051-3 assume !(0 == ~T10_E~0); 11319#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10615#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10616#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10619#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11490#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10402#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10403#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10455#L1091-3 assume !(0 == ~E_8~0); 10456#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11465#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11466#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11092#L484-33 assume 1 == ~m_pc~0; 11093#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11012#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11013#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10310#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10311#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10779#L503-33 assume !(1 == ~t1_pc~0); 10780#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 11233#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11160#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10689#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10690#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11129#L522-33 assume 1 == ~t2_pc~0; 11130#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10443#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10444#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11238#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11147#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11148#L541-33 assume 1 == ~t3_pc~0; 10469#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10308#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10309#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11119#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11120#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11314#L560-33 assume 1 == ~t4_pc~0; 11019#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10380#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10381#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10639#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 11296#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10299#L579-33 assume 1 == ~t5_pc~0; 10300#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10546#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11505#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11174#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11175#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11203#L598-33 assume !(1 == ~t6_pc~0); 10977#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 10803#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10804#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10644#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10645#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11454#L617-33 assume 1 == ~t7_pc~0; 11460#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10437#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11388#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11495#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11491#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10368#L636-33 assume !(1 == ~t8_pc~0); 10369#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 11288#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11289#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11514#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11279#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11280#L655-33 assume 1 == ~t9_pc~0; 11538#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10746#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10747#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11103#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11367#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10923#L674-33 assume !(1 == ~t10_pc~0); 10800#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 10799#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10660#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10661#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11138#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11515#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11522#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11526#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11536#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10685#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10686#L1139-3 assume !(1 == ~T5_E~0); 10916#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10917#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11059#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11329#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11330#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11497#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10801#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10802#L1179-3 assume !(1 == ~E_3~0); 11421#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10431#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10432#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10742#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10743#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11046#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10322#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10323#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11237#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10408#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10759#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 10760#L1539 assume !(0 == start_simulation_~tmp~3#1); 10852#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11028#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10835#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10968#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 10751#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10752#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11356#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 10853#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 10304#L1520-2 [2021-11-20 05:32:30,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:30,422 INFO L85 PathProgramCache]: Analyzing trace with hash -1012009875, now seen corresponding path program 1 times [2021-11-20 05:32:30,422 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:30,422 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [379220820] [2021-11-20 05:32:30,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:30,422 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:30,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:30,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:30,478 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:30,479 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [379220820] [2021-11-20 05:32:30,479 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [379220820] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:30,479 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:30,479 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:30,479 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2015988728] [2021-11-20 05:32:30,480 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:30,480 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:32:30,480 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:30,481 INFO L85 PathProgramCache]: Analyzing trace with hash -1010948599, now seen corresponding path program 1 times [2021-11-20 05:32:30,481 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:30,481 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1124262299] [2021-11-20 05:32:30,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:30,481 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:30,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:30,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:30,525 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:30,525 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1124262299] [2021-11-20 05:32:30,526 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1124262299] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:30,526 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:30,526 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:30,526 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [82452350] [2021-11-20 05:32:30,526 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:30,527 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:32:30,527 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:32:30,527 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:32:30,527 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:32:30,528 INFO L87 Difference]: Start difference. First operand 1278 states and 1898 transitions. cyclomatic complexity: 621 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:30,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:32:30,555 INFO L93 Difference]: Finished difference Result 1278 states and 1897 transitions. [2021-11-20 05:32:30,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:32:30,556 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1897 transitions. [2021-11-20 05:32:30,567 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-11-20 05:32:30,578 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1897 transitions. [2021-11-20 05:32:30,578 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2021-11-20 05:32:30,579 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2021-11-20 05:32:30,579 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1897 transitions. [2021-11-20 05:32:30,581 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:32:30,582 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1897 transitions. [2021-11-20 05:32:30,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1897 transitions. [2021-11-20 05:32:30,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2021-11-20 05:32:30,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4843505477308294) internal successors, (1897), 1277 states have internal predecessors, (1897), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:30,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1897 transitions. [2021-11-20 05:32:30,611 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1897 transitions. [2021-11-20 05:32:30,611 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1897 transitions. [2021-11-20 05:32:30,612 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-20 05:32:30,612 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1897 transitions. [2021-11-20 05:32:30,619 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-11-20 05:32:30,619 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:32:30,619 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:32:30,622 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:30,622 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:30,622 INFO L791 eck$LassoCheckResult]: Stem: 13812#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 13813#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 14087#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14075#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14076#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 14096#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14097#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13380#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13098#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13099#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14005#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14006#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13991#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13992#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14027#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13152#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13153#L1006 assume !(0 == ~M_E~0); 13001#L1006-2 assume !(0 == ~T1_E~0); 13002#L1011-1 assume !(0 == ~T2_E~0); 14049#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14064#L1021-1 assume !(0 == ~T4_E~0); 12883#L1026-1 assume !(0 == ~T5_E~0); 12884#L1031-1 assume !(0 == ~T6_E~0); 13757#L1036-1 assume !(0 == ~T7_E~0); 13753#L1041-1 assume !(0 == ~T8_E~0); 13754#L1046-1 assume !(0 == ~T9_E~0); 13183#L1051-1 assume !(0 == ~T10_E~0); 13184#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 13886#L1061-1 assume !(0 == ~E_2~0); 13102#L1066-1 assume !(0 == ~E_3~0); 13103#L1071-1 assume !(0 == ~E_4~0); 13865#L1076-1 assume !(0 == ~E_5~0); 13012#L1081-1 assume !(0 == ~E_6~0); 13013#L1086-1 assume !(0 == ~E_7~0); 13355#L1091-1 assume !(0 == ~E_8~0); 14042#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 14043#L1101-1 assume !(0 == ~E_10~0); 13417#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13418#L484 assume !(1 == ~m_pc~0); 13061#L484-2 is_master_triggered_~__retres1~0#1 := 0; 13060#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13676#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13960#L1245 assume !(0 != activate_threads_~tmp~1#1); 13961#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13745#L503 assume 1 == ~t1_pc~0; 13746#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13763#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13878#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13531#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 12911#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12912#L522 assume !(1 == ~t2_pc~0); 13712#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13115#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13116#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13586#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 14007#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14072#L541 assume 1 == ~t3_pc~0; 13661#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13477#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13292#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13293#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 13715#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13716#L560 assume !(1 == ~t4_pc~0); 12995#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12994#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13620#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12879#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 12880#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13166#L579 assume 1 == ~t5_pc~0; 12830#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12831#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12939#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13623#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 14063#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14084#L598 assume 1 == ~t6_pc~0; 13260#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13261#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13563#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13983#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 13794#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13736#L617 assume !(1 == ~t7_pc~0); 13233#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13232#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13518#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13519#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13454#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13455#L636 assume 1 == ~t8_pc~0; 13617#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13618#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13419#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13420#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 13572#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13573#L655 assume !(1 == ~t9_pc~0); 13600#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 13601#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13212#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13213#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 13814#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13815#L674 assume 1 == ~t10_pc~0; 12988#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12989#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14074#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14105#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 13560#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13561#L1119 assume !(1 == ~M_E~0); 13084#L1119-2 assume !(1 == ~T1_E~0); 13085#L1124-1 assume !(1 == ~T2_E~0); 12903#L1129-1 assume !(1 == ~T3_E~0); 12904#L1134-1 assume !(1 == ~T4_E~0); 13217#L1139-1 assume !(1 == ~T5_E~0); 13218#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13450#L1149-1 assume !(1 == ~T7_E~0); 13079#L1154-1 assume !(1 == ~T8_E~0); 13080#L1159-1 assume !(1 == ~T9_E~0); 13167#L1164-1 assume !(1 == ~T10_E~0); 13589#L1169-1 assume !(1 == ~E_1~0); 13487#L1174-1 assume !(1 == ~E_2~0); 13274#L1179-1 assume !(1 == ~E_3~0); 13156#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 13157#L1189-1 assume !(1 == ~E_5~0); 13210#L1194-1 assume !(1 == ~E_6~0); 13333#L1199-1 assume !(1 == ~E_7~0); 13284#L1204-1 assume !(1 == ~E_8~0); 13285#L1209-1 assume !(1 == ~E_9~0); 13808#L1214-1 assume !(1 == ~E_10~0); 13809#L1219-1 assume { :end_inline_reset_delta_events } true; 12867#L1520-2 [2021-11-20 05:32:30,623 INFO L793 eck$LassoCheckResult]: Loop: 12867#L1520-2 assume !false; 12868#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12971#L981 assume !false; 13163#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13835#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 12853#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13953#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14003#L836 assume !(0 != eval_~tmp~0#1); 13445#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13446#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13441#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13442#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13912#L1011-3 assume !(0 == ~T2_E~0); 13913#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13952#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13635#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13636#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13880#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13881#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13943#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13944#L1051-3 assume !(0 == ~T10_E~0); 13882#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13180#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13181#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13182#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14053#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12965#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12966#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13020#L1091-3 assume !(0 == ~E_8~0); 13021#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14028#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14029#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13655#L484-33 assume 1 == ~m_pc~0; 13656#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13575#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13576#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12873#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12874#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13345#L503-33 assume !(1 == ~t1_pc~0); 13346#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 13796#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13725#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13252#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13253#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13692#L522-33 assume 1 == ~t2_pc~0; 13693#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13008#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13009#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13802#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13710#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13711#L541-33 assume 1 == ~t3_pc~0; 13032#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12871#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12872#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13682#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13683#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13877#L560-33 assume 1 == ~t4_pc~0; 13582#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12943#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12944#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13200#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 13859#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12859#L579-33 assume 1 == ~t5_pc~0; 12860#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13108#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14068#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13737#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13738#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13762#L598-33 assume 1 == ~t6_pc~0; 14069#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13366#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13367#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13207#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13208#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14017#L617-33 assume 1 == ~t7_pc~0; 14023#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13000#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13951#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14058#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14054#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12931#L636-33 assume !(1 == ~t8_pc~0); 12932#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 13851#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13852#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14077#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13840#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13841#L655-33 assume 1 == ~t9_pc~0; 14101#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13307#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13308#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13666#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13930#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13486#L674-33 assume 1 == ~t10_pc~0; 13361#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13362#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13223#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13224#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13701#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14078#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14085#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14088#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14099#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13245#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13246#L1139-3 assume !(1 == ~T5_E~0); 13479#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13480#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13622#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13892#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13893#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14059#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13364#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13365#L1179-3 assume !(1 == ~E_3~0); 13984#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12991#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12992#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13305#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13306#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13609#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12885#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12886#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13799#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 12968#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13322#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 13323#L1539 assume !(0 == start_simulation_~tmp~3#1); 13415#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13591#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13398#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13530#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 13314#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13315#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13919#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 13416#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 12867#L1520-2 [2021-11-20 05:32:30,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:30,624 INFO L85 PathProgramCache]: Analyzing trace with hash 709992811, now seen corresponding path program 1 times [2021-11-20 05:32:30,624 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:30,624 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [687026548] [2021-11-20 05:32:30,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:30,625 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:30,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:30,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:30,661 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:30,661 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [687026548] [2021-11-20 05:32:30,662 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [687026548] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:30,662 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:30,662 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:30,662 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1613306341] [2021-11-20 05:32:30,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:30,664 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:32:30,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:30,667 INFO L85 PathProgramCache]: Analyzing trace with hash -2115858485, now seen corresponding path program 1 times [2021-11-20 05:32:30,667 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:30,671 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1844329943] [2021-11-20 05:32:30,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:30,672 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:30,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:30,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:30,720 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:30,720 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1844329943] [2021-11-20 05:32:30,727 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1844329943] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:30,727 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:30,727 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:30,727 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [599973343] [2021-11-20 05:32:30,728 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:30,728 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:32:30,728 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:32:30,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:32:30,729 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:32:30,730 INFO L87 Difference]: Start difference. First operand 1278 states and 1897 transitions. cyclomatic complexity: 620 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:30,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:32:30,758 INFO L93 Difference]: Finished difference Result 1278 states and 1896 transitions. [2021-11-20 05:32:30,758 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:32:30,759 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1896 transitions. [2021-11-20 05:32:30,770 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-11-20 05:32:30,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1896 transitions. [2021-11-20 05:32:30,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2021-11-20 05:32:30,804 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2021-11-20 05:32:30,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1896 transitions. [2021-11-20 05:32:30,807 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:32:30,807 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1896 transitions. [2021-11-20 05:32:30,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1896 transitions. [2021-11-20 05:32:30,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2021-11-20 05:32:30,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.483568075117371) internal successors, (1896), 1277 states have internal predecessors, (1896), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:30,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1896 transitions. [2021-11-20 05:32:30,840 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1896 transitions. [2021-11-20 05:32:30,840 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1896 transitions. [2021-11-20 05:32:30,840 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-20 05:32:30,841 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1896 transitions. [2021-11-20 05:32:30,849 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-11-20 05:32:30,849 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:32:30,849 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:32:30,852 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:30,852 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:30,852 INFO L791 eck$LassoCheckResult]: Stem: 16375#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 16376#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 16650#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16638#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16639#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 16659#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16660#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15943#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15663#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15664#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16568#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16569#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16554#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16555#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16590#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15715#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15716#L1006 assume !(0 == ~M_E~0); 15567#L1006-2 assume !(0 == ~T1_E~0); 15568#L1011-1 assume !(0 == ~T2_E~0); 16612#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16627#L1021-1 assume !(0 == ~T4_E~0); 15446#L1026-1 assume !(0 == ~T5_E~0); 15447#L1031-1 assume !(0 == ~T6_E~0); 16322#L1036-1 assume !(0 == ~T7_E~0); 16316#L1041-1 assume !(0 == ~T8_E~0); 16317#L1046-1 assume !(0 == ~T9_E~0); 15746#L1051-1 assume !(0 == ~T10_E~0); 15747#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 16449#L1061-1 assume !(0 == ~E_2~0); 15665#L1066-1 assume !(0 == ~E_3~0); 15666#L1071-1 assume !(0 == ~E_4~0); 16428#L1076-1 assume !(0 == ~E_5~0); 15575#L1081-1 assume !(0 == ~E_6~0); 15576#L1086-1 assume !(0 == ~E_7~0); 15919#L1091-1 assume !(0 == ~E_8~0); 16605#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 16606#L1101-1 assume !(0 == ~E_10~0); 15980#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15981#L484 assume !(1 == ~m_pc~0); 15624#L484-2 is_master_triggered_~__retres1~0#1 := 0; 15623#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16239#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16523#L1245 assume !(0 != activate_threads_~tmp~1#1); 16524#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16308#L503 assume 1 == ~t1_pc~0; 16309#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16327#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16441#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16094#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 15476#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15477#L522 assume !(1 == ~t2_pc~0); 16275#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15679#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15680#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16149#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 16570#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16635#L541 assume 1 == ~t3_pc~0; 16226#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16040#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15855#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15856#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 16282#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16283#L560 assume !(1 == ~t4_pc~0); 15558#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15557#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16183#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15442#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 15443#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15729#L579 assume 1 == ~t5_pc~0; 15393#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15394#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15502#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16186#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 16626#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16647#L598 assume 1 == ~t6_pc~0; 15825#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15826#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16128#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16546#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 16357#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16299#L617 assume !(1 == ~t7_pc~0); 15796#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15795#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16081#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16082#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16018#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16019#L636 assume 1 == ~t8_pc~0; 16180#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16181#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15982#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15983#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 16135#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16136#L655 assume !(1 == ~t9_pc~0); 16165#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 16166#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15775#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15776#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 16377#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16378#L674 assume 1 == ~t10_pc~0; 15551#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15552#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16637#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16668#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 16123#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16124#L1119 assume !(1 == ~M_E~0); 15647#L1119-2 assume !(1 == ~T1_E~0); 15648#L1124-1 assume !(1 == ~T2_E~0); 15466#L1129-1 assume !(1 == ~T3_E~0); 15467#L1134-1 assume !(1 == ~T4_E~0); 15780#L1139-1 assume !(1 == ~T5_E~0); 15781#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16013#L1149-1 assume !(1 == ~T7_E~0); 15642#L1154-1 assume !(1 == ~T8_E~0); 15643#L1159-1 assume !(1 == ~T9_E~0); 15730#L1164-1 assume !(1 == ~T10_E~0); 16152#L1169-1 assume !(1 == ~E_1~0); 16050#L1174-1 assume !(1 == ~E_2~0); 15839#L1179-1 assume !(1 == ~E_3~0); 15719#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15720#L1189-1 assume !(1 == ~E_5~0); 15774#L1194-1 assume !(1 == ~E_6~0); 15896#L1199-1 assume !(1 == ~E_7~0); 15847#L1204-1 assume !(1 == ~E_8~0); 15848#L1209-1 assume !(1 == ~E_9~0); 16371#L1214-1 assume !(1 == ~E_10~0); 16372#L1219-1 assume { :end_inline_reset_delta_events } true; 15430#L1520-2 [2021-11-20 05:32:30,853 INFO L793 eck$LassoCheckResult]: Loop: 15430#L1520-2 assume !false; 15431#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15531#L981 assume !false; 15726#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16398#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 15416#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16516#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16566#L836 assume !(0 != eval_~tmp~0#1); 16011#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16012#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16004#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16005#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16475#L1011-3 assume !(0 == ~T2_E~0); 16476#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16515#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16198#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16199#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16443#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16444#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16504#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16505#L1051-3 assume !(0 == ~T10_E~0); 16445#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15741#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15742#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15745#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16616#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15528#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15529#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15581#L1091-3 assume !(0 == ~E_8~0); 15582#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16591#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16592#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16218#L484-33 assume 1 == ~m_pc~0; 16219#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16138#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16139#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15436#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15437#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15905#L503-33 assume !(1 == ~t1_pc~0); 15906#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16359#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16285#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15813#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15814#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16255#L522-33 assume 1 == ~t2_pc~0; 16256#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15569#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15570#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16364#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16273#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16274#L541-33 assume 1 == ~t3_pc~0; 15595#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15434#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15435#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16245#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16246#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16440#L560-33 assume 1 == ~t4_pc~0; 16145#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15506#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15507#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15765#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 16422#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15425#L579-33 assume 1 == ~t5_pc~0; 15426#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15672#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16631#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16300#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16301#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16326#L598-33 assume !(1 == ~t6_pc~0); 16103#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 15929#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15930#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15770#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15771#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16580#L617-33 assume 1 == ~t7_pc~0; 16586#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15563#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16514#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16621#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16617#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15494#L636-33 assume !(1 == ~t8_pc~0); 15495#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 16414#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16415#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16640#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16405#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16406#L655-33 assume 1 == ~t9_pc~0; 16664#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15870#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15871#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16229#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16493#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16049#L674-33 assume 1 == ~t10_pc~0; 15924#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15925#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15786#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15787#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16264#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16641#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16648#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16652#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16662#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15811#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15812#L1139-3 assume !(1 == ~T5_E~0); 16042#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16043#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16185#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16455#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16456#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16623#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15927#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15928#L1179-3 assume !(1 == ~E_3~0); 16547#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15554#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15555#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15868#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15869#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16172#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15448#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15449#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16363#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 15534#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 15885#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 15886#L1539 assume !(0 == start_simulation_~tmp~3#1); 15978#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16154#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 15961#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16093#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 15877#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15878#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16482#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 15979#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 15430#L1520-2 [2021-11-20 05:32:30,854 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:30,854 INFO L85 PathProgramCache]: Analyzing trace with hash 1042635949, now seen corresponding path program 1 times [2021-11-20 05:32:30,854 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:30,854 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [903041625] [2021-11-20 05:32:30,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:30,855 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:30,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:30,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:30,887 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:30,888 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [903041625] [2021-11-20 05:32:30,888 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [903041625] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:30,888 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:30,888 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:30,888 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1426599958] [2021-11-20 05:32:30,889 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:30,889 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:32:30,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:30,890 INFO L85 PathProgramCache]: Analyzing trace with hash -1410939798, now seen corresponding path program 2 times [2021-11-20 05:32:30,890 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:30,890 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [736658977] [2021-11-20 05:32:30,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:30,891 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:30,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:30,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:30,939 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:30,939 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [736658977] [2021-11-20 05:32:30,939 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [736658977] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:30,939 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:30,940 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:30,940 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [157017311] [2021-11-20 05:32:30,940 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:30,940 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:32:30,941 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:32:30,941 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:32:30,941 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:32:30,941 INFO L87 Difference]: Start difference. First operand 1278 states and 1896 transitions. cyclomatic complexity: 619 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:30,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:32:30,971 INFO L93 Difference]: Finished difference Result 1278 states and 1895 transitions. [2021-11-20 05:32:30,972 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:32:30,974 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1895 transitions. [2021-11-20 05:32:30,986 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-11-20 05:32:30,998 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1895 transitions. [2021-11-20 05:32:30,998 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2021-11-20 05:32:30,999 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2021-11-20 05:32:31,000 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1895 transitions. [2021-11-20 05:32:31,002 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:32:31,002 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1895 transitions. [2021-11-20 05:32:31,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1895 transitions. [2021-11-20 05:32:31,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2021-11-20 05:32:31,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4827856025039123) internal successors, (1895), 1277 states have internal predecessors, (1895), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:31,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1895 transitions. [2021-11-20 05:32:31,036 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1895 transitions. [2021-11-20 05:32:31,036 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1895 transitions. [2021-11-20 05:32:31,036 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-20 05:32:31,036 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1895 transitions. [2021-11-20 05:32:31,042 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-11-20 05:32:31,042 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:32:31,042 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:32:31,045 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:31,045 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:31,046 INFO L791 eck$LassoCheckResult]: Stem: 18937#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 18938#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 19213#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19201#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19202#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 19222#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19223#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18506#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18224#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18225#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19131#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19132#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19117#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19118#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19153#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18276#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18277#L1006 assume !(0 == ~M_E~0); 18127#L1006-2 assume !(0 == ~T1_E~0); 18128#L1011-1 assume !(0 == ~T2_E~0); 19175#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19190#L1021-1 assume !(0 == ~T4_E~0); 18007#L1026-1 assume !(0 == ~T5_E~0); 18008#L1031-1 assume !(0 == ~T6_E~0); 18883#L1036-1 assume !(0 == ~T7_E~0); 18879#L1041-1 assume !(0 == ~T8_E~0); 18880#L1046-1 assume !(0 == ~T9_E~0); 18309#L1051-1 assume !(0 == ~T10_E~0); 18310#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 19012#L1061-1 assume !(0 == ~E_2~0); 18228#L1066-1 assume !(0 == ~E_3~0); 18229#L1071-1 assume !(0 == ~E_4~0); 18991#L1076-1 assume !(0 == ~E_5~0); 18138#L1081-1 assume !(0 == ~E_6~0); 18139#L1086-1 assume !(0 == ~E_7~0); 18481#L1091-1 assume !(0 == ~E_8~0); 19167#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 19168#L1101-1 assume !(0 == ~E_10~0); 18543#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18544#L484 assume !(1 == ~m_pc~0); 18187#L484-2 is_master_triggered_~__retres1~0#1 := 0; 18186#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18802#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19086#L1245 assume !(0 != activate_threads_~tmp~1#1); 19087#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18871#L503 assume 1 == ~t1_pc~0; 18872#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18888#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19004#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18654#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 18037#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18038#L522 assume !(1 == ~t2_pc~0); 18838#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18241#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18242#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18712#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 19133#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19198#L541 assume 1 == ~t3_pc~0; 18787#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18603#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18418#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18419#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 18841#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18842#L560 assume !(1 == ~t4_pc~0); 18119#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18118#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18746#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18005#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 18006#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18290#L579 assume 1 == ~t5_pc~0; 17956#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17957#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18065#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18749#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 19188#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19210#L598 assume 1 == ~t6_pc~0; 18386#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18387#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18688#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19109#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 18920#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18862#L617 assume !(1 == ~t7_pc~0); 18359#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18358#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18644#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18645#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18580#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18581#L636 assume 1 == ~t8_pc~0; 18743#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18744#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18545#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18546#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 18696#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18697#L655 assume !(1 == ~t9_pc~0); 18724#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 18725#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18338#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18339#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 18939#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18940#L674 assume 1 == ~t10_pc~0; 18114#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18115#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19200#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19231#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 18686#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18687#L1119 assume !(1 == ~M_E~0); 18210#L1119-2 assume !(1 == ~T1_E~0); 18211#L1124-1 assume !(1 == ~T2_E~0); 18029#L1129-1 assume !(1 == ~T3_E~0); 18030#L1134-1 assume !(1 == ~T4_E~0); 18340#L1139-1 assume !(1 == ~T5_E~0); 18341#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18576#L1149-1 assume !(1 == ~T7_E~0); 18205#L1154-1 assume !(1 == ~T8_E~0); 18206#L1159-1 assume !(1 == ~T9_E~0); 18293#L1164-1 assume !(1 == ~T10_E~0); 18715#L1169-1 assume !(1 == ~E_1~0); 18613#L1174-1 assume !(1 == ~E_2~0); 18400#L1179-1 assume !(1 == ~E_3~0); 18282#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18283#L1189-1 assume !(1 == ~E_5~0); 18335#L1194-1 assume !(1 == ~E_6~0); 18459#L1199-1 assume !(1 == ~E_7~0); 18410#L1204-1 assume !(1 == ~E_8~0); 18411#L1209-1 assume !(1 == ~E_9~0); 18934#L1214-1 assume !(1 == ~E_10~0); 18935#L1219-1 assume { :end_inline_reset_delta_events } true; 17993#L1520-2 [2021-11-20 05:32:31,046 INFO L793 eck$LassoCheckResult]: Loop: 17993#L1520-2 assume !false; 17994#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18094#L981 assume !false; 18286#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 18961#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 17979#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19079#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19129#L836 assume !(0 != eval_~tmp~0#1); 18571#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18572#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18567#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18568#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19038#L1011-3 assume !(0 == ~T2_E~0); 19039#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19078#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18759#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18760#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19006#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19007#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19067#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19068#L1051-3 assume !(0 == ~T10_E~0); 19008#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18304#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18305#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18308#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19179#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18091#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18092#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18144#L1091-3 assume !(0 == ~E_8~0); 18145#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19154#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19155#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18781#L484-33 assume 1 == ~m_pc~0; 18782#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 18701#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18702#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17999#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18000#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18468#L503-33 assume !(1 == ~t1_pc~0); 18469#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 18922#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18849#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18378#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18379#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18818#L522-33 assume 1 == ~t2_pc~0; 18819#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18132#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18133#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18927#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18836#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18837#L541-33 assume 1 == ~t3_pc~0; 18158#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17997#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17998#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18808#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18809#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19003#L560-33 assume 1 == ~t4_pc~0; 18708#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18069#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18070#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18328#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 18985#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17988#L579-33 assume 1 == ~t5_pc~0; 17989#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18235#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19194#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18863#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18864#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18892#L598-33 assume !(1 == ~t6_pc~0); 18666#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 18492#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18493#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18333#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18334#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19143#L617-33 assume 1 == ~t7_pc~0; 19149#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18126#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19077#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19184#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19180#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18057#L636-33 assume !(1 == ~t8_pc~0); 18058#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 18977#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18978#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19203#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18968#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18969#L655-33 assume 1 == ~t9_pc~0; 19227#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18435#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18436#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18792#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19056#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18612#L674-33 assume 1 == ~t10_pc~0; 18487#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18488#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18349#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18350#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 18827#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19204#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19211#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19215#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19225#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18374#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18375#L1139-3 assume !(1 == ~T5_E~0); 18605#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18606#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18748#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19018#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19019#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19186#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18490#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18491#L1179-3 assume !(1 == ~E_3~0); 19110#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18120#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18121#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18431#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18432#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18735#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18011#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18012#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 18926#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18097#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 18448#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 18449#L1539 assume !(0 == start_simulation_~tmp~3#1); 18541#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 18717#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18524#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 18657#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 18440#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18441#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19045#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 18542#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 17993#L1520-2 [2021-11-20 05:32:31,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:31,047 INFO L85 PathProgramCache]: Analyzing trace with hash -886296277, now seen corresponding path program 1 times [2021-11-20 05:32:31,047 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:31,047 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1299379070] [2021-11-20 05:32:31,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:31,048 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:31,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:31,078 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:31,078 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:31,079 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1299379070] [2021-11-20 05:32:31,079 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1299379070] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:31,080 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:31,080 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:31,081 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [688832927] [2021-11-20 05:32:31,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:31,081 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:32:31,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:31,082 INFO L85 PathProgramCache]: Analyzing trace with hash -1410939798, now seen corresponding path program 3 times [2021-11-20 05:32:31,085 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:31,090 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1433299018] [2021-11-20 05:32:31,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:31,092 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:31,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:31,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:31,142 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:31,144 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1433299018] [2021-11-20 05:32:31,146 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1433299018] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:31,146 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:31,147 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:31,148 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2067203735] [2021-11-20 05:32:31,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:31,149 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:32:31,149 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:32:31,149 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:32:31,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:32:31,149 INFO L87 Difference]: Start difference. First operand 1278 states and 1895 transitions. cyclomatic complexity: 618 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:31,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:32:31,186 INFO L93 Difference]: Finished difference Result 1278 states and 1894 transitions. [2021-11-20 05:32:31,187 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:32:31,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1894 transitions. [2021-11-20 05:32:31,201 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-11-20 05:32:31,211 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1894 transitions. [2021-11-20 05:32:31,211 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2021-11-20 05:32:31,212 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2021-11-20 05:32:31,213 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1894 transitions. [2021-11-20 05:32:31,215 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:32:31,215 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1894 transitions. [2021-11-20 05:32:31,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1894 transitions. [2021-11-20 05:32:31,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2021-11-20 05:32:31,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.482003129890454) internal successors, (1894), 1277 states have internal predecessors, (1894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:31,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1894 transitions. [2021-11-20 05:32:31,279 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1894 transitions. [2021-11-20 05:32:31,279 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1894 transitions. [2021-11-20 05:32:31,279 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-20 05:32:31,279 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1894 transitions. [2021-11-20 05:32:31,284 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-11-20 05:32:31,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:32:31,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:32:31,287 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:31,287 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:31,288 INFO L791 eck$LassoCheckResult]: Stem: 21500#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 21501#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 21776#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21764#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21765#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 21785#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21786#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21069#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20787#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20788#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21694#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21695#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21680#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 21681#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21716#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20839#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20840#L1006 assume !(0 == ~M_E~0); 20690#L1006-2 assume !(0 == ~T1_E~0); 20691#L1011-1 assume !(0 == ~T2_E~0); 21738#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21753#L1021-1 assume !(0 == ~T4_E~0); 20570#L1026-1 assume !(0 == ~T5_E~0); 20571#L1031-1 assume !(0 == ~T6_E~0); 21446#L1036-1 assume !(0 == ~T7_E~0); 21442#L1041-1 assume !(0 == ~T8_E~0); 21443#L1046-1 assume !(0 == ~T9_E~0); 20872#L1051-1 assume !(0 == ~T10_E~0); 20873#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 21575#L1061-1 assume !(0 == ~E_2~0); 20791#L1066-1 assume !(0 == ~E_3~0); 20792#L1071-1 assume !(0 == ~E_4~0); 21554#L1076-1 assume !(0 == ~E_5~0); 20701#L1081-1 assume !(0 == ~E_6~0); 20702#L1086-1 assume !(0 == ~E_7~0); 21044#L1091-1 assume !(0 == ~E_8~0); 21730#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 21731#L1101-1 assume !(0 == ~E_10~0); 21106#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21107#L484 assume !(1 == ~m_pc~0); 20750#L484-2 is_master_triggered_~__retres1~0#1 := 0; 20749#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21365#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21649#L1245 assume !(0 != activate_threads_~tmp~1#1); 21650#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21434#L503 assume 1 == ~t1_pc~0; 21435#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21451#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21567#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21217#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 20600#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20601#L522 assume !(1 == ~t2_pc~0); 21401#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20804#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20805#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21275#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 21696#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21761#L541 assume 1 == ~t3_pc~0; 21350#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21166#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20981#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20982#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 21404#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21405#L560 assume !(1 == ~t4_pc~0); 20682#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20681#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21309#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20568#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 20569#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20855#L579 assume 1 == ~t5_pc~0; 20519#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20520#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20628#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21312#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 21751#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21773#L598 assume 1 == ~t6_pc~0; 20949#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20950#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21251#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21672#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 21483#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21425#L617 assume !(1 == ~t7_pc~0); 20922#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20921#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21207#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21208#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21143#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21144#L636 assume 1 == ~t8_pc~0; 21306#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21307#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21108#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21109#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 21259#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21260#L655 assume !(1 == ~t9_pc~0); 21287#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21288#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20901#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20902#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 21502#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21503#L674 assume 1 == ~t10_pc~0; 20677#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20678#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21763#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21794#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 21249#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21250#L1119 assume !(1 == ~M_E~0); 20773#L1119-2 assume !(1 == ~T1_E~0); 20774#L1124-1 assume !(1 == ~T2_E~0); 20592#L1129-1 assume !(1 == ~T3_E~0); 20593#L1134-1 assume !(1 == ~T4_E~0); 20904#L1139-1 assume !(1 == ~T5_E~0); 20905#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21139#L1149-1 assume !(1 == ~T7_E~0); 20768#L1154-1 assume !(1 == ~T8_E~0); 20769#L1159-1 assume !(1 == ~T9_E~0); 20856#L1164-1 assume !(1 == ~T10_E~0); 21278#L1169-1 assume !(1 == ~E_1~0); 21176#L1174-1 assume !(1 == ~E_2~0); 20963#L1179-1 assume !(1 == ~E_3~0); 20845#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 20846#L1189-1 assume !(1 == ~E_5~0); 20898#L1194-1 assume !(1 == ~E_6~0); 21022#L1199-1 assume !(1 == ~E_7~0); 20973#L1204-1 assume !(1 == ~E_8~0); 20974#L1209-1 assume !(1 == ~E_9~0); 21497#L1214-1 assume !(1 == ~E_10~0); 21498#L1219-1 assume { :end_inline_reset_delta_events } true; 20556#L1520-2 [2021-11-20 05:32:31,288 INFO L793 eck$LassoCheckResult]: Loop: 20556#L1520-2 assume !false; 20557#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20657#L981 assume !false; 20849#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21524#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 20542#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21642#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21692#L836 assume !(0 != eval_~tmp~0#1); 21134#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21135#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21130#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21131#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21601#L1011-3 assume !(0 == ~T2_E~0); 21602#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21641#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21322#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21323#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21569#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21570#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21630#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21631#L1051-3 assume !(0 == ~T10_E~0); 21571#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20867#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20868#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20871#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21742#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20654#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20655#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20707#L1091-3 assume !(0 == ~E_8~0); 20708#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21717#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21718#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21344#L484-33 assume 1 == ~m_pc~0; 21345#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21264#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21265#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20562#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20563#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21031#L503-33 assume !(1 == ~t1_pc~0); 21032#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 21485#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21412#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20941#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20942#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21381#L522-33 assume 1 == ~t2_pc~0; 21382#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20695#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20696#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21490#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21399#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21400#L541-33 assume 1 == ~t3_pc~0; 20721#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20560#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20561#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21371#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21372#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21566#L560-33 assume 1 == ~t4_pc~0; 21271#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20632#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20633#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20891#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 21548#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20551#L579-33 assume 1 == ~t5_pc~0; 20552#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20798#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21757#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21426#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21427#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21455#L598-33 assume !(1 == ~t6_pc~0); 21229#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 21055#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21056#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20896#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20897#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21706#L617-33 assume 1 == ~t7_pc~0; 21712#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20689#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21640#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21747#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21743#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20620#L636-33 assume !(1 == ~t8_pc~0); 20621#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 21540#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21541#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21766#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21531#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21532#L655-33 assume 1 == ~t9_pc~0; 21790#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20998#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20999#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21355#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21619#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21175#L674-33 assume 1 == ~t10_pc~0; 21050#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21051#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20912#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20913#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21390#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21767#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21774#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21778#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21788#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20937#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20938#L1139-3 assume !(1 == ~T5_E~0); 21168#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21169#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21311#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21581#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21582#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21749#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21053#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21054#L1179-3 assume !(1 == ~E_3~0); 21673#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20683#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20684#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20994#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20995#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21298#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20574#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20575#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21489#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 20660#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21011#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 21012#L1539 assume !(0 == start_simulation_~tmp~3#1); 21104#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21280#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 21087#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21220#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 21003#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21004#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21608#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 21105#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 20556#L1520-2 [2021-11-20 05:32:31,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:31,289 INFO L85 PathProgramCache]: Analyzing trace with hash 1406784749, now seen corresponding path program 1 times [2021-11-20 05:32:31,289 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:31,289 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1244522594] [2021-11-20 05:32:31,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:31,290 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:31,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:31,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:31,318 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:31,318 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1244522594] [2021-11-20 05:32:31,318 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1244522594] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:31,318 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:31,318 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:31,319 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1790355062] [2021-11-20 05:32:31,319 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:31,319 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:32:31,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:31,320 INFO L85 PathProgramCache]: Analyzing trace with hash -1410939798, now seen corresponding path program 4 times [2021-11-20 05:32:31,320 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:31,320 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899075326] [2021-11-20 05:32:31,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:31,321 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:31,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:31,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:31,370 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:31,370 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [899075326] [2021-11-20 05:32:31,370 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [899075326] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:31,371 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:31,371 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:31,372 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [438756079] [2021-11-20 05:32:31,372 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:31,372 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:32:31,372 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:32:31,373 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:32:31,373 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:32:31,373 INFO L87 Difference]: Start difference. First operand 1278 states and 1894 transitions. cyclomatic complexity: 617 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:31,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:32:31,402 INFO L93 Difference]: Finished difference Result 1278 states and 1893 transitions. [2021-11-20 05:32:31,403 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:32:31,403 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1893 transitions. [2021-11-20 05:32:31,412 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-11-20 05:32:31,422 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1893 transitions. [2021-11-20 05:32:31,423 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2021-11-20 05:32:31,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2021-11-20 05:32:31,426 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1893 transitions. [2021-11-20 05:32:31,428 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:32:31,429 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1893 transitions. [2021-11-20 05:32:31,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1893 transitions. [2021-11-20 05:32:31,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2021-11-20 05:32:31,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4812206572769953) internal successors, (1893), 1277 states have internal predecessors, (1893), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:31,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1893 transitions. [2021-11-20 05:32:31,458 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1893 transitions. [2021-11-20 05:32:31,458 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1893 transitions. [2021-11-20 05:32:31,458 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-20 05:32:31,458 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1893 transitions. [2021-11-20 05:32:31,464 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-11-20 05:32:31,464 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:32:31,464 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:32:31,466 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:31,466 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:31,467 INFO L791 eck$LassoCheckResult]: Stem: 24064#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 24065#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 24339#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24327#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24328#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 24348#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24349#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23632#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23350#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23351#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24257#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24258#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24243#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24244#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24279#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 23404#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23405#L1006 assume !(0 == ~M_E~0); 23253#L1006-2 assume !(0 == ~T1_E~0); 23254#L1011-1 assume !(0 == ~T2_E~0); 24301#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24316#L1021-1 assume !(0 == ~T4_E~0); 23135#L1026-1 assume !(0 == ~T5_E~0); 23136#L1031-1 assume !(0 == ~T6_E~0); 24009#L1036-1 assume !(0 == ~T7_E~0); 24005#L1041-1 assume !(0 == ~T8_E~0); 24006#L1046-1 assume !(0 == ~T9_E~0); 23435#L1051-1 assume !(0 == ~T10_E~0); 23436#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 24138#L1061-1 assume !(0 == ~E_2~0); 23354#L1066-1 assume !(0 == ~E_3~0); 23355#L1071-1 assume !(0 == ~E_4~0); 24117#L1076-1 assume !(0 == ~E_5~0); 23264#L1081-1 assume !(0 == ~E_6~0); 23265#L1086-1 assume !(0 == ~E_7~0); 23608#L1091-1 assume !(0 == ~E_8~0); 24294#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 24295#L1101-1 assume !(0 == ~E_10~0); 23669#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23670#L484 assume !(1 == ~m_pc~0); 23313#L484-2 is_master_triggered_~__retres1~0#1 := 0; 23312#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23928#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24212#L1245 assume !(0 != activate_threads_~tmp~1#1); 24213#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23997#L503 assume 1 == ~t1_pc~0; 23998#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24015#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24130#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23783#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 23163#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23164#L522 assume !(1 == ~t2_pc~0); 23964#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23367#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23368#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23838#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 24259#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24324#L541 assume 1 == ~t3_pc~0; 23913#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23729#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23544#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23545#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 23967#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23968#L560 assume !(1 == ~t4_pc~0); 23247#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 23246#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23872#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23131#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 23132#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23418#L579 assume 1 == ~t5_pc~0; 23082#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23083#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23191#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23875#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 24315#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24336#L598 assume 1 == ~t6_pc~0; 23512#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23513#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23815#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24235#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 24046#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23988#L617 assume !(1 == ~t7_pc~0); 23485#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 23484#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23770#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23771#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 23706#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23707#L636 assume 1 == ~t8_pc~0; 23869#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23870#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23671#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23672#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 23824#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23825#L655 assume !(1 == ~t9_pc~0); 23852#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 23853#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23464#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23465#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 24066#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24067#L674 assume 1 == ~t10_pc~0; 23240#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23241#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24326#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24357#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 23812#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23813#L1119 assume !(1 == ~M_E~0); 23336#L1119-2 assume !(1 == ~T1_E~0); 23337#L1124-1 assume !(1 == ~T2_E~0); 23155#L1129-1 assume !(1 == ~T3_E~0); 23156#L1134-1 assume !(1 == ~T4_E~0); 23469#L1139-1 assume !(1 == ~T5_E~0); 23470#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23702#L1149-1 assume !(1 == ~T7_E~0); 23331#L1154-1 assume !(1 == ~T8_E~0); 23332#L1159-1 assume !(1 == ~T9_E~0); 23419#L1164-1 assume !(1 == ~T10_E~0); 23841#L1169-1 assume !(1 == ~E_1~0); 23739#L1174-1 assume !(1 == ~E_2~0); 23526#L1179-1 assume !(1 == ~E_3~0); 23408#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 23409#L1189-1 assume !(1 == ~E_5~0); 23462#L1194-1 assume !(1 == ~E_6~0); 23585#L1199-1 assume !(1 == ~E_7~0); 23536#L1204-1 assume !(1 == ~E_8~0); 23537#L1209-1 assume !(1 == ~E_9~0); 24060#L1214-1 assume !(1 == ~E_10~0); 24061#L1219-1 assume { :end_inline_reset_delta_events } true; 23119#L1520-2 [2021-11-20 05:32:31,467 INFO L793 eck$LassoCheckResult]: Loop: 23119#L1520-2 assume !false; 23120#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23223#L981 assume !false; 23415#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24087#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23105#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24205#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24255#L836 assume !(0 != eval_~tmp~0#1); 23697#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23698#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23693#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23694#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24164#L1011-3 assume !(0 == ~T2_E~0); 24165#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24204#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23887#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23888#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24132#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24133#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24195#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 24196#L1051-3 assume !(0 == ~T10_E~0); 24134#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23432#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23433#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23434#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24305#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23217#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23218#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23272#L1091-3 assume !(0 == ~E_8~0); 23273#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 24280#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24281#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23907#L484-33 assume 1 == ~m_pc~0; 23908#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23827#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23828#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23125#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23126#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23597#L503-33 assume !(1 == ~t1_pc~0); 23598#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 24048#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23977#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23504#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23505#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23944#L522-33 assume 1 == ~t2_pc~0; 23945#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23260#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23261#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24054#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23962#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23963#L541-33 assume 1 == ~t3_pc~0; 23284#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23123#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23124#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23934#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23935#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24129#L560-33 assume 1 == ~t4_pc~0; 23834#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23195#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23196#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23452#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 24111#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23111#L579-33 assume 1 == ~t5_pc~0; 23112#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23360#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24320#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23989#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23990#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24014#L598-33 assume 1 == ~t6_pc~0; 24321#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23618#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23619#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23459#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23460#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24269#L617-33 assume 1 == ~t7_pc~0; 24275#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23252#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24203#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24310#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24306#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23183#L636-33 assume !(1 == ~t8_pc~0); 23184#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 24103#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24104#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24329#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24092#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24093#L655-33 assume 1 == ~t9_pc~0; 24353#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23559#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23560#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23918#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24182#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23738#L674-33 assume 1 == ~t10_pc~0; 23613#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23614#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23475#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23476#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23953#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24330#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24337#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24340#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24351#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23497#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23498#L1139-3 assume !(1 == ~T5_E~0); 23731#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23732#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23874#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24144#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24145#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24311#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23616#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23617#L1179-3 assume !(1 == ~E_3~0); 24236#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23243#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23244#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23557#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23558#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23861#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23137#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23138#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24051#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23220#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23574#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 23575#L1539 assume !(0 == start_simulation_~tmp~3#1); 23667#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 23843#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23650#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23782#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 23566#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23567#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24171#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 23668#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 23119#L1520-2 [2021-11-20 05:32:31,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:31,468 INFO L85 PathProgramCache]: Analyzing trace with hash 935428399, now seen corresponding path program 1 times [2021-11-20 05:32:31,469 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:31,469 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1853744834] [2021-11-20 05:32:31,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:31,469 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:31,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:31,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:31,522 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:31,522 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1853744834] [2021-11-20 05:32:31,522 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1853744834] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:31,522 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:31,523 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:31,523 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [610288126] [2021-11-20 05:32:31,523 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:31,524 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:32:31,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:31,525 INFO L85 PathProgramCache]: Analyzing trace with hash -2115858485, now seen corresponding path program 2 times [2021-11-20 05:32:31,525 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:31,525 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854555227] [2021-11-20 05:32:31,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:31,526 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:31,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:31,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:31,578 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:31,578 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [854555227] [2021-11-20 05:32:31,578 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [854555227] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:31,578 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:31,578 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:31,579 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [416452685] [2021-11-20 05:32:31,579 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:31,579 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:32:31,579 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:32:31,580 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 05:32:31,580 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 05:32:31,580 INFO L87 Difference]: Start difference. First operand 1278 states and 1893 transitions. cyclomatic complexity: 616 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:31,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:32:31,706 INFO L93 Difference]: Finished difference Result 2439 states and 3606 transitions. [2021-11-20 05:32:31,706 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 05:32:31,707 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2439 states and 3606 transitions. [2021-11-20 05:32:31,723 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2282 [2021-11-20 05:32:31,742 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2439 states to 2439 states and 3606 transitions. [2021-11-20 05:32:31,743 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2439 [2021-11-20 05:32:31,745 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2439 [2021-11-20 05:32:31,745 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2439 states and 3606 transitions. [2021-11-20 05:32:31,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:32:31,749 INFO L681 BuchiCegarLoop]: Abstraction has 2439 states and 3606 transitions. [2021-11-20 05:32:31,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2439 states and 3606 transitions. [2021-11-20 05:32:31,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2439 to 2439. [2021-11-20 05:32:31,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2439 states, 2439 states have (on average 1.4784747847478474) internal successors, (3606), 2438 states have internal predecessors, (3606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:31,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2439 states to 2439 states and 3606 transitions. [2021-11-20 05:32:31,850 INFO L704 BuchiCegarLoop]: Abstraction has 2439 states and 3606 transitions. [2021-11-20 05:32:31,850 INFO L587 BuchiCegarLoop]: Abstraction has 2439 states and 3606 transitions. [2021-11-20 05:32:31,851 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-20 05:32:31,851 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2439 states and 3606 transitions. [2021-11-20 05:32:31,861 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2282 [2021-11-20 05:32:31,861 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:32:31,862 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:32:31,864 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:31,864 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:31,864 INFO L791 eck$LassoCheckResult]: Stem: 27804#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 27805#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 28126#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28106#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28107#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 28142#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28143#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27363#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27081#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27082#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28015#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 28016#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 27998#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27999#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28043#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 27133#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27134#L1006 assume !(0 == ~M_E~0); 26984#L1006-2 assume !(0 == ~T1_E~0); 26985#L1011-1 assume !(0 == ~T2_E~0); 28071#L1016-1 assume !(0 == ~T3_E~0); 28093#L1021-1 assume !(0 == ~T4_E~0); 26862#L1026-1 assume !(0 == ~T5_E~0); 26863#L1031-1 assume !(0 == ~T6_E~0); 27751#L1036-1 assume !(0 == ~T7_E~0); 27745#L1041-1 assume !(0 == ~T8_E~0); 27746#L1046-1 assume !(0 == ~T9_E~0); 27164#L1051-1 assume !(0 == ~T10_E~0); 27165#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 27882#L1061-1 assume !(0 == ~E_2~0); 27083#L1066-1 assume !(0 == ~E_3~0); 27084#L1071-1 assume !(0 == ~E_4~0); 27858#L1076-1 assume !(0 == ~E_5~0); 26992#L1081-1 assume !(0 == ~E_6~0); 26993#L1086-1 assume !(0 == ~E_7~0); 27339#L1091-1 assume !(0 == ~E_8~0); 28061#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 28062#L1101-1 assume !(0 == ~E_10~0); 27403#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27404#L484 assume !(1 == ~m_pc~0); 27041#L484-2 is_master_triggered_~__retres1~0#1 := 0; 27040#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27667#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27962#L1245 assume !(0 != activate_threads_~tmp~1#1); 27963#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27737#L503 assume 1 == ~t1_pc~0; 27738#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27758#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27873#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27518#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 26893#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26894#L522 assume !(1 == ~t2_pc~0); 27703#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27097#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27098#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27573#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 28017#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28102#L541 assume 1 == ~t3_pc~0; 27654#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27463#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27274#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27275#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 27710#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27711#L560 assume !(1 == ~t4_pc~0); 26975#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26974#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27608#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26858#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 26859#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27147#L579 assume 1 == ~t5_pc~0; 26809#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26810#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26919#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27611#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 28092#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28123#L598 assume 1 == ~t6_pc~0; 27244#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27245#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27552#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27989#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 27786#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27728#L617 assume !(1 == ~t7_pc~0); 27215#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 27214#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27505#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27506#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27441#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27442#L636 assume 1 == ~t8_pc~0; 27605#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27606#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27405#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27406#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 27559#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27560#L655 assume !(1 == ~t9_pc~0); 27590#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27591#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27194#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27195#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 27806#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27807#L674 assume 1 == ~t10_pc~0; 26968#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26969#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28105#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28153#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 27547#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27548#L1119 assume !(1 == ~M_E~0); 27064#L1119-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27065#L1124-1 assume !(1 == ~T2_E~0); 28287#L1129-1 assume !(1 == ~T3_E~0); 26883#L1134-1 assume !(1 == ~T4_E~0); 28285#L1139-1 assume !(1 == ~T5_E~0); 28284#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28282#L1149-1 assume !(1 == ~T7_E~0); 28280#L1154-1 assume !(1 == ~T8_E~0); 28278#L1159-1 assume !(1 == ~T9_E~0); 28276#L1164-1 assume !(1 == ~T10_E~0); 28274#L1169-1 assume !(1 == ~E_1~0); 28271#L1174-1 assume !(1 == ~E_2~0); 28269#L1179-1 assume !(1 == ~E_3~0); 28267#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 28265#L1189-1 assume !(1 == ~E_5~0); 28201#L1194-1 assume !(1 == ~E_6~0); 28198#L1199-1 assume !(1 == ~E_7~0); 28196#L1204-1 assume !(1 == ~E_8~0); 28195#L1209-1 assume !(1 == ~E_9~0); 28194#L1214-1 assume !(1 == ~E_10~0); 28188#L1219-1 assume { :end_inline_reset_delta_events } true; 28182#L1520-2 [2021-11-20 05:32:31,865 INFO L793 eck$LassoCheckResult]: Loop: 28182#L1520-2 assume !false; 28178#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28177#L981 assume !false; 28176#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28167#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 27954#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 27955#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28066#L836 assume !(0 != eval_~tmp~0#1); 27434#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27435#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27427#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27428#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28160#L1011-3 assume !(0 == ~T2_E~0); 28522#L1016-3 assume !(0 == ~T3_E~0); 28521#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28520#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28519#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28518#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28517#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28516#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28515#L1051-3 assume !(0 == ~T10_E~0); 28514#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28513#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28512#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28511#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28510#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28509#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28508#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28507#L1091-3 assume !(0 == ~E_8~0); 28506#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28505#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28504#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28503#L484-33 assume 1 == ~m_pc~0; 28501#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 28500#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28499#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28498#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28497#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28496#L503-33 assume !(1 == ~t1_pc~0); 28494#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 28493#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28492#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28491#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28490#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28489#L522-33 assume 1 == ~t2_pc~0; 28487#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28486#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28485#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28484#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28483#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28482#L541-33 assume !(1 == ~t3_pc~0); 28480#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 28479#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28478#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28477#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28476#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28475#L560-33 assume 1 == ~t4_pc~0; 28473#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28472#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28471#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28470#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 28469#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28468#L579-33 assume 1 == ~t5_pc~0; 28466#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28465#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28464#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28463#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28462#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28461#L598-33 assume !(1 == ~t6_pc~0); 28459#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 28458#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28457#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28456#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 28455#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28454#L617-33 assume 1 == ~t7_pc~0; 28452#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28451#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28450#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28449#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28079#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26911#L636-33 assume !(1 == ~t8_pc~0); 26912#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 28443#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28442#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28441#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28439#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28437#L655-33 assume 1 == ~t9_pc~0; 28149#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27291#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27292#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27657#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28414#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28412#L674-33 assume !(1 == ~t10_pc~0); 28409#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 28407#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28405#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28403#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28401#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28399#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28397#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28129#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28394#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28146#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28391#L1139-3 assume !(1 == ~T5_E~0); 28389#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28387#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28385#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28384#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28383#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28381#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28379#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28377#L1179-3 assume !(1 == ~E_3~0); 28375#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28373#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28371#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28369#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28368#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28367#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28366#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28365#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28354#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28352#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28349#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 28347#L1539 assume !(0 == start_simulation_~tmp~3#1); 28345#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28218#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28212#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28211#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 28207#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27916#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27917#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 28189#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 28182#L1520-2 [2021-11-20 05:32:31,866 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:31,866 INFO L85 PathProgramCache]: Analyzing trace with hash -1629133905, now seen corresponding path program 1 times [2021-11-20 05:32:31,866 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:31,866 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1965056342] [2021-11-20 05:32:31,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:31,867 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:31,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:31,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:31,905 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:31,905 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1965056342] [2021-11-20 05:32:31,905 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1965056342] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:31,905 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:31,905 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:31,906 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2065514198] [2021-11-20 05:32:31,906 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:31,906 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:32:31,906 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:31,907 INFO L85 PathProgramCache]: Analyzing trace with hash 17017706, now seen corresponding path program 1 times [2021-11-20 05:32:31,907 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:31,907 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [309374710] [2021-11-20 05:32:31,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:31,907 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:31,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:31,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:31,955 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:31,956 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [309374710] [2021-11-20 05:32:31,956 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [309374710] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:31,956 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:31,956 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:31,956 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1096291680] [2021-11-20 05:32:31,956 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:31,957 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:32:31,957 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:32:31,958 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 05:32:31,958 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 05:32:31,958 INFO L87 Difference]: Start difference. First operand 2439 states and 3606 transitions. cyclomatic complexity: 1169 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:32,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:32:32,144 INFO L93 Difference]: Finished difference Result 4593 states and 6787 transitions. [2021-11-20 05:32:32,145 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 05:32:32,145 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4593 states and 6787 transitions. [2021-11-20 05:32:32,172 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4404 [2021-11-20 05:32:32,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4593 states to 4593 states and 6787 transitions. [2021-11-20 05:32:32,213 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4593 [2021-11-20 05:32:32,218 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4593 [2021-11-20 05:32:32,218 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4593 states and 6787 transitions. [2021-11-20 05:32:32,225 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:32:32,225 INFO L681 BuchiCegarLoop]: Abstraction has 4593 states and 6787 transitions. [2021-11-20 05:32:32,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4593 states and 6787 transitions. [2021-11-20 05:32:32,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4593 to 4589. [2021-11-20 05:32:32,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4589 states, 4589 states have (on average 1.4780998038788407) internal successors, (6783), 4588 states have internal predecessors, (6783), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:32,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4589 states to 4589 states and 6783 transitions. [2021-11-20 05:32:32,329 INFO L704 BuchiCegarLoop]: Abstraction has 4589 states and 6783 transitions. [2021-11-20 05:32:32,329 INFO L587 BuchiCegarLoop]: Abstraction has 4589 states and 6783 transitions. [2021-11-20 05:32:32,329 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-20 05:32:32,329 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4589 states and 6783 transitions. [2021-11-20 05:32:32,372 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4404 [2021-11-20 05:32:32,372 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:32:32,372 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:32:32,375 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:32,375 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:32,375 INFO L791 eck$LassoCheckResult]: Stem: 34852#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 34853#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 35150#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35135#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35136#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 35161#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35162#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34406#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34120#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34121#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35049#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35050#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35035#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35036#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35078#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 34176#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34177#L1006 assume !(0 == ~M_E~0); 34022#L1006-2 assume !(0 == ~T1_E~0); 34023#L1011-1 assume !(0 == ~T2_E~0); 35103#L1016-1 assume !(0 == ~T3_E~0); 35120#L1021-1 assume !(0 == ~T4_E~0); 33904#L1026-1 assume !(0 == ~T5_E~0); 33905#L1031-1 assume !(0 == ~T6_E~0); 34795#L1036-1 assume !(0 == ~T7_E~0); 34791#L1041-1 assume !(0 == ~T8_E~0); 34792#L1046-1 assume !(0 == ~T9_E~0); 34207#L1051-1 assume !(0 == ~T10_E~0); 34208#L1056-1 assume !(0 == ~E_1~0); 34928#L1061-1 assume !(0 == ~E_2~0); 34124#L1066-1 assume !(0 == ~E_3~0); 34125#L1071-1 assume !(0 == ~E_4~0); 34907#L1076-1 assume !(0 == ~E_5~0); 34033#L1081-1 assume !(0 == ~E_6~0); 34034#L1086-1 assume !(0 == ~E_7~0); 34381#L1091-1 assume !(0 == ~E_8~0); 35094#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 35095#L1101-1 assume !(0 == ~E_10~0); 34445#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34446#L484 assume !(1 == ~m_pc~0); 34082#L484-2 is_master_triggered_~__retres1~0#1 := 0; 34081#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34709#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 35004#L1245 assume !(0 != activate_threads_~tmp~1#1); 35005#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34783#L503 assume 1 == ~t1_pc~0; 34784#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34800#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34920#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34558#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 33932#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33933#L522 assume !(1 == ~t2_pc~0); 34746#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34137#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34138#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34616#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 35051#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35131#L541 assume 1 == ~t3_pc~0; 34693#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34505#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34317#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34318#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 34749#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34750#L560 assume !(1 == ~t4_pc~0); 34016#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 34015#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34652#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33900#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 33901#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34190#L579 assume 1 == ~t5_pc~0; 33851#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33852#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33960#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34655#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 35118#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35147#L598 assume 1 == ~t6_pc~0; 34284#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34285#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34593#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35027#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 34833#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34774#L617 assume !(1 == ~t7_pc~0); 34257#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 34256#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34547#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34548#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 34482#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34483#L636 assume 1 == ~t8_pc~0; 34649#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34650#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34447#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34448#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 34600#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34601#L655 assume !(1 == ~t9_pc~0); 34632#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 34633#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34236#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34237#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 34854#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34855#L674 assume 1 == ~t10_pc~0; 34009#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34010#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35133#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35173#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 34590#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34591#L1119 assume !(1 == ~M_E~0); 34105#L1119-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34106#L1124-1 assume !(1 == ~T2_E~0); 33924#L1129-1 assume !(1 == ~T3_E~0); 33925#L1134-1 assume !(1 == ~T4_E~0); 34762#L1139-1 assume !(1 == ~T5_E~0); 35366#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35364#L1149-1 assume !(1 == ~T7_E~0); 35327#L1154-1 assume !(1 == ~T8_E~0); 35325#L1159-1 assume !(1 == ~T9_E~0); 35323#L1164-1 assume !(1 == ~T10_E~0); 35321#L1169-1 assume !(1 == ~E_1~0); 35319#L1174-1 assume !(1 == ~E_2~0); 35290#L1179-1 assume !(1 == ~E_3~0); 35260#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 35248#L1189-1 assume !(1 == ~E_5~0); 35246#L1194-1 assume !(1 == ~E_6~0); 35244#L1199-1 assume !(1 == ~E_7~0); 35242#L1204-1 assume !(1 == ~E_8~0); 35231#L1209-1 assume !(1 == ~E_9~0); 35223#L1214-1 assume !(1 == ~E_10~0); 35215#L1219-1 assume { :end_inline_reset_delta_events } true; 35209#L1520-2 [2021-11-20 05:32:32,376 INFO L793 eck$LassoCheckResult]: Loop: 35209#L1520-2 assume !false; 35204#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35202#L981 assume !false; 35201#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35192#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35189#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 35188#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 35186#L836 assume !(0 != eval_~tmp~0#1); 35185#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35184#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35183#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 35181#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35182#L1011-3 assume !(0 == ~T2_E~0); 36543#L1016-3 assume !(0 == ~T3_E~0); 36541#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36498#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36493#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36488#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36487#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36486#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36485#L1051-3 assume !(0 == ~T10_E~0); 36484#L1056-3 assume !(0 == ~E_1~0); 36483#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36482#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36481#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36480#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36479#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36478#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36477#L1091-3 assume !(0 == ~E_8~0); 36476#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36475#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36473#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36471#L484-33 assume 1 == ~m_pc~0; 36468#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 36217#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36215#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36213#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36211#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36209#L503-33 assume !(1 == ~t1_pc~0); 36205#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 36203#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36201#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36199#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36198#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36197#L522-33 assume 1 == ~t2_pc~0; 36195#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36194#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36193#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36192#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36191#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36190#L541-33 assume !(1 == ~t3_pc~0); 36188#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 36186#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36018#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36015#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36013#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36011#L560-33 assume 1 == ~t4_pc~0; 36008#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36005#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36003#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36001#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 35999#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35997#L579-33 assume 1 == ~t5_pc~0; 35994#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35991#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35989#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35987#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35985#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35128#L598-33 assume 1 == ~t6_pc~0; 35129#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34392#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34393#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34231#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34232#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35062#L617-33 assume 1 == ~t7_pc~0; 35073#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34021#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34993#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35112#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35108#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33949#L636-33 assume !(1 == ~t8_pc~0); 33950#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 34892#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34893#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35137#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 34881#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34882#L655-33 assume 1 == ~t9_pc~0; 35169#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34332#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34333#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34698#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 34971#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34511#L674-33 assume 1 == ~t10_pc~0; 34385#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34386#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34247#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34248#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35584#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35548#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35546#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35152#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35543#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35165#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35540#L1139-3 assume !(1 == ~T5_E~0); 35538#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35536#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35533#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35531#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35529#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35470#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35468#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35467#L1179-3 assume !(1 == ~E_3~0); 35464#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35462#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35407#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35405#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35403#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35361#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35359#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35305#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35278#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35276#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 35274#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 35273#L1539 assume !(0 == start_simulation_~tmp~3#1); 35271#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35253#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35247#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 35245#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 35243#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35232#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35224#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 35216#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 35209#L1520-2 [2021-11-20 05:32:32,376 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:32,377 INFO L85 PathProgramCache]: Analyzing trace with hash -598093007, now seen corresponding path program 1 times [2021-11-20 05:32:32,377 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:32,377 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1906728587] [2021-11-20 05:32:32,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:32,377 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:32,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:32,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:32,413 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:32,413 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1906728587] [2021-11-20 05:32:32,413 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1906728587] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:32,415 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:32,416 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:32,417 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [573724660] [2021-11-20 05:32:32,417 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:32,418 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:32:32,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:32,418 INFO L85 PathProgramCache]: Analyzing trace with hash 1559712174, now seen corresponding path program 1 times [2021-11-20 05:32:32,418 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:32,419 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [659724379] [2021-11-20 05:32:32,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:32,419 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:32,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:32,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:32,461 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:32,461 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [659724379] [2021-11-20 05:32:32,461 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [659724379] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:32,461 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:32,461 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:32,462 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [36762656] [2021-11-20 05:32:32,462 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:32,462 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:32:32,462 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:32:32,463 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 05:32:32,463 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 05:32:32,463 INFO L87 Difference]: Start difference. First operand 4589 states and 6783 transitions. cyclomatic complexity: 2198 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:32,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:32:32,651 INFO L93 Difference]: Finished difference Result 8697 states and 12836 transitions. [2021-11-20 05:32:32,652 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 05:32:32,652 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8697 states and 12836 transitions. [2021-11-20 05:32:32,702 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8492 [2021-11-20 05:32:32,756 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8697 states to 8697 states and 12836 transitions. [2021-11-20 05:32:32,757 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8697 [2021-11-20 05:32:32,767 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8697 [2021-11-20 05:32:32,767 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8697 states and 12836 transitions. [2021-11-20 05:32:32,780 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:32:32,780 INFO L681 BuchiCegarLoop]: Abstraction has 8697 states and 12836 transitions. [2021-11-20 05:32:32,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8697 states and 12836 transitions. [2021-11-20 05:32:32,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8697 to 8693. [2021-11-20 05:32:32,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8693 states, 8693 states have (on average 1.4761302197170136) internal successors, (12832), 8692 states have internal predecessors, (12832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:33,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8693 states to 8693 states and 12832 transitions. [2021-11-20 05:32:33,032 INFO L704 BuchiCegarLoop]: Abstraction has 8693 states and 12832 transitions. [2021-11-20 05:32:33,032 INFO L587 BuchiCegarLoop]: Abstraction has 8693 states and 12832 transitions. [2021-11-20 05:32:33,033 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-20 05:32:33,033 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8693 states and 12832 transitions. [2021-11-20 05:32:33,075 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8492 [2021-11-20 05:32:33,075 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:32:33,075 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:32:33,078 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:33,078 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:33,079 INFO L791 eck$LassoCheckResult]: Stem: 48148#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 48149#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 48450#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48438#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48439#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 48467#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48468#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47701#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47417#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47418#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48360#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48361#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48346#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48347#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48384#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47471#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47472#L1006 assume !(0 == ~M_E~0); 47319#L1006-2 assume !(0 == ~T1_E~0); 47320#L1011-1 assume !(0 == ~T2_E~0); 48409#L1016-1 assume !(0 == ~T3_E~0); 48426#L1021-1 assume !(0 == ~T4_E~0); 47198#L1026-1 assume !(0 == ~T5_E~0); 47199#L1031-1 assume !(0 == ~T6_E~0); 48094#L1036-1 assume !(0 == ~T7_E~0); 48090#L1041-1 assume !(0 == ~T8_E~0); 48091#L1046-1 assume !(0 == ~T9_E~0); 47504#L1051-1 assume !(0 == ~T10_E~0); 47505#L1056-1 assume !(0 == ~E_1~0); 48227#L1061-1 assume !(0 == ~E_2~0); 47421#L1066-1 assume !(0 == ~E_3~0); 47422#L1071-1 assume !(0 == ~E_4~0); 48205#L1076-1 assume !(0 == ~E_5~0); 47330#L1081-1 assume !(0 == ~E_6~0); 47331#L1086-1 assume !(0 == ~E_7~0); 47676#L1091-1 assume !(0 == ~E_8~0); 48398#L1096-1 assume !(0 == ~E_9~0); 48399#L1101-1 assume !(0 == ~E_10~0); 47739#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47740#L484 assume !(1 == ~m_pc~0); 47379#L484-2 is_master_triggered_~__retres1~0#1 := 0; 47378#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48010#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 48313#L1245 assume !(0 != activate_threads_~tmp~1#1); 48314#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48082#L503 assume 1 == ~t1_pc~0; 48083#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 48099#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48219#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47856#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 47229#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47230#L522 assume !(1 == ~t2_pc~0); 48047#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 47434#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47435#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47914#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 48362#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48435#L541 assume 1 == ~t3_pc~0; 47994#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47801#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47613#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47614#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 48050#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48051#L560 assume !(1 == ~t4_pc~0); 47311#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47310#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47951#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47196#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 47197#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47485#L579 assume 1 == ~t5_pc~0; 47147#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47148#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47257#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47955#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 48424#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48447#L598 assume 1 == ~t6_pc~0; 47581#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47582#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47890#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48338#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 48131#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48073#L617 assume !(1 == ~t7_pc~0); 47554#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 47553#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47846#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47847#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47777#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47778#L636 assume 1 == ~t8_pc~0; 47948#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47949#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47741#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47742#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 47898#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47899#L655 assume !(1 == ~t9_pc~0); 47927#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 47928#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47533#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47534#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 48150#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48151#L674 assume 1 == ~t10_pc~0; 47306#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 47307#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48437#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48478#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 47888#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47889#L1119 assume !(1 == ~M_E~0); 47402#L1119-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47403#L1124-1 assume !(1 == ~T2_E~0); 48819#L1129-1 assume !(1 == ~T3_E~0); 48817#L1134-1 assume !(1 == ~T4_E~0); 48815#L1139-1 assume !(1 == ~T5_E~0); 48813#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48812#L1149-1 assume !(1 == ~T7_E~0); 47397#L1154-1 assume !(1 == ~T8_E~0); 47398#L1159-1 assume !(1 == ~T9_E~0); 47488#L1164-1 assume !(1 == ~T10_E~0); 48480#L1169-1 assume !(1 == ~E_1~0); 48698#L1174-1 assume !(1 == ~E_2~0); 48601#L1179-1 assume !(1 == ~E_3~0); 48599#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 48587#L1189-1 assume !(1 == ~E_5~0); 48585#L1194-1 assume !(1 == ~E_6~0); 48583#L1199-1 assume !(1 == ~E_7~0); 48557#L1204-1 assume !(1 == ~E_8~0); 48543#L1209-1 assume !(1 == ~E_9~0); 48533#L1214-1 assume !(1 == ~E_10~0); 48525#L1219-1 assume { :end_inline_reset_delta_events } true; 48519#L1520-2 [2021-11-20 05:32:33,079 INFO L793 eck$LassoCheckResult]: Loop: 48519#L1520-2 assume !false; 48514#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48512#L981 assume !false; 48511#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 48502#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 48499#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 48498#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 48496#L836 assume !(0 != eval_~tmp~0#1); 48495#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 48494#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48493#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48492#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 48253#L1011-3 assume !(0 == ~T2_E~0); 48254#L1016-3 assume !(0 == ~T3_E~0); 48301#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47965#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47966#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 48221#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 48222#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48289#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48290#L1051-3 assume !(0 == ~T10_E~0); 48223#L1056-3 assume !(0 == ~E_1~0); 47499#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47500#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47503#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48413#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47283#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47284#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47336#L1091-3 assume !(0 == ~E_8~0); 47337#L1096-3 assume !(0 == ~E_9~0); 48385#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 48386#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47988#L484-33 assume 1 == ~m_pc~0; 47989#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 47903#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47904#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47190#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47191#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47663#L503-33 assume !(1 == ~t1_pc~0); 47664#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 48133#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48058#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47573#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47574#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48027#L522-33 assume 1 == ~t2_pc~0; 48028#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47324#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47325#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48138#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 48045#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48046#L541-33 assume 1 == ~t3_pc~0; 47350#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47188#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47189#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48016#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 48017#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48218#L560-33 assume 1 == ~t4_pc~0; 47910#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47261#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47262#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47523#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 48199#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47179#L579-33 assume 1 == ~t5_pc~0; 47180#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47428#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48430#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48074#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48075#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48103#L598-33 assume 1 == ~t6_pc~0; 48433#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47687#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47688#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47528#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47529#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48373#L617-33 assume !(1 == ~t7_pc~0); 47317#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 47318#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50388#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50386#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50384#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50382#L636-33 assume !(1 == ~t8_pc~0); 50378#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 50376#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50373#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50371#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50369#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50367#L655-33 assume 1 == ~t9_pc~0; 50364#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50362#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50359#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50357#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50355#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50353#L674-33 assume !(1 == ~t10_pc~0); 50349#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 50346#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50344#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50342#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50340#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50338#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50336#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48454#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 49824#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49821#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49819#L1139-3 assume !(1 == ~T5_E~0); 49816#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49814#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49812#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49810#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49808#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 49465#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49461#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49458#L1179-3 assume !(1 == ~E_3~0); 49457#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49456#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49239#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49055#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49053#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49051#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 48825#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 48822#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 48744#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 48742#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 48740#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 48639#L1539 assume !(0 == start_simulation_~tmp~3#1); 48636#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 48592#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 48586#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 48584#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 48558#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48544#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48534#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 48526#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 48519#L1520-2 [2021-11-20 05:32:33,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:33,080 INFO L85 PathProgramCache]: Analyzing trace with hash 1756292275, now seen corresponding path program 1 times [2021-11-20 05:32:33,080 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:33,081 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842618296] [2021-11-20 05:32:33,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:33,081 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:33,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:33,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:33,119 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:33,119 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842618296] [2021-11-20 05:32:33,119 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [842618296] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:33,119 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:33,119 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:33,120 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953589124] [2021-11-20 05:32:33,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:33,120 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:32:33,121 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:33,121 INFO L85 PathProgramCache]: Analyzing trace with hash 769490639, now seen corresponding path program 1 times [2021-11-20 05:32:33,121 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:33,121 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [477427416] [2021-11-20 05:32:33,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:33,122 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:33,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:33,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:33,162 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:33,163 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [477427416] [2021-11-20 05:32:33,163 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [477427416] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:33,163 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:33,163 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:33,163 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1926764556] [2021-11-20 05:32:33,164 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:33,164 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:32:33,164 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:32:33,165 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 05:32:33,165 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 05:32:33,165 INFO L87 Difference]: Start difference. First operand 8693 states and 12832 transitions. cyclomatic complexity: 4147 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:33,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:32:33,521 INFO L93 Difference]: Finished difference Result 24691 states and 36036 transitions. [2021-11-20 05:32:33,521 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 05:32:33,523 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24691 states and 36036 transitions. [2021-11-20 05:32:33,731 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24124 [2021-11-20 05:32:33,828 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24691 states to 24691 states and 36036 transitions. [2021-11-20 05:32:33,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24691 [2021-11-20 05:32:33,856 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24691 [2021-11-20 05:32:33,856 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24691 states and 36036 transitions. [2021-11-20 05:32:33,882 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:32:33,882 INFO L681 BuchiCegarLoop]: Abstraction has 24691 states and 36036 transitions. [2021-11-20 05:32:33,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24691 states and 36036 transitions. [2021-11-20 05:32:34,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24691 to 23775. [2021-11-20 05:32:34,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23775 states, 23775 states have (on average 1.4623764458464774) internal successors, (34768), 23774 states have internal predecessors, (34768), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:34,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23775 states to 23775 states and 34768 transitions. [2021-11-20 05:32:34,515 INFO L704 BuchiCegarLoop]: Abstraction has 23775 states and 34768 transitions. [2021-11-20 05:32:34,515 INFO L587 BuchiCegarLoop]: Abstraction has 23775 states and 34768 transitions. [2021-11-20 05:32:34,515 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-20 05:32:34,516 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23775 states and 34768 transitions. [2021-11-20 05:32:34,655 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23556 [2021-11-20 05:32:34,655 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:32:34,655 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:32:34,658 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:34,663 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:34,664 INFO L791 eck$LassoCheckResult]: Stem: 81557#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 81558#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 81939#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 81910#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 81911#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 81959#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 81960#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81091#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 80806#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 80807#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81808#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 81809#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 81791#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 81792#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 81841#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 80860#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 80861#L1006 assume !(0 == ~M_E~0); 80714#L1006-2 assume !(0 == ~T1_E~0); 80715#L1011-1 assume !(0 == ~T2_E~0); 81873#L1016-1 assume !(0 == ~T3_E~0); 81894#L1021-1 assume !(0 == ~T4_E~0); 80594#L1026-1 assume !(0 == ~T5_E~0); 80595#L1031-1 assume !(0 == ~T6_E~0); 81499#L1036-1 assume !(0 == ~T7_E~0); 81493#L1041-1 assume !(0 == ~T8_E~0); 81494#L1046-1 assume !(0 == ~T9_E~0); 80891#L1051-1 assume !(0 == ~T10_E~0); 80892#L1056-1 assume !(0 == ~E_1~0); 81649#L1061-1 assume !(0 == ~E_2~0); 80810#L1066-1 assume !(0 == ~E_3~0); 80811#L1071-1 assume !(0 == ~E_4~0); 81625#L1076-1 assume !(0 == ~E_5~0); 80722#L1081-1 assume !(0 == ~E_6~0); 80723#L1086-1 assume !(0 == ~E_7~0); 81067#L1091-1 assume !(0 == ~E_8~0); 81860#L1096-1 assume !(0 == ~E_9~0); 81861#L1101-1 assume !(0 == ~E_10~0); 81128#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81129#L484 assume !(1 == ~m_pc~0); 81233#L484-2 is_master_triggered_~__retres1~0#1 := 0; 81234#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81405#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 81748#L1245 assume !(0 != activate_threads_~tmp~1#1); 81749#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81486#L503 assume !(1 == ~t1_pc~0); 81487#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 81686#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81641#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 81251#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 80622#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80623#L522 assume !(1 == ~t2_pc~0); 81441#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 80822#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80823#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 81307#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 81810#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81906#L541 assume 1 == ~t3_pc~0; 81388#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 81191#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81003#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 81004#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 81447#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81448#L560 assume !(1 == ~t4_pc~0); 80706#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 80705#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81346#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 80590#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 80591#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 80874#L579 assume 1 == ~t5_pc~0; 80541#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 80542#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 80650#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81350#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 81893#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81933#L598 assume 1 == ~t6_pc~0; 80969#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 80970#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81286#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81779#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 81538#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81474#L617 assume !(1 == ~t7_pc~0); 80941#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 80940#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81235#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 81236#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 81165#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 81166#L636 assume 1 == ~t8_pc~0; 81343#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 81344#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 81130#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 81131#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 81293#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 81294#L655 assume !(1 == ~t9_pc~0); 81323#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 81324#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 80921#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 80922#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 81559#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 81560#L674 assume 1 == ~t10_pc~0; 80699#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 80700#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 81909#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 81979#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 81281#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81282#L1119 assume !(1 == ~M_E~0); 80791#L1119-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 80792#L1124-1 assume !(1 == ~T2_E~0); 80614#L1129-1 assume !(1 == ~T3_E~0); 80615#L1134-1 assume !(1 == ~T4_E~0); 91711#L1139-1 assume !(1 == ~T5_E~0); 91709#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 81989#L1149-1 assume !(1 == ~T7_E~0); 80786#L1154-1 assume !(1 == ~T8_E~0); 80787#L1159-1 assume !(1 == ~T9_E~0); 80875#L1164-1 assume !(1 == ~T10_E~0); 81310#L1169-1 assume !(1 == ~E_1~0); 81311#L1174-1 assume !(1 == ~E_2~0); 96619#L1179-1 assume !(1 == ~E_3~0); 96607#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 96605#L1189-1 assume !(1 == ~E_5~0); 96603#L1194-1 assume !(1 == ~E_6~0); 96602#L1199-1 assume !(1 == ~E_7~0); 80993#L1204-1 assume !(1 == ~E_8~0); 80994#L1209-1 assume !(1 == ~E_9~0); 81553#L1214-1 assume !(1 == ~E_10~0); 81554#L1219-1 assume { :end_inline_reset_delta_events } true; 80578#L1520-2 [2021-11-20 05:32:34,664 INFO L793 eck$LassoCheckResult]: Loop: 80578#L1520-2 assume !false; 80579#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 103250#L981 assume !false; 103249#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 103240#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 81738#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 81739#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 81866#L836 assume !(0 != eval_~tmp~0#1); 81159#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 81160#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 81152#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 81153#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 81681#L1011-3 assume !(0 == ~T2_E~0); 81682#L1016-3 assume !(0 == ~T3_E~0); 81732#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 81362#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 81363#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 81643#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 81644#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 81721#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 81722#L1051-3 assume !(0 == ~T10_E~0); 81645#L1056-3 assume !(0 == ~E_1~0); 80886#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 80887#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 80890#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 81880#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 80675#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 80676#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 80732#L1091-3 assume !(0 == ~E_8~0); 80733#L1096-3 assume !(0 == ~E_9~0); 81842#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 81843#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81382#L484-33 assume !(1 == ~m_pc~0); 81383#L484-35 is_master_triggered_~__retres1~0#1 := 0; 81296#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81297#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 80584#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 80585#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81051#L503-33 assume !(1 == ~t1_pc~0); 81052#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 81540#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81453#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 80958#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 80959#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81418#L522-33 assume 1 == ~t2_pc~0; 81419#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 80718#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80719#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 81545#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 81439#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81440#L541-33 assume !(1 == ~t3_pc~0); 80743#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 80582#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80583#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 81411#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 81412#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81640#L560-33 assume 1 == ~t4_pc~0; 81303#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 80654#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 80655#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 80909#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 81618#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 80570#L579-33 assume 1 == ~t5_pc~0; 80571#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 80816#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81901#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81475#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 81476#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81504#L598-33 assume !(1 == ~t6_pc~0); 81257#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 81077#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81078#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 80916#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 80917#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81826#L617-33 assume !(1 == ~t7_pc~0); 80710#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 80711#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81730#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 81886#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 81881#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 80639#L636-33 assume 1 == ~t8_pc~0; 80641#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 81609#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 81610#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 103456#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 103454#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 103452#L655-33 assume 1 == ~t9_pc~0; 103449#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 103446#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 103444#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 103442#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 103440#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 103438#L674-33 assume !(1 == ~t10_pc~0); 103435#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 81922#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 80932#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 80933#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 81430#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103363#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 103361#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 81943#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 103358#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 81963#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 103355#L1139-3 assume !(1 == ~T5_E~0); 103353#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 103351#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 103350#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 103349#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 103348#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 103347#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 97576#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 103346#L1179-3 assume !(1 == ~E_3~0); 103345#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 103344#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 103343#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 103342#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 103341#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 103340#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 95470#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 103339#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 103328#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 81854#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 81034#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 81035#L1539 assume !(0 == start_simulation_~tmp~3#1); 81125#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 81314#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 81109#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 81250#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 81025#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 81026#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 81827#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 81828#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 80578#L1520-2 [2021-11-20 05:32:34,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:34,665 INFO L85 PathProgramCache]: Analyzing trace with hash -228536430, now seen corresponding path program 1 times [2021-11-20 05:32:34,665 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:34,666 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [361175980] [2021-11-20 05:32:34,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:34,666 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:34,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:34,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:34,708 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:34,708 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [361175980] [2021-11-20 05:32:34,708 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [361175980] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:34,708 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:34,708 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:34,709 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [469199445] [2021-11-20 05:32:34,709 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:34,709 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:32:34,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:34,710 INFO L85 PathProgramCache]: Analyzing trace with hash -811908019, now seen corresponding path program 1 times [2021-11-20 05:32:34,710 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:34,710 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [454916958] [2021-11-20 05:32:34,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:34,711 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:34,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:34,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:34,754 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:34,754 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [454916958] [2021-11-20 05:32:34,754 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [454916958] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:34,754 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:34,754 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:34,755 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2004084176] [2021-11-20 05:32:34,755 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:34,755 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:32:34,756 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:32:34,756 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 05:32:34,756 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 05:32:34,757 INFO L87 Difference]: Start difference. First operand 23775 states and 34768 transitions. cyclomatic complexity: 11009 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:35,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:32:35,646 INFO L93 Difference]: Finished difference Result 67830 states and 98347 transitions. [2021-11-20 05:32:35,647 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 05:32:35,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67830 states and 98347 transitions. [2021-11-20 05:32:36,014 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 66808 [2021-11-20 05:32:36,235 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67830 states to 67830 states and 98347 transitions. [2021-11-20 05:32:36,236 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67830 [2021-11-20 05:32:36,387 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67830 [2021-11-20 05:32:36,388 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67830 states and 98347 transitions. [2021-11-20 05:32:36,492 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:32:36,524 INFO L681 BuchiCegarLoop]: Abstraction has 67830 states and 98347 transitions. [2021-11-20 05:32:36,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67830 states and 98347 transitions. [2021-11-20 05:32:37,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67830 to 65698. [2021-11-20 05:32:37,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65698 states, 65698 states have (on average 1.4524490852080734) internal successors, (95423), 65697 states have internal predecessors, (95423), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:37,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65698 states to 65698 states and 95423 transitions. [2021-11-20 05:32:37,637 INFO L704 BuchiCegarLoop]: Abstraction has 65698 states and 95423 transitions. [2021-11-20 05:32:37,637 INFO L587 BuchiCegarLoop]: Abstraction has 65698 states and 95423 transitions. [2021-11-20 05:32:37,637 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-20 05:32:37,637 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65698 states and 95423 transitions. [2021-11-20 05:32:38,085 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 65440 [2021-11-20 05:32:38,085 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:32:38,085 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:32:38,088 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:38,088 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:38,088 INFO L791 eck$LassoCheckResult]: Stem: 173162#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 173163#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 173538#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 173517#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 173518#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 173566#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 173567#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 172705#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 172421#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 172422#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 173417#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 173418#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 173393#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 173394#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 173448#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 172475#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 172476#L1006 assume !(0 == ~M_E~0); 172327#L1006-2 assume !(0 == ~T1_E~0); 172328#L1011-1 assume !(0 == ~T2_E~0); 173477#L1016-1 assume !(0 == ~T3_E~0); 173499#L1021-1 assume !(0 == ~T4_E~0); 172209#L1026-1 assume !(0 == ~T5_E~0); 172210#L1031-1 assume !(0 == ~T6_E~0); 173109#L1036-1 assume !(0 == ~T7_E~0); 173103#L1041-1 assume !(0 == ~T8_E~0); 173104#L1046-1 assume !(0 == ~T9_E~0); 172506#L1051-1 assume !(0 == ~T10_E~0); 172507#L1056-1 assume !(0 == ~E_1~0); 173256#L1061-1 assume !(0 == ~E_2~0); 172423#L1066-1 assume !(0 == ~E_3~0); 172424#L1071-1 assume !(0 == ~E_4~0); 173234#L1076-1 assume !(0 == ~E_5~0); 172335#L1081-1 assume !(0 == ~E_6~0); 172336#L1086-1 assume !(0 == ~E_7~0); 172680#L1091-1 assume !(0 == ~E_8~0); 173468#L1096-1 assume !(0 == ~E_9~0); 173469#L1101-1 assume !(0 == ~E_10~0); 172745#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 172746#L484 assume !(1 == ~m_pc~0); 172855#L484-2 is_master_triggered_~__retres1~0#1 := 0; 172856#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 173024#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 173350#L1245 assume !(0 != activate_threads_~tmp~1#1); 173351#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 173096#L503 assume !(1 == ~t1_pc~0); 173097#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 173295#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 173247#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 172873#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 172237#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 172238#L522 assume !(1 == ~t2_pc~0); 173060#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 172437#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 172438#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 172928#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 173419#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 173513#L541 assume !(1 == ~t3_pc~0); 172810#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 172811#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 172617#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 172618#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 173067#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 173068#L560 assume !(1 == ~t4_pc~0); 172319#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 172318#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 172964#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 172205#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 172206#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 172489#L579 assume 1 == ~t5_pc~0; 172156#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 172157#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 172265#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 172969#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 173498#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 173534#L598 assume 1 == ~t6_pc~0; 172584#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 172585#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 172907#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 173379#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 173145#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 173087#L617 assume !(1 == ~t7_pc~0); 172557#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 172556#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 172857#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 172858#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 172787#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 172788#L636 assume 1 == ~t8_pc~0; 172961#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 172962#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 172747#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 172748#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 172912#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 172913#L655 assume !(1 == ~t9_pc~0); 172944#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 172945#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 172537#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 172538#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 173164#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 173165#L674 assume 1 == ~t10_pc~0; 172312#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 172313#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 173516#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 173586#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 172902#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 172903#L1119 assume !(1 == ~M_E~0); 172404#L1119-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 172405#L1124-1 assume !(1 == ~T2_E~0); 172229#L1129-1 assume !(1 == ~T3_E~0); 172230#L1134-1 assume !(1 == ~T4_E~0); 172542#L1139-1 assume !(1 == ~T5_E~0); 172543#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 173603#L1149-1 assume !(1 == ~T7_E~0); 173604#L1154-1 assume !(1 == ~T8_E~0); 172490#L1159-1 assume !(1 == ~T9_E~0); 172491#L1164-1 assume !(1 == ~T10_E~0); 172931#L1169-1 assume !(1 == ~E_1~0); 172932#L1174-1 assume !(1 == ~E_2~0); 172600#L1179-1 assume !(1 == ~E_3~0); 172601#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 172535#L1189-1 assume !(1 == ~E_5~0); 172536#L1194-1 assume !(1 == ~E_6~0); 173608#L1199-1 assume !(1 == ~E_7~0); 173609#L1204-1 assume !(1 == ~E_8~0); 173555#L1209-1 assume !(1 == ~E_9~0); 173556#L1214-1 assume !(1 == ~E_10~0); 173591#L1219-1 assume { :end_inline_reset_delta_events } true; 173592#L1520-2 [2021-11-20 05:32:38,089 INFO L793 eck$LassoCheckResult]: Loop: 173592#L1520-2 assume !false; 187162#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 187159#L981 assume !false; 187157#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 187158#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 190835#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 187137#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 187131#L836 assume !(0 != eval_~tmp~0#1); 187133#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 204592#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 204591#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 204590#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 204589#L1011-3 assume !(0 == ~T2_E~0); 204588#L1016-3 assume !(0 == ~T3_E~0); 204587#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 204586#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 204585#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 204584#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 204583#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 204582#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 204581#L1051-3 assume !(0 == ~T10_E~0); 204580#L1056-3 assume !(0 == ~E_1~0); 204579#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 204578#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 204577#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 204576#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 204575#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 204574#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 204573#L1091-3 assume !(0 == ~E_8~0); 204572#L1096-3 assume !(0 == ~E_9~0); 204571#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 204570#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 204569#L484-33 assume !(1 == ~m_pc~0); 204568#L484-35 is_master_triggered_~__retres1~0#1 := 0; 204567#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 204566#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 204565#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 204564#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 204563#L503-33 assume !(1 == ~t1_pc~0); 204562#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 204561#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 204560#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 204559#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 204558#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 204557#L522-33 assume 1 == ~t2_pc~0; 204555#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 204554#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 204553#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 204552#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 204551#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 204550#L541-33 assume !(1 == ~t3_pc~0); 204549#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 204548#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 204547#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 204546#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 204545#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 204544#L560-33 assume !(1 == ~t4_pc~0); 204543#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 204541#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 204540#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 204539#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 204538#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 204537#L579-33 assume 1 == ~t5_pc~0; 204535#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 204534#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 204533#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 204532#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 204531#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 204530#L598-33 assume 1 == ~t6_pc~0; 204529#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 187887#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 187882#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 187883#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 204520#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 204518#L617-33 assume 1 == ~t7_pc~0; 204515#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 204514#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 204513#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 204512#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 204511#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 204510#L636-33 assume 1 == ~t8_pc~0; 204509#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 204507#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 204506#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 204505#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 204504#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 204503#L655-33 assume !(1 == ~t9_pc~0); 204502#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 204500#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 204499#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 204498#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 204497#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 204496#L674-33 assume 1 == ~t10_pc~0; 204495#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 204493#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 204492#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 204491#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 204488#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 204486#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 204484#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 181799#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 204481#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 201604#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 204477#L1139-3 assume !(1 == ~T5_E~0); 204475#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 204473#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 204471#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 204469#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 204467#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 187638#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 185818#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 187635#L1179-3 assume !(1 == ~E_3~0); 187632#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 187629#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 187626#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 187627#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 195385#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 187620#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 186624#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 187618#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 187566#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 187557#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 187548#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 187539#L1539 assume !(0 == start_simulation_~tmp~3#1); 187320#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 187219#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 187213#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 187210#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 187211#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 191560#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 191558#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 191556#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 173592#L1520-2 [2021-11-20 05:32:38,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:38,090 INFO L85 PathProgramCache]: Analyzing trace with hash 678220017, now seen corresponding path program 1 times [2021-11-20 05:32:38,090 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:38,090 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246365145] [2021-11-20 05:32:38,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:38,090 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:38,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:38,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:38,127 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:38,128 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [246365145] [2021-11-20 05:32:38,128 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [246365145] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:38,128 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:38,128 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-20 05:32:38,128 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [680492220] [2021-11-20 05:32:38,128 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:38,129 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:32:38,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:38,129 INFO L85 PathProgramCache]: Analyzing trace with hash -2004057426, now seen corresponding path program 1 times [2021-11-20 05:32:38,130 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:38,130 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [504155372] [2021-11-20 05:32:38,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:38,130 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:38,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:38,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:38,164 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:38,164 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [504155372] [2021-11-20 05:32:38,164 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [504155372] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:38,165 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:38,165 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:38,165 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2077911511] [2021-11-20 05:32:38,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:38,166 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:32:38,166 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:32:38,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-20 05:32:38,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-20 05:32:38,166 INFO L87 Difference]: Start difference. First operand 65698 states and 95423 transitions. cyclomatic complexity: 29757 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:39,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:32:39,002 INFO L93 Difference]: Finished difference Result 124969 states and 180909 transitions. [2021-11-20 05:32:39,002 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-20 05:32:39,004 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124969 states and 180909 transitions. [2021-11-20 05:32:39,946 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 124508 [2021-11-20 05:32:40,379 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124969 states to 124969 states and 180909 transitions. [2021-11-20 05:32:40,379 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 124969 [2021-11-20 05:32:40,443 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 124969 [2021-11-20 05:32:40,443 INFO L73 IsDeterministic]: Start isDeterministic. Operand 124969 states and 180909 transitions. [2021-11-20 05:32:40,591 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:32:40,591 INFO L681 BuchiCegarLoop]: Abstraction has 124969 states and 180909 transitions. [2021-11-20 05:32:40,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124969 states and 180909 transitions. [2021-11-20 05:32:41,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124969 to 124825. [2021-11-20 05:32:41,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124825 states, 124825 states have (on average 1.4481474063689166) internal successors, (180765), 124824 states have internal predecessors, (180765), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:42,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124825 states to 124825 states and 180765 transitions. [2021-11-20 05:32:42,616 INFO L704 BuchiCegarLoop]: Abstraction has 124825 states and 180765 transitions. [2021-11-20 05:32:42,617 INFO L587 BuchiCegarLoop]: Abstraction has 124825 states and 180765 transitions. [2021-11-20 05:32:42,617 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-20 05:32:42,617 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124825 states and 180765 transitions. [2021-11-20 05:32:42,926 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 124364 [2021-11-20 05:32:42,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:32:42,927 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:32:42,930 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:42,930 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:42,930 INFO L791 eck$LassoCheckResult]: Stem: 363847#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 363848#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 364239#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 364213#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 364214#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 364260#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 364261#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 363380#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 363094#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 363095#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 364108#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 364109#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 364083#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 364084#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 364138#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 363146#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 363147#L1006 assume !(0 == ~M_E~0); 362999#L1006-2 assume !(0 == ~T1_E~0); 363000#L1011-1 assume !(0 == ~T2_E~0); 364167#L1016-1 assume !(0 == ~T3_E~0); 364196#L1021-1 assume !(0 == ~T4_E~0); 362880#L1026-1 assume !(0 == ~T5_E~0); 362881#L1031-1 assume !(0 == ~T6_E~0); 363788#L1036-1 assume !(0 == ~T7_E~0); 363782#L1041-1 assume !(0 == ~T8_E~0); 363783#L1046-1 assume !(0 == ~T9_E~0); 363177#L1051-1 assume !(0 == ~T10_E~0); 363178#L1056-1 assume !(0 == ~E_1~0); 363940#L1061-1 assume !(0 == ~E_2~0); 363096#L1066-1 assume !(0 == ~E_3~0); 363097#L1071-1 assume !(0 == ~E_4~0); 363918#L1076-1 assume !(0 == ~E_5~0); 363007#L1081-1 assume !(0 == ~E_6~0); 363008#L1086-1 assume !(0 == ~E_7~0); 363356#L1091-1 assume !(0 == ~E_8~0); 364156#L1096-1 assume !(0 == ~E_9~0); 364157#L1101-1 assume !(0 == ~E_10~0); 363418#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 363419#L484 assume !(1 == ~m_pc~0); 363525#L484-2 is_master_triggered_~__retres1~0#1 := 0; 363526#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 363702#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 364040#L1245 assume !(0 != activate_threads_~tmp~1#1); 364041#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 363775#L503 assume !(1 == ~t1_pc~0); 363776#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 363986#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 363932#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 363545#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 362911#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 362912#L522 assume !(1 == ~t2_pc~0); 363740#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 363110#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 363111#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 363602#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 364110#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 364209#L541 assume !(1 == ~t3_pc~0); 363476#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 363477#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 363290#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 363291#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 363747#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 363748#L560 assume !(1 == ~t4_pc~0); 362991#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 362990#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 363638#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 362876#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 362877#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 363160#L579 assume !(1 == ~t5_pc~0); 363161#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 362937#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 362938#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 363643#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 364195#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 364236#L598 assume 1 == ~t6_pc~0; 363257#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 363258#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 363580#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 364073#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 363828#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 363766#L617 assume !(1 == ~t7_pc~0); 363227#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 363226#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 363527#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 363528#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 363455#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 363456#L636 assume 1 == ~t8_pc~0; 363635#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 363636#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 363420#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 363421#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 363587#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 363588#L655 assume !(1 == ~t9_pc~0); 363619#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 363620#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 363207#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 363208#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 363849#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 363850#L674 assume 1 == ~t10_pc~0; 362984#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 362985#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 364212#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 364288#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 363575#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 363576#L1119 assume !(1 == ~M_E~0); 363077#L1119-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 363078#L1124-1 assume !(1 == ~T2_E~0); 363500#L1129-1 assume !(1 == ~T3_E~0); 373062#L1134-1 assume !(1 == ~T4_E~0); 373060#L1139-1 assume !(1 == ~T5_E~0); 373058#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 364302#L1149-1 assume !(1 == ~T7_E~0); 364303#L1154-1 assume !(1 == ~T8_E~0); 372970#L1159-1 assume !(1 == ~T9_E~0); 364294#L1164-1 assume !(1 == ~T10_E~0); 364295#L1169-1 assume !(1 == ~E_1~0); 372955#L1174-1 assume !(1 == ~E_2~0); 372953#L1179-1 assume !(1 == ~E_3~0); 372951#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 372949#L1189-1 assume !(1 == ~E_5~0); 372947#L1194-1 assume !(1 == ~E_6~0); 372945#L1199-1 assume !(1 == ~E_7~0); 372943#L1204-1 assume !(1 == ~E_8~0); 372931#L1209-1 assume !(1 == ~E_9~0); 372929#L1214-1 assume !(1 == ~E_10~0); 372928#L1219-1 assume { :end_inline_reset_delta_events } true; 372924#L1520-2 [2021-11-20 05:32:42,931 INFO L793 eck$LassoCheckResult]: Loop: 372924#L1520-2 assume !false; 372917#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 372914#L981 assume !false; 372912#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 372893#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 372887#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 372882#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 372874#L836 assume !(0 != eval_~tmp~0#1); 372875#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 373905#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 373903#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 373901#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 373899#L1011-3 assume !(0 == ~T2_E~0); 373897#L1016-3 assume !(0 == ~T3_E~0); 373895#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 373893#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 373892#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 373889#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 373887#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 373885#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 373883#L1051-3 assume !(0 == ~T10_E~0); 373881#L1056-3 assume !(0 == ~E_1~0); 373879#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 373877#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 373875#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 373873#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 373871#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 373869#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 373867#L1091-3 assume !(0 == ~E_8~0); 373864#L1096-3 assume !(0 == ~E_9~0); 373862#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 373860#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 373858#L484-33 assume !(1 == ~m_pc~0); 373856#L484-35 is_master_triggered_~__retres1~0#1 := 0; 373854#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 373851#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 373849#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 373847#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 373845#L503-33 assume !(1 == ~t1_pc~0); 373843#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 373841#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 373840#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 373839#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 373838#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 373836#L522-33 assume 1 == ~t2_pc~0; 373833#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 373831#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 373829#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 373827#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 373825#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 373823#L541-33 assume !(1 == ~t3_pc~0); 373821#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 373819#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 373817#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 373815#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 373813#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 373250#L560-33 assume !(1 == ~t4_pc~0); 373247#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 373244#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 373242#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 373240#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 373238#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 373236#L579-33 assume !(1 == ~t5_pc~0); 373233#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 373231#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 373229#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 373227#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 373225#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 373223#L598-33 assume 1 == ~t6_pc~0; 373220#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 373217#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 373215#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 373213#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 373211#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 373209#L617-33 assume !(1 == ~t7_pc~0); 373207#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 373204#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 373203#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 373202#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 373201#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 373200#L636-33 assume !(1 == ~t8_pc~0); 373197#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 373195#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 373193#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 373191#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 373189#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 373187#L655-33 assume !(1 == ~t9_pc~0); 373185#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 373182#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 373180#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 373178#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 373176#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 373173#L674-33 assume 1 == ~t10_pc~0; 373171#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 373168#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 373166#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 373164#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 373162#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 373160#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 373158#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 373154#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 373152#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 373148#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 373146#L1139-3 assume !(1 == ~T5_E~0); 373143#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 373141#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 373139#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 373137#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 373135#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 373133#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 373128#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 373126#L1179-3 assume !(1 == ~E_3~0); 373124#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 373122#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 373120#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 373118#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 373115#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 373113#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 373109#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 373107#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 373081#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 373080#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 373076#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 373073#L1539 assume !(0 == start_simulation_~tmp~3#1); 373070#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 372984#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 372978#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 372977#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 372976#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 372963#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 372941#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 372927#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 372924#L1520-2 [2021-11-20 05:32:42,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:42,932 INFO L85 PathProgramCache]: Analyzing trace with hash -463427376, now seen corresponding path program 1 times [2021-11-20 05:32:42,932 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:42,932 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857367091] [2021-11-20 05:32:42,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:42,933 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:42,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:42,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:42,970 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:42,970 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1857367091] [2021-11-20 05:32:42,970 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1857367091] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:42,971 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:42,971 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:42,971 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1892061664] [2021-11-20 05:32:42,971 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:42,972 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:32:42,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:42,972 INFO L85 PathProgramCache]: Analyzing trace with hash 1354450699, now seen corresponding path program 1 times [2021-11-20 05:32:42,972 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:42,972 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [592746874] [2021-11-20 05:32:42,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:42,973 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:42,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:43,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:43,006 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:43,006 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [592746874] [2021-11-20 05:32:43,006 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [592746874] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:43,006 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:43,007 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:43,007 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [93584799] [2021-11-20 05:32:43,007 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:43,007 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:32:43,008 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:32:43,008 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-20 05:32:43,008 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-20 05:32:43,009 INFO L87 Difference]: Start difference. First operand 124825 states and 180765 transitions. cyclomatic complexity: 56004 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:44,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:32:44,648 INFO L93 Difference]: Finished difference Result 353680 states and 509014 transitions. [2021-11-20 05:32:44,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-20 05:32:44,649 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 353680 states and 509014 transitions. [2021-11-20 05:32:46,694 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 349476 [2021-11-20 05:32:47,554 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 353680 states to 353680 states and 509014 transitions. [2021-11-20 05:32:47,554 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 353680 [2021-11-20 05:32:47,699 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 353680 [2021-11-20 05:32:47,699 INFO L73 IsDeterministic]: Start isDeterministic. Operand 353680 states and 509014 transitions. [2021-11-20 05:32:47,842 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:32:47,842 INFO L681 BuchiCegarLoop]: Abstraction has 353680 states and 509014 transitions. [2021-11-20 05:32:48,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 353680 states and 509014 transitions. [2021-11-20 05:32:50,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 353680 to 345200. [2021-11-20 05:32:51,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 345200 states, 345200 states have (on average 1.441500579374276) internal successors, (497606), 345199 states have internal predecessors, (497606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:53,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 345200 states to 345200 states and 497606 transitions. [2021-11-20 05:32:53,139 INFO L704 BuchiCegarLoop]: Abstraction has 345200 states and 497606 transitions. [2021-11-20 05:32:53,139 INFO L587 BuchiCegarLoop]: Abstraction has 345200 states and 497606 transitions. [2021-11-20 05:32:53,139 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-20 05:32:53,139 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 345200 states and 497606 transitions. [2021-11-20 05:32:53,962 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 344292 [2021-11-20 05:32:53,962 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-20 05:32:53,962 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-20 05:32:53,965 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:53,965 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-20 05:32:53,966 INFO L791 eck$LassoCheckResult]: Stem: 842403#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 842404#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 842897#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 842863#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 842864#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 842931#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 842932#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 841895#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 841611#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 841612#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 842722#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 842723#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 842691#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 842692#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 842757#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 841664#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 841665#L1006 assume !(0 == ~M_E~0); 841515#L1006-2 assume !(0 == ~T1_E~0); 841516#L1011-1 assume !(0 == ~T2_E~0); 842810#L1016-1 assume !(0 == ~T3_E~0); 842843#L1021-1 assume !(0 == ~T4_E~0); 841394#L1026-1 assume !(0 == ~T5_E~0); 841395#L1031-1 assume !(0 == ~T6_E~0); 842339#L1036-1 assume !(0 == ~T7_E~0); 842332#L1041-1 assume !(0 == ~T8_E~0); 842333#L1046-1 assume !(0 == ~T9_E~0); 841695#L1051-1 assume !(0 == ~T10_E~0); 841696#L1056-1 assume !(0 == ~E_1~0); 842520#L1061-1 assume !(0 == ~E_2~0); 841613#L1066-1 assume !(0 == ~E_3~0); 841614#L1071-1 assume !(0 == ~E_4~0); 842493#L1076-1 assume !(0 == ~E_5~0); 841523#L1081-1 assume !(0 == ~E_6~0); 841524#L1086-1 assume !(0 == ~E_7~0); 841871#L1091-1 assume !(0 == ~E_8~0); 842785#L1096-1 assume !(0 == ~E_9~0); 842786#L1101-1 assume !(0 == ~E_10~0); 841940#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 841941#L484 assume !(1 == ~m_pc~0); 842047#L484-2 is_master_triggered_~__retres1~0#1 := 0; 842048#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 842240#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 842630#L1245 assume !(0 != activate_threads_~tmp~1#1); 842631#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 842325#L503 assume !(1 == ~t1_pc~0); 842326#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 842566#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 842511#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 842070#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 841424#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 841425#L522 assume !(1 == ~t2_pc~0); 842283#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 841628#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 841629#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 842132#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 842724#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 842860#L541 assume !(1 == ~t3_pc~0); 842002#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 842003#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 841805#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 841806#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 842290#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 842291#L560 assume !(1 == ~t4_pc~0); 841507#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 841506#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 842170#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 841390#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 841391#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 841678#L579 assume !(1 == ~t5_pc~0); 841679#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 841451#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 841452#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 842175#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 842842#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 842890#L598 assume !(1 == ~t6_pc~0); 842543#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 842110#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 842111#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 842676#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 842380#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 842316#L617 assume !(1 == ~t7_pc~0); 841747#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 841746#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 842049#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 842050#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 841978#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 841979#L636 assume 1 == ~t8_pc~0; 842167#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 842168#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 841942#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 841943#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 842118#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 842119#L655 assume !(1 == ~t9_pc~0); 842151#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 842152#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 841727#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 841728#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 842405#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 842406#L674 assume 1 == ~t10_pc~0; 841500#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 841501#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 842862#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 842971#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 842104#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 842105#L1119 assume !(1 == ~M_E~0); 841593#L1119-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 841594#L1124-1 assume !(1 == ~T2_E~0); 841414#L1129-1 assume !(1 == ~T3_E~0); 841415#L1134-1 assume !(1 == ~T4_E~0); 841732#L1139-1 assume !(1 == ~T5_E~0); 841733#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 841976#L1149-1 assume !(1 == ~T7_E~0); 841587#L1154-1 assume !(1 == ~T8_E~0); 841588#L1159-1 assume !(1 == ~T9_E~0); 841680#L1164-1 assume !(1 == ~T10_E~0); 842135#L1169-1 assume !(1 == ~E_1~0); 842014#L1174-1 assume !(1 == ~E_2~0); 841788#L1179-1 assume !(1 == ~E_3~0); 841668#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 841669#L1189-1 assume !(1 == ~E_5~0); 841726#L1194-1 assume !(1 == ~E_6~0); 841848#L1199-1 assume !(1 == ~E_7~0); 841795#L1204-1 assume !(1 == ~E_8~0); 841796#L1209-1 assume !(1 == ~E_9~0); 842915#L1214-1 assume !(1 == ~E_10~0); 1063717#L1219-1 assume { :end_inline_reset_delta_events } true; 1063715#L1520-2 [2021-11-20 05:32:53,966 INFO L793 eck$LassoCheckResult]: Loop: 1063715#L1520-2 assume !false; 1063410#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1063407#L981 assume !false; 1063405#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1063370#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1063362#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1062485#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1062480#L836 assume !(0 != eval_~tmp~0#1); 1062481#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1064437#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1064434#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1064432#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1064430#L1011-3 assume !(0 == ~T2_E~0); 1064428#L1016-3 assume !(0 == ~T3_E~0); 1064426#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1064424#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1064421#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1064419#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1064417#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1064415#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1064413#L1051-3 assume !(0 == ~T10_E~0); 1064411#L1056-3 assume !(0 == ~E_1~0); 1064408#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1064406#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1064404#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1064402#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1064400#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1064399#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1064396#L1091-3 assume !(0 == ~E_8~0); 1064394#L1096-3 assume !(0 == ~E_9~0); 1064392#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1064387#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1064382#L484-33 assume !(1 == ~m_pc~0); 1064376#L484-35 is_master_triggered_~__retres1~0#1 := 0; 1064374#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1064372#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1064371#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1064370#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1064369#L503-33 assume !(1 == ~t1_pc~0); 1064368#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1064367#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1064366#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1064365#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1064364#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1064363#L522-33 assume 1 == ~t2_pc~0; 1064361#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1064349#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1064347#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1064345#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1064342#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1064340#L541-33 assume !(1 == ~t3_pc~0); 1064338#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1064336#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1064334#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1064332#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1064330#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1064328#L560-33 assume 1 == ~t4_pc~0; 1064325#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1064323#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1064321#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1064319#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 1064317#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1064315#L579-33 assume !(1 == ~t5_pc~0); 1064313#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1064311#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1064309#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1064307#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1064305#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1064303#L598-33 assume !(1 == ~t6_pc~0); 1064301#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 1064299#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1064297#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1064295#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1064293#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1064291#L617-33 assume 1 == ~t7_pc~0; 1064288#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1064286#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1064284#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1064282#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1064280#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1064278#L636-33 assume !(1 == ~t8_pc~0); 1064275#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1064273#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1064271#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1064269#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1064267#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1064265#L655-33 assume 1 == ~t9_pc~0; 1064261#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1064259#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1064257#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1064255#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1064253#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1064251#L674-33 assume !(1 == ~t10_pc~0); 1064248#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 1064246#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1064244#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1064242#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1064240#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1064238#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1064235#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 957587#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1064232#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1064169#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1064229#L1139-3 assume !(1 == ~T5_E~0); 1064227#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1064225#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1064223#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1064221#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1064219#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1064217#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1063961#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1064214#L1179-3 assume !(1 == ~E_3~0); 1064212#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1064210#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1064208#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1064206#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1064204#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1064201#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1050736#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1064198#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1063744#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1063742#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1063741#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1063739#L1539 assume !(0 == start_simulation_~tmp~3#1); 1063737#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1063730#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1063725#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1063724#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1063723#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1063722#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1063720#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1063718#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 1063715#L1520-2 [2021-11-20 05:32:53,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:53,968 INFO L85 PathProgramCache]: Analyzing trace with hash -1164995601, now seen corresponding path program 1 times [2021-11-20 05:32:53,968 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:53,968 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967113216] [2021-11-20 05:32:53,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:53,968 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:53,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:54,013 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:54,013 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:54,013 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967113216] [2021-11-20 05:32:54,013 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [967113216] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:54,014 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:54,014 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-20 05:32:54,014 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [534583814] [2021-11-20 05:32:54,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:54,015 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-20 05:32:54,015 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-20 05:32:54,015 INFO L85 PathProgramCache]: Analyzing trace with hash 534927596, now seen corresponding path program 1 times [2021-11-20 05:32:54,016 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-20 05:32:54,016 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1450151961] [2021-11-20 05:32:54,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-20 05:32:54,016 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-20 05:32:54,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-20 05:32:54,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-20 05:32:54,052 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-20 05:32:54,052 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1450151961] [2021-11-20 05:32:54,052 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1450151961] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-20 05:32:54,052 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-20 05:32:54,053 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-20 05:32:54,053 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1301274086] [2021-11-20 05:32:54,053 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-20 05:32:54,053 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-20 05:32:54,054 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-20 05:32:54,054 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-20 05:32:54,054 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-20 05:32:54,054 INFO L87 Difference]: Start difference. First operand 345200 states and 497606 transitions. cyclomatic complexity: 152534 Second operand has 5 states, 5 states have (on average 25.2) internal successors, (126), 5 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-20 05:32:57,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-20 05:32:57,996 INFO L93 Difference]: Finished difference Result 841951 states and 1225543 transitions. [2021-11-20 05:32:57,997 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-20 05:32:57,997 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 841951 states and 1225543 transitions. [2021-11-20 05:33:02,934 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 839456 [2021-11-20 05:33:05,546 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 841951 states to 841951 states and 1225543 transitions. [2021-11-20 05:33:05,546 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 841951 [2021-11-20 05:33:05,864 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 841951 [2021-11-20 05:33:05,864 INFO L73 IsDeterministic]: Start isDeterministic. Operand 841951 states and 1225543 transitions. [2021-11-20 05:33:06,652 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-20 05:33:06,652 INFO L681 BuchiCegarLoop]: Abstraction has 841951 states and 1225543 transitions. [2021-11-20 05:33:06,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 841951 states and 1225543 transitions.